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drm/radeon: remove r600 blit mutex v2
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
5a0e3ad6 28#include <linux/slab.h>
3ce0a23d
JG		 29#include <linux/seq_file.h>
30#include <linux/firmware.h>
31#include <linux/platform_device.h>
e0cd3608 32#include <linux/module.h>
771fe6b9 33#include "drmP.h"
3ce0a23d 34#include "radeon_drm.h"
771fe6b9 35#include "radeon.h"
e6990375 36#include "radeon_asic.h"
3ce0a23d 37#include "radeon_mode.h"
3ce0a23d 38#include "r600d.h"
3ce0a23d 39#include "atom.h"
d39c3b89 40#include "avivod.h"
771fe6b9 41
3ce0a23d
JG		 42#define PFP_UCODE_SIZE 576
43#define PM4_UCODE_SIZE 1792
d8f60cfc 44#define RLC_UCODE_SIZE 768
3ce0a23d
JG		 45#define R700_PFP_UCODE_SIZE 848
46#define R700_PM4_UCODE_SIZE 1360
d8f60cfc 47#define R700_RLC_UCODE_SIZE 1024
fe251e2f
AD		 48#define EVERGREEN_PFP_UCODE_SIZE 1120
49#define EVERGREEN_PM4_UCODE_SIZE 1376
45f9a39b 50#define EVERGREEN_RLC_UCODE_SIZE 768
12727809 51#define CAYMAN_RLC_UCODE_SIZE 1024
c420c745 52#define ARUBA_RLC_UCODE_SIZE 1536
3ce0a23d
JG		 53
54/* Firmware Names */
55MODULE_FIRMWARE("radeon/R600_pfp.bin");
56MODULE_FIRMWARE("radeon/R600_me.bin");
57MODULE_FIRMWARE("radeon/RV610_pfp.bin");
58MODULE_FIRMWARE("radeon/RV610_me.bin");
59MODULE_FIRMWARE("radeon/RV630_pfp.bin");
60MODULE_FIRMWARE("radeon/RV630_me.bin");
61MODULE_FIRMWARE("radeon/RV620_pfp.bin");
62MODULE_FIRMWARE("radeon/RV620_me.bin");
63MODULE_FIRMWARE("radeon/RV635_pfp.bin");
64MODULE_FIRMWARE("radeon/RV635_me.bin");
65MODULE_FIRMWARE("radeon/RV670_pfp.bin");
66MODULE_FIRMWARE("radeon/RV670_me.bin");
67MODULE_FIRMWARE("radeon/RS780_pfp.bin");
68MODULE_FIRMWARE("radeon/RS780_me.bin");
69MODULE_FIRMWARE("radeon/RV770_pfp.bin");
70MODULE_FIRMWARE("radeon/RV770_me.bin");
71MODULE_FIRMWARE("radeon/RV730_pfp.bin");
72MODULE_FIRMWARE("radeon/RV730_me.bin");
73MODULE_FIRMWARE("radeon/RV710_pfp.bin");
74MODULE_FIRMWARE("radeon/RV710_me.bin");
d8f60cfc
AD		 75MODULE_FIRMWARE("radeon/R600_rlc.bin");
76MODULE_FIRMWARE("radeon/R700_rlc.bin");
fe251e2f
AD		 77MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
78MODULE_FIRMWARE("radeon/CEDAR_me.bin");
45f9a39b 79MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
fe251e2f
AD		 80MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
81MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
45f9a39b 82MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
fe251e2f
AD		 83MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
84MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
45f9a39b 85MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
a7433742 86MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
fe251e2f 87MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
45f9a39b 88MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
439bd6cd
AD		 89MODULE_FIRMWARE("radeon/PALM_pfp.bin");
90MODULE_FIRMWARE("radeon/PALM_me.bin");
91MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
d5c5a72f
AD		 92MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
93MODULE_FIRMWARE("radeon/SUMO_me.bin");
94MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
95MODULE_FIRMWARE("radeon/SUMO2_me.bin");
3ce0a23d
JG		 96
97int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 98
1a029b76 99/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9
JG		 100int r600_mc_wait_for_idle(struct radeon_device *rdev);
101void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 102void r600_fini(struct radeon_device *rdev);
45f9a39b 103void r600_irq_disable(struct radeon_device *rdev);
9e46a48d 104static void r600_pcie_gen2_enable(struct radeon_device *rdev);
771fe6b9 105
21a8122a 106/* get temperature in millidegrees */
20d391d7 107int rv6xx_get_temp(struct radeon_device *rdev)
21a8122a
AD		 108{
109 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
110 ASIC_T_SHIFT;
20d391d7 111 int actual_temp = temp & 0xff;
21a8122a 112
20d391d7
AD		 113 if (temp & 0x100)
114 actual_temp -= 256;
115
116 return actual_temp * 1000;
21a8122a
AD		 117}
118
ce8f5370 119void r600_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 120{
121 int i;
122
ce8f5370
AD		 123 rdev->pm.dynpm_can_upclock = true;
124 rdev->pm.dynpm_can_downclock = true;
a48b9b4e
AD		 125
126 /* power state array is low to high, default is first */
127 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
128 int min_power_state_index = 0;
129
130 if (rdev->pm.num_power_states > 2)
131 min_power_state_index = 1;
132
ce8f5370
AD		 133 switch (rdev->pm.dynpm_planned_action) {
134 case DYNPM_ACTION_MINIMUM:
a48b9b4e
AD		 135 rdev->pm.requested_power_state_index = min_power_state_index;
136 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 137 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 138 break;
ce8f5370 139 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 140 if (rdev->pm.current_power_state_index == min_power_state_index) {
141 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 142 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 143 } else {
144 if (rdev->pm.active_crtc_count > 1) {
145 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 146 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 147 continue;
148 else if (i >= rdev->pm.current_power_state_index) {
149 rdev->pm.requested_power_state_index =
150 rdev->pm.current_power_state_index;
151 break;
152 } else {
153 rdev->pm.requested_power_state_index = i;
154 break;
155 }
156 }
773c3fa3
AD		 157 } else {
158 if (rdev->pm.current_power_state_index == 0)
159 rdev->pm.requested_power_state_index =
160 rdev->pm.num_power_states - 1;
161 else
162 rdev->pm.requested_power_state_index =
163 rdev->pm.current_power_state_index - 1;
164 }
a48b9b4e
AD		 165 }
166 rdev->pm.requested_clock_mode_index = 0;
d7311171
AD		 167 /* don't use the power state if crtcs are active and no display flag is set */
168 if ((rdev->pm.active_crtc_count > 0) &&
169 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
170 clock_info[rdev->pm.requested_clock_mode_index].flags &
171 RADEON_PM_MODE_NO_DISPLAY)) {
172 rdev->pm.requested_power_state_index++;
173 }
a48b9b4e 174 break;
ce8f5370 175 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 176 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
177 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 178 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 179 } else {
180 if (rdev->pm.active_crtc_count > 1) {
181 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 182 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 183 continue;
184 else if (i <= rdev->pm.current_power_state_index) {
185 rdev->pm.requested_power_state_index =
186 rdev->pm.current_power_state_index;
187 break;
188 } else {
189 rdev->pm.requested_power_state_index = i;
190 break;
191 }
192 }
193 } else
194 rdev->pm.requested_power_state_index =
195 rdev->pm.current_power_state_index + 1;
196 }
197 rdev->pm.requested_clock_mode_index = 0;
198 break;
ce8f5370 199 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 200 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
201 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 202 rdev->pm.dynpm_can_upclock = false;
58e21dff 203 break;
ce8f5370 204 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 205 default:
206 DRM_ERROR("Requested mode for not defined action\n");
207 return;
208 }
209 } else {
210 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
211 /* for now just select the first power state and switch between clock modes */
212 /* power state array is low to high, default is first (0) */
213 if (rdev->pm.active_crtc_count > 1) {
214 rdev->pm.requested_power_state_index = -1;
215 /* start at 1 as we don't want the default mode */
216 for (i = 1; i < rdev->pm.num_power_states; i++) {
d7311171 217 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 218 continue;
219 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
220 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
221 rdev->pm.requested_power_state_index = i;
222 break;
223 }
224 }
225 /* if nothing selected, grab the default state. */
226 if (rdev->pm.requested_power_state_index == -1)
227 rdev->pm.requested_power_state_index = 0;
228 } else
229 rdev->pm.requested_power_state_index = 1;
230
ce8f5370
AD		 231 switch (rdev->pm.dynpm_planned_action) {
232 case DYNPM_ACTION_MINIMUM:
a48b9b4e 233 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 234 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 235 break;
ce8f5370 236 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 237 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
238 if (rdev->pm.current_clock_mode_index == 0) {
239 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 240 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 241 } else
242 rdev->pm.requested_clock_mode_index =
243 rdev->pm.current_clock_mode_index - 1;
244 } else {
245 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 246 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 247 }
d7311171
AD		 248 /* don't use the power state if crtcs are active and no display flag is set */
249 if ((rdev->pm.active_crtc_count > 0) &&
250 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
251 clock_info[rdev->pm.requested_clock_mode_index].flags &
252 RADEON_PM_MODE_NO_DISPLAY)) {
253 rdev->pm.requested_clock_mode_index++;
254 }
a48b9b4e 255 break;
ce8f5370 256 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 257 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
258 if (rdev->pm.current_clock_mode_index ==
259 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
260 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
ce8f5370 261 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 262 } else
263 rdev->pm.requested_clock_mode_index =
264 rdev->pm.current_clock_mode_index + 1;
265 } else {
266 rdev->pm.requested_clock_mode_index =
267 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
ce8f5370 268 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 269 }
270 break;
ce8f5370 271 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 272 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
273 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 274 rdev->pm.dynpm_can_upclock = false;
58e21dff 275 break;
ce8f5370 276 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 277 default:
278 DRM_ERROR("Requested mode for not defined action\n");
279 return;
280 }
281 }
282
d9fdaafb 283 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 284 rdev->pm.power_state[rdev->pm.requested_power_state_index].
285 clock_info[rdev->pm.requested_clock_mode_index].sclk,
286 rdev->pm.power_state[rdev->pm.requested_power_state_index].
287 clock_info[rdev->pm.requested_clock_mode_index].mclk,
288 rdev->pm.power_state[rdev->pm.requested_power_state_index].
289 pcie_lanes);
a48b9b4e
AD		 290}
291
ce8f5370
AD		 292void rs780_pm_init_profile(struct radeon_device *rdev)
293{
294 if (rdev->pm.num_power_states == 2) {
295 /* default */
296 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
297 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
298 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
299 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
300 /* low sh */
301 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
303 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
304 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 305 /* mid sh */
306 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 310 /* high sh */
311 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
313 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
315 /* low mh */
316 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 320 /* mid mh */
321 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 325 /* high mh */
326 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
328 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
330 } else if (rdev->pm.num_power_states == 3) {
331 /* default */
332 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
333 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
334 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
336 /* low sh */
337 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
338 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
339 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 341 /* mid sh */
342 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
343 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
344 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 346 /* high sh */
347 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
348 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
349 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
350 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
351 /* low mh */
352 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
353 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
354 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
355 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 356 /* mid mh */
357 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
358 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
359 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
360 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 361 /* high mh */
362 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
363 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
364 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
365 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
366 } else {
367 /* default */
368 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
369 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
370 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
371 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
372 /* low sh */
373 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
374 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
375 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
376 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 377 /* mid sh */
378 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
379 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
380 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
381 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 382 /* high sh */
383 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
384 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
385 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
386 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
387 /* low mh */
388 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
389 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
390 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
391 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 392 /* mid mh */
393 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
394 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
395 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
396 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 397 /* high mh */
398 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
399 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
400 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
401 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
402 }
403}
bae6b562 404
ce8f5370
AD		 405void r600_pm_init_profile(struct radeon_device *rdev)
406{
bbe26ffe
AD		 407 int idx;
408
ce8f5370
AD		 409 if (rdev->family == CHIP_R600) {
410 /* XXX */
411 /* default */
412 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
413 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
414 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
4bff5171 415 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 416 /* low sh */
417 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
418 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
419 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 420 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 421 /* mid sh */
422 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
423 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
424 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
425 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 426 /* high sh */
427 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
428 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
429 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 430 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 431 /* low mh */
432 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
433 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
434 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 435 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 436 /* mid mh */
437 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
439 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
440 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 441 /* high mh */
442 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
443 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
444 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 445 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 446 } else {
447 if (rdev->pm.num_power_states < 4) {
448 /* default */
449 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
450 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
451 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
452 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
453 /* low sh */
4bff5171
AD		 454 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
455 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370 456 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 457 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
458 /* mid sh */
459 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
460 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
461 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
462 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 463 /* high sh */
4bff5171
AD		 464 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
465 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370
AD		 466 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
467 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
468 /* low mh */
4bff5171
AD		 469 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
470 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370 471 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 472 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
473 /* low mh */
474 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
475 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
476 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
477 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 478 /* high mh */
4bff5171
AD		 479 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
480 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370
AD		 481 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
482 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
483 } else {
484 /* default */
485 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
488 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
489 /* low sh */
bbe26ffe
AD		 490 if (rdev->flags & RADEON_IS_MOBILITY)
491 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
492 else
493 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
495 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
496 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
497 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21 498 /* mid sh */
bbe26ffe
AD		 499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
500 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
501 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
502 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 503 /* high sh */
bbe26ffe
AD		 504 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
505 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
506 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
ce8f5370
AD		 507 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
508 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
509 /* low mh */
bbe26ffe
AD		 510 if (rdev->flags & RADEON_IS_MOBILITY)
511 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
512 else
513 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
514 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
515 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
516 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
517 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21 518 /* mid mh */
bbe26ffe
AD		 519 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
520 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
521 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
522 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 523 /* high mh */
bbe26ffe
AD		 524 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
525 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
526 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
ce8f5370
AD		 527 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
528 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
529 }
530 }
bae6b562
AD		 531}
532
49e02b73
AD		 533void r600_pm_misc(struct radeon_device *rdev)
534{
a081a9d6
RM		 535 int req_ps_idx = rdev->pm.requested_power_state_index;
536 int req_cm_idx = rdev->pm.requested_clock_mode_index;
537 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
538 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
7ac9aa5a 539
4d60173f 540 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
a377e187
AD		 541 /* 0xff01 is a flag rather then an actual voltage */
542 if (voltage->voltage == 0xff01)
543 return;
4d60173f 544 if (voltage->voltage != rdev->pm.current_vddc) {
8a83ec5e 545 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 546 rdev->pm.current_vddc = voltage->voltage;
d9fdaafb 547 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 548 }
549 }
49e02b73
AD		 550}
551
def9ba9c
AD		 552bool r600_gui_idle(struct radeon_device *rdev)
553{
554 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
555 return false;
556 else
557 return true;
558}
559
e0df1ac5
AD		 560/* hpd for digital panel detect/disconnect */
561bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
562{
563 bool connected = false;
564
565 if (ASIC_IS_DCE3(rdev)) {
566 switch (hpd) {
567 case RADEON_HPD_1:
568 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
569 connected = true;
570 break;
571 case RADEON_HPD_2:
572 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
573 connected = true;
574 break;
575 case RADEON_HPD_3:
576 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
577 connected = true;
578 break;
579 case RADEON_HPD_4:
580 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
581 connected = true;
582 break;
583 /* DCE 3.2 */
584 case RADEON_HPD_5:
585 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
586 connected = true;
587 break;
588 case RADEON_HPD_6:
589 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
590 connected = true;
591 break;
592 default:
593 break;
594 }
595 } else {
596 switch (hpd) {
597 case RADEON_HPD_1:
598 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
599 connected = true;
600 break;
601 case RADEON_HPD_2:
602 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
603 connected = true;
604 break;
605 case RADEON_HPD_3:
606 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
607 connected = true;
608 break;
609 default:
610 break;
611 }
612 }
613 return connected;
614}
615
616void r600_hpd_set_polarity(struct radeon_device *rdev,
429770b3 617 enum radeon_hpd_id hpd)
e0df1ac5
AD		 618{
619 u32 tmp;
620 bool connected = r600_hpd_sense(rdev, hpd);
621
622 if (ASIC_IS_DCE3(rdev)) {
623 switch (hpd) {
624 case RADEON_HPD_1:
625 tmp = RREG32(DC_HPD1_INT_CONTROL);
626 if (connected)
627 tmp &= ~DC_HPDx_INT_POLARITY;
628 else
629 tmp |= DC_HPDx_INT_POLARITY;
630 WREG32(DC_HPD1_INT_CONTROL, tmp);
631 break;
632 case RADEON_HPD_2:
633 tmp = RREG32(DC_HPD2_INT_CONTROL);
634 if (connected)
635 tmp &= ~DC_HPDx_INT_POLARITY;
636 else
637 tmp |= DC_HPDx_INT_POLARITY;
638 WREG32(DC_HPD2_INT_CONTROL, tmp);
639 break;
640 case RADEON_HPD_3:
641 tmp = RREG32(DC_HPD3_INT_CONTROL);
642 if (connected)
643 tmp &= ~DC_HPDx_INT_POLARITY;
644 else
645 tmp |= DC_HPDx_INT_POLARITY;
646 WREG32(DC_HPD3_INT_CONTROL, tmp);
647 break;
648 case RADEON_HPD_4:
649 tmp = RREG32(DC_HPD4_INT_CONTROL);
650 if (connected)
651 tmp &= ~DC_HPDx_INT_POLARITY;
652 else
653 tmp |= DC_HPDx_INT_POLARITY;
654 WREG32(DC_HPD4_INT_CONTROL, tmp);
655 break;
656 case RADEON_HPD_5:
657 tmp = RREG32(DC_HPD5_INT_CONTROL);
658 if (connected)
659 tmp &= ~DC_HPDx_INT_POLARITY;
660 else
661 tmp |= DC_HPDx_INT_POLARITY;
662 WREG32(DC_HPD5_INT_CONTROL, tmp);
663 break;
664 /* DCE 3.2 */
665 case RADEON_HPD_6:
666 tmp = RREG32(DC_HPD6_INT_CONTROL);
667 if (connected)
668 tmp &= ~DC_HPDx_INT_POLARITY;
669 else
670 tmp |= DC_HPDx_INT_POLARITY;
671 WREG32(DC_HPD6_INT_CONTROL, tmp);
672 break;
673 default:
674 break;
675 }
676 } else {
677 switch (hpd) {
678 case RADEON_HPD_1:
679 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
680 if (connected)
681 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
682 else
683 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
684 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
685 break;
686 case RADEON_HPD_2:
687 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
688 if (connected)
689 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
690 else
691 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
692 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
693 break;
694 case RADEON_HPD_3:
695 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
696 if (connected)
697 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
698 else
699 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
700 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
701 break;
702 default:
703 break;
704 }
705 }
706}
707
708void r600_hpd_init(struct radeon_device *rdev)
709{
710 struct drm_device *dev = rdev->ddev;
711 struct drm_connector *connector;
712
64912e99
AD		 713 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
714 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
715
716 if (ASIC_IS_DCE3(rdev)) {
717 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
718 if (ASIC_IS_DCE32(rdev))
719 tmp |= DC_HPDx_EN;
e0df1ac5 720
e0df1ac5
AD		 721 switch (radeon_connector->hpd.hpd) {
722 case RADEON_HPD_1:
723 WREG32(DC_HPD1_CONTROL, tmp);
724 rdev->irq.hpd[0] = true;
725 break;
726 case RADEON_HPD_2:
727 WREG32(DC_HPD2_CONTROL, tmp);
728 rdev->irq.hpd[1] = true;
729 break;
730 case RADEON_HPD_3:
731 WREG32(DC_HPD3_CONTROL, tmp);
732 rdev->irq.hpd[2] = true;
733 break;
734 case RADEON_HPD_4:
735 WREG32(DC_HPD4_CONTROL, tmp);
736 rdev->irq.hpd[3] = true;
737 break;
738 /* DCE 3.2 */
739 case RADEON_HPD_5:
740 WREG32(DC_HPD5_CONTROL, tmp);
741 rdev->irq.hpd[4] = true;
742 break;
743 case RADEON_HPD_6:
744 WREG32(DC_HPD6_CONTROL, tmp);
745 rdev->irq.hpd[5] = true;
746 break;
747 default:
748 break;
749 }
64912e99 750 } else {
e0df1ac5
AD		 751 switch (radeon_connector->hpd.hpd) {
752 case RADEON_HPD_1:
753 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
754 rdev->irq.hpd[0] = true;
755 break;
756 case RADEON_HPD_2:
757 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
758 rdev->irq.hpd[1] = true;
759 break;
760 case RADEON_HPD_3:
761 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
762 rdev->irq.hpd[2] = true;
763 break;
764 default:
765 break;
766 }
767 }
64912e99 768 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
e0df1ac5 769 }
003e69f9
JG		 770 if (rdev->irq.installed)
771 r600_irq_set(rdev);
e0df1ac5
AD		 772}
773
774void r600_hpd_fini(struct radeon_device *rdev)
775{
776 struct drm_device *dev = rdev->ddev;
777 struct drm_connector *connector;
778
779 if (ASIC_IS_DCE3(rdev)) {
780 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
781 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
782 switch (radeon_connector->hpd.hpd) {
783 case RADEON_HPD_1:
784 WREG32(DC_HPD1_CONTROL, 0);
785 rdev->irq.hpd[0] = false;
786 break;
787 case RADEON_HPD_2:
788 WREG32(DC_HPD2_CONTROL, 0);
789 rdev->irq.hpd[1] = false;
790 break;
791 case RADEON_HPD_3:
792 WREG32(DC_HPD3_CONTROL, 0);
793 rdev->irq.hpd[2] = false;
794 break;
795 case RADEON_HPD_4:
796 WREG32(DC_HPD4_CONTROL, 0);
797 rdev->irq.hpd[3] = false;
798 break;
799 /* DCE 3.2 */
800 case RADEON_HPD_5:
801 WREG32(DC_HPD5_CONTROL, 0);
802 rdev->irq.hpd[4] = false;
803 break;
804 case RADEON_HPD_6:
805 WREG32(DC_HPD6_CONTROL, 0);
806 rdev->irq.hpd[5] = false;
807 break;
808 default:
809 break;
810 }
811 }
812 } else {
813 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
814 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
815 switch (radeon_connector->hpd.hpd) {
816 case RADEON_HPD_1:
817 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
818 rdev->irq.hpd[0] = false;
819 break;
820 case RADEON_HPD_2:
821 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
822 rdev->irq.hpd[1] = false;
823 break;
824 case RADEON_HPD_3:
825 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
826 rdev->irq.hpd[2] = false;
827 break;
828 default:
829 break;
830 }
831 }
832 }
833}
834
771fe6b9 835/*
3ce0a23d 836 * R600 PCIE GART
771fe6b9 837 */
3ce0a23d
JG		 838void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
839{
840 unsigned i;
841 u32 tmp;
842
2e98f10a 843 /* flush hdp cache so updates hit vram */
f3886f85
AD		 844 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
845 !(rdev->flags & RADEON_IS_AGP)) {
c9a1be96 846 void __iomem *ptr = (void *)rdev->gart.ptr;
812d0469
AD		 847 u32 tmp;
848
849 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
850 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
f3886f85
AD		 851 * This seems to cause problems on some AGP cards. Just use the old
852 * method for them.
812d0469
AD		 853 */
854 WREG32(HDP_DEBUG1, 0);
855 tmp = readl((void __iomem *)ptr);
856 } else
857 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2e98f10a 858
3ce0a23d
JG		 859 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
860 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
861 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
862 for (i = 0; i < rdev->usec_timeout; i++) {
863 /* read MC_STATUS */
864 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
865 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
866 if (tmp == 2) {
867 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
868 return;
869 }
870 if (tmp) {
871 return;
872 }
873 udelay(1);
874 }
875}
876
4aac0473 877int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 878{
4aac0473 879 int r;
3ce0a23d 880
c9a1be96 881 if (rdev->gart.robj) {
fce7d61b 882 WARN(1, "R600 PCIE GART already initialized\n");
4aac0473
JG		 883 return 0;
884 }
3ce0a23d
JG		 885 /* Initialize common gart structure */
886 r = radeon_gart_init(rdev);
4aac0473 887 if (r)
3ce0a23d 888 return r;
3ce0a23d 889 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 890 return radeon_gart_table_vram_alloc(rdev);
891}
892
893int r600_pcie_gart_enable(struct radeon_device *rdev)
894{
895 u32 tmp;
896 int r, i;
897
c9a1be96 898 if (rdev->gart.robj == NULL) {
4aac0473
JG		 899 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
900 return -EINVAL;
771fe6b9 901 }
4aac0473
JG		 902 r = radeon_gart_table_vram_pin(rdev);
903 if (r)
904 return r;
82568565 905 radeon_gart_restore(rdev);
bc1a631e 906
3ce0a23d
JG		 907 /* Setup L2 cache */
908 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
909 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
910 EFFECTIVE_L2_QUEUE_SIZE(7));
911 WREG32(VM_L2_CNTL2, 0);
912 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
913 /* Setup TLB control */
914 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
915 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
916 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
917 ENABLE_WAIT_L2_QUERY;
918 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
919 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
920 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
921 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
922 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
923 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
924 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
925 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
926 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
927 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
928 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
929 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
930 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
931 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
932 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 933 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 934 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
935 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
936 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
937 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
938 (u32)(rdev->dummy_page.addr >> 12));
939 for (i = 1; i < 7; i++)
940 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 941
3ce0a23d 942 r600_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 943 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
944 (unsigned)(rdev->mc.gtt_size >> 20),
945 (unsigned long long)rdev->gart.table_addr);
3ce0a23d 946 rdev->gart.ready = true;
771fe6b9
JG		 947 return 0;
948}
949
3ce0a23d 950void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 951{
3ce0a23d 952 u32 tmp;
c9a1be96 953 int i;
771fe6b9 954
3ce0a23d
JG		 955 /* Disable all tables */
956 for (i = 0; i < 7; i++)
957 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 958
3ce0a23d
JG		 959 /* Disable L2 cache */
960 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
961 EFFECTIVE_L2_QUEUE_SIZE(7));
962 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
963 /* Setup L1 TLB control */
964 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
965 ENABLE_WAIT_L2_QUERY;
966 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
967 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
968 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
969 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
970 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
971 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
972 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
973 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
974 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
975 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
976 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
977 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
978 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
979 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
c9a1be96 980 radeon_gart_table_vram_unpin(rdev);
4aac0473
JG		 981}
982
983void r600_pcie_gart_fini(struct radeon_device *rdev)
984{
f9274562 985 radeon_gart_fini(rdev);
4aac0473
JG		 986 r600_pcie_gart_disable(rdev);
987 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 988}
989
1a029b76
JG		 990void r600_agp_enable(struct radeon_device *rdev)
991{
992 u32 tmp;
993 int i;
994
995 /* Setup L2 cache */
996 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
997 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
998 EFFECTIVE_L2_QUEUE_SIZE(7));
999 WREG32(VM_L2_CNTL2, 0);
1000 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1001 /* Setup TLB control */
1002 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1003 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1004 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1005 ENABLE_WAIT_L2_QUERY;
1006 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1007 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1008 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1009 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1010 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1011 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1012 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1013 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1014 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1015 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1016 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1017 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1018 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1019 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1020 for (i = 0; i < 7; i++)
1021 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1022}
1023
771fe6b9
JG		 1024int r600_mc_wait_for_idle(struct radeon_device *rdev)
1025{
3ce0a23d
JG		 1026 unsigned i;
1027 u32 tmp;
1028
1029 for (i = 0; i < rdev->usec_timeout; i++) {
1030 /* read MC_STATUS */
1031 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1032 if (!tmp)
1033 return 0;
1034 udelay(1);
1035 }
1036 return -1;
771fe6b9
JG		 1037}
1038
a3c1945a 1039static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 1040{
a3c1945a 1041 struct rv515_mc_save save;
3ce0a23d
JG		 1042 u32 tmp;
1043 int i, j;
771fe6b9 1044
3ce0a23d
JG		 1045 /* Initialize HDP */
1046 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1047 WREG32((0x2c14 + j), 0x00000000);
1048 WREG32((0x2c18 + j), 0x00000000);
1049 WREG32((0x2c1c + j), 0x00000000);
1050 WREG32((0x2c20 + j), 0x00000000);
1051 WREG32((0x2c24 + j), 0x00000000);
1052 }
1053 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 1054
a3c1945a 1055 rv515_mc_stop(rdev, &save);
3ce0a23d 1056 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1057 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1058 }
a3c1945a 1059 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 1060 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 1061 /* Update configuration */
1a029b76
JG		 1062 if (rdev->flags & RADEON_IS_AGP) {
1063 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1064 /* VRAM before AGP */
1065 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1066 rdev->mc.vram_start >> 12);
1067 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1068 rdev->mc.gtt_end >> 12);
1069 } else {
1070 /* VRAM after AGP */
1071 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1072 rdev->mc.gtt_start >> 12);
1073 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1074 rdev->mc.vram_end >> 12);
1075 }
1076 } else {
1077 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1078 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1079 }
16cdf04d 1080 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1a029b76 1081 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 1082 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1083 WREG32(MC_VM_FB_LOCATION, tmp);
1084 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1085 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1086 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 1087 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 1088 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1089 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 1090 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1091 } else {
1092 WREG32(MC_VM_AGP_BASE, 0);
1093 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1094 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1095 }
3ce0a23d 1096 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1097 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1098 }
a3c1945a 1099 rv515_mc_resume(rdev, &save);
698443d9
DA		 1100 /* we need to own VRAM, so turn off the VGA renderer here
1101 * to stop it overwriting our objects */
d39c3b89 1102 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 1103}
1104
d594e46a
JG		 1105/**
1106 * r600_vram_gtt_location - try to find VRAM & GTT location
1107 * @rdev: radeon device structure holding all necessary informations
1108 * @mc: memory controller structure holding memory informations
1109 *
1110 * Function will place try to place VRAM at same place as in CPU (PCI)
1111 * address space as some GPU seems to have issue when we reprogram at
1112 * different address space.
1113 *
1114 * If there is not enough space to fit the unvisible VRAM after the
1115 * aperture then we limit the VRAM size to the aperture.
1116 *
1117 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1118 * them to be in one from GPU point of view so that we can program GPU to
1119 * catch access outside them (weird GPU policy see ??).
1120 *
1121 * This function will never fails, worst case are limiting VRAM or GTT.
1122 *
1123 * Note: GTT start, end, size should be initialized before calling this
1124 * function on AGP platform.
1125 */
0ef0c1f7 1126static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
d594e46a
JG		 1127{
1128 u64 size_bf, size_af;
1129
1130 if (mc->mc_vram_size > 0xE0000000) {
1131 /* leave room for at least 512M GTT */
1132 dev_warn(rdev->dev, "limiting VRAM\n");
1133 mc->real_vram_size = 0xE0000000;
1134 mc->mc_vram_size = 0xE0000000;
1135 }
1136 if (rdev->flags & RADEON_IS_AGP) {
1137 size_bf = mc->gtt_start;
dfc6ae5b 1138 size_af = 0xFFFFFFFF - mc->gtt_end;
d594e46a
JG		 1139 if (size_bf > size_af) {
1140 if (mc->mc_vram_size > size_bf) {
1141 dev_warn(rdev->dev, "limiting VRAM\n");
1142 mc->real_vram_size = size_bf;
1143 mc->mc_vram_size = size_bf;
1144 }
1145 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1146 } else {
1147 if (mc->mc_vram_size > size_af) {
1148 dev_warn(rdev->dev, "limiting VRAM\n");
1149 mc->real_vram_size = size_af;
1150 mc->mc_vram_size = size_af;
1151 }
dfc6ae5b 1152 mc->vram_start = mc->gtt_end + 1;
d594e46a
JG		 1153 }
1154 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1155 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1156 mc->mc_vram_size >> 20, mc->vram_start,
1157 mc->vram_end, mc->real_vram_size >> 20);
1158 } else {
1159 u64 base = 0;
8961d52d
AD		 1160 if (rdev->flags & RADEON_IS_IGP) {
1161 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1162 base <<= 24;
1163 }
d594e46a 1164 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 1165 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 1166 radeon_gtt_location(rdev, mc);
1167 }
1168}
1169
3ce0a23d 1170int r600_mc_init(struct radeon_device *rdev)
771fe6b9 1171{
3ce0a23d 1172 u32 tmp;
5885b7a9 1173 int chansize, numchan;
771fe6b9 1174
3ce0a23d 1175 /* Get VRAM informations */
771fe6b9 1176 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 1177 tmp = RREG32(RAMCFG);
1178 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 1179 chansize = 16;
3ce0a23d 1180 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 1181 chansize = 64;
1182 } else {
1183 chansize = 32;
1184 }
5885b7a9
AD		 1185 tmp = RREG32(CHMAP);
1186 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1187 case 0:
1188 default:
1189 numchan = 1;
1190 break;
1191 case 1:
1192 numchan = 2;
1193 break;
1194 case 2:
1195 numchan = 4;
1196 break;
1197 case 3:
1198 numchan = 8;
1199 break;
771fe6b9 1200 }
5885b7a9 1201 rdev->mc.vram_width = numchan * chansize;
3ce0a23d 1202 /* Could aper size report 0 ? */
01d73a69
JC		 1203 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1204 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 1205 /* Setup GPU memory space */
1206 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1207 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 1208 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a 1209 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5 1210
f892034a
AD		 1211 if (rdev->flags & RADEON_IS_IGP) {
1212 rs690_pm_info(rdev);
06b6476d 1213 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
f892034a 1214 }
f47299c5 1215 radeon_update_bandwidth_info(rdev);
3ce0a23d 1216 return 0;
771fe6b9
JG		 1217}
1218
16cdf04d
AD		 1219int r600_vram_scratch_init(struct radeon_device *rdev)
1220{
1221 int r;
1222
1223 if (rdev->vram_scratch.robj == NULL) {
1224 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1225 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1226 &rdev->vram_scratch.robj);
1227 if (r) {
1228 return r;
1229 }
1230 }
1231
1232 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1233 if (unlikely(r != 0))
1234 return r;
1235 r = radeon_bo_pin(rdev->vram_scratch.robj,
1236 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1237 if (r) {
1238 radeon_bo_unreserve(rdev->vram_scratch.robj);
1239 return r;
1240 }
1241 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1242 (void **)&rdev->vram_scratch.ptr);
1243 if (r)
1244 radeon_bo_unpin(rdev->vram_scratch.robj);
1245 radeon_bo_unreserve(rdev->vram_scratch.robj);
1246
1247 return r;
1248}
1249
1250void r600_vram_scratch_fini(struct radeon_device *rdev)
1251{
1252 int r;
1253
1254 if (rdev->vram_scratch.robj == NULL) {
1255 return;
1256 }
1257 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1258 if (likely(r == 0)) {
1259 radeon_bo_kunmap(rdev->vram_scratch.robj);
1260 radeon_bo_unpin(rdev->vram_scratch.robj);
1261 radeon_bo_unreserve(rdev->vram_scratch.robj);
1262 }
1263 radeon_bo_unref(&rdev->vram_scratch.robj);
1264}
1265
3ce0a23d
JG		 1266/* We doesn't check that the GPU really needs a reset we simply do the
1267 * reset, it's up to the caller to determine if the GPU needs one. We
1268 * might add an helper function to check that.
1269 */
1270int r600_gpu_soft_reset(struct radeon_device *rdev)
771fe6b9 1271{
a3c1945a 1272 struct rv515_mc_save save;
3ce0a23d
JG		 1273 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1274 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1275 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1276 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1277 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1278 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1279 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1280 S_008010_GUI_ACTIVE(1);
1281 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1282 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1283 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1284 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1285 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1286 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1287 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1288 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
a3c1945a 1289 u32 tmp;
771fe6b9 1290
8d96fe93
AD		 1291 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1292 return 0;
1293
1a029b76
JG		 1294 dev_info(rdev->dev, "GPU softreset \n");
1295 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1296 RREG32(R_008010_GRBM_STATUS));
1297 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
a3c1945a 1298 RREG32(R_008014_GRBM_STATUS2));
1a029b76
JG		 1299 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1300 RREG32(R_000E50_SRBM_STATUS));
a3c1945a
JG		 1301 rv515_mc_stop(rdev, &save);
1302 if (r600_mc_wait_for_idle(rdev)) {
1303 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1304 }
3ce0a23d 1305 /* Disable CP parsing/prefetching */
90aca4d2 1306 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
3ce0a23d
JG		 1307 /* Check if any of the rendering block is busy and reset it */
1308 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1309 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
a3c1945a 1310 tmp = S_008020_SOFT_RESET_CR(1) |
3ce0a23d
JG		 1311 S_008020_SOFT_RESET_DB(1) |
1312 S_008020_SOFT_RESET_CB(1) |
1313 S_008020_SOFT_RESET_PA(1) |
1314 S_008020_SOFT_RESET_SC(1) |
1315 S_008020_SOFT_RESET_SMX(1) |
1316 S_008020_SOFT_RESET_SPI(1) |
1317 S_008020_SOFT_RESET_SX(1) |
1318 S_008020_SOFT_RESET_SH(1) |
1319 S_008020_SOFT_RESET_TC(1) |
1320 S_008020_SOFT_RESET_TA(1) |
1321 S_008020_SOFT_RESET_VC(1) |
a3c1945a 1322 S_008020_SOFT_RESET_VGT(1);
1a029b76 1323 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
a3c1945a 1324 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1325 RREG32(R_008020_GRBM_SOFT_RESET);
1326 mdelay(15);
3ce0a23d 1327 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d
JG		 1328 }
1329 /* Reset CP (we always reset CP) */
a3c1945a
JG		 1330 tmp = S_008020_SOFT_RESET_CP(1);
1331 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1332 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1333 RREG32(R_008020_GRBM_SOFT_RESET);
1334 mdelay(15);
3ce0a23d 1335 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d 1336 /* Wait a little for things to settle down */
225758d8 1337 mdelay(1);
1a029b76
JG		 1338 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1339 RREG32(R_008010_GRBM_STATUS));
1340 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1341 RREG32(R_008014_GRBM_STATUS2));
1342 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1343 RREG32(R_000E50_SRBM_STATUS));
a3c1945a 1344 rv515_mc_resume(rdev, &save);
3ce0a23d
JG		 1345 return 0;
1346}
1347
e32eb50d 1348bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
225758d8
JG		 1349{
1350 u32 srbm_status;
1351 u32 grbm_status;
1352 u32 grbm_status2;
225758d8
JG		 1353
1354 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1355 grbm_status = RREG32(R_008010_GRBM_STATUS);
1356 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1357 if (!G_008010_GUI_ACTIVE(grbm_status)) {
069211e5 1358 radeon_ring_lockup_update(ring);
225758d8
JG		 1359 return false;
1360 }
1361 /* force CP activities */
7b9ef16b 1362 radeon_ring_force_activity(rdev, ring);
069211e5 1363 return radeon_ring_test_lockup(rdev, ring);
225758d8
JG		 1364}
1365
a2d07b74 1366int r600_asic_reset(struct radeon_device *rdev)
3ce0a23d
JG		 1367{
1368 return r600_gpu_soft_reset(rdev);
1369}
1370
1371static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1372 u32 num_backends,
1373 u32 backend_disable_mask)
1374{
1375 u32 backend_map = 0;
1376 u32 enabled_backends_mask;
1377 u32 enabled_backends_count;
1378 u32 cur_pipe;
1379 u32 swizzle_pipe[R6XX_MAX_PIPES];
1380 u32 cur_backend;
1381 u32 i;
1382
1383 if (num_tile_pipes > R6XX_MAX_PIPES)
1384 num_tile_pipes = R6XX_MAX_PIPES;
1385 if (num_tile_pipes < 1)
1386 num_tile_pipes = 1;
1387 if (num_backends > R6XX_MAX_BACKENDS)
1388 num_backends = R6XX_MAX_BACKENDS;
1389 if (num_backends < 1)
1390 num_backends = 1;
1391
1392 enabled_backends_mask = 0;
1393 enabled_backends_count = 0;
1394 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1395 if (((backend_disable_mask >> i) & 1) == 0) {
1396 enabled_backends_mask |= (1 << i);
1397 ++enabled_backends_count;
1398 }
1399 if (enabled_backends_count == num_backends)
1400 break;
1401 }
1402
1403 if (enabled_backends_count == 0) {
1404 enabled_backends_mask = 1;
1405 enabled_backends_count = 1;
1406 }
1407
1408 if (enabled_backends_count != num_backends)
1409 num_backends = enabled_backends_count;
1410
1411 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1412 switch (num_tile_pipes) {
1413 case 1:
1414 swizzle_pipe[0] = 0;
1415 break;
1416 case 2:
1417 swizzle_pipe[0] = 0;
1418 swizzle_pipe[1] = 1;
1419 break;
1420 case 3:
1421 swizzle_pipe[0] = 0;
1422 swizzle_pipe[1] = 1;
1423 swizzle_pipe[2] = 2;
1424 break;
1425 case 4:
1426 swizzle_pipe[0] = 0;
1427 swizzle_pipe[1] = 1;
1428 swizzle_pipe[2] = 2;
1429 swizzle_pipe[3] = 3;
1430 break;
1431 case 5:
1432 swizzle_pipe[0] = 0;
1433 swizzle_pipe[1] = 1;
1434 swizzle_pipe[2] = 2;
1435 swizzle_pipe[3] = 3;
1436 swizzle_pipe[4] = 4;
1437 break;
1438 case 6:
1439 swizzle_pipe[0] = 0;
1440 swizzle_pipe[1] = 2;
1441 swizzle_pipe[2] = 4;
1442 swizzle_pipe[3] = 5;
1443 swizzle_pipe[4] = 1;
1444 swizzle_pipe[5] = 3;
1445 break;
1446 case 7:
1447 swizzle_pipe[0] = 0;
1448 swizzle_pipe[1] = 2;
1449 swizzle_pipe[2] = 4;
1450 swizzle_pipe[3] = 6;
1451 swizzle_pipe[4] = 1;
1452 swizzle_pipe[5] = 3;
1453 swizzle_pipe[6] = 5;
1454 break;
1455 case 8:
1456 swizzle_pipe[0] = 0;
1457 swizzle_pipe[1] = 2;
1458 swizzle_pipe[2] = 4;
1459 swizzle_pipe[3] = 6;
1460 swizzle_pipe[4] = 1;
1461 swizzle_pipe[5] = 3;
1462 swizzle_pipe[6] = 5;
1463 swizzle_pipe[7] = 7;
1464 break;
1465 }
1466
1467 cur_backend = 0;
1468 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1469 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1470 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1471
1472 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1473
1474 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1475 }
1476
1477 return backend_map;
1478}
1479
1480int r600_count_pipe_bits(uint32_t val)
1481{
1482 int i, ret = 0;
1483
1484 for (i = 0; i < 32; i++) {
1485 ret += val & 1;
1486 val >>= 1;
1487 }
1488 return ret;
771fe6b9
JG		 1489}
1490
3ce0a23d
JG		 1491void r600_gpu_init(struct radeon_device *rdev)
1492{
1493 u32 tiling_config;
1494 u32 ramcfg;
d03f5d59
AD		 1495 u32 backend_map;
1496 u32 cc_rb_backend_disable;
1497 u32 cc_gc_shader_pipe_config;
3ce0a23d
JG		 1498 u32 tmp;
1499 int i, j;
1500 u32 sq_config;
1501 u32 sq_gpr_resource_mgmt_1 = 0;
1502 u32 sq_gpr_resource_mgmt_2 = 0;
1503 u32 sq_thread_resource_mgmt = 0;
1504 u32 sq_stack_resource_mgmt_1 = 0;
1505 u32 sq_stack_resource_mgmt_2 = 0;
1506
1507 /* FIXME: implement */
1508 switch (rdev->family) {
1509 case CHIP_R600:
1510 rdev->config.r600.max_pipes = 4;
1511 rdev->config.r600.max_tile_pipes = 8;
1512 rdev->config.r600.max_simds = 4;
1513 rdev->config.r600.max_backends = 4;
1514 rdev->config.r600.max_gprs = 256;
1515 rdev->config.r600.max_threads = 192;
1516 rdev->config.r600.max_stack_entries = 256;
1517 rdev->config.r600.max_hw_contexts = 8;
1518 rdev->config.r600.max_gs_threads = 16;
1519 rdev->config.r600.sx_max_export_size = 128;
1520 rdev->config.r600.sx_max_export_pos_size = 16;
1521 rdev->config.r600.sx_max_export_smx_size = 128;
1522 rdev->config.r600.sq_num_cf_insts = 2;
1523 break;
1524 case CHIP_RV630:
1525 case CHIP_RV635:
1526 rdev->config.r600.max_pipes = 2;
1527 rdev->config.r600.max_tile_pipes = 2;
1528 rdev->config.r600.max_simds = 3;
1529 rdev->config.r600.max_backends = 1;
1530 rdev->config.r600.max_gprs = 128;
1531 rdev->config.r600.max_threads = 192;
1532 rdev->config.r600.max_stack_entries = 128;
1533 rdev->config.r600.max_hw_contexts = 8;
1534 rdev->config.r600.max_gs_threads = 4;
1535 rdev->config.r600.sx_max_export_size = 128;
1536 rdev->config.r600.sx_max_export_pos_size = 16;
1537 rdev->config.r600.sx_max_export_smx_size = 128;
1538 rdev->config.r600.sq_num_cf_insts = 2;
1539 break;
1540 case CHIP_RV610:
1541 case CHIP_RV620:
1542 case CHIP_RS780:
1543 case CHIP_RS880:
1544 rdev->config.r600.max_pipes = 1;
1545 rdev->config.r600.max_tile_pipes = 1;
1546 rdev->config.r600.max_simds = 2;
1547 rdev->config.r600.max_backends = 1;
1548 rdev->config.r600.max_gprs = 128;
1549 rdev->config.r600.max_threads = 192;
1550 rdev->config.r600.max_stack_entries = 128;
1551 rdev->config.r600.max_hw_contexts = 4;
1552 rdev->config.r600.max_gs_threads = 4;
1553 rdev->config.r600.sx_max_export_size = 128;
1554 rdev->config.r600.sx_max_export_pos_size = 16;
1555 rdev->config.r600.sx_max_export_smx_size = 128;
1556 rdev->config.r600.sq_num_cf_insts = 1;
1557 break;
1558 case CHIP_RV670:
1559 rdev->config.r600.max_pipes = 4;
1560 rdev->config.r600.max_tile_pipes = 4;
1561 rdev->config.r600.max_simds = 4;
1562 rdev->config.r600.max_backends = 4;
1563 rdev->config.r600.max_gprs = 192;
1564 rdev->config.r600.max_threads = 192;
1565 rdev->config.r600.max_stack_entries = 256;
1566 rdev->config.r600.max_hw_contexts = 8;
1567 rdev->config.r600.max_gs_threads = 16;
1568 rdev->config.r600.sx_max_export_size = 128;
1569 rdev->config.r600.sx_max_export_pos_size = 16;
1570 rdev->config.r600.sx_max_export_smx_size = 128;
1571 rdev->config.r600.sq_num_cf_insts = 2;
1572 break;
1573 default:
1574 break;
1575 }
1576
1577 /* Initialize HDP */
1578 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1579 WREG32((0x2c14 + j), 0x00000000);
1580 WREG32((0x2c18 + j), 0x00000000);
1581 WREG32((0x2c1c + j), 0x00000000);
1582 WREG32((0x2c20 + j), 0x00000000);
1583 WREG32((0x2c24 + j), 0x00000000);
1584 }
1585
1586 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1587
1588 /* Setup tiling */
1589 tiling_config = 0;
1590 ramcfg = RREG32(RAMCFG);
1591 switch (rdev->config.r600.max_tile_pipes) {
1592 case 1:
1593 tiling_config |= PIPE_TILING(0);
1594 break;
1595 case 2:
1596 tiling_config |= PIPE_TILING(1);
1597 break;
1598 case 4:
1599 tiling_config |= PIPE_TILING(2);
1600 break;
1601 case 8:
1602 tiling_config |= PIPE_TILING(3);
1603 break;
1604 default:
1605 break;
1606 }
d03f5d59 1607 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
961fb597 1608 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
3ce0a23d 1609 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
881fe6c1
AD		 1610 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1611 if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1612 rdev->config.r600.tiling_group_size = 512;
1613 else
1614 rdev->config.r600.tiling_group_size = 256;
3ce0a23d
JG		 1615 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1616 if (tmp > 3) {
1617 tiling_config |= ROW_TILING(3);
1618 tiling_config |= SAMPLE_SPLIT(3);
1619 } else {
1620 tiling_config |= ROW_TILING(tmp);
1621 tiling_config |= SAMPLE_SPLIT(tmp);
1622 }
1623 tiling_config |= BANK_SWAPS(1);
d03f5d59
AD		 1624
1625 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1626 cc_rb_backend_disable |=
1627 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1628
1629 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1630 cc_gc_shader_pipe_config |=
1631 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1632 cc_gc_shader_pipe_config |=
1633 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1634
1635 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1636 (R6XX_MAX_BACKENDS -
1637 r600_count_pipe_bits((cc_rb_backend_disable &
1638 R6XX_MAX_BACKENDS_MASK) >> 16)),
1639 (cc_rb_backend_disable >> 16));
e7aeeba6 1640 rdev->config.r600.tile_config = tiling_config;
e55b9422 1641 rdev->config.r600.backend_map = backend_map;
d03f5d59 1642 tiling_config |= BACKEND_MAP(backend_map);
3ce0a23d
JG		 1643 WREG32(GB_TILING_CONFIG, tiling_config);
1644 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1645 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1646
3ce0a23d 1647 /* Setup pipes */
d03f5d59
AD		 1648 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1649 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
f867c60d 1650 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
3ce0a23d 1651
d03f5d59 1652 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 1653 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1654 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1655
1656 /* Setup some CP states */
1657 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1658 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1659
1660 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1661 SYNC_WALKER | SYNC_ALIGNER));
1662 /* Setup various GPU states */
1663 if (rdev->family == CHIP_RV670)
1664 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1665
1666 tmp = RREG32(SX_DEBUG_1);
1667 tmp |= SMX_EVENT_RELEASE;
1668 if ((rdev->family > CHIP_R600))
1669 tmp |= ENABLE_NEW_SMX_ADDRESS;
1670 WREG32(SX_DEBUG_1, tmp);
1671
1672 if (((rdev->family) == CHIP_R600) ||
1673 ((rdev->family) == CHIP_RV630) ||
1674 ((rdev->family) == CHIP_RV610) ||
1675 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1676 ((rdev->family) == CHIP_RS780) ||
1677 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1678 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1679 } else {
1680 WREG32(DB_DEBUG, 0);
1681 }
1682 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1683 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1684
1685 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1686 WREG32(VGT_NUM_INSTANCES, 0);
1687
1688 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1689 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1690
1691 tmp = RREG32(SQ_MS_FIFO_SIZES);
1692 if (((rdev->family) == CHIP_RV610) ||
1693 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1694 ((rdev->family) == CHIP_RS780) ||
1695 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1696 tmp = (CACHE_FIFO_SIZE(0xa) |
1697 FETCH_FIFO_HIWATER(0xa) |
1698 DONE_FIFO_HIWATER(0xe0) |
1699 ALU_UPDATE_FIFO_HIWATER(0x8));
1700 } else if (((rdev->family) == CHIP_R600) ||
1701 ((rdev->family) == CHIP_RV630)) {
1702 tmp &= ~DONE_FIFO_HIWATER(0xff);
1703 tmp |= DONE_FIFO_HIWATER(0x4);
1704 }
1705 WREG32(SQ_MS_FIFO_SIZES, tmp);
1706
1707 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1708 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1709 */
1710 sq_config = RREG32(SQ_CONFIG);
1711 sq_config &= ~(PS_PRIO(3) |
1712 VS_PRIO(3) |
1713 GS_PRIO(3) |
1714 ES_PRIO(3));
1715 sq_config |= (DX9_CONSTS |
1716 VC_ENABLE |
1717 PS_PRIO(0) |
1718 VS_PRIO(1) |
1719 GS_PRIO(2) |
1720 ES_PRIO(3));
1721
1722 if ((rdev->family) == CHIP_R600) {
1723 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1724 NUM_VS_GPRS(124) |
1725 NUM_CLAUSE_TEMP_GPRS(4));
1726 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1727 NUM_ES_GPRS(0));
1728 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1729 NUM_VS_THREADS(48) |
1730 NUM_GS_THREADS(4) |
1731 NUM_ES_THREADS(4));
1732 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1733 NUM_VS_STACK_ENTRIES(128));
1734 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1735 NUM_ES_STACK_ENTRIES(0));
1736 } else if (((rdev->family) == CHIP_RV610) ||
1737 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1738 ((rdev->family) == CHIP_RS780) ||
1739 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1740 /* no vertex cache */
1741 sq_config &= ~VC_ENABLE;
1742
1743 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1744 NUM_VS_GPRS(44) |
1745 NUM_CLAUSE_TEMP_GPRS(2));
1746 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1747 NUM_ES_GPRS(17));
1748 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1749 NUM_VS_THREADS(78) |
1750 NUM_GS_THREADS(4) |
1751 NUM_ES_THREADS(31));
1752 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1753 NUM_VS_STACK_ENTRIES(40));
1754 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1755 NUM_ES_STACK_ENTRIES(16));
1756 } else if (((rdev->family) == CHIP_RV630) ||
1757 ((rdev->family) == CHIP_RV635)) {
1758 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1759 NUM_VS_GPRS(44) |
1760 NUM_CLAUSE_TEMP_GPRS(2));
1761 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1762 NUM_ES_GPRS(18));
1763 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1764 NUM_VS_THREADS(78) |
1765 NUM_GS_THREADS(4) |
1766 NUM_ES_THREADS(31));
1767 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1768 NUM_VS_STACK_ENTRIES(40));
1769 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1770 NUM_ES_STACK_ENTRIES(16));
1771 } else if ((rdev->family) == CHIP_RV670) {
1772 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1773 NUM_VS_GPRS(44) |
1774 NUM_CLAUSE_TEMP_GPRS(2));
1775 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1776 NUM_ES_GPRS(17));
1777 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1778 NUM_VS_THREADS(78) |
1779 NUM_GS_THREADS(4) |
1780 NUM_ES_THREADS(31));
1781 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1782 NUM_VS_STACK_ENTRIES(64));
1783 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1784 NUM_ES_STACK_ENTRIES(64));
1785 }
1786
1787 WREG32(SQ_CONFIG, sq_config);
1788 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1789 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1790 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1791 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1792 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1793
1794 if (((rdev->family) == CHIP_RV610) ||
1795 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1796 ((rdev->family) == CHIP_RS780) ||
1797 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1798 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1799 } else {
1800 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1801 }
1802
1803 /* More default values. 2D/3D driver should adjust as needed */
1804 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1805 S1_X(0x4) | S1_Y(0xc)));
1806 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1807 S1_X(0x2) | S1_Y(0x2) |
1808 S2_X(0xa) | S2_Y(0x6) |
1809 S3_X(0x6) | S3_Y(0xa)));
1810 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1811 S1_X(0x4) | S1_Y(0xc) |
1812 S2_X(0x1) | S2_Y(0x6) |
1813 S3_X(0xa) | S3_Y(0xe)));
1814 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1815 S5_X(0x0) | S5_Y(0x0) |
1816 S6_X(0xb) | S6_Y(0x4) |
1817 S7_X(0x7) | S7_Y(0x8)));
1818
1819 WREG32(VGT_STRMOUT_EN, 0);
1820 tmp = rdev->config.r600.max_pipes * 16;
1821 switch (rdev->family) {
1822 case CHIP_RV610:
3ce0a23d 1823 case CHIP_RV620:
ee59f2b4
AD		 1824 case CHIP_RS780:
1825 case CHIP_RS880:
3ce0a23d
JG		 1826 tmp += 32;
1827 break;
1828 case CHIP_RV670:
1829 tmp += 128;
1830 break;
1831 default:
1832 break;
1833 }
1834 if (tmp > 256) {
1835 tmp = 256;
1836 }
1837 WREG32(VGT_ES_PER_GS, 128);
1838 WREG32(VGT_GS_PER_ES, tmp);
1839 WREG32(VGT_GS_PER_VS, 2);
1840 WREG32(VGT_GS_VERTEX_REUSE, 16);
1841
1842 /* more default values. 2D/3D driver should adjust as needed */
1843 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1844 WREG32(VGT_STRMOUT_EN, 0);
1845 WREG32(SX_MISC, 0);
1846 WREG32(PA_SC_MODE_CNTL, 0);
1847 WREG32(PA_SC_AA_CONFIG, 0);
1848 WREG32(PA_SC_LINE_STIPPLE, 0);
1849 WREG32(SPI_INPUT_Z, 0);
1850 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1851 WREG32(CB_COLOR7_FRAG, 0);
1852
1853 /* Clear render buffer base addresses */
1854 WREG32(CB_COLOR0_BASE, 0);
1855 WREG32(CB_COLOR1_BASE, 0);
1856 WREG32(CB_COLOR2_BASE, 0);
1857 WREG32(CB_COLOR3_BASE, 0);
1858 WREG32(CB_COLOR4_BASE, 0);
1859 WREG32(CB_COLOR5_BASE, 0);
1860 WREG32(CB_COLOR6_BASE, 0);
1861 WREG32(CB_COLOR7_BASE, 0);
1862 WREG32(CB_COLOR7_FRAG, 0);
1863
1864 switch (rdev->family) {
1865 case CHIP_RV610:
3ce0a23d 1866 case CHIP_RV620:
ee59f2b4
AD		 1867 case CHIP_RS780:
1868 case CHIP_RS880:
3ce0a23d
JG		 1869 tmp = TC_L2_SIZE(8);
1870 break;
1871 case CHIP_RV630:
1872 case CHIP_RV635:
1873 tmp = TC_L2_SIZE(4);
1874 break;
1875 case CHIP_R600:
1876 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1877 break;
1878 default:
1879 tmp = TC_L2_SIZE(0);
1880 break;
1881 }
1882 WREG32(TC_CNTL, tmp);
1883
1884 tmp = RREG32(HDP_HOST_PATH_CNTL);
1885 WREG32(HDP_HOST_PATH_CNTL, tmp);
1886
1887 tmp = RREG32(ARB_POP);
1888 tmp |= ENABLE_TC128;
1889 WREG32(ARB_POP, tmp);
1890
1891 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1892 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1893 NUM_CLIP_SEQ(3)));
1894 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1895}
1896
1897
771fe6b9
JG		 1898/*
1899 * Indirect registers accessor
1900 */
3ce0a23d
JG		 1901u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1902{
1903 u32 r;
1904
1905 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1906 (void)RREG32(PCIE_PORT_INDEX);
1907 r = RREG32(PCIE_PORT_DATA);
1908 return r;
1909}
1910
1911void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1912{
1913 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1914 (void)RREG32(PCIE_PORT_INDEX);
1915 WREG32(PCIE_PORT_DATA, (v));
1916 (void)RREG32(PCIE_PORT_DATA);
1917}
1918
3ce0a23d
JG		 1919/*
1920 * CP & Ring
1921 */
1922void r600_cp_stop(struct radeon_device *rdev)
1923{
53595338 1924 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3ce0a23d 1925 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
724c80e1 1926 WREG32(SCRATCH_UMSK, 0);
3ce0a23d
JG		 1927}
1928
d8f60cfc 1929int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d
JG		 1930{
1931 struct platform_device *pdev;
1932 const char *chip_name;
d8f60cfc
AD		 1933 const char *rlc_chip_name;
1934 size_t pfp_req_size, me_req_size, rlc_req_size;
3ce0a23d
JG		 1935 char fw_name[30];
1936 int err;
1937
1938 DRM_DEBUG("\n");
1939
1940 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1941 err = IS_ERR(pdev);
1942 if (err) {
1943 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1944 return -EINVAL;
1945 }
1946
1947 switch (rdev->family) {
d8f60cfc
AD		 1948 case CHIP_R600:
1949 chip_name = "R600";
1950 rlc_chip_name = "R600";
1951 break;
1952 case CHIP_RV610:
1953 chip_name = "RV610";
1954 rlc_chip_name = "R600";
1955 break;
1956 case CHIP_RV630:
1957 chip_name = "RV630";
1958 rlc_chip_name = "R600";
1959 break;
1960 case CHIP_RV620:
1961 chip_name = "RV620";
1962 rlc_chip_name = "R600";
1963 break;
1964 case CHIP_RV635:
1965 chip_name = "RV635";
1966 rlc_chip_name = "R600";
1967 break;
1968 case CHIP_RV670:
1969 chip_name = "RV670";
1970 rlc_chip_name = "R600";
1971 break;
3ce0a23d 1972 case CHIP_RS780:
d8f60cfc
AD		 1973 case CHIP_RS880:
1974 chip_name = "RS780";
1975 rlc_chip_name = "R600";
1976 break;
1977 case CHIP_RV770:
1978 chip_name = "RV770";
1979 rlc_chip_name = "R700";
1980 break;
3ce0a23d 1981 case CHIP_RV730:
d8f60cfc
AD		 1982 case CHIP_RV740:
1983 chip_name = "RV730";
1984 rlc_chip_name = "R700";
1985 break;
1986 case CHIP_RV710:
1987 chip_name = "RV710";
1988 rlc_chip_name = "R700";
1989 break;
fe251e2f
AD		 1990 case CHIP_CEDAR:
1991 chip_name = "CEDAR";
45f9a39b 1992 rlc_chip_name = "CEDAR";
fe251e2f
AD		 1993 break;
1994 case CHIP_REDWOOD:
1995 chip_name = "REDWOOD";
45f9a39b 1996 rlc_chip_name = "REDWOOD";
fe251e2f
AD		 1997 break;
1998 case CHIP_JUNIPER:
1999 chip_name = "JUNIPER";
45f9a39b 2000 rlc_chip_name = "JUNIPER";
fe251e2f
AD		 2001 break;
2002 case CHIP_CYPRESS:
2003 case CHIP_HEMLOCK:
2004 chip_name = "CYPRESS";
45f9a39b 2005 rlc_chip_name = "CYPRESS";
fe251e2f 2006 break;
439bd6cd
AD		 2007 case CHIP_PALM:
2008 chip_name = "PALM";
2009 rlc_chip_name = "SUMO";
2010 break;
d5c5a72f
AD		 2011 case CHIP_SUMO:
2012 chip_name = "SUMO";
2013 rlc_chip_name = "SUMO";
2014 break;
2015 case CHIP_SUMO2:
2016 chip_name = "SUMO2";
2017 rlc_chip_name = "SUMO";
2018 break;
3ce0a23d
JG		 2019 default: BUG();
2020 }
2021
fe251e2f
AD		 2022 if (rdev->family >= CHIP_CEDAR) {
2023 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2024 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
45f9a39b 2025 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
fe251e2f 2026 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2027 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2028 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 2029 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2030 } else {
2031 pfp_req_size = PFP_UCODE_SIZE * 4;
2032 me_req_size = PM4_UCODE_SIZE * 12;
d8f60cfc 2033 rlc_req_size = RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2034 }
2035
d8f60cfc 2036 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 2037
2038 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2039 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2040 if (err)
2041 goto out;
2042 if (rdev->pfp_fw->size != pfp_req_size) {
2043 printk(KERN_ERR
2044 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2045 rdev->pfp_fw->size, fw_name);
2046 err = -EINVAL;
2047 goto out;
2048 }
2049
2050 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2051 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2052 if (err)
2053 goto out;
2054 if (rdev->me_fw->size != me_req_size) {
2055 printk(KERN_ERR
2056 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2057 rdev->me_fw->size, fw_name);
2058 err = -EINVAL;
2059 }
d8f60cfc
AD		 2060
2061 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2062 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2063 if (err)
2064 goto out;
2065 if (rdev->rlc_fw->size != rlc_req_size) {
2066 printk(KERN_ERR
2067 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2068 rdev->rlc_fw->size, fw_name);
2069 err = -EINVAL;
2070 }
2071
3ce0a23d
JG		 2072out:
2073 platform_device_unregister(pdev);
2074
2075 if (err) {
2076 if (err != -EINVAL)
2077 printk(KERN_ERR
2078 "r600_cp: Failed to load firmware \"%s\"\n",
2079 fw_name);
2080 release_firmware(rdev->pfp_fw);
2081 rdev->pfp_fw = NULL;
2082 release_firmware(rdev->me_fw);
2083 rdev->me_fw = NULL;
d8f60cfc
AD		 2084 release_firmware(rdev->rlc_fw);
2085 rdev->rlc_fw = NULL;
3ce0a23d
JG		 2086 }
2087 return err;
2088}
2089
2090static int r600_cp_load_microcode(struct radeon_device *rdev)
2091{
2092 const __be32 *fw_data;
2093 int i;
2094
2095 if (!rdev->me_fw || !rdev->pfp_fw)
2096 return -EINVAL;
2097
2098 r600_cp_stop(rdev);
2099
4eace7fd
CC		 2100 WREG32(CP_RB_CNTL,
2101#ifdef __BIG_ENDIAN
2102 BUF_SWAP_32BIT |
2103#endif
2104 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
3ce0a23d
JG		 2105
2106 /* Reset cp */
2107 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2108 RREG32(GRBM_SOFT_RESET);
2109 mdelay(15);
2110 WREG32(GRBM_SOFT_RESET, 0);
2111
2112 WREG32(CP_ME_RAM_WADDR, 0);
2113
2114 fw_data = (const __be32 *)rdev->me_fw->data;
2115 WREG32(CP_ME_RAM_WADDR, 0);
2116 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2117 WREG32(CP_ME_RAM_DATA,
2118 be32_to_cpup(fw_data++));
2119
2120 fw_data = (const __be32 *)rdev->pfp_fw->data;
2121 WREG32(CP_PFP_UCODE_ADDR, 0);
2122 for (i = 0; i < PFP_UCODE_SIZE; i++)
2123 WREG32(CP_PFP_UCODE_DATA,
2124 be32_to_cpup(fw_data++));
2125
2126 WREG32(CP_PFP_UCODE_ADDR, 0);
2127 WREG32(CP_ME_RAM_WADDR, 0);
2128 WREG32(CP_ME_RAM_RADDR, 0);
2129 return 0;
2130}
2131
2132int r600_cp_start(struct radeon_device *rdev)
2133{
e32eb50d 2134 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 2135 int r;
2136 uint32_t cp_me;
2137
e32eb50d 2138 r = radeon_ring_lock(rdev, ring, 7);
3ce0a23d
JG		 2139 if (r) {
2140 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2141 return r;
2142 }
e32eb50d
CK		 2143 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2144 radeon_ring_write(ring, 0x1);
7e7b41d2 2145 if (rdev->family >= CHIP_RV770) {
e32eb50d
CK		 2146 radeon_ring_write(ring, 0x0);
2147 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
fe251e2f 2148 } else {
e32eb50d
CK		 2149 radeon_ring_write(ring, 0x3);
2150 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
3ce0a23d 2151 }
e32eb50d
CK		 2152 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2153 radeon_ring_write(ring, 0);
2154 radeon_ring_write(ring, 0);
2155 radeon_ring_unlock_commit(rdev, ring);
3ce0a23d
JG		 2156
2157 cp_me = 0xff;
2158 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2159 return 0;
2160}
2161
2162int r600_cp_resume(struct radeon_device *rdev)
2163{
e32eb50d 2164 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 2165 u32 tmp;
2166 u32 rb_bufsz;
2167 int r;
2168
2169 /* Reset cp */
2170 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2171 RREG32(GRBM_SOFT_RESET);
2172 mdelay(15);
2173 WREG32(GRBM_SOFT_RESET, 0);
2174
2175 /* Set ring buffer size */
e32eb50d 2176 rb_bufsz = drm_order(ring->ring_size / 8);
724c80e1 2177 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 2178#ifdef __BIG_ENDIAN
d6f28938 2179 tmp |= BUF_SWAP_32BIT;
3ce0a23d 2180#endif
d6f28938 2181 WREG32(CP_RB_CNTL, tmp);
15d3332f 2182 WREG32(CP_SEM_WAIT_TIMER, 0x0);
3ce0a23d
JG		 2183
2184 /* Set the write pointer delay */
2185 WREG32(CP_RB_WPTR_DELAY, 0);
2186
2187 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 2188 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2189 WREG32(CP_RB_RPTR_WR, 0);
e32eb50d
CK		 2190 ring->wptr = 0;
2191 WREG32(CP_RB_WPTR, ring->wptr);
724c80e1
AD		 2192
2193 /* set the wb address whether it's enabled or not */
4eace7fd 2194 WREG32(CP_RB_RPTR_ADDR,
4eace7fd 2195 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 2196 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2197 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2198
2199 if (rdev->wb.enabled)
2200 WREG32(SCRATCH_UMSK, 0xff);
2201 else {
2202 tmp |= RB_NO_UPDATE;
2203 WREG32(SCRATCH_UMSK, 0);
2204 }
2205
3ce0a23d
JG		 2206 mdelay(1);
2207 WREG32(CP_RB_CNTL, tmp);
2208
e32eb50d 2209 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
3ce0a23d
JG		 2210 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2211
e32eb50d 2212 ring->rptr = RREG32(CP_RB_RPTR);
3ce0a23d
JG		 2213
2214 r600_cp_start(rdev);
e32eb50d 2215 ring->ready = true;
f712812e 2216 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
3ce0a23d 2217 if (r) {
e32eb50d 2218 ring->ready = false;
3ce0a23d
JG		 2219 return r;
2220 }
2221 return 0;
2222}
2223
e32eb50d 2224void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
3ce0a23d
JG		 2225{
2226 u32 rb_bufsz;
2227
2228 /* Align ring size */
2229 rb_bufsz = drm_order(ring_size / 8);
2230 ring_size = (1 << (rb_bufsz + 1)) * 4;
e32eb50d
CK		 2231 ring->ring_size = ring_size;
2232 ring->align_mask = 16 - 1;
3ce0a23d
JG		 2233}
2234
655efd3d
JG		 2235void r600_cp_fini(struct radeon_device *rdev)
2236{
2237 r600_cp_stop(rdev);
e32eb50d 2238 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
655efd3d
JG		 2239}
2240
3ce0a23d
JG		 2241
2242/*
2243 * GPU scratch registers helpers function.
2244 */
2245void r600_scratch_init(struct radeon_device *rdev)
2246{
2247 int i;
2248
2249 rdev->scratch.num_reg = 7;
724c80e1 2250 rdev->scratch.reg_base = SCRATCH_REG0;
3ce0a23d
JG		 2251 for (i = 0; i < rdev->scratch.num_reg; i++) {
2252 rdev->scratch.free[i] = true;
724c80e1 2253 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3ce0a23d
JG		 2254 }
2255}
2256
e32eb50d 2257int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d
JG		 2258{
2259 uint32_t scratch;
2260 uint32_t tmp = 0;
e32eb50d 2261 unsigned i, ridx = radeon_ring_index(rdev, ring);
3ce0a23d
JG		 2262 int r;
2263
2264 r = radeon_scratch_get(rdev, &scratch);
2265 if (r) {
2266 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2267 return r;
2268 }
2269 WREG32(scratch, 0xCAFEDEAD);
e32eb50d 2270 r = radeon_ring_lock(rdev, ring, 3);
3ce0a23d 2271 if (r) {
bf852799 2272 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ridx, r);
3ce0a23d
JG		 2273 radeon_scratch_free(rdev, scratch);
2274 return r;
2275 }
e32eb50d
CK		 2276 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2277 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2278 radeon_ring_write(ring, 0xDEADBEEF);
2279 radeon_ring_unlock_commit(rdev, ring);
3ce0a23d
JG		 2280 for (i = 0; i < rdev->usec_timeout; i++) {
2281 tmp = RREG32(scratch);
2282 if (tmp == 0xDEADBEEF)
2283 break;
2284 DRM_UDELAY(1);
2285 }
2286 if (i < rdev->usec_timeout) {
bf852799 2287 DRM_INFO("ring test on %d succeeded in %d usecs\n", ridx, i);
3ce0a23d 2288 } else {
bf852799
CK		 2289 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2290 ridx, scratch, tmp);
3ce0a23d
JG		 2291 r = -EINVAL;
2292 }
2293 radeon_scratch_free(rdev, scratch);
2294 return r;
2295}
2296
3ce0a23d
JG		 2297void r600_fence_ring_emit(struct radeon_device *rdev,
2298 struct radeon_fence *fence)
2299{
e32eb50d 2300 struct radeon_ring *ring = &rdev->ring[fence->ring];
7b1f2485 2301
d0f8a854 2302 if (rdev->wb.use_event) {
30eb77f4 2303 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
77b1bad4 2304 /* flush read cache over gart */
e32eb50d
CK		 2305 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2306 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2307 PACKET3_VC_ACTION_ENA |
2308 PACKET3_SH_ACTION_ENA);
2309 radeon_ring_write(ring, 0xFFFFFFFF);
2310 radeon_ring_write(ring, 0);
2311 radeon_ring_write(ring, 10); /* poll interval */
d0f8a854 2312 /* EVENT_WRITE_EOP - flush caches, send int */
e32eb50d
CK		 2313 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2314 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2315 radeon_ring_write(ring, addr & 0xffffffff);
2316 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2317 radeon_ring_write(ring, fence->seq);
2318 radeon_ring_write(ring, 0);
d0f8a854 2319 } else {
77b1bad4 2320 /* flush read cache over gart */
e32eb50d
CK		 2321 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2322 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2323 PACKET3_VC_ACTION_ENA |
2324 PACKET3_SH_ACTION_ENA);
2325 radeon_ring_write(ring, 0xFFFFFFFF);
2326 radeon_ring_write(ring, 0);
2327 radeon_ring_write(ring, 10); /* poll interval */
2328 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2329 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
d0f8a854 2330 /* wait for 3D idle clean */
e32eb50d
CK		 2331 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2332 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2333 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
d0f8a854 2334 /* Emit fence sequence & fire IRQ */
e32eb50d
CK		 2335 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2336 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2337 radeon_ring_write(ring, fence->seq);
d0f8a854 2338 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
e32eb50d
CK		 2339 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2340 radeon_ring_write(ring, RB_INT_STAT);
d0f8a854 2341 }
3ce0a23d
JG		 2342}
2343
15d3332f 2344void r600_semaphore_ring_emit(struct radeon_device *rdev,
e32eb50d 2345 struct radeon_ring *ring,
15d3332f 2346 struct radeon_semaphore *semaphore,
7b1f2485 2347 bool emit_wait)
15d3332f
CK		 2348{
2349 uint64_t addr = semaphore->gpu_addr;
2350 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2351
0be70439
CK		 2352 if (rdev->family < CHIP_CAYMAN)
2353 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2354
e32eb50d
CK		 2355 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2356 radeon_ring_write(ring, addr & 0xffffffff);
2357 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
15d3332f
CK		 2358}
2359
3ce0a23d 2360int r600_copy_blit(struct radeon_device *rdev,
003cefe0
AD		 2361 uint64_t src_offset,
2362 uint64_t dst_offset,
2363 unsigned num_gpu_pages,
2364 struct radeon_fence *fence)
3ce0a23d 2365{
f237750f 2366 struct radeon_sa_bo *vb = NULL;
ff82f052
JG		 2367 int r;
2368
f237750f 2369 r = r600_blit_prepare_copy(rdev, num_gpu_pages, &vb);
ff82f052 2370 if (r) {
ff82f052
JG		 2371 return r;
2372 }
f237750f
CK		 2373 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb);
2374 r600_blit_done_copy(rdev, fence, vb);
3ce0a23d
JG		 2375 return 0;
2376}
2377
6ddddfe7
AD		 2378void r600_blit_suspend(struct radeon_device *rdev)
2379{
2380 int r;
2381
2382 /* unpin shaders bo */
2383 if (rdev->r600_blit.shader_obj) {
2384 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2385 if (!r) {
2386 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2387 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2388 }
2389 }
2390}
2391
3ce0a23d
JG		 2392int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2393 uint32_t tiling_flags, uint32_t pitch,
2394 uint32_t offset, uint32_t obj_size)
2395{
2396 /* FIXME: implement */
2397 return 0;
2398}
2399
2400void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2401{
2402 /* FIXME: implement */
2403}
2404
fc30b8ef 2405int r600_startup(struct radeon_device *rdev)
3ce0a23d 2406{
e32eb50d 2407 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 2408 int r;
2409
9e46a48d
AD		 2410 /* enable pcie gen2 link */
2411 r600_pcie_gen2_enable(rdev);
2412
779720a3
AD		 2413 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2414 r = r600_init_microcode(rdev);
2415 if (r) {
2416 DRM_ERROR("Failed to load firmware!\n");
2417 return r;
2418 }
2419 }
2420
16cdf04d
AD		 2421 r = r600_vram_scratch_init(rdev);
2422 if (r)
2423 return r;
2424
a3c1945a 2425 r600_mc_program(rdev);
1a029b76
JG		 2426 if (rdev->flags & RADEON_IS_AGP) {
2427 r600_agp_enable(rdev);
2428 } else {
2429 r = r600_pcie_gart_enable(rdev);
2430 if (r)
2431 return r;
2432 }
3ce0a23d 2433 r600_gpu_init(rdev);
c38c7b64
JG		 2434 r = r600_blit_init(rdev);
2435 if (r) {
2436 r600_blit_fini(rdev);
27cd7769 2437 rdev->asic->copy.copy = NULL;
c38c7b64
JG		 2438 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2439 }
b70d6bb3 2440
724c80e1
AD		 2441 /* allocate wb buffer */
2442 r = radeon_wb_init(rdev);
2443 if (r)
2444 return r;
2445
30eb77f4
JG		 2446 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2447 if (r) {
2448 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2449 return r;
2450 }
2451
d8f60cfc 2452 /* Enable IRQ */
d8f60cfc
AD		 2453 r = r600_irq_init(rdev);
2454 if (r) {
2455 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2456 radeon_irq_kms_fini(rdev);
2457 return r;
2458 }
2459 r600_irq_set(rdev);
2460
e32eb50d 2461 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 2462 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
2463 0, 0xfffff, RADEON_CP_PACKET2);
5596a9db 2464
3ce0a23d
JG		 2465 if (r)
2466 return r;
2467 r = r600_cp_load_microcode(rdev);
2468 if (r)
2469 return r;
2470 r = r600_cp_resume(rdev);
2471 if (r)
2472 return r;
724c80e1 2473
b15ba512
JG		 2474 r = radeon_ib_pool_start(rdev);
2475 if (r)
2476 return r;
2477
7bd560e8
CK		 2478 r = radeon_ib_ring_tests(rdev);
2479 if (r)
b15ba512 2480 return r;
b15ba512 2481
3ce0a23d
JG		 2482 return 0;
2483}
2484
28d52043
DA		 2485void r600_vga_set_state(struct radeon_device *rdev, bool state)
2486{
2487 uint32_t temp;
2488
2489 temp = RREG32(CONFIG_CNTL);
2490 if (state == false) {
2491 temp &= ~(1<<0);
2492 temp |= (1<<1);
2493 } else {
2494 temp &= ~(1<<1);
2495 }
2496 WREG32(CONFIG_CNTL, temp);
2497}
2498
fc30b8ef
DA		 2499int r600_resume(struct radeon_device *rdev)
2500{
2501 int r;
2502
1a029b76
JG		 2503 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2504 * posting will perform necessary task to bring back GPU into good
2505 * shape.
2506 */
fc30b8ef 2507 /* post card */
e7d40b9a 2508 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef 2509
b15ba512 2510 rdev->accel_working = true;
fc30b8ef
DA		 2511 r = r600_startup(rdev);
2512 if (r) {
2513 DRM_ERROR("r600 startup failed on resume\n");
6b7746e8 2514 rdev->accel_working = false;
fc30b8ef
DA		 2515 return r;
2516 }
2517
38fd2c6f
RM		 2518 r = r600_audio_init(rdev);
2519 if (r) {
2520 DRM_ERROR("radeon: audio resume failed\n");
2521 return r;
2522 }
2523
fc30b8ef
DA		 2524 return r;
2525}
2526
3ce0a23d
JG		 2527int r600_suspend(struct radeon_device *rdev)
2528{
38fd2c6f 2529 r600_audio_fini(rdev);
b15ba512
JG		 2530 radeon_ib_pool_suspend(rdev);
2531 r600_blit_suspend(rdev);
3ce0a23d
JG		 2532 /* FIXME: we should wait for ring to be empty */
2533 r600_cp_stop(rdev);
e32eb50d 2534 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
0c45249f 2535 r600_irq_suspend(rdev);
724c80e1 2536 radeon_wb_disable(rdev);
4aac0473 2537 r600_pcie_gart_disable(rdev);
6ddddfe7 2538
3ce0a23d
JG		 2539 return 0;
2540}
2541
2542/* Plan is to move initialization in that function and use
2543 * helper function so that radeon_device_init pretty much
2544 * do nothing more than calling asic specific function. This
2545 * should also allow to remove a bunch of callback function
2546 * like vram_info.
2547 */
2548int r600_init(struct radeon_device *rdev)
771fe6b9 2549{
3ce0a23d 2550 int r;
771fe6b9 2551
3ce0a23d
JG		 2552 if (r600_debugfs_mc_info_init(rdev)) {
2553 DRM_ERROR("Failed to register debugfs file for mc !\n");
2554 }
2555 /* This don't do much */
2556 r = radeon_gem_init(rdev);
2557 if (r)
2558 return r;
2559 /* Read BIOS */
2560 if (!radeon_get_bios(rdev)) {
2561 if (ASIC_IS_AVIVO(rdev))
2562 return -EINVAL;
2563 }
2564 /* Must be an ATOMBIOS */
e7d40b9a
JG		 2565 if (!rdev->is_atom_bios) {
2566 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 2567 return -EINVAL;
e7d40b9a 2568 }
3ce0a23d
JG		 2569 r = radeon_atombios_init(rdev);
2570 if (r)
2571 return r;
2572 /* Post card if necessary */
fd909c37 2573 if (!radeon_card_posted(rdev)) {
72542d77
DA		 2574 if (!rdev->bios) {
2575 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2576 return -EINVAL;
2577 }
3ce0a23d
JG		 2578 DRM_INFO("GPU not posted. posting now...\n");
2579 atom_asic_init(rdev->mode_info.atom_context);
2580 }
2581 /* Initialize scratch registers */
2582 r600_scratch_init(rdev);
2583 /* Initialize surface registers */
2584 radeon_surface_init(rdev);
7433874e 2585 /* Initialize clocks */
5e6dde7e 2586 radeon_get_clock_info(rdev->ddev);
3ce0a23d 2587 /* Fence driver */
30eb77f4 2588 r = radeon_fence_driver_init(rdev);
3ce0a23d
JG		 2589 if (r)
2590 return r;
700a0cc0
JG		 2591 if (rdev->flags & RADEON_IS_AGP) {
2592 r = radeon_agp_init(rdev);
2593 if (r)
2594 radeon_agp_disable(rdev);
2595 }
3ce0a23d 2596 r = r600_mc_init(rdev);
b574f251 2597 if (r)
3ce0a23d 2598 return r;
3ce0a23d 2599 /* Memory manager */
4c788679 2600 r = radeon_bo_init(rdev);
3ce0a23d
JG		 2601 if (r)
2602 return r;
d8f60cfc
AD		 2603
2604 r = radeon_irq_kms_init(rdev);
2605 if (r)
2606 return r;
2607
e32eb50d
CK		 2608 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2609 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3ce0a23d 2610
d8f60cfc
AD		 2611 rdev->ih.ring_obj = NULL;
2612 r600_ih_ring_init(rdev, 64 * 1024);
3ce0a23d 2613
4aac0473
JG		 2614 r = r600_pcie_gart_init(rdev);
2615 if (r)
2616 return r;
2617
b15ba512 2618 r = radeon_ib_pool_init(rdev);
779720a3 2619 rdev->accel_working = true;
b15ba512
JG		 2620 if (r) {
2621 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2622 rdev->accel_working = false;
2623 }
2624
fc30b8ef 2625 r = r600_startup(rdev);
3ce0a23d 2626 if (r) {
655efd3d
JG		 2627 dev_err(rdev->dev, "disabling GPU acceleration\n");
2628 r600_cp_fini(rdev);
655efd3d 2629 r600_irq_fini(rdev);
724c80e1 2630 radeon_wb_fini(rdev);
b15ba512 2631 r100_ib_fini(rdev);
655efd3d 2632 radeon_irq_kms_fini(rdev);
75c81298 2633 r600_pcie_gart_fini(rdev);
733289c2 2634 rdev->accel_working = false;
3ce0a23d 2635 }
dafc3bd5
CK		 2636
2637 r = r600_audio_init(rdev);
2638 if (r)
2639 return r; /* TODO error handling */
3ce0a23d
JG		 2640 return 0;
2641}
2642
2643void r600_fini(struct radeon_device *rdev)
2644{
dafc3bd5 2645 r600_audio_fini(rdev);
3ce0a23d 2646 r600_blit_fini(rdev);
655efd3d 2647 r600_cp_fini(rdev);
d8f60cfc 2648 r600_irq_fini(rdev);
724c80e1 2649 radeon_wb_fini(rdev);
b15ba512 2650 r100_ib_fini(rdev);
d8f60cfc 2651 radeon_irq_kms_fini(rdev);
4aac0473 2652 r600_pcie_gart_fini(rdev);
16cdf04d 2653 r600_vram_scratch_fini(rdev);
655efd3d 2654 radeon_agp_fini(rdev);
3ce0a23d
JG		 2655 radeon_gem_fini(rdev);
2656 radeon_fence_driver_fini(rdev);
4c788679 2657 radeon_bo_fini(rdev);
e7d40b9a 2658 radeon_atombios_fini(rdev);
3ce0a23d
JG		 2659 kfree(rdev->bios);
2660 rdev->bios = NULL;
3ce0a23d
JG		 2661}
2662
2663
2664/*
2665 * CS stuff
2666 */
2667void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2668{
e32eb50d 2669 struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
7b1f2485 2670
3ce0a23d 2671 /* FIXME: implement */
e32eb50d
CK		 2672 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2673 radeon_ring_write(ring,
4eace7fd
CC		 2674#ifdef __BIG_ENDIAN
2675 (2 << 0) |
2676#endif
2677 (ib->gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 2678 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
2679 radeon_ring_write(ring, ib->length_dw);
3ce0a23d
JG		 2680}
2681
f712812e 2682int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d
JG		 2683{
2684 struct radeon_ib *ib;
2685 uint32_t scratch;
2686 uint32_t tmp = 0;
2687 unsigned i;
2688 int r;
f712812e 2689 int ring_index = radeon_ring_index(rdev, ring);
3ce0a23d
JG		 2690
2691 r = radeon_scratch_get(rdev, &scratch);
2692 if (r) {
2693 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2694 return r;
2695 }
2696 WREG32(scratch, 0xCAFEDEAD);
f712812e 2697 r = radeon_ib_get(rdev, ring_index, &ib, 256);
3ce0a23d
JG		 2698 if (r) {
2699 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2700 return r;
2701 }
2702 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2703 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2704 ib->ptr[2] = 0xDEADBEEF;
442f7cfa 2705 ib->length_dw = 3;
3ce0a23d
JG		 2706 r = radeon_ib_schedule(rdev, ib);
2707 if (r) {
2708 radeon_scratch_free(rdev, scratch);
2709 radeon_ib_free(rdev, &ib);
2710 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2711 return r;
2712 }
2713 r = radeon_fence_wait(ib->fence, false);
2714 if (r) {
2715 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2716 return r;
2717 }
2718 for (i = 0; i < rdev->usec_timeout; i++) {
2719 tmp = RREG32(scratch);
2720 if (tmp == 0xDEADBEEF)
2721 break;
2722 DRM_UDELAY(1);
2723 }
2724 if (i < rdev->usec_timeout) {
7b1f2485 2725 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib->fence->ring, i);
3ce0a23d 2726 } else {
4417d7f6 2727 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 2728 scratch, tmp);
2729 r = -EINVAL;
2730 }
2731 radeon_scratch_free(rdev, scratch);
2732 radeon_ib_free(rdev, &ib);
771fe6b9
JG		 2733 return r;
2734}
2735
d8f60cfc
AD		 2736/*
2737 * Interrupts
2738 *
2739 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2740 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2741 * writing to the ring and the GPU consuming, the GPU writes to the ring
2742 * and host consumes. As the host irq handler processes interrupts, it
2743 * increments the rptr. When the rptr catches up with the wptr, all the
2744 * current interrupts have been processed.
2745 */
2746
2747void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2748{
2749 u32 rb_bufsz;
2750
2751 /* Align ring size */
2752 rb_bufsz = drm_order(ring_size / 4);
2753 ring_size = (1 << rb_bufsz) * 4;
2754 rdev->ih.ring_size = ring_size;
0c45249f
JG		 2755 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2756 rdev->ih.rptr = 0;
d8f60cfc
AD		 2757}
2758
25a857fb 2759int r600_ih_ring_alloc(struct radeon_device *rdev)
d8f60cfc
AD		 2760{
2761 int r;
2762
d8f60cfc
AD		 2763 /* Allocate ring buffer */
2764 if (rdev->ih.ring_obj == NULL) {
441921d5 2765 r = radeon_bo_create(rdev, rdev->ih.ring_size,
268b2510 2766 PAGE_SIZE, true,
4c788679
JG		 2767 RADEON_GEM_DOMAIN_GTT,
2768 &rdev->ih.ring_obj);
d8f60cfc
AD		 2769 if (r) {
2770 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2771 return r;
2772 }
4c788679
JG		 2773 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2774 if (unlikely(r != 0))
2775 return r;
2776 r = radeon_bo_pin(rdev->ih.ring_obj,
2777 RADEON_GEM_DOMAIN_GTT,
2778 &rdev->ih.gpu_addr);
d8f60cfc 2779 if (r) {
4c788679 2780 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2781 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2782 return r;
2783 }
4c788679
JG		 2784 r = radeon_bo_kmap(rdev->ih.ring_obj,
2785 (void **)&rdev->ih.ring);
2786 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2787 if (r) {
2788 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2789 return r;
2790 }
2791 }
d8f60cfc
AD		 2792 return 0;
2793}
2794
25a857fb 2795void r600_ih_ring_fini(struct radeon_device *rdev)
d8f60cfc 2796{
4c788679 2797 int r;
d8f60cfc 2798 if (rdev->ih.ring_obj) {
4c788679
JG		 2799 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2800 if (likely(r == 0)) {
2801 radeon_bo_kunmap(rdev->ih.ring_obj);
2802 radeon_bo_unpin(rdev->ih.ring_obj);
2803 radeon_bo_unreserve(rdev->ih.ring_obj);
2804 }
2805 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 2806 rdev->ih.ring = NULL;
2807 rdev->ih.ring_obj = NULL;
2808 }
2809}
2810
45f9a39b 2811void r600_rlc_stop(struct radeon_device *rdev)
d8f60cfc
AD		 2812{
2813
45f9a39b
AD		 2814 if ((rdev->family >= CHIP_RV770) &&
2815 (rdev->family <= CHIP_RV740)) {
d8f60cfc
AD		 2816 /* r7xx asics need to soft reset RLC before halting */
2817 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2818 RREG32(SRBM_SOFT_RESET);
4de833c3 2819 mdelay(15);
d8f60cfc
AD		 2820 WREG32(SRBM_SOFT_RESET, 0);
2821 RREG32(SRBM_SOFT_RESET);
2822 }
2823
2824 WREG32(RLC_CNTL, 0);
2825}
2826
2827static void r600_rlc_start(struct radeon_device *rdev)
2828{
2829 WREG32(RLC_CNTL, RLC_ENABLE);
2830}
2831
2832static int r600_rlc_init(struct radeon_device *rdev)
2833{
2834 u32 i;
2835 const __be32 *fw_data;
2836
2837 if (!rdev->rlc_fw)
2838 return -EINVAL;
2839
2840 r600_rlc_stop(rdev);
2841
d8f60cfc 2842 WREG32(RLC_HB_CNTL, 0);
c420c745
AD		 2843
2844 if (rdev->family == CHIP_ARUBA) {
2845 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
2846 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
2847 }
2848 if (rdev->family <= CHIP_CAYMAN) {
2849 WREG32(RLC_HB_BASE, 0);
2850 WREG32(RLC_HB_RPTR, 0);
2851 WREG32(RLC_HB_WPTR, 0);
2852 }
12727809
AD		 2853 if (rdev->family <= CHIP_CAICOS) {
2854 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2855 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2856 }
d8f60cfc
AD		 2857 WREG32(RLC_MC_CNTL, 0);
2858 WREG32(RLC_UCODE_CNTL, 0);
2859
2860 fw_data = (const __be32 *)rdev->rlc_fw->data;
c420c745
AD		 2861 if (rdev->family >= CHIP_ARUBA) {
2862 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
2863 WREG32(RLC_UCODE_ADDR, i);
2864 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2865 }
2866 } else if (rdev->family >= CHIP_CAYMAN) {
12727809
AD		 2867 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
2868 WREG32(RLC_UCODE_ADDR, i);
2869 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2870 }
2871 } else if (rdev->family >= CHIP_CEDAR) {
45f9a39b
AD		 2872 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2873 WREG32(RLC_UCODE_ADDR, i);
2874 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2875 }
2876 } else if (rdev->family >= CHIP_RV770) {
d8f60cfc
AD		 2877 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2878 WREG32(RLC_UCODE_ADDR, i);
2879 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2880 }
2881 } else {
2882 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2883 WREG32(RLC_UCODE_ADDR, i);
2884 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2885 }
2886 }
2887 WREG32(RLC_UCODE_ADDR, 0);
2888
2889 r600_rlc_start(rdev);
2890
2891 return 0;
2892}
2893
2894static void r600_enable_interrupts(struct radeon_device *rdev)
2895{
2896 u32 ih_cntl = RREG32(IH_CNTL);
2897 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2898
2899 ih_cntl |= ENABLE_INTR;
2900 ih_rb_cntl |= IH_RB_ENABLE;
2901 WREG32(IH_CNTL, ih_cntl);
2902 WREG32(IH_RB_CNTL, ih_rb_cntl);
2903 rdev->ih.enabled = true;
2904}
2905
45f9a39b 2906void r600_disable_interrupts(struct radeon_device *rdev)
d8f60cfc
AD		 2907{
2908 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2909 u32 ih_cntl = RREG32(IH_CNTL);
2910
2911 ih_rb_cntl &= ~IH_RB_ENABLE;
2912 ih_cntl &= ~ENABLE_INTR;
2913 WREG32(IH_RB_CNTL, ih_rb_cntl);
2914 WREG32(IH_CNTL, ih_cntl);
2915 /* set rptr, wptr to 0 */
2916 WREG32(IH_RB_RPTR, 0);
2917 WREG32(IH_RB_WPTR, 0);
2918 rdev->ih.enabled = false;
2919 rdev->ih.wptr = 0;
2920 rdev->ih.rptr = 0;
2921}
2922
e0df1ac5
AD		 2923static void r600_disable_interrupt_state(struct radeon_device *rdev)
2924{
2925 u32 tmp;
2926
3555e53b 2927 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
e0df1ac5
AD		 2928 WREG32(GRBM_INT_CNTL, 0);
2929 WREG32(DxMODE_INT_MASK, 0);
6f34be50
AD		 2930 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
2931 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
e0df1ac5
AD		 2932 if (ASIC_IS_DCE3(rdev)) {
2933 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2934 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2935 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2936 WREG32(DC_HPD1_INT_CONTROL, tmp);
2937 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2938 WREG32(DC_HPD2_INT_CONTROL, tmp);
2939 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2940 WREG32(DC_HPD3_INT_CONTROL, tmp);
2941 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2942 WREG32(DC_HPD4_INT_CONTROL, tmp);
2943 if (ASIC_IS_DCE32(rdev)) {
2944 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2945 WREG32(DC_HPD5_INT_CONTROL, tmp);
e0df1ac5 2946 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2947 WREG32(DC_HPD6_INT_CONTROL, tmp);
c6543a6e
RM		 2948 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2949 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
2950 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2951 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
f122c610
AD		 2952 } else {
2953 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2954 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
2955 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2956 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
e0df1ac5
AD		 2957 }
2958 } else {
2959 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2960 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2961 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2962 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
e0df1ac5 2963 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2964 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
e0df1ac5 2965 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2966 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
f122c610
AD		 2967 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2968 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
2969 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2970 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
e0df1ac5
AD		 2971 }
2972}
2973
d8f60cfc
AD		 2974int r600_irq_init(struct radeon_device *rdev)
2975{
2976 int ret = 0;
2977 int rb_bufsz;
2978 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2979
2980 /* allocate ring */
0c45249f 2981 ret = r600_ih_ring_alloc(rdev);
d8f60cfc
AD		 2982 if (ret)
2983 return ret;
2984
2985 /* disable irqs */
2986 r600_disable_interrupts(rdev);
2987
2988 /* init rlc */
2989 ret = r600_rlc_init(rdev);
2990 if (ret) {
2991 r600_ih_ring_fini(rdev);
2992 return ret;
2993 }
2994
2995 /* setup interrupt control */
2996 /* set dummy read address to ring address */
2997 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2998 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2999 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3000 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3001 */
3002 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3003 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3004 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3005 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3006
3007 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3008 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3009
3010 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3011 IH_WPTR_OVERFLOW_CLEAR |
3012 (rb_bufsz << 1));
724c80e1
AD		 3013
3014 if (rdev->wb.enabled)
3015 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3016
3017 /* set the writeback address whether it's enabled or not */
3018 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3019 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
d8f60cfc
AD		 3020
3021 WREG32(IH_RB_CNTL, ih_rb_cntl);
3022
3023 /* set rptr, wptr to 0 */
3024 WREG32(IH_RB_RPTR, 0);
3025 WREG32(IH_RB_WPTR, 0);
3026
3027 /* Default settings for IH_CNTL (disabled at first) */
3028 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3029 /* RPTR_REARM only works if msi's are enabled */
3030 if (rdev->msi_enabled)
3031 ih_cntl |= RPTR_REARM;
d8f60cfc
AD		 3032 WREG32(IH_CNTL, ih_cntl);
3033
3034 /* force the active interrupt state to all disabled */
45f9a39b
AD		 3035 if (rdev->family >= CHIP_CEDAR)
3036 evergreen_disable_interrupt_state(rdev);
3037 else
3038 r600_disable_interrupt_state(rdev);
d8f60cfc 3039
2099810f
DA		 3040 /* at this point everything should be setup correctly to enable master */
3041 pci_set_master(rdev->pdev);
3042
d8f60cfc
AD		 3043 /* enable irqs */
3044 r600_enable_interrupts(rdev);
3045
3046 return ret;
3047}
3048
0c45249f 3049void r600_irq_suspend(struct radeon_device *rdev)
d8f60cfc 3050{
45f9a39b 3051 r600_irq_disable(rdev);
d8f60cfc 3052 r600_rlc_stop(rdev);
0c45249f
JG		 3053}
3054
3055void r600_irq_fini(struct radeon_device *rdev)
3056{
3057 r600_irq_suspend(rdev);
d8f60cfc
AD		 3058 r600_ih_ring_fini(rdev);
3059}
3060
3061int r600_irq_set(struct radeon_device *rdev)
3062{
e0df1ac5
AD		 3063 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3064 u32 mode_int = 0;
3065 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2031f77c 3066 u32 grbm_int_cntl = 0;
f122c610 3067 u32 hdmi0, hdmi1;
6f34be50 3068 u32 d1grph = 0, d2grph = 0;
d8f60cfc 3069
003e69f9 3070 if (!rdev->irq.installed) {
fce7d61b 3071 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 3072 return -EINVAL;
3073 }
d8f60cfc 3074 /* don't enable anything if the ih is disabled */
79c2bbc5
JG		 3075 if (!rdev->ih.enabled) {
3076 r600_disable_interrupts(rdev);
3077 /* force the active interrupt state to all disabled */
3078 r600_disable_interrupt_state(rdev);
d8f60cfc 3079 return 0;
79c2bbc5 3080 }
d8f60cfc 3081
e0df1ac5
AD		 3082 if (ASIC_IS_DCE3(rdev)) {
3083 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3084 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3085 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3086 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3087 if (ASIC_IS_DCE32(rdev)) {
3088 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3089 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
c6543a6e
RM		 3090 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3091 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
f122c610
AD		 3092 } else {
3093 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3094 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
e0df1ac5
AD		 3095 }
3096 } else {
3097 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3098 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3099 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
f122c610
AD		 3100 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3101 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
e0df1ac5
AD		 3102 }
3103
1b37078b 3104 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
d8f60cfc
AD		 3105 DRM_DEBUG("r600_irq_set: sw int\n");
3106 cp_int_cntl |= RB_INT_ENABLE;
d0f8a854 3107 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
d8f60cfc 3108 }
6f34be50
AD		 3109 if (rdev->irq.crtc_vblank_int[0] ||
3110 rdev->irq.pflip[0]) {
d8f60cfc
AD		 3111 DRM_DEBUG("r600_irq_set: vblank 0\n");
3112 mode_int |= D1MODE_VBLANK_INT_MASK;
3113 }
6f34be50
AD		 3114 if (rdev->irq.crtc_vblank_int[1] ||
3115 rdev->irq.pflip[1]) {
d8f60cfc
AD		 3116 DRM_DEBUG("r600_irq_set: vblank 1\n");
3117 mode_int |= D2MODE_VBLANK_INT_MASK;
3118 }
e0df1ac5
AD		 3119 if (rdev->irq.hpd[0]) {
3120 DRM_DEBUG("r600_irq_set: hpd 1\n");
3121 hpd1 |= DC_HPDx_INT_EN;
3122 }
3123 if (rdev->irq.hpd[1]) {
3124 DRM_DEBUG("r600_irq_set: hpd 2\n");
3125 hpd2 |= DC_HPDx_INT_EN;
3126 }
3127 if (rdev->irq.hpd[2]) {
3128 DRM_DEBUG("r600_irq_set: hpd 3\n");
3129 hpd3 |= DC_HPDx_INT_EN;
3130 }
3131 if (rdev->irq.hpd[3]) {
3132 DRM_DEBUG("r600_irq_set: hpd 4\n");
3133 hpd4 |= DC_HPDx_INT_EN;
3134 }
3135 if (rdev->irq.hpd[4]) {
3136 DRM_DEBUG("r600_irq_set: hpd 5\n");
3137 hpd5 |= DC_HPDx_INT_EN;
3138 }
3139 if (rdev->irq.hpd[5]) {
3140 DRM_DEBUG("r600_irq_set: hpd 6\n");
3141 hpd6 |= DC_HPDx_INT_EN;
3142 }
f122c610
AD		 3143 if (rdev->irq.afmt[0]) {
3144 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3145 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
f2594933 3146 }
f122c610
AD		 3147 if (rdev->irq.afmt[1]) {
3148 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3149 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
f2594933 3150 }
2031f77c
AD		 3151 if (rdev->irq.gui_idle) {
3152 DRM_DEBUG("gui idle\n");
3153 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3154 }
d8f60cfc
AD		 3155
3156 WREG32(CP_INT_CNTL, cp_int_cntl);
3157 WREG32(DxMODE_INT_MASK, mode_int);
6f34be50
AD		 3158 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3159 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
2031f77c 3160 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
e0df1ac5
AD		 3161 if (ASIC_IS_DCE3(rdev)) {
3162 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3163 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3164 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3165 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3166 if (ASIC_IS_DCE32(rdev)) {
3167 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3168 WREG32(DC_HPD6_INT_CONTROL, hpd6);
c6543a6e
RM		 3169 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3170 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
f122c610
AD		 3171 } else {
3172 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3173 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
e0df1ac5
AD		 3174 }
3175 } else {
3176 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3177 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3178 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
f122c610
AD		 3179 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3180 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
e0df1ac5 3181 }
d8f60cfc
AD		 3182
3183 return 0;
3184}
3185
ce580fab 3186static void r600_irq_ack(struct radeon_device *rdev)
d8f60cfc 3187{
e0df1ac5
AD		 3188 u32 tmp;
3189
3190 if (ASIC_IS_DCE3(rdev)) {
6f34be50
AD		 3191 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3192 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3193 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
f122c610 3194 if (ASIC_IS_DCE32(rdev)) {
c6543a6e
RM		 3195 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3196 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
f122c610
AD		 3197 } else {
3198 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3199 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3200 }
e0df1ac5 3201 } else {
6f34be50
AD		 3202 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3203 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3204 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
f122c610
AD		 3205 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3206 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
6f34be50
AD		 3207 }
3208 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3209 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3210
3211 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3212 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3213 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3214 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3215 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
d8f60cfc 3216 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3217 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
d8f60cfc 3218 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3219 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
d8f60cfc 3220 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3221 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
d8f60cfc 3222 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3223 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
e0df1ac5
AD		 3224 if (ASIC_IS_DCE3(rdev)) {
3225 tmp = RREG32(DC_HPD1_INT_CONTROL);
3226 tmp |= DC_HPDx_INT_ACK;
3227 WREG32(DC_HPD1_INT_CONTROL, tmp);
3228 } else {
3229 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3230 tmp |= DC_HPDx_INT_ACK;
3231 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3232 }
3233 }
6f34be50 3234 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
e0df1ac5
AD		 3235 if (ASIC_IS_DCE3(rdev)) {
3236 tmp = RREG32(DC_HPD2_INT_CONTROL);
3237 tmp |= DC_HPDx_INT_ACK;
3238 WREG32(DC_HPD2_INT_CONTROL, tmp);
3239 } else {
3240 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3241 tmp |= DC_HPDx_INT_ACK;
3242 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3243 }
3244 }
6f34be50 3245 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
e0df1ac5
AD		 3246 if (ASIC_IS_DCE3(rdev)) {
3247 tmp = RREG32(DC_HPD3_INT_CONTROL);
3248 tmp |= DC_HPDx_INT_ACK;
3249 WREG32(DC_HPD3_INT_CONTROL, tmp);
3250 } else {
3251 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3252 tmp |= DC_HPDx_INT_ACK;
3253 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3254 }
3255 }
6f34be50 3256 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
e0df1ac5
AD		 3257 tmp = RREG32(DC_HPD4_INT_CONTROL);
3258 tmp |= DC_HPDx_INT_ACK;
3259 WREG32(DC_HPD4_INT_CONTROL, tmp);
3260 }
3261 if (ASIC_IS_DCE32(rdev)) {
6f34be50 3262 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
e0df1ac5
AD		 3263 tmp = RREG32(DC_HPD5_INT_CONTROL);
3264 tmp |= DC_HPDx_INT_ACK;
3265 WREG32(DC_HPD5_INT_CONTROL, tmp);
3266 }
6f34be50 3267 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
e0df1ac5
AD		 3268 tmp = RREG32(DC_HPD5_INT_CONTROL);
3269 tmp |= DC_HPDx_INT_ACK;
3270 WREG32(DC_HPD6_INT_CONTROL, tmp);
3271 }
f122c610 3272 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
c6543a6e 3273 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
f122c610 3274 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
c6543a6e 3275 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
f122c610
AD		 3276 }
3277 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
c6543a6e 3278 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
f122c610 3279 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
c6543a6e 3280 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
f2594933
CK		 3281 }
3282 } else {
f122c610
AD		 3283 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3284 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3285 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3286 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3287 }
3288 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3289 if (ASIC_IS_DCE3(rdev)) {
3290 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3291 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3292 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3293 } else {
3294 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3295 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3296 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3297 }
f2594933
CK		 3298 }
3299 }
d8f60cfc
AD		 3300}
3301
3302void r600_irq_disable(struct radeon_device *rdev)
3303{
d8f60cfc
AD		 3304 r600_disable_interrupts(rdev);
3305 /* Wait and acknowledge irq */
3306 mdelay(1);
6f34be50 3307 r600_irq_ack(rdev);
e0df1ac5 3308 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 3309}
3310
ce580fab 3311static u32 r600_get_ih_wptr(struct radeon_device *rdev)
d8f60cfc
AD		 3312{
3313 u32 wptr, tmp;
3ce0a23d 3314
724c80e1 3315 if (rdev->wb.enabled)
204ae24d 3316 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 3317 else
3318 wptr = RREG32(IH_RB_WPTR);
3ce0a23d 3319
d8f60cfc 3320 if (wptr & RB_OVERFLOW) {
7924e5eb
JG		 3321 /* When a ring buffer overflow happen start parsing interrupt
3322 * from the last not overwritten vector (wptr + 16). Hopefully
3323 * this should allow us to catchup.
3324 */
3325 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3326 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3327 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
d8f60cfc
AD		 3328 tmp = RREG32(IH_RB_CNTL);
3329 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3330 WREG32(IH_RB_CNTL, tmp);
3331 }
0c45249f 3332 return (wptr & rdev->ih.ptr_mask);
d8f60cfc 3333}
3ce0a23d 3334
d8f60cfc
AD		 3335/* r600 IV Ring
3336 * Each IV ring entry is 128 bits:
3337 * [7:0] - interrupt source id
3338 * [31:8] - reserved
3339 * [59:32] - interrupt source data
3340 * [127:60] - reserved
3341 *
3342 * The basic interrupt vector entries
3343 * are decoded as follows:
3344 * src_id src_data description
3345 * 1 0 D1 Vblank
3346 * 1 1 D1 Vline
3347 * 5 0 D2 Vblank
3348 * 5 1 D2 Vline
3349 * 19 0 FP Hot plug detection A
3350 * 19 1 FP Hot plug detection B
3351 * 19 2 DAC A auto-detection
3352 * 19 3 DAC B auto-detection
f2594933
CK		 3353 * 21 4 HDMI block A
3354 * 21 5 HDMI block B
d8f60cfc
AD		 3355 * 176 - CP_INT RB
3356 * 177 - CP_INT IB1
3357 * 178 - CP_INT IB2
3358 * 181 - EOP Interrupt
3359 * 233 - GUI Idle
3360 *
3361 * Note, these are based on r600 and may need to be
3362 * adjusted or added to on newer asics
3363 */
3364
3365int r600_irq_process(struct radeon_device *rdev)
3366{
682f1a54
DA		 3367 u32 wptr;
3368 u32 rptr;
d8f60cfc 3369 u32 src_id, src_data;
6f34be50 3370 u32 ring_index;
d8f60cfc 3371 unsigned long flags;
d4877cf2 3372 bool queue_hotplug = false;
f122c610 3373 bool queue_hdmi = false;
d8f60cfc 3374
682f1a54 3375 if (!rdev->ih.enabled || rdev->shutdown)
79c2bbc5 3376 return IRQ_NONE;
d8f60cfc 3377
f6a56939
BH		 3378 /* No MSIs, need a dummy read to flush PCI DMAs */
3379 if (!rdev->msi_enabled)
3380 RREG32(IH_RB_WPTR);
3381
682f1a54
DA		 3382 wptr = r600_get_ih_wptr(rdev);
3383 rptr = rdev->ih.rptr;
3384 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3385
d8f60cfc
AD		 3386 spin_lock_irqsave(&rdev->ih.lock, flags);
3387
3388 if (rptr == wptr) {
3389 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3390 return IRQ_NONE;
3391 }
d8f60cfc
AD		 3392
3393restart_ih:
964f6645
BH		 3394 /* Order reading of wptr vs. reading of IH ring data */
3395 rmb();
3396
d8f60cfc 3397 /* display interrupts */
6f34be50 3398 r600_irq_ack(rdev);
d8f60cfc
AD		 3399
3400 rdev->ih.wptr = wptr;
3401 while (rptr != wptr) {
3402 /* wptr/rptr are in bytes! */
3403 ring_index = rptr / 4;
4eace7fd
CC		 3404 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3405 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
d8f60cfc
AD		 3406
3407 switch (src_id) {
3408 case 1: /* D1 vblank/vline */
3409 switch (src_data) {
3410 case 0: /* D1 vblank */
6f34be50 3411 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 3412 if (rdev->irq.crtc_vblank_int[0]) {
3413 drm_handle_vblank(rdev->ddev, 0);
3414 rdev->pm.vblank_sync = true;
3415 wake_up(&rdev->irq.vblank_queue);
3416 }
3e4ea742
MK		 3417 if (rdev->irq.pflip[0])
3418 radeon_crtc_handle_flip(rdev, 0);
6f34be50 3419 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
d8f60cfc
AD		 3420 DRM_DEBUG("IH: D1 vblank\n");
3421 }
3422 break;
3423 case 1: /* D1 vline */
6f34be50
AD		 3424 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3425 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
d8f60cfc
AD		 3426 DRM_DEBUG("IH: D1 vline\n");
3427 }
3428 break;
3429 default:
b042589c 3430 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3431 break;
3432 }
3433 break;
3434 case 5: /* D2 vblank/vline */
3435 switch (src_data) {
3436 case 0: /* D2 vblank */
6f34be50 3437 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 3438 if (rdev->irq.crtc_vblank_int[1]) {
3439 drm_handle_vblank(rdev->ddev, 1);
3440 rdev->pm.vblank_sync = true;
3441 wake_up(&rdev->irq.vblank_queue);
3442 }
3e4ea742
MK		 3443 if (rdev->irq.pflip[1])
3444 radeon_crtc_handle_flip(rdev, 1);
6f34be50 3445 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
d8f60cfc
AD		 3446 DRM_DEBUG("IH: D2 vblank\n");
3447 }
3448 break;
3449 case 1: /* D1 vline */
6f34be50
AD		 3450 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3451 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
d8f60cfc
AD		 3452 DRM_DEBUG("IH: D2 vline\n");
3453 }
3454 break;
3455 default:
b042589c 3456 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3457 break;
3458 }
3459 break;
e0df1ac5
AD		 3460 case 19: /* HPD/DAC hotplug */
3461 switch (src_data) {
3462 case 0:
6f34be50
AD		 3463 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3464 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
d4877cf2
AD		 3465 queue_hotplug = true;
3466 DRM_DEBUG("IH: HPD1\n");
e0df1ac5
AD		 3467 }
3468 break;
3469 case 1:
6f34be50
AD		 3470 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3471 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
d4877cf2
AD		 3472 queue_hotplug = true;
3473 DRM_DEBUG("IH: HPD2\n");
e0df1ac5
AD		 3474 }
3475 break;
3476 case 4:
6f34be50
AD		 3477 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3478 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
d4877cf2
AD		 3479 queue_hotplug = true;
3480 DRM_DEBUG("IH: HPD3\n");
e0df1ac5
AD		 3481 }
3482 break;
3483 case 5:
6f34be50
AD		 3484 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3485 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
d4877cf2
AD		 3486 queue_hotplug = true;
3487 DRM_DEBUG("IH: HPD4\n");
e0df1ac5
AD		 3488 }
3489 break;
3490 case 10:
6f34be50
AD		 3491 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3492 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
d4877cf2
AD		 3493 queue_hotplug = true;
3494 DRM_DEBUG("IH: HPD5\n");
e0df1ac5
AD		 3495 }
3496 break;
3497 case 12:
6f34be50
AD		 3498 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3499 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
d4877cf2
AD		 3500 queue_hotplug = true;
3501 DRM_DEBUG("IH: HPD6\n");
e0df1ac5
AD		 3502 }
3503 break;
3504 default:
b042589c 3505 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
e0df1ac5
AD		 3506 break;
3507 }
3508 break;
f122c610
AD		 3509 case 21: /* hdmi */
3510 switch (src_data) {
3511 case 4:
3512 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3513 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3514 queue_hdmi = true;
3515 DRM_DEBUG("IH: HDMI0\n");
3516 }
3517 break;
3518 case 5:
3519 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3520 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3521 queue_hdmi = true;
3522 DRM_DEBUG("IH: HDMI1\n");
3523 }
3524 break;
3525 default:
3526 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3527 break;
3528 }
f2594933 3529 break;
d8f60cfc
AD		 3530 case 176: /* CP_INT in ring buffer */
3531 case 177: /* CP_INT in IB1 */
3532 case 178: /* CP_INT in IB2 */
3533 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
7465280c 3534 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
d8f60cfc
AD		 3535 break;
3536 case 181: /* CP EOP event */
3537 DRM_DEBUG("IH: CP EOP\n");
7465280c 3538 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
d8f60cfc 3539 break;
2031f77c 3540 case 233: /* GUI IDLE */
303c805c 3541 DRM_DEBUG("IH: GUI idle\n");
2031f77c
AD		 3542 rdev->pm.gui_idle = true;
3543 wake_up(&rdev->irq.idle_queue);
3544 break;
d8f60cfc 3545 default:
b042589c 3546 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3547 break;
3548 }
3549
3550 /* wptr/rptr are in bytes! */
0c45249f
JG		 3551 rptr += 16;
3552 rptr &= rdev->ih.ptr_mask;
d8f60cfc
AD		 3553 }
3554 /* make sure wptr hasn't changed while processing */
3555 wptr = r600_get_ih_wptr(rdev);
3556 if (wptr != rdev->ih.wptr)
3557 goto restart_ih;
d4877cf2 3558 if (queue_hotplug)
32c87fca 3559 schedule_work(&rdev->hotplug_work);
f122c610
AD		 3560 if (queue_hdmi)
3561 schedule_work(&rdev->audio_work);
d8f60cfc
AD		 3562 rdev->ih.rptr = rptr;
3563 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3564 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3565 return IRQ_HANDLED;
3566}
3ce0a23d
JG		 3567
3568/*
3569 * Debugfs info
3570 */
3571#if defined(CONFIG_DEBUG_FS)
3572
3ce0a23d
JG		 3573static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3574{
3575 struct drm_info_node *node = (struct drm_info_node *) m->private;
3576 struct drm_device *dev = node->minor->dev;
3577 struct radeon_device *rdev = dev->dev_private;
3578
3579 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3580 DREG32_SYS(m, rdev, VM_L2_STATUS);
3581 return 0;
3582}
3583
3584static struct drm_info_list r600_mc_info_list[] = {
3585 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3ce0a23d
JG		 3586};
3587#endif
3588
3589int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3590{
3591#if defined(CONFIG_DEBUG_FS)
3592 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3593#else
3594 return 0;
3595#endif
771fe6b9 3596}
062b389c
JG		 3597
3598/**
3599 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3600 * rdev: radeon device structure
3601 * bo: buffer object struct which userspace is waiting for idle
3602 *
3603 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3604 * through ring buffer, this leads to corruption in rendering, see
3605 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3606 * directly perform HDP flush by writing register through MMIO.
3607 */
3608void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3609{
812d0469 3610 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
f3886f85
AD		 3611 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3612 * This seems to cause problems on some AGP cards. Just use the old
3613 * method for them.
812d0469 3614 */
e488459a 3615 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
f3886f85 3616 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
87cbf8f2 3617 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
812d0469
AD		 3618 u32 tmp;
3619
3620 WREG32(HDP_DEBUG1, 0);
3621 tmp = readl((void __iomem *)ptr);
3622 } else
3623 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
062b389c 3624}
3313e3d4
AD		 3625
3626void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
3627{
3628 u32 link_width_cntl, mask, target_reg;
3629
3630 if (rdev->flags & RADEON_IS_IGP)
3631 return;
3632
3633 if (!(rdev->flags & RADEON_IS_PCIE))
3634 return;
3635
3636 /* x2 cards have a special sequence */
3637 if (ASIC_IS_X2(rdev))
3638 return;
3639
3640 /* FIXME wait for idle */
3641
3642 switch (lanes) {
3643 case 0:
3644 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
3645 break;
3646 case 1:
3647 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
3648 break;
3649 case 2:
3650 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
3651 break;
3652 case 4:
3653 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
3654 break;
3655 case 8:
3656 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
3657 break;
3658 case 12:
3659 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
3660 break;
3661 case 16:
3662 default:
3663 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
3664 break;
3665 }
3666
3667 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3668
3669 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
3670 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
3671 return;
3672
3673 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
3674 return;
3675
3676 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
3677 RADEON_PCIE_LC_RECONFIG_NOW |
3678 R600_PCIE_LC_RENEGOTIATE_EN |
3679 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3680 link_width_cntl |= mask;
3681
3682 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3683
3684 /* some northbridges can renegotiate the link rather than requiring
3685 * a complete re-config.
3686 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3687 */
3688 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
3689 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
3690 else
3691 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
3692
3693 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
3694 RADEON_PCIE_LC_RECONFIG_NOW));
3695
3696 if (rdev->family >= CHIP_RV770)
3697 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
3698 else
3699 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
3700
3701 /* wait for lane set to complete */
3702 link_width_cntl = RREG32(target_reg);
3703 while (link_width_cntl == 0xffffffff)
3704 link_width_cntl = RREG32(target_reg);
3705
3706}
3707
3708int r600_get_pcie_lanes(struct radeon_device *rdev)
3709{
3710 u32 link_width_cntl;
3711
3712 if (rdev->flags & RADEON_IS_IGP)
3713 return 0;
3714
3715 if (!(rdev->flags & RADEON_IS_PCIE))
3716 return 0;
3717
3718 /* x2 cards have a special sequence */
3719 if (ASIC_IS_X2(rdev))
3720 return 0;
3721
3722 /* FIXME wait for idle */
3723
3724 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3725
3726 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3727 case RADEON_PCIE_LC_LINK_WIDTH_X0:
3728 return 0;
3729 case RADEON_PCIE_LC_LINK_WIDTH_X1:
3730 return 1;
3731 case RADEON_PCIE_LC_LINK_WIDTH_X2:
3732 return 2;
3733 case RADEON_PCIE_LC_LINK_WIDTH_X4:
3734 return 4;
3735 case RADEON_PCIE_LC_LINK_WIDTH_X8:
3736 return 8;
3737 case RADEON_PCIE_LC_LINK_WIDTH_X16:
3738 default:
3739 return 16;
3740 }
3741}
3742
9e46a48d
AD		 3743static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3744{
3745 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
3746 u16 link_cntl2;
3747
d42dd579
AD		 3748 if (radeon_pcie_gen2 == 0)
3749 return;
3750
9e46a48d
AD		 3751 if (rdev->flags & RADEON_IS_IGP)
3752 return;
3753
3754 if (!(rdev->flags & RADEON_IS_PCIE))
3755 return;
3756
3757 /* x2 cards have a special sequence */
3758 if (ASIC_IS_X2(rdev))
3759 return;
3760
3761 /* only RV6xx+ chips are supported */
3762 if (rdev->family <= CHIP_R600)
3763 return;
3764
3765 /* 55 nm r6xx asics */
3766 if ((rdev->family == CHIP_RV670) ||
3767 (rdev->family == CHIP_RV620) ||
3768 (rdev->family == CHIP_RV635)) {
3769 /* advertise upconfig capability */
3770 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3771 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3772 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3773 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3774 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
3775 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
3776 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
3777 LC_RECONFIG_ARC_MISSING_ESCAPE);
3778 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
3779 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3780 } else {
3781 link_width_cntl |= LC_UPCONFIGURE_DIS;
3782 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3783 }
3784 }
3785
3786 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3787 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3788 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3789
3790 /* 55 nm r6xx asics */
3791 if ((rdev->family == CHIP_RV670) ||
3792 (rdev->family == CHIP_RV620) ||
3793 (rdev->family == CHIP_RV635)) {
3794 WREG32(MM_CFGREGS_CNTL, 0x8);
3795 link_cntl2 = RREG32(0x4088);
3796 WREG32(MM_CFGREGS_CNTL, 0);
3797 /* not supported yet */
3798 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
3799 return;
3800 }
3801
3802 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
3803 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
3804 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
3805 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
3806 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
3807 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3808
3809 tmp = RREG32(0x541c);
3810 WREG32(0x541c, tmp | 0x8);
3811 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
3812 link_cntl2 = RREG16(0x4088);
3813 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
3814 link_cntl2 |= 0x2;
3815 WREG16(0x4088, link_cntl2);
3816 WREG32(MM_CFGREGS_CNTL, 0);
3817
3818 if ((rdev->family == CHIP_RV670) ||
3819 (rdev->family == CHIP_RV620) ||
3820 (rdev->family == CHIP_RV635)) {
3821 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
3822 training_cntl &= ~LC_POINT_7_PLUS_EN;
3823 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
3824 } else {
3825 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3826 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3827 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3828 }
3829
3830 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3831 speed_cntl |= LC_GEN2_EN_STRAP;
3832 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3833
3834 } else {
3835 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3836 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3837 if (1)
3838 link_width_cntl |= LC_UPCONFIGURE_DIS;
3839 else
3840 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3841 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3842 }
3843}
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