]>
Commit | Line | Data |
---|---|---|
3ce0a23d JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
40e2a5c1 | 28 | #include <linux/kernel.h> |
3ce0a23d JG |
29 | #include "drmP.h" |
30 | #include "radeon.h" | |
3ce0a23d | 31 | #include "r600d.h" |
961fb597 | 32 | #include "r600_reg_safe.h" |
3ce0a23d JG |
33 | |
34 | static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, | |
35 | struct radeon_cs_reloc **cs_reloc); | |
36 | static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, | |
37 | struct radeon_cs_reloc **cs_reloc); | |
38 | typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**); | |
39 | static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm; | |
961fb597 JG |
40 | extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size); |
41 | ||
3ce0a23d | 42 | |
c8c15ff1 | 43 | struct r600_cs_track { |
961fb597 JG |
44 | /* configuration we miror so that we use same code btw kms/ums */ |
45 | u32 group_size; | |
46 | u32 nbanks; | |
47 | u32 npipes; | |
48 | /* value we track */ | |
5f77df36 | 49 | u32 sq_config; |
c116cc94 | 50 | u32 log_nsamples; |
961fb597 JG |
51 | u32 nsamples; |
52 | u32 cb_color_base_last[8]; | |
53 | struct radeon_bo *cb_color_bo[8]; | |
16790569 | 54 | u64 cb_color_bo_mc[8]; |
c116cc94 MO |
55 | u64 cb_color_bo_offset[8]; |
56 | struct radeon_bo *cb_color_frag_bo[8]; | |
57 | u64 cb_color_frag_offset[8]; | |
58 | struct radeon_bo *cb_color_tile_bo[8]; | |
59 | u64 cb_color_tile_offset[8]; | |
60 | u32 cb_color_mask[8]; | |
961fb597 | 61 | u32 cb_color_info[8]; |
285484e2 | 62 | u32 cb_color_view[8]; |
3c12513d | 63 | u32 cb_color_size_idx[8]; /* unused */ |
961fb597 | 64 | u32 cb_target_mask; |
3c12513d | 65 | u32 cb_shader_mask; /* unused */ |
961fb597 JG |
66 | u32 cb_color_size[8]; |
67 | u32 vgt_strmout_en; | |
68 | u32 vgt_strmout_buffer_en; | |
dd220a00 | 69 | struct radeon_bo *vgt_strmout_bo[4]; |
3c12513d | 70 | u64 vgt_strmout_bo_mc[4]; /* unused */ |
dd220a00 MO |
71 | u32 vgt_strmout_bo_offset[4]; |
72 | u32 vgt_strmout_size[4]; | |
961fb597 JG |
73 | u32 db_depth_control; |
74 | u32 db_depth_info; | |
75 | u32 db_depth_size_idx; | |
76 | u32 db_depth_view; | |
77 | u32 db_depth_size; | |
78 | u32 db_offset; | |
79 | struct radeon_bo *db_bo; | |
16790569 | 80 | u64 db_bo_mc; |
779923bc | 81 | bool sx_misc_kill_all_prims; |
3c12513d MO |
82 | bool cb_dirty; |
83 | bool db_dirty; | |
84 | bool streamout_dirty; | |
88f50c80 JG |
85 | struct radeon_bo *htile_bo; |
86 | u64 htile_offset; | |
87 | u32 htile_surface; | |
c8c15ff1 JG |
88 | }; |
89 | ||
fe6f0bd0 MO |
90 | #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 } |
91 | #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 } | |
285484e2 | 92 | #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 4, 0, CHIP_R600 } |
fe6f0bd0 | 93 | #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 } |
285484e2 | 94 | #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 8, 0, CHIP_R600 } |
fe6f0bd0 MO |
95 | #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 } |
96 | #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 } | |
97 | #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 } | |
60b212f8 DA |
98 | |
99 | struct gpu_formats { | |
100 | unsigned blockwidth; | |
101 | unsigned blockheight; | |
102 | unsigned blocksize; | |
103 | unsigned valid_color; | |
fe6f0bd0 | 104 | enum radeon_family min_family; |
60b212f8 DA |
105 | }; |
106 | ||
107 | static const struct gpu_formats color_formats_table[] = { | |
108 | /* 8 bit */ | |
109 | FMT_8_BIT(V_038004_COLOR_8, 1), | |
110 | FMT_8_BIT(V_038004_COLOR_4_4, 1), | |
111 | FMT_8_BIT(V_038004_COLOR_3_3_2, 1), | |
112 | FMT_8_BIT(V_038004_FMT_1, 0), | |
113 | ||
114 | /* 16-bit */ | |
115 | FMT_16_BIT(V_038004_COLOR_16, 1), | |
116 | FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1), | |
117 | FMT_16_BIT(V_038004_COLOR_8_8, 1), | |
118 | FMT_16_BIT(V_038004_COLOR_5_6_5, 1), | |
119 | FMT_16_BIT(V_038004_COLOR_6_5_5, 1), | |
120 | FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1), | |
121 | FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1), | |
122 | FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1), | |
123 | ||
124 | /* 24-bit */ | |
125 | FMT_24_BIT(V_038004_FMT_8_8_8), | |
285484e2 | 126 | |
60b212f8 DA |
127 | /* 32-bit */ |
128 | FMT_32_BIT(V_038004_COLOR_32, 1), | |
129 | FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1), | |
130 | FMT_32_BIT(V_038004_COLOR_16_16, 1), | |
131 | FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1), | |
132 | FMT_32_BIT(V_038004_COLOR_8_24, 1), | |
133 | FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1), | |
134 | FMT_32_BIT(V_038004_COLOR_24_8, 1), | |
135 | FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1), | |
136 | FMT_32_BIT(V_038004_COLOR_10_11_11, 1), | |
137 | FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1), | |
138 | FMT_32_BIT(V_038004_COLOR_11_11_10, 1), | |
139 | FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1), | |
140 | FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1), | |
141 | FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1), | |
142 | FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1), | |
143 | FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0), | |
144 | FMT_32_BIT(V_038004_FMT_32_AS_8, 0), | |
145 | FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0), | |
146 | ||
147 | /* 48-bit */ | |
148 | FMT_48_BIT(V_038004_FMT_16_16_16), | |
149 | FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT), | |
150 | ||
151 | /* 64-bit */ | |
152 | FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1), | |
153 | FMT_64_BIT(V_038004_COLOR_32_32, 1), | |
154 | FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1), | |
155 | FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1), | |
156 | FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1), | |
157 | ||
158 | FMT_96_BIT(V_038004_FMT_32_32_32), | |
159 | FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT), | |
160 | ||
161 | /* 128-bit */ | |
162 | FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1), | |
163 | FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1), | |
164 | ||
165 | [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 }, | |
166 | [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 }, | |
167 | ||
168 | /* block compressed formats */ | |
169 | [V_038004_FMT_BC1] = { 4, 4, 8, 0 }, | |
170 | [V_038004_FMT_BC2] = { 4, 4, 16, 0 }, | |
171 | [V_038004_FMT_BC3] = { 4, 4, 16, 0 }, | |
172 | [V_038004_FMT_BC4] = { 4, 4, 8, 0 }, | |
173 | [V_038004_FMT_BC5] = { 4, 4, 16, 0}, | |
fe6f0bd0 MO |
174 | [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */ |
175 | [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */ | |
60b212f8 | 176 | |
fe6f0bd0 MO |
177 | /* The other Evergreen formats */ |
178 | [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR}, | |
60b212f8 DA |
179 | }; |
180 | ||
285484e2 | 181 | bool r600_fmt_is_valid_color(u32 format) |
60b212f8 | 182 | { |
cf8a47d1 | 183 | if (format >= ARRAY_SIZE(color_formats_table)) |
60b212f8 | 184 | return false; |
285484e2 | 185 | |
60b212f8 DA |
186 | if (color_formats_table[format].valid_color) |
187 | return true; | |
188 | ||
189 | return false; | |
190 | } | |
191 | ||
285484e2 | 192 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family) |
60b212f8 | 193 | { |
cf8a47d1 | 194 | if (format >= ARRAY_SIZE(color_formats_table)) |
60b212f8 | 195 | return false; |
285484e2 | 196 | |
fe6f0bd0 MO |
197 | if (family < color_formats_table[format].min_family) |
198 | return false; | |
199 | ||
60b212f8 DA |
200 | if (color_formats_table[format].blockwidth > 0) |
201 | return true; | |
202 | ||
203 | return false; | |
204 | } | |
205 | ||
285484e2 | 206 | int r600_fmt_get_blocksize(u32 format) |
60b212f8 | 207 | { |
cf8a47d1 | 208 | if (format >= ARRAY_SIZE(color_formats_table)) |
60b212f8 DA |
209 | return 0; |
210 | ||
211 | return color_formats_table[format].blocksize; | |
212 | } | |
213 | ||
285484e2 | 214 | int r600_fmt_get_nblocksx(u32 format, u32 w) |
60b212f8 DA |
215 | { |
216 | unsigned bw; | |
cf8a47d1 DC |
217 | |
218 | if (format >= ARRAY_SIZE(color_formats_table)) | |
60b212f8 DA |
219 | return 0; |
220 | ||
221 | bw = color_formats_table[format].blockwidth; | |
222 | if (bw == 0) | |
223 | return 0; | |
224 | ||
225 | return (w + bw - 1) / bw; | |
226 | } | |
227 | ||
285484e2 | 228 | int r600_fmt_get_nblocksy(u32 format, u32 h) |
60b212f8 DA |
229 | { |
230 | unsigned bh; | |
cf8a47d1 DC |
231 | |
232 | if (format >= ARRAY_SIZE(color_formats_table)) | |
60b212f8 DA |
233 | return 0; |
234 | ||
235 | bh = color_formats_table[format].blockheight; | |
236 | if (bh == 0) | |
237 | return 0; | |
238 | ||
239 | return (h + bh - 1) / bh; | |
240 | } | |
241 | ||
16790569 AD |
242 | struct array_mode_checker { |
243 | int array_mode; | |
244 | u32 group_size; | |
245 | u32 nbanks; | |
246 | u32 npipes; | |
247 | u32 nsamples; | |
60b212f8 | 248 | u32 blocksize; |
16790569 AD |
249 | }; |
250 | ||
251 | /* returns alignment in pixels for pitch/height/depth and bytes for base */ | |
488479eb | 252 | static int r600_get_array_mode_alignment(struct array_mode_checker *values, |
16790569 AD |
253 | u32 *pitch_align, |
254 | u32 *height_align, | |
255 | u32 *depth_align, | |
256 | u64 *base_align) | |
257 | { | |
258 | u32 tile_width = 8; | |
259 | u32 tile_height = 8; | |
260 | u32 macro_tile_width = values->nbanks; | |
261 | u32 macro_tile_height = values->npipes; | |
60b212f8 | 262 | u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples; |
16790569 AD |
263 | u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes; |
264 | ||
265 | switch (values->array_mode) { | |
266 | case ARRAY_LINEAR_GENERAL: | |
267 | /* technically tile_width/_height for pitch/height */ | |
268 | *pitch_align = 1; /* tile_width */ | |
269 | *height_align = 1; /* tile_height */ | |
270 | *depth_align = 1; | |
271 | *base_align = 1; | |
272 | break; | |
273 | case ARRAY_LINEAR_ALIGNED: | |
60b212f8 | 274 | *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize)); |
285484e2 | 275 | *height_align = 1; |
16790569 AD |
276 | *depth_align = 1; |
277 | *base_align = values->group_size; | |
278 | break; | |
279 | case ARRAY_1D_TILED_THIN1: | |
280 | *pitch_align = max((u32)tile_width, | |
281 | (u32)(values->group_size / | |
60b212f8 | 282 | (tile_height * values->blocksize * values->nsamples))); |
16790569 AD |
283 | *height_align = tile_height; |
284 | *depth_align = 1; | |
285 | *base_align = values->group_size; | |
286 | break; | |
287 | case ARRAY_2D_TILED_THIN1: | |
285484e2 JG |
288 | *pitch_align = max((u32)macro_tile_width * tile_width, |
289 | (u32)((values->group_size * values->nbanks) / | |
290 | (values->blocksize * values->nsamples * tile_width))); | |
16790569 AD |
291 | *height_align = macro_tile_height * tile_height; |
292 | *depth_align = 1; | |
293 | *base_align = max(macro_tile_bytes, | |
60b212f8 | 294 | (*pitch_align) * values->blocksize * (*height_align) * values->nsamples); |
16790569 AD |
295 | break; |
296 | default: | |
297 | return -EINVAL; | |
298 | } | |
299 | ||
300 | return 0; | |
301 | } | |
302 | ||
961fb597 JG |
303 | static void r600_cs_track_init(struct r600_cs_track *track) |
304 | { | |
305 | int i; | |
306 | ||
5f77df36 AD |
307 | /* assume DX9 mode */ |
308 | track->sq_config = DX9_CONSTS; | |
961fb597 JG |
309 | for (i = 0; i < 8; i++) { |
310 | track->cb_color_base_last[i] = 0; | |
311 | track->cb_color_size[i] = 0; | |
312 | track->cb_color_size_idx[i] = 0; | |
313 | track->cb_color_info[i] = 0; | |
285484e2 | 314 | track->cb_color_view[i] = 0xFFFFFFFF; |
961fb597 JG |
315 | track->cb_color_bo[i] = NULL; |
316 | track->cb_color_bo_offset[i] = 0xFFFFFFFF; | |
16790569 | 317 | track->cb_color_bo_mc[i] = 0xFFFFFFFF; |
961fb597 JG |
318 | } |
319 | track->cb_target_mask = 0xFFFFFFFF; | |
320 | track->cb_shader_mask = 0xFFFFFFFF; | |
3c12513d | 321 | track->cb_dirty = true; |
961fb597 | 322 | track->db_bo = NULL; |
16790569 | 323 | track->db_bo_mc = 0xFFFFFFFF; |
961fb597 JG |
324 | /* assume the biggest format and that htile is enabled */ |
325 | track->db_depth_info = 7 | (1 << 25); | |
326 | track->db_depth_view = 0xFFFFC000; | |
327 | track->db_depth_size = 0xFFFFFFFF; | |
328 | track->db_depth_size_idx = 0; | |
329 | track->db_depth_control = 0xFFFFFFFF; | |
3c12513d | 330 | track->db_dirty = true; |
88f50c80 JG |
331 | track->htile_bo = NULL; |
332 | track->htile_offset = 0xFFFFFFFF; | |
333 | track->htile_surface = 0; | |
dd220a00 MO |
334 | |
335 | for (i = 0; i < 4; i++) { | |
336 | track->vgt_strmout_size[i] = 0; | |
337 | track->vgt_strmout_bo[i] = NULL; | |
338 | track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF; | |
339 | track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF; | |
340 | } | |
3c12513d | 341 | track->streamout_dirty = true; |
779923bc | 342 | track->sx_misc_kill_all_prims = false; |
961fb597 JG |
343 | } |
344 | ||
488479eb | 345 | static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) |
961fb597 JG |
346 | { |
347 | struct r600_cs_track *track = p->track; | |
60b212f8 | 348 | u32 slice_tile_max, size, tmp; |
16790569 AD |
349 | u32 height, height_align, pitch, pitch_align, depth_align; |
350 | u64 base_offset, base_align; | |
351 | struct array_mode_checker array_check; | |
f2e39221 | 352 | volatile u32 *ib = p->ib.ptr; |
f30df2fa | 353 | unsigned array_mode; |
60b212f8 | 354 | u32 format; |
285484e2 | 355 | |
1729dd33 | 356 | size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i]; |
60b212f8 | 357 | format = G_0280A0_FORMAT(track->cb_color_info[i]); |
285484e2 | 358 | if (!r600_fmt_is_valid_color(format)) { |
961fb597 | 359 | dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n", |
60b212f8 | 360 | __func__, __LINE__, format, |
961fb597 JG |
361 | i, track->cb_color_info[i]); |
362 | return -EINVAL; | |
363 | } | |
16790569 AD |
364 | /* pitch in pixels */ |
365 | pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8; | |
961fb597 | 366 | slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1; |
f30df2fa | 367 | slice_tile_max *= 64; |
16790569 | 368 | height = slice_tile_max / pitch; |
961fb597 JG |
369 | if (height > 8192) |
370 | height = 8192; | |
f30df2fa | 371 | array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]); |
16790569 AD |
372 | |
373 | base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i]; | |
374 | array_check.array_mode = array_mode; | |
375 | array_check.group_size = track->group_size; | |
376 | array_check.nbanks = track->nbanks; | |
377 | array_check.npipes = track->npipes; | |
378 | array_check.nsamples = track->nsamples; | |
285484e2 | 379 | array_check.blocksize = r600_fmt_get_blocksize(format); |
16790569 AD |
380 | if (r600_get_array_mode_alignment(&array_check, |
381 | &pitch_align, &height_align, &depth_align, &base_align)) { | |
382 | dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, | |
383 | G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, | |
384 | track->cb_color_info[i]); | |
385 | return -EINVAL; | |
386 | } | |
f30df2fa | 387 | switch (array_mode) { |
961fb597 | 388 | case V_0280A0_ARRAY_LINEAR_GENERAL: |
40e2a5c1 | 389 | break; |
961fb597 | 390 | case V_0280A0_ARRAY_LINEAR_ALIGNED: |
961fb597 JG |
391 | break; |
392 | case V_0280A0_ARRAY_1D_TILED_THIN1: | |
8f895da5 AD |
393 | /* avoid breaking userspace */ |
394 | if (height > 7) | |
395 | height &= ~0x7; | |
961fb597 JG |
396 | break; |
397 | case V_0280A0_ARRAY_2D_TILED_THIN1: | |
961fb597 JG |
398 | break; |
399 | default: | |
400 | dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, | |
401 | G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, | |
402 | track->cb_color_info[i]); | |
403 | return -EINVAL; | |
404 | } | |
16790569 AD |
405 | |
406 | if (!IS_ALIGNED(pitch, pitch_align)) { | |
c2049b3d AD |
407 | dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n", |
408 | __func__, __LINE__, pitch, pitch_align, array_mode); | |
16790569 AD |
409 | return -EINVAL; |
410 | } | |
411 | if (!IS_ALIGNED(height, height_align)) { | |
c2049b3d AD |
412 | dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n", |
413 | __func__, __LINE__, height, height_align, array_mode); | |
16790569 AD |
414 | return -EINVAL; |
415 | } | |
416 | if (!IS_ALIGNED(base_offset, base_align)) { | |
c2049b3d AD |
417 | dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i, |
418 | base_offset, base_align, array_mode); | |
16790569 AD |
419 | return -EINVAL; |
420 | } | |
421 | ||
961fb597 | 422 | /* check offset */ |
fcdeefe4 MO |
423 | tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) * |
424 | r600_fmt_get_blocksize(format) * track->nsamples; | |
285484e2 JG |
425 | switch (array_mode) { |
426 | default: | |
427 | case V_0280A0_ARRAY_LINEAR_GENERAL: | |
428 | case V_0280A0_ARRAY_LINEAR_ALIGNED: | |
429 | tmp += track->cb_color_view[i] & 0xFF; | |
430 | break; | |
431 | case V_0280A0_ARRAY_1D_TILED_THIN1: | |
432 | case V_0280A0_ARRAY_2D_TILED_THIN1: | |
433 | tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp; | |
434 | break; | |
435 | } | |
961fb597 | 436 | if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { |
f30df2fa DA |
437 | if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) { |
438 | /* the initial DDX does bad things with the CB size occasionally */ | |
439 | /* it rounds up height too far for slice tile max but the BO is smaller */ | |
a1a82133 AD |
440 | /* r600c,g also seem to flush at bad times in some apps resulting in |
441 | * bogus values here. So for linear just allow anything to avoid breaking | |
442 | * broken userspace. | |
443 | */ | |
f30df2fa | 444 | } else { |
c116cc94 | 445 | dev_warn(p->dev, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n", |
285484e2 | 446 | __func__, i, array_mode, |
c2049b3d | 447 | track->cb_color_bo_offset[i], tmp, |
285484e2 JG |
448 | radeon_bo_size(track->cb_color_bo[i]), |
449 | pitch, height, r600_fmt_get_nblocksx(format, pitch), | |
450 | r600_fmt_get_nblocksy(format, height), | |
451 | r600_fmt_get_blocksize(format)); | |
f30df2fa DA |
452 | return -EINVAL; |
453 | } | |
40e2a5c1 | 454 | } |
961fb597 | 455 | /* limit max tile */ |
16790569 | 456 | tmp = (height * pitch) >> 6; |
961fb597 JG |
457 | if (tmp < slice_tile_max) |
458 | slice_tile_max = tmp; | |
16790569 | 459 | tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) | |
961fb597 JG |
460 | S_028060_SLICE_TILE_MAX(slice_tile_max - 1); |
461 | ib[track->cb_color_size_idx[i]] = tmp; | |
c116cc94 MO |
462 | |
463 | /* FMASK/CMASK */ | |
464 | switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) { | |
465 | case V_0280A0_TILE_DISABLE: | |
466 | break; | |
467 | case V_0280A0_FRAG_ENABLE: | |
468 | if (track->nsamples > 1) { | |
469 | uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]); | |
470 | /* the tile size is 8x8, but the size is in units of bits. | |
471 | * for bytes, do just * 8. */ | |
472 | uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1); | |
473 | ||
474 | if (bytes + track->cb_color_frag_offset[i] > | |
475 | radeon_bo_size(track->cb_color_frag_bo[i])) { | |
476 | dev_warn(p->dev, "%s FMASK_TILE_MAX too large " | |
477 | "(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n", | |
478 | __func__, tile_max, bytes, | |
479 | track->cb_color_frag_offset[i], | |
480 | radeon_bo_size(track->cb_color_frag_bo[i])); | |
481 | return -EINVAL; | |
482 | } | |
483 | } | |
484 | /* fall through */ | |
485 | case V_0280A0_CLEAR_ENABLE: | |
486 | { | |
487 | uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]); | |
488 | /* One block = 128x128 pixels, one 8x8 tile has 4 bits.. | |
489 | * (128*128) / (8*8) / 2 = 128 bytes per block. */ | |
490 | uint32_t bytes = (block_max + 1) * 128; | |
491 | ||
492 | if (bytes + track->cb_color_tile_offset[i] > | |
493 | radeon_bo_size(track->cb_color_tile_bo[i])) { | |
494 | dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large " | |
495 | "(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n", | |
496 | __func__, block_max, bytes, | |
497 | track->cb_color_tile_offset[i], | |
498 | radeon_bo_size(track->cb_color_tile_bo[i])); | |
499 | return -EINVAL; | |
500 | } | |
501 | break; | |
502 | } | |
503 | default: | |
504 | dev_warn(p->dev, "%s invalid tile mode\n", __func__); | |
505 | return -EINVAL; | |
506 | } | |
961fb597 JG |
507 | return 0; |
508 | } | |
509 | ||
88f50c80 JG |
510 | static int r600_cs_track_validate_db(struct radeon_cs_parser *p) |
511 | { | |
512 | struct r600_cs_track *track = p->track; | |
513 | u32 nviews, bpe, ntiles, size, slice_tile_max, tmp; | |
514 | u32 height_align, pitch_align, depth_align; | |
515 | u32 pitch = 8192; | |
516 | u32 height = 8192; | |
517 | u64 base_offset, base_align; | |
518 | struct array_mode_checker array_check; | |
519 | int array_mode; | |
f2e39221 | 520 | volatile u32 *ib = p->ib.ptr; |
88f50c80 JG |
521 | |
522 | ||
523 | if (track->db_bo == NULL) { | |
524 | dev_warn(p->dev, "z/stencil with no depth buffer\n"); | |
525 | return -EINVAL; | |
526 | } | |
527 | switch (G_028010_FORMAT(track->db_depth_info)) { | |
528 | case V_028010_DEPTH_16: | |
529 | bpe = 2; | |
530 | break; | |
531 | case V_028010_DEPTH_X8_24: | |
532 | case V_028010_DEPTH_8_24: | |
533 | case V_028010_DEPTH_X8_24_FLOAT: | |
534 | case V_028010_DEPTH_8_24_FLOAT: | |
535 | case V_028010_DEPTH_32_FLOAT: | |
536 | bpe = 4; | |
537 | break; | |
538 | case V_028010_DEPTH_X24_8_32_FLOAT: | |
539 | bpe = 8; | |
540 | break; | |
541 | default: | |
542 | dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info)); | |
543 | return -EINVAL; | |
544 | } | |
545 | if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) { | |
546 | if (!track->db_depth_size_idx) { | |
547 | dev_warn(p->dev, "z/stencil buffer size not set\n"); | |
548 | return -EINVAL; | |
549 | } | |
550 | tmp = radeon_bo_size(track->db_bo) - track->db_offset; | |
551 | tmp = (tmp / bpe) >> 6; | |
552 | if (!tmp) { | |
553 | dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n", | |
554 | track->db_depth_size, bpe, track->db_offset, | |
555 | radeon_bo_size(track->db_bo)); | |
556 | return -EINVAL; | |
557 | } | |
558 | ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF); | |
559 | } else { | |
560 | size = radeon_bo_size(track->db_bo); | |
561 | /* pitch in pixels */ | |
562 | pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8; | |
563 | slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; | |
564 | slice_tile_max *= 64; | |
565 | height = slice_tile_max / pitch; | |
566 | if (height > 8192) | |
567 | height = 8192; | |
568 | base_offset = track->db_bo_mc + track->db_offset; | |
569 | array_mode = G_028010_ARRAY_MODE(track->db_depth_info); | |
570 | array_check.array_mode = array_mode; | |
571 | array_check.group_size = track->group_size; | |
572 | array_check.nbanks = track->nbanks; | |
573 | array_check.npipes = track->npipes; | |
574 | array_check.nsamples = track->nsamples; | |
575 | array_check.blocksize = bpe; | |
576 | if (r600_get_array_mode_alignment(&array_check, | |
577 | &pitch_align, &height_align, &depth_align, &base_align)) { | |
578 | dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, | |
579 | G_028010_ARRAY_MODE(track->db_depth_info), | |
580 | track->db_depth_info); | |
581 | return -EINVAL; | |
582 | } | |
583 | switch (array_mode) { | |
584 | case V_028010_ARRAY_1D_TILED_THIN1: | |
585 | /* don't break userspace */ | |
586 | height &= ~0x7; | |
587 | break; | |
588 | case V_028010_ARRAY_2D_TILED_THIN1: | |
589 | break; | |
590 | default: | |
591 | dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, | |
592 | G_028010_ARRAY_MODE(track->db_depth_info), | |
593 | track->db_depth_info); | |
594 | return -EINVAL; | |
595 | } | |
596 | ||
597 | if (!IS_ALIGNED(pitch, pitch_align)) { | |
598 | dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n", | |
599 | __func__, __LINE__, pitch, pitch_align, array_mode); | |
600 | return -EINVAL; | |
601 | } | |
602 | if (!IS_ALIGNED(height, height_align)) { | |
603 | dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n", | |
604 | __func__, __LINE__, height, height_align, array_mode); | |
605 | return -EINVAL; | |
606 | } | |
607 | if (!IS_ALIGNED(base_offset, base_align)) { | |
608 | dev_warn(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__, | |
609 | base_offset, base_align, array_mode); | |
610 | return -EINVAL; | |
611 | } | |
612 | ||
613 | ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; | |
614 | nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; | |
fcdeefe4 | 615 | tmp = ntiles * bpe * 64 * nviews * track->nsamples; |
88f50c80 JG |
616 | if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { |
617 | dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n", | |
618 | array_mode, | |
619 | track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, | |
620 | radeon_bo_size(track->db_bo)); | |
621 | return -EINVAL; | |
622 | } | |
623 | } | |
624 | ||
625 | /* hyperz */ | |
626 | if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) { | |
627 | unsigned long size; | |
628 | unsigned nbx, nby; | |
629 | ||
630 | if (track->htile_bo == NULL) { | |
631 | dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n", | |
632 | __func__, __LINE__, track->db_depth_info); | |
633 | return -EINVAL; | |
634 | } | |
635 | if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) { | |
636 | dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n", | |
637 | __func__, __LINE__, track->db_depth_size); | |
638 | return -EINVAL; | |
639 | } | |
640 | ||
641 | nbx = pitch; | |
642 | nby = height; | |
643 | if (G_028D24_LINEAR(track->htile_surface)) { | |
644 | /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */ | |
645 | nbx = round_up(nbx, 16 * 8); | |
646 | /* nby is npipes htiles aligned == npipes * 8 pixel aligned */ | |
647 | nby = round_up(nby, track->npipes * 8); | |
648 | } else { | |
649 | /* htile widht & nby (8 or 4) make 2 bits number */ | |
650 | tmp = track->htile_surface & 3; | |
651 | /* align is htile align * 8, htile align vary according to | |
652 | * number of pipe and tile width and nby | |
653 | */ | |
654 | switch (track->npipes) { | |
655 | case 8: | |
656 | switch (tmp) { | |
657 | case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ | |
658 | nbx = round_up(nbx, 64 * 8); | |
659 | nby = round_up(nby, 64 * 8); | |
660 | break; | |
661 | case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/ | |
662 | case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/ | |
663 | nbx = round_up(nbx, 64 * 8); | |
664 | nby = round_up(nby, 32 * 8); | |
665 | break; | |
666 | case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/ | |
667 | nbx = round_up(nbx, 32 * 8); | |
668 | nby = round_up(nby, 32 * 8); | |
669 | break; | |
670 | default: | |
671 | return -EINVAL; | |
672 | } | |
673 | break; | |
674 | case 4: | |
675 | switch (tmp) { | |
676 | case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ | |
677 | nbx = round_up(nbx, 64 * 8); | |
678 | nby = round_up(nby, 32 * 8); | |
679 | break; | |
680 | case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/ | |
681 | case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/ | |
682 | nbx = round_up(nbx, 32 * 8); | |
683 | nby = round_up(nby, 32 * 8); | |
684 | break; | |
685 | case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/ | |
686 | nbx = round_up(nbx, 32 * 8); | |
687 | nby = round_up(nby, 16 * 8); | |
688 | break; | |
689 | default: | |
690 | return -EINVAL; | |
691 | } | |
692 | break; | |
693 | case 2: | |
694 | switch (tmp) { | |
695 | case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ | |
696 | nbx = round_up(nbx, 32 * 8); | |
697 | nby = round_up(nby, 32 * 8); | |
698 | break; | |
699 | case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/ | |
700 | case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/ | |
701 | nbx = round_up(nbx, 32 * 8); | |
702 | nby = round_up(nby, 16 * 8); | |
703 | break; | |
704 | case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/ | |
705 | nbx = round_up(nbx, 16 * 8); | |
706 | nby = round_up(nby, 16 * 8); | |
707 | break; | |
708 | default: | |
709 | return -EINVAL; | |
710 | } | |
711 | break; | |
712 | case 1: | |
713 | switch (tmp) { | |
714 | case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ | |
715 | nbx = round_up(nbx, 32 * 8); | |
716 | nby = round_up(nby, 16 * 8); | |
717 | break; | |
718 | case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/ | |
719 | case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/ | |
720 | nbx = round_up(nbx, 16 * 8); | |
721 | nby = round_up(nby, 16 * 8); | |
722 | break; | |
723 | case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/ | |
724 | nbx = round_up(nbx, 16 * 8); | |
725 | nby = round_up(nby, 8 * 8); | |
726 | break; | |
727 | default: | |
728 | return -EINVAL; | |
729 | } | |
730 | break; | |
731 | default: | |
732 | dev_warn(p->dev, "%s:%d invalid num pipes %d\n", | |
733 | __func__, __LINE__, track->npipes); | |
734 | return -EINVAL; | |
735 | } | |
736 | } | |
737 | /* compute number of htile */ | |
738 | nbx = G_028D24_HTILE_WIDTH(track->htile_surface) ? nbx / 8 : nbx / 4; | |
739 | nby = G_028D24_HTILE_HEIGHT(track->htile_surface) ? nby / 8 : nby / 4; | |
740 | size = nbx * nby * 4; | |
741 | size += track->htile_offset; | |
742 | ||
743 | if (size > radeon_bo_size(track->htile_bo)) { | |
744 | dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n", | |
745 | __func__, __LINE__, radeon_bo_size(track->htile_bo), | |
746 | size, nbx, nby); | |
747 | return -EINVAL; | |
748 | } | |
749 | } | |
750 | ||
751 | track->db_dirty = false; | |
752 | return 0; | |
753 | } | |
754 | ||
961fb597 JG |
755 | static int r600_cs_track_check(struct radeon_cs_parser *p) |
756 | { | |
757 | struct r600_cs_track *track = p->track; | |
758 | u32 tmp; | |
759 | int r, i; | |
961fb597 JG |
760 | |
761 | /* on legacy kernel we don't perform advanced check */ | |
762 | if (p->rdev == NULL) | |
763 | return 0; | |
dd220a00 MO |
764 | |
765 | /* check streamout */ | |
3c12513d | 766 | if (track->streamout_dirty && track->vgt_strmout_en) { |
dd220a00 MO |
767 | for (i = 0; i < 4; i++) { |
768 | if (track->vgt_strmout_buffer_en & (1 << i)) { | |
769 | if (track->vgt_strmout_bo[i]) { | |
770 | u64 offset = (u64)track->vgt_strmout_bo_offset[i] + | |
771 | (u64)track->vgt_strmout_size[i]; | |
772 | if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) { | |
773 | DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n", | |
774 | i, offset, | |
775 | radeon_bo_size(track->vgt_strmout_bo[i])); | |
776 | return -EINVAL; | |
777 | } | |
778 | } else { | |
779 | dev_warn(p->dev, "No buffer for streamout %d\n", i); | |
780 | return -EINVAL; | |
781 | } | |
782 | } | |
783 | } | |
3c12513d | 784 | track->streamout_dirty = false; |
961fb597 | 785 | } |
dd220a00 | 786 | |
779923bc MO |
787 | if (track->sx_misc_kill_all_prims) |
788 | return 0; | |
789 | ||
961fb597 JG |
790 | /* check that we have a cb for each enabled target, we don't check |
791 | * shader_mask because it seems mesa isn't always setting it :( | |
792 | */ | |
3c12513d MO |
793 | if (track->cb_dirty) { |
794 | tmp = track->cb_target_mask; | |
795 | for (i = 0; i < 8; i++) { | |
796 | if ((tmp >> (i * 4)) & 0xF) { | |
797 | /* at least one component is enabled */ | |
798 | if (track->cb_color_bo[i] == NULL) { | |
799 | dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", | |
800 | __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); | |
801 | return -EINVAL; | |
802 | } | |
803 | /* perform rewrite of CB_COLOR[0-7]_SIZE */ | |
804 | r = r600_cs_track_validate_cb(p, i); | |
805 | if (r) | |
806 | return r; | |
961fb597 | 807 | } |
961fb597 | 808 | } |
3c12513d | 809 | track->cb_dirty = false; |
961fb597 | 810 | } |
3c12513d | 811 | |
88f50c80 | 812 | /* Check depth buffer */ |
0f457e48 MO |
813 | if (track->db_dirty && |
814 | G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID && | |
815 | (G_028800_STENCIL_ENABLE(track->db_depth_control) || | |
816 | G_028800_Z_ENABLE(track->db_depth_control))) { | |
88f50c80 JG |
817 | r = r600_cs_track_validate_db(p); |
818 | if (r) | |
819 | return r; | |
961fb597 | 820 | } |
88f50c80 | 821 | |
961fb597 JG |
822 | return 0; |
823 | } | |
824 | ||
3ce0a23d JG |
825 | /** |
826 | * r600_cs_packet_parse() - parse cp packet and point ib index to next packet | |
827 | * @parser: parser structure holding parsing context. | |
828 | * @pkt: where to store packet informations | |
829 | * | |
830 | * Assume that chunk_ib_index is properly set. Will return -EINVAL | |
831 | * if packet is bigger than remaining ib size. or if packets is unknown. | |
832 | **/ | |
833 | int r600_cs_packet_parse(struct radeon_cs_parser *p, | |
834 | struct radeon_cs_packet *pkt, | |
835 | unsigned idx) | |
836 | { | |
837 | struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; | |
838 | uint32_t header; | |
839 | ||
840 | if (idx >= ib_chunk->length_dw) { | |
841 | DRM_ERROR("Can not parse packet at %d after CS end %d !\n", | |
842 | idx, ib_chunk->length_dw); | |
843 | return -EINVAL; | |
844 | } | |
513bcb46 | 845 | header = radeon_get_ib_value(p, idx); |
3ce0a23d JG |
846 | pkt->idx = idx; |
847 | pkt->type = CP_PACKET_GET_TYPE(header); | |
848 | pkt->count = CP_PACKET_GET_COUNT(header); | |
849 | pkt->one_reg_wr = 0; | |
850 | switch (pkt->type) { | |
851 | case PACKET_TYPE0: | |
852 | pkt->reg = CP_PACKET0_GET_REG(header); | |
853 | break; | |
854 | case PACKET_TYPE3: | |
855 | pkt->opcode = CP_PACKET3_GET_OPCODE(header); | |
856 | break; | |
857 | case PACKET_TYPE2: | |
858 | pkt->count = -1; | |
859 | break; | |
860 | default: | |
861 | DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); | |
862 | return -EINVAL; | |
863 | } | |
864 | if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { | |
865 | DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", | |
866 | pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); | |
867 | return -EINVAL; | |
868 | } | |
869 | return 0; | |
870 | } | |
871 | ||
872 | /** | |
873 | * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3 | |
874 | * @parser: parser structure holding parsing context. | |
875 | * @data: pointer to relocation data | |
876 | * @offset_start: starting offset | |
877 | * @offset_mask: offset mask (to align start offset on) | |
878 | * @reloc: reloc informations | |
879 | * | |
880 | * Check next packet is relocation packet3, do bo validation and compute | |
881 | * GPU offset using the provided start. | |
882 | **/ | |
883 | static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, | |
884 | struct radeon_cs_reloc **cs_reloc) | |
885 | { | |
3ce0a23d JG |
886 | struct radeon_cs_chunk *relocs_chunk; |
887 | struct radeon_cs_packet p3reloc; | |
888 | unsigned idx; | |
889 | int r; | |
890 | ||
891 | if (p->chunk_relocs_idx == -1) { | |
892 | DRM_ERROR("No relocation chunk !\n"); | |
893 | return -EINVAL; | |
894 | } | |
895 | *cs_reloc = NULL; | |
3ce0a23d JG |
896 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; |
897 | r = r600_cs_packet_parse(p, &p3reloc, p->idx); | |
898 | if (r) { | |
899 | return r; | |
900 | } | |
901 | p->idx += p3reloc.count + 2; | |
902 | if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { | |
903 | DRM_ERROR("No packet3 for relocation for packet at %d.\n", | |
904 | p3reloc.idx); | |
905 | return -EINVAL; | |
906 | } | |
513bcb46 | 907 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); |
3ce0a23d JG |
908 | if (idx >= relocs_chunk->length_dw) { |
909 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", | |
910 | idx, relocs_chunk->length_dw); | |
911 | return -EINVAL; | |
912 | } | |
913 | /* FIXME: we assume reloc size is 4 dwords */ | |
914 | *cs_reloc = p->relocs_ptr[(idx / 4)]; | |
915 | return 0; | |
916 | } | |
917 | ||
918 | /** | |
919 | * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3 | |
920 | * @parser: parser structure holding parsing context. | |
921 | * @data: pointer to relocation data | |
922 | * @offset_start: starting offset | |
923 | * @offset_mask: offset mask (to align start offset on) | |
924 | * @reloc: reloc informations | |
925 | * | |
926 | * Check next packet is relocation packet3, do bo validation and compute | |
927 | * GPU offset using the provided start. | |
928 | **/ | |
929 | static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, | |
930 | struct radeon_cs_reloc **cs_reloc) | |
931 | { | |
3ce0a23d JG |
932 | struct radeon_cs_chunk *relocs_chunk; |
933 | struct radeon_cs_packet p3reloc; | |
934 | unsigned idx; | |
935 | int r; | |
936 | ||
937 | if (p->chunk_relocs_idx == -1) { | |
938 | DRM_ERROR("No relocation chunk !\n"); | |
939 | return -EINVAL; | |
940 | } | |
941 | *cs_reloc = NULL; | |
3ce0a23d JG |
942 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; |
943 | r = r600_cs_packet_parse(p, &p3reloc, p->idx); | |
944 | if (r) { | |
945 | return r; | |
946 | } | |
947 | p->idx += p3reloc.count + 2; | |
948 | if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { | |
949 | DRM_ERROR("No packet3 for relocation for packet at %d.\n", | |
950 | p3reloc.idx); | |
951 | return -EINVAL; | |
952 | } | |
513bcb46 | 953 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); |
3ce0a23d JG |
954 | if (idx >= relocs_chunk->length_dw) { |
955 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", | |
956 | idx, relocs_chunk->length_dw); | |
957 | return -EINVAL; | |
958 | } | |
e265f39e | 959 | *cs_reloc = p->relocs; |
3ce0a23d JG |
960 | (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32; |
961 | (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0]; | |
962 | return 0; | |
963 | } | |
964 | ||
c8c15ff1 JG |
965 | /** |
966 | * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc | |
967 | * @parser: parser structure holding parsing context. | |
968 | * | |
969 | * Check next packet is relocation packet3, do bo validation and compute | |
970 | * GPU offset using the provided start. | |
971 | **/ | |
488479eb | 972 | static int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p) |
c8c15ff1 JG |
973 | { |
974 | struct radeon_cs_packet p3reloc; | |
975 | int r; | |
976 | ||
977 | r = r600_cs_packet_parse(p, &p3reloc, p->idx); | |
978 | if (r) { | |
979 | return 0; | |
980 | } | |
981 | if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { | |
982 | return 0; | |
983 | } | |
984 | return 1; | |
985 | } | |
986 | ||
2f67c6e0 AD |
987 | /** |
988 | * r600_cs_packet_next_vline() - parse userspace VLINE packet | |
989 | * @parser: parser structure holding parsing context. | |
990 | * | |
991 | * Userspace sends a special sequence for VLINE waits. | |
992 | * PACKET0 - VLINE_START_END + value | |
993 | * PACKET3 - WAIT_REG_MEM poll vline status reg | |
994 | * RELOC (P3) - crtc_id in reloc. | |
995 | * | |
996 | * This function parses this and relocates the VLINE START END | |
997 | * and WAIT_REG_MEM packets to the correct crtc. | |
998 | * It also detects a switched off crtc and nulls out the | |
999 | * wait in that case. | |
1000 | */ | |
1001 | static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p) | |
1002 | { | |
1003 | struct drm_mode_object *obj; | |
1004 | struct drm_crtc *crtc; | |
1005 | struct radeon_crtc *radeon_crtc; | |
1006 | struct radeon_cs_packet p3reloc, wait_reg_mem; | |
1007 | int crtc_id; | |
1008 | int r; | |
1009 | uint32_t header, h_idx, reg, wait_reg_mem_info; | |
1010 | volatile uint32_t *ib; | |
1011 | ||
f2e39221 | 1012 | ib = p->ib.ptr; |
2f67c6e0 AD |
1013 | |
1014 | /* parse the WAIT_REG_MEM */ | |
1015 | r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx); | |
1016 | if (r) | |
1017 | return r; | |
1018 | ||
1019 | /* check its a WAIT_REG_MEM */ | |
1020 | if (wait_reg_mem.type != PACKET_TYPE3 || | |
1021 | wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { | |
1022 | DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n"); | |
a3a88a66 | 1023 | return -EINVAL; |
2f67c6e0 AD |
1024 | } |
1025 | ||
1026 | wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); | |
1027 | /* bit 4 is reg (0) or mem (1) */ | |
1028 | if (wait_reg_mem_info & 0x10) { | |
1029 | DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n"); | |
a3a88a66 | 1030 | return -EINVAL; |
2f67c6e0 AD |
1031 | } |
1032 | /* waiting for value to be equal */ | |
1033 | if ((wait_reg_mem_info & 0x7) != 0x3) { | |
1034 | DRM_ERROR("vline WAIT_REG_MEM function not equal\n"); | |
a3a88a66 | 1035 | return -EINVAL; |
2f67c6e0 AD |
1036 | } |
1037 | if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) { | |
1038 | DRM_ERROR("vline WAIT_REG_MEM bad reg\n"); | |
a3a88a66 | 1039 | return -EINVAL; |
2f67c6e0 AD |
1040 | } |
1041 | ||
1042 | if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) { | |
1043 | DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n"); | |
a3a88a66 | 1044 | return -EINVAL; |
2f67c6e0 AD |
1045 | } |
1046 | ||
1047 | /* jump over the NOP */ | |
1048 | r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2); | |
1049 | if (r) | |
1050 | return r; | |
1051 | ||
1052 | h_idx = p->idx - 2; | |
1053 | p->idx += wait_reg_mem.count + 2; | |
1054 | p->idx += p3reloc.count + 2; | |
1055 | ||
1056 | header = radeon_get_ib_value(p, h_idx); | |
1057 | crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); | |
d4ac6a05 | 1058 | reg = CP_PACKET0_GET_REG(header); |
29508eb6 | 1059 | |
2f67c6e0 AD |
1060 | obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); |
1061 | if (!obj) { | |
1062 | DRM_ERROR("cannot find crtc %d\n", crtc_id); | |
a3a88a66 | 1063 | return -EINVAL; |
2f67c6e0 AD |
1064 | } |
1065 | crtc = obj_to_crtc(obj); | |
1066 | radeon_crtc = to_radeon_crtc(crtc); | |
1067 | crtc_id = radeon_crtc->crtc_id; | |
1068 | ||
1069 | if (!crtc->enabled) { | |
1070 | /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */ | |
1071 | ib[h_idx + 2] = PACKET2(0); | |
1072 | ib[h_idx + 3] = PACKET2(0); | |
1073 | ib[h_idx + 4] = PACKET2(0); | |
1074 | ib[h_idx + 5] = PACKET2(0); | |
1075 | ib[h_idx + 6] = PACKET2(0); | |
1076 | ib[h_idx + 7] = PACKET2(0); | |
1077 | ib[h_idx + 8] = PACKET2(0); | |
1078 | } else if (crtc_id == 1) { | |
1079 | switch (reg) { | |
1080 | case AVIVO_D1MODE_VLINE_START_END: | |
1081 | header &= ~R600_CP_PACKET0_REG_MASK; | |
1082 | header |= AVIVO_D2MODE_VLINE_START_END >> 2; | |
1083 | break; | |
1084 | default: | |
1085 | DRM_ERROR("unknown crtc reloc\n"); | |
a3a88a66 | 1086 | return -EINVAL; |
2f67c6e0 AD |
1087 | } |
1088 | ib[h_idx] = header; | |
1089 | ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2; | |
1090 | } | |
a3a88a66 PB |
1091 | |
1092 | return 0; | |
2f67c6e0 AD |
1093 | } |
1094 | ||
3ce0a23d JG |
1095 | static int r600_packet0_check(struct radeon_cs_parser *p, |
1096 | struct radeon_cs_packet *pkt, | |
1097 | unsigned idx, unsigned reg) | |
1098 | { | |
2f67c6e0 AD |
1099 | int r; |
1100 | ||
3ce0a23d JG |
1101 | switch (reg) { |
1102 | case AVIVO_D1MODE_VLINE_START_END: | |
2f67c6e0 AD |
1103 | r = r600_cs_packet_parse_vline(p); |
1104 | if (r) { | |
1105 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1106 | idx, reg); | |
1107 | return r; | |
1108 | } | |
3ce0a23d JG |
1109 | break; |
1110 | default: | |
1111 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", | |
1112 | reg, idx); | |
1113 | return -EINVAL; | |
1114 | } | |
1115 | return 0; | |
1116 | } | |
1117 | ||
1118 | static int r600_cs_parse_packet0(struct radeon_cs_parser *p, | |
1119 | struct radeon_cs_packet *pkt) | |
1120 | { | |
1121 | unsigned reg, i; | |
1122 | unsigned idx; | |
1123 | int r; | |
1124 | ||
1125 | idx = pkt->idx + 1; | |
1126 | reg = pkt->reg; | |
1127 | for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { | |
1128 | r = r600_packet0_check(p, pkt, idx, reg); | |
1129 | if (r) { | |
1130 | return r; | |
1131 | } | |
1132 | } | |
1133 | return 0; | |
1134 | } | |
1135 | ||
961fb597 JG |
1136 | /** |
1137 | * r600_cs_check_reg() - check if register is authorized or not | |
1138 | * @parser: parser structure holding parsing context | |
1139 | * @reg: register we are testing | |
1140 | * @idx: index into the cs buffer | |
1141 | * | |
1142 | * This function will test against r600_reg_safe_bm and return 0 | |
1143 | * if register is safe. If register is not flag as safe this function | |
1144 | * will test it against a list of register needind special handling. | |
1145 | */ | |
488479eb | 1146 | static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) |
961fb597 JG |
1147 | { |
1148 | struct r600_cs_track *track = (struct r600_cs_track *)p->track; | |
1149 | struct radeon_cs_reloc *reloc; | |
961fb597 JG |
1150 | u32 m, i, tmp, *ib; |
1151 | int r; | |
1152 | ||
1153 | i = (reg >> 7); | |
88498839 | 1154 | if (i >= ARRAY_SIZE(r600_reg_safe_bm)) { |
961fb597 JG |
1155 | dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); |
1156 | return -EINVAL; | |
1157 | } | |
1158 | m = 1 << ((reg >> 2) & 31); | |
1159 | if (!(r600_reg_safe_bm[i] & m)) | |
1160 | return 0; | |
f2e39221 | 1161 | ib = p->ib.ptr; |
961fb597 | 1162 | switch (reg) { |
25985edc | 1163 | /* force following reg to 0 in an attempt to disable out buffer |
961fb597 JG |
1164 | * which will need us to better understand how it works to perform |
1165 | * security check on it (Jerome) | |
1166 | */ | |
1167 | case R_0288A8_SQ_ESGS_RING_ITEMSIZE: | |
1168 | case R_008C44_SQ_ESGS_RING_SIZE: | |
1169 | case R_0288B0_SQ_ESTMP_RING_ITEMSIZE: | |
1170 | case R_008C54_SQ_ESTMP_RING_SIZE: | |
1171 | case R_0288C0_SQ_FBUF_RING_ITEMSIZE: | |
1172 | case R_008C74_SQ_FBUF_RING_SIZE: | |
1173 | case R_0288B4_SQ_GSTMP_RING_ITEMSIZE: | |
1174 | case R_008C5C_SQ_GSTMP_RING_SIZE: | |
1175 | case R_0288AC_SQ_GSVS_RING_ITEMSIZE: | |
1176 | case R_008C4C_SQ_GSVS_RING_SIZE: | |
1177 | case R_0288BC_SQ_PSTMP_RING_ITEMSIZE: | |
1178 | case R_008C6C_SQ_PSTMP_RING_SIZE: | |
1179 | case R_0288C4_SQ_REDUC_RING_ITEMSIZE: | |
1180 | case R_008C7C_SQ_REDUC_RING_SIZE: | |
1181 | case R_0288B8_SQ_VSTMP_RING_ITEMSIZE: | |
1182 | case R_008C64_SQ_VSTMP_RING_SIZE: | |
1183 | case R_0288C8_SQ_GS_VERT_ITEMSIZE: | |
1184 | /* get value to populate the IB don't remove */ | |
1185 | tmp =radeon_get_ib_value(p, idx); | |
1186 | ib[idx] = 0; | |
1187 | break; | |
5f77df36 AD |
1188 | case SQ_CONFIG: |
1189 | track->sq_config = radeon_get_ib_value(p, idx); | |
1190 | break; | |
961fb597 JG |
1191 | case R_028800_DB_DEPTH_CONTROL: |
1192 | track->db_depth_control = radeon_get_ib_value(p, idx); | |
3c12513d | 1193 | track->db_dirty = true; |
961fb597 JG |
1194 | break; |
1195 | case R_028010_DB_DEPTH_INFO: | |
721604a1 | 1196 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) && |
e70f224c | 1197 | r600_cs_packet_next_is_pkt3_nop(p)) { |
7f813377 AD |
1198 | r = r600_cs_packet_next_reloc(p, &reloc); |
1199 | if (r) { | |
1200 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1201 | "0x%04X\n", reg); | |
1202 | return -EINVAL; | |
1203 | } | |
1204 | track->db_depth_info = radeon_get_ib_value(p, idx); | |
1205 | ib[idx] &= C_028010_ARRAY_MODE; | |
1206 | track->db_depth_info &= C_028010_ARRAY_MODE; | |
1207 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { | |
1208 | ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); | |
1209 | track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); | |
1210 | } else { | |
1211 | ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); | |
1212 | track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); | |
1213 | } | |
3c12513d | 1214 | } else { |
7f813377 | 1215 | track->db_depth_info = radeon_get_ib_value(p, idx); |
3c12513d MO |
1216 | } |
1217 | track->db_dirty = true; | |
961fb597 JG |
1218 | break; |
1219 | case R_028004_DB_DEPTH_VIEW: | |
1220 | track->db_depth_view = radeon_get_ib_value(p, idx); | |
3c12513d | 1221 | track->db_dirty = true; |
961fb597 JG |
1222 | break; |
1223 | case R_028000_DB_DEPTH_SIZE: | |
1224 | track->db_depth_size = radeon_get_ib_value(p, idx); | |
1225 | track->db_depth_size_idx = idx; | |
3c12513d | 1226 | track->db_dirty = true; |
961fb597 JG |
1227 | break; |
1228 | case R_028AB0_VGT_STRMOUT_EN: | |
1229 | track->vgt_strmout_en = radeon_get_ib_value(p, idx); | |
3c12513d | 1230 | track->streamout_dirty = true; |
961fb597 JG |
1231 | break; |
1232 | case R_028B20_VGT_STRMOUT_BUFFER_EN: | |
1233 | track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx); | |
3c12513d | 1234 | track->streamout_dirty = true; |
961fb597 | 1235 | break; |
dd220a00 MO |
1236 | case VGT_STRMOUT_BUFFER_BASE_0: |
1237 | case VGT_STRMOUT_BUFFER_BASE_1: | |
1238 | case VGT_STRMOUT_BUFFER_BASE_2: | |
1239 | case VGT_STRMOUT_BUFFER_BASE_3: | |
1240 | r = r600_cs_packet_next_reloc(p, &reloc); | |
1241 | if (r) { | |
1242 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1243 | "0x%04X\n", reg); | |
1244 | return -EINVAL; | |
1245 | } | |
1246 | tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; | |
1247 | track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; | |
1248 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1249 | track->vgt_strmout_bo[tmp] = reloc->robj; | |
1250 | track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset; | |
3c12513d | 1251 | track->streamout_dirty = true; |
dd220a00 MO |
1252 | break; |
1253 | case VGT_STRMOUT_BUFFER_SIZE_0: | |
1254 | case VGT_STRMOUT_BUFFER_SIZE_1: | |
1255 | case VGT_STRMOUT_BUFFER_SIZE_2: | |
1256 | case VGT_STRMOUT_BUFFER_SIZE_3: | |
1257 | tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16; | |
1258 | /* size in register is DWs, convert to bytes */ | |
1259 | track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; | |
3c12513d | 1260 | track->streamout_dirty = true; |
dd220a00 MO |
1261 | break; |
1262 | case CP_COHER_BASE: | |
1263 | r = r600_cs_packet_next_reloc(p, &reloc); | |
1264 | if (r) { | |
1265 | dev_warn(p->dev, "missing reloc for CP_COHER_BASE " | |
1266 | "0x%04X\n", reg); | |
1267 | return -EINVAL; | |
1268 | } | |
1269 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1270 | break; | |
961fb597 JG |
1271 | case R_028238_CB_TARGET_MASK: |
1272 | track->cb_target_mask = radeon_get_ib_value(p, idx); | |
3c12513d | 1273 | track->cb_dirty = true; |
961fb597 JG |
1274 | break; |
1275 | case R_02823C_CB_SHADER_MASK: | |
1276 | track->cb_shader_mask = radeon_get_ib_value(p, idx); | |
1277 | break; | |
1278 | case R_028C04_PA_SC_AA_CONFIG: | |
1279 | tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx)); | |
c116cc94 | 1280 | track->log_nsamples = tmp; |
961fb597 | 1281 | track->nsamples = 1 << tmp; |
3c12513d | 1282 | track->cb_dirty = true; |
961fb597 JG |
1283 | break; |
1284 | case R_0280A0_CB_COLOR0_INFO: | |
1285 | case R_0280A4_CB_COLOR1_INFO: | |
1286 | case R_0280A8_CB_COLOR2_INFO: | |
1287 | case R_0280AC_CB_COLOR3_INFO: | |
1288 | case R_0280B0_CB_COLOR4_INFO: | |
1289 | case R_0280B4_CB_COLOR5_INFO: | |
1290 | case R_0280B8_CB_COLOR6_INFO: | |
1291 | case R_0280BC_CB_COLOR7_INFO: | |
721604a1 | 1292 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) && |
e70f224c | 1293 | r600_cs_packet_next_is_pkt3_nop(p)) { |
7f813377 AD |
1294 | r = r600_cs_packet_next_reloc(p, &reloc); |
1295 | if (r) { | |
1296 | dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); | |
1297 | return -EINVAL; | |
1298 | } | |
1299 | tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; | |
1300 | track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); | |
1301 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { | |
1302 | ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); | |
1303 | track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); | |
1304 | } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { | |
1305 | ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); | |
1306 | track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); | |
1307 | } | |
1308 | } else { | |
1309 | tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; | |
1310 | track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); | |
1311 | } | |
3c12513d | 1312 | track->cb_dirty = true; |
961fb597 | 1313 | break; |
285484e2 JG |
1314 | case R_028080_CB_COLOR0_VIEW: |
1315 | case R_028084_CB_COLOR1_VIEW: | |
1316 | case R_028088_CB_COLOR2_VIEW: | |
1317 | case R_02808C_CB_COLOR3_VIEW: | |
1318 | case R_028090_CB_COLOR4_VIEW: | |
1319 | case R_028094_CB_COLOR5_VIEW: | |
1320 | case R_028098_CB_COLOR6_VIEW: | |
1321 | case R_02809C_CB_COLOR7_VIEW: | |
1322 | tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4; | |
1323 | track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); | |
3c12513d | 1324 | track->cb_dirty = true; |
285484e2 | 1325 | break; |
961fb597 JG |
1326 | case R_028060_CB_COLOR0_SIZE: |
1327 | case R_028064_CB_COLOR1_SIZE: | |
1328 | case R_028068_CB_COLOR2_SIZE: | |
1329 | case R_02806C_CB_COLOR3_SIZE: | |
1330 | case R_028070_CB_COLOR4_SIZE: | |
1331 | case R_028074_CB_COLOR5_SIZE: | |
1332 | case R_028078_CB_COLOR6_SIZE: | |
1333 | case R_02807C_CB_COLOR7_SIZE: | |
1334 | tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4; | |
1335 | track->cb_color_size[tmp] = radeon_get_ib_value(p, idx); | |
1336 | track->cb_color_size_idx[tmp] = idx; | |
3c12513d | 1337 | track->cb_dirty = true; |
961fb597 JG |
1338 | break; |
1339 | /* This register were added late, there is userspace | |
1340 | * which does provide relocation for those but set | |
1341 | * 0 offset. In order to avoid breaking old userspace | |
1342 | * we detect this and set address to point to last | |
1343 | * CB_COLOR0_BASE, note that if userspace doesn't set | |
1344 | * CB_COLOR0_BASE before this register we will report | |
1345 | * error. Old userspace always set CB_COLOR0_BASE | |
1346 | * before any of this. | |
1347 | */ | |
1348 | case R_0280E0_CB_COLOR0_FRAG: | |
1349 | case R_0280E4_CB_COLOR1_FRAG: | |
1350 | case R_0280E8_CB_COLOR2_FRAG: | |
1351 | case R_0280EC_CB_COLOR3_FRAG: | |
1352 | case R_0280F0_CB_COLOR4_FRAG: | |
1353 | case R_0280F4_CB_COLOR5_FRAG: | |
1354 | case R_0280F8_CB_COLOR6_FRAG: | |
1355 | case R_0280FC_CB_COLOR7_FRAG: | |
1356 | tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4; | |
1357 | if (!r600_cs_packet_next_is_pkt3_nop(p)) { | |
1358 | if (!track->cb_color_base_last[tmp]) { | |
1359 | dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); | |
1360 | return -EINVAL; | |
1361 | } | |
961fb597 | 1362 | track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp]; |
c116cc94 MO |
1363 | track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp]; |
1364 | ib[idx] = track->cb_color_base_last[tmp]; | |
961fb597 JG |
1365 | } else { |
1366 | r = r600_cs_packet_next_reloc(p, &reloc); | |
1367 | if (r) { | |
1368 | dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); | |
1369 | return -EINVAL; | |
1370 | } | |
961fb597 | 1371 | track->cb_color_frag_bo[tmp] = reloc->robj; |
c116cc94 MO |
1372 | track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8; |
1373 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1374 | } | |
1375 | if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { | |
1376 | track->cb_dirty = true; | |
961fb597 JG |
1377 | } |
1378 | break; | |
1379 | case R_0280C0_CB_COLOR0_TILE: | |
1380 | case R_0280C4_CB_COLOR1_TILE: | |
1381 | case R_0280C8_CB_COLOR2_TILE: | |
1382 | case R_0280CC_CB_COLOR3_TILE: | |
1383 | case R_0280D0_CB_COLOR4_TILE: | |
1384 | case R_0280D4_CB_COLOR5_TILE: | |
1385 | case R_0280D8_CB_COLOR6_TILE: | |
1386 | case R_0280DC_CB_COLOR7_TILE: | |
1387 | tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4; | |
1388 | if (!r600_cs_packet_next_is_pkt3_nop(p)) { | |
1389 | if (!track->cb_color_base_last[tmp]) { | |
1390 | dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); | |
1391 | return -EINVAL; | |
1392 | } | |
961fb597 | 1393 | track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp]; |
c116cc94 MO |
1394 | track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp]; |
1395 | ib[idx] = track->cb_color_base_last[tmp]; | |
961fb597 JG |
1396 | } else { |
1397 | r = r600_cs_packet_next_reloc(p, &reloc); | |
1398 | if (r) { | |
1399 | dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); | |
1400 | return -EINVAL; | |
1401 | } | |
961fb597 | 1402 | track->cb_color_tile_bo[tmp] = reloc->robj; |
c116cc94 MO |
1403 | track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8; |
1404 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1405 | } | |
1406 | if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { | |
1407 | track->cb_dirty = true; | |
1408 | } | |
1409 | break; | |
1410 | case R_028100_CB_COLOR0_MASK: | |
1411 | case R_028104_CB_COLOR1_MASK: | |
1412 | case R_028108_CB_COLOR2_MASK: | |
1413 | case R_02810C_CB_COLOR3_MASK: | |
1414 | case R_028110_CB_COLOR4_MASK: | |
1415 | case R_028114_CB_COLOR5_MASK: | |
1416 | case R_028118_CB_COLOR6_MASK: | |
1417 | case R_02811C_CB_COLOR7_MASK: | |
1418 | tmp = (reg - R_028100_CB_COLOR0_MASK) / 4; | |
305a3d20 | 1419 | track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx); |
c116cc94 MO |
1420 | if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { |
1421 | track->cb_dirty = true; | |
961fb597 JG |
1422 | } |
1423 | break; | |
1424 | case CB_COLOR0_BASE: | |
1425 | case CB_COLOR1_BASE: | |
1426 | case CB_COLOR2_BASE: | |
1427 | case CB_COLOR3_BASE: | |
1428 | case CB_COLOR4_BASE: | |
1429 | case CB_COLOR5_BASE: | |
1430 | case CB_COLOR6_BASE: | |
1431 | case CB_COLOR7_BASE: | |
1432 | r = r600_cs_packet_next_reloc(p, &reloc); | |
1433 | if (r) { | |
1434 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1435 | "0x%04X\n", reg); | |
1436 | return -EINVAL; | |
1437 | } | |
7cb72ef4 | 1438 | tmp = (reg - CB_COLOR0_BASE) / 4; |
1729dd33 | 1439 | track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; |
961fb597 | 1440 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); |
961fb597 JG |
1441 | track->cb_color_base_last[tmp] = ib[idx]; |
1442 | track->cb_color_bo[tmp] = reloc->robj; | |
16790569 | 1443 | track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset; |
3c12513d | 1444 | track->cb_dirty = true; |
961fb597 JG |
1445 | break; |
1446 | case DB_DEPTH_BASE: | |
1447 | r = r600_cs_packet_next_reloc(p, &reloc); | |
1448 | if (r) { | |
1449 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1450 | "0x%04X\n", reg); | |
1451 | return -EINVAL; | |
1452 | } | |
1729dd33 | 1453 | track->db_offset = radeon_get_ib_value(p, idx) << 8; |
961fb597 JG |
1454 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); |
1455 | track->db_bo = reloc->robj; | |
16790569 | 1456 | track->db_bo_mc = reloc->lobj.gpu_offset; |
3c12513d | 1457 | track->db_dirty = true; |
961fb597 JG |
1458 | break; |
1459 | case DB_HTILE_DATA_BASE: | |
88f50c80 JG |
1460 | r = r600_cs_packet_next_reloc(p, &reloc); |
1461 | if (r) { | |
1462 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1463 | "0x%04X\n", reg); | |
1464 | return -EINVAL; | |
1465 | } | |
1466 | track->htile_offset = radeon_get_ib_value(p, idx) << 8; | |
1467 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1468 | track->htile_bo = reloc->robj; | |
1469 | track->db_dirty = true; | |
1470 | break; | |
1471 | case DB_HTILE_SURFACE: | |
1472 | track->htile_surface = radeon_get_ib_value(p, idx); | |
1473 | track->db_dirty = true; | |
1474 | break; | |
961fb597 JG |
1475 | case SQ_PGM_START_FS: |
1476 | case SQ_PGM_START_ES: | |
1477 | case SQ_PGM_START_VS: | |
1478 | case SQ_PGM_START_GS: | |
1479 | case SQ_PGM_START_PS: | |
5f77df36 AD |
1480 | case SQ_ALU_CONST_CACHE_GS_0: |
1481 | case SQ_ALU_CONST_CACHE_GS_1: | |
1482 | case SQ_ALU_CONST_CACHE_GS_2: | |
1483 | case SQ_ALU_CONST_CACHE_GS_3: | |
1484 | case SQ_ALU_CONST_CACHE_GS_4: | |
1485 | case SQ_ALU_CONST_CACHE_GS_5: | |
1486 | case SQ_ALU_CONST_CACHE_GS_6: | |
1487 | case SQ_ALU_CONST_CACHE_GS_7: | |
1488 | case SQ_ALU_CONST_CACHE_GS_8: | |
1489 | case SQ_ALU_CONST_CACHE_GS_9: | |
1490 | case SQ_ALU_CONST_CACHE_GS_10: | |
1491 | case SQ_ALU_CONST_CACHE_GS_11: | |
1492 | case SQ_ALU_CONST_CACHE_GS_12: | |
1493 | case SQ_ALU_CONST_CACHE_GS_13: | |
1494 | case SQ_ALU_CONST_CACHE_GS_14: | |
1495 | case SQ_ALU_CONST_CACHE_GS_15: | |
1496 | case SQ_ALU_CONST_CACHE_PS_0: | |
1497 | case SQ_ALU_CONST_CACHE_PS_1: | |
1498 | case SQ_ALU_CONST_CACHE_PS_2: | |
1499 | case SQ_ALU_CONST_CACHE_PS_3: | |
1500 | case SQ_ALU_CONST_CACHE_PS_4: | |
1501 | case SQ_ALU_CONST_CACHE_PS_5: | |
1502 | case SQ_ALU_CONST_CACHE_PS_6: | |
1503 | case SQ_ALU_CONST_CACHE_PS_7: | |
1504 | case SQ_ALU_CONST_CACHE_PS_8: | |
1505 | case SQ_ALU_CONST_CACHE_PS_9: | |
1506 | case SQ_ALU_CONST_CACHE_PS_10: | |
1507 | case SQ_ALU_CONST_CACHE_PS_11: | |
1508 | case SQ_ALU_CONST_CACHE_PS_12: | |
1509 | case SQ_ALU_CONST_CACHE_PS_13: | |
1510 | case SQ_ALU_CONST_CACHE_PS_14: | |
1511 | case SQ_ALU_CONST_CACHE_PS_15: | |
1512 | case SQ_ALU_CONST_CACHE_VS_0: | |
1513 | case SQ_ALU_CONST_CACHE_VS_1: | |
1514 | case SQ_ALU_CONST_CACHE_VS_2: | |
1515 | case SQ_ALU_CONST_CACHE_VS_3: | |
1516 | case SQ_ALU_CONST_CACHE_VS_4: | |
1517 | case SQ_ALU_CONST_CACHE_VS_5: | |
1518 | case SQ_ALU_CONST_CACHE_VS_6: | |
1519 | case SQ_ALU_CONST_CACHE_VS_7: | |
1520 | case SQ_ALU_CONST_CACHE_VS_8: | |
1521 | case SQ_ALU_CONST_CACHE_VS_9: | |
1522 | case SQ_ALU_CONST_CACHE_VS_10: | |
1523 | case SQ_ALU_CONST_CACHE_VS_11: | |
1524 | case SQ_ALU_CONST_CACHE_VS_12: | |
1525 | case SQ_ALU_CONST_CACHE_VS_13: | |
1526 | case SQ_ALU_CONST_CACHE_VS_14: | |
1527 | case SQ_ALU_CONST_CACHE_VS_15: | |
961fb597 JG |
1528 | r = r600_cs_packet_next_reloc(p, &reloc); |
1529 | if (r) { | |
1530 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1531 | "0x%04X\n", reg); | |
1532 | return -EINVAL; | |
033b5650 AD |
1533 | } |
1534 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1535 | break; | |
1536 | case SX_MEMORY_EXPORT_BASE: | |
1537 | r = r600_cs_packet_next_reloc(p, &reloc); | |
1538 | if (r) { | |
1539 | dev_warn(p->dev, "bad SET_CONFIG_REG " | |
1540 | "0x%04X\n", reg); | |
1541 | return -EINVAL; | |
961fb597 JG |
1542 | } |
1543 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1544 | break; | |
779923bc MO |
1545 | case SX_MISC: |
1546 | track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; | |
1547 | break; | |
961fb597 JG |
1548 | default: |
1549 | dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); | |
1550 | return -EINVAL; | |
1551 | } | |
1552 | return 0; | |
1553 | } | |
1554 | ||
285484e2 | 1555 | unsigned r600_mip_minify(unsigned size, unsigned level) |
961fb597 | 1556 | { |
60b212f8 DA |
1557 | unsigned val; |
1558 | ||
1559 | val = max(1U, size >> level); | |
1560 | if (level > 0) | |
1561 | val = roundup_pow_of_two(val); | |
1562 | return val; | |
961fb597 JG |
1563 | } |
1564 | ||
60b212f8 | 1565 | static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel, |
fcdeefe4 | 1566 | unsigned w0, unsigned h0, unsigned d0, unsigned nsamples, unsigned format, |
60b212f8 | 1567 | unsigned block_align, unsigned height_align, unsigned base_align, |
40e2a5c1 | 1568 | unsigned *l0_size, unsigned *mipmap_size) |
961fb597 | 1569 | { |
60b212f8 DA |
1570 | unsigned offset, i, level; |
1571 | unsigned width, height, depth, size; | |
1572 | unsigned blocksize; | |
1573 | unsigned nbx, nby; | |
1574 | unsigned nlevels = llevel - blevel + 1; | |
961fb597 | 1575 | |
60b212f8 | 1576 | *l0_size = -1; |
285484e2 | 1577 | blocksize = r600_fmt_get_blocksize(format); |
60b212f8 | 1578 | |
285484e2 JG |
1579 | w0 = r600_mip_minify(w0, 0); |
1580 | h0 = r600_mip_minify(h0, 0); | |
1581 | d0 = r600_mip_minify(d0, 0); | |
961fb597 | 1582 | for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) { |
285484e2 JG |
1583 | width = r600_mip_minify(w0, i); |
1584 | nbx = r600_fmt_get_nblocksx(format, width); | |
60b212f8 DA |
1585 | |
1586 | nbx = round_up(nbx, block_align); | |
1587 | ||
285484e2 JG |
1588 | height = r600_mip_minify(h0, i); |
1589 | nby = r600_fmt_get_nblocksy(format, height); | |
60b212f8 DA |
1590 | nby = round_up(nby, height_align); |
1591 | ||
285484e2 | 1592 | depth = r600_mip_minify(d0, i); |
60b212f8 | 1593 | |
fcdeefe4 | 1594 | size = nbx * nby * blocksize * nsamples; |
60b212f8 DA |
1595 | if (nfaces) |
1596 | size *= nfaces; | |
1597 | else | |
1598 | size *= depth; | |
1599 | ||
1600 | if (i == 0) | |
1601 | *l0_size = size; | |
1602 | ||
1603 | if (i == 0 || i == 1) | |
1604 | offset = round_up(offset, base_align); | |
1605 | ||
1606 | offset += size; | |
961fb597 | 1607 | } |
961fb597 | 1608 | *mipmap_size = offset; |
60b212f8 | 1609 | if (llevel == 0) |
961fb597 | 1610 | *mipmap_size = *l0_size; |
1729dd33 AD |
1611 | if (!blevel) |
1612 | *mipmap_size -= *l0_size; | |
961fb597 JG |
1613 | } |
1614 | ||
1615 | /** | |
1616 | * r600_check_texture_resource() - check if register is authorized or not | |
1617 | * @p: parser structure holding parsing context | |
1618 | * @idx: index into the cs buffer | |
1619 | * @texture: texture's bo structure | |
1620 | * @mipmap: mipmap's bo structure | |
1621 | * | |
1622 | * This function will check that the resource has valid field and that | |
1623 | * the texture and mipmap bo object are big enough to cover this resource. | |
1624 | */ | |
488479eb | 1625 | static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, |
7f813377 AD |
1626 | struct radeon_bo *texture, |
1627 | struct radeon_bo *mipmap, | |
16790569 AD |
1628 | u64 base_offset, |
1629 | u64 mip_offset, | |
7f813377 | 1630 | u32 tiling_flags) |
961fb597 | 1631 | { |
40e2a5c1 | 1632 | struct r600_cs_track *track = p->track; |
f00245f1 MO |
1633 | u32 dim, nfaces, llevel, blevel, w0, h0, d0; |
1634 | u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5; | |
16790569 | 1635 | u32 height_align, pitch, pitch_align, depth_align; |
f00245f1 | 1636 | u32 barray, larray; |
16790569 AD |
1637 | u64 base_align; |
1638 | struct array_mode_checker array_check; | |
60b212f8 | 1639 | u32 format; |
f00245f1 | 1640 | bool is_array; |
961fb597 JG |
1641 | |
1642 | /* on legacy kernel we don't perform advanced check */ | |
1643 | if (p->rdev == NULL) | |
1644 | return 0; | |
7f813377 | 1645 | |
16790569 AD |
1646 | /* convert to bytes */ |
1647 | base_offset <<= 8; | |
1648 | mip_offset <<= 8; | |
1649 | ||
961fb597 | 1650 | word0 = radeon_get_ib_value(p, idx + 0); |
721604a1 | 1651 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
e70f224c MO |
1652 | if (tiling_flags & RADEON_TILING_MACRO) |
1653 | word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); | |
1654 | else if (tiling_flags & RADEON_TILING_MICRO) | |
1655 | word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); | |
1656 | } | |
961fb597 | 1657 | word1 = radeon_get_ib_value(p, idx + 1); |
f00245f1 MO |
1658 | word2 = radeon_get_ib_value(p, idx + 2) << 8; |
1659 | word3 = radeon_get_ib_value(p, idx + 3) << 8; | |
1660 | word4 = radeon_get_ib_value(p, idx + 4); | |
1661 | word5 = radeon_get_ib_value(p, idx + 5); | |
1662 | dim = G_038000_DIM(word0); | |
961fb597 | 1663 | w0 = G_038000_TEX_WIDTH(word0) + 1; |
f00245f1 | 1664 | pitch = (G_038000_PITCH(word0) + 1) * 8; |
961fb597 JG |
1665 | h0 = G_038004_TEX_HEIGHT(word1) + 1; |
1666 | d0 = G_038004_TEX_DEPTH(word1); | |
f00245f1 MO |
1667 | format = G_038004_DATA_FORMAT(word1); |
1668 | blevel = G_038010_BASE_LEVEL(word4); | |
1669 | llevel = G_038014_LAST_LEVEL(word5); | |
1670 | /* pitch in texels */ | |
1671 | array_check.array_mode = G_038000_TILE_MODE(word0); | |
1672 | array_check.group_size = track->group_size; | |
1673 | array_check.nbanks = track->nbanks; | |
1674 | array_check.npipes = track->npipes; | |
1675 | array_check.nsamples = 1; | |
1676 | array_check.blocksize = r600_fmt_get_blocksize(format); | |
961fb597 | 1677 | nfaces = 1; |
f00245f1 MO |
1678 | is_array = false; |
1679 | switch (dim) { | |
961fb597 JG |
1680 | case V_038000_SQ_TEX_DIM_1D: |
1681 | case V_038000_SQ_TEX_DIM_2D: | |
1682 | case V_038000_SQ_TEX_DIM_3D: | |
1683 | break; | |
1684 | case V_038000_SQ_TEX_DIM_CUBEMAP: | |
60b212f8 DA |
1685 | if (p->family >= CHIP_RV770) |
1686 | nfaces = 8; | |
1687 | else | |
1688 | nfaces = 6; | |
961fb597 JG |
1689 | break; |
1690 | case V_038000_SQ_TEX_DIM_1D_ARRAY: | |
1691 | case V_038000_SQ_TEX_DIM_2D_ARRAY: | |
f00245f1 | 1692 | is_array = true; |
60b212f8 | 1693 | break; |
961fb597 | 1694 | case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA: |
b51ad12a MO |
1695 | is_array = true; |
1696 | /* fall through */ | |
1697 | case V_038000_SQ_TEX_DIM_2D_MSAA: | |
1698 | array_check.nsamples = 1 << llevel; | |
1699 | llevel = 0; | |
1700 | break; | |
961fb597 JG |
1701 | default: |
1702 | dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0)); | |
1703 | return -EINVAL; | |
1704 | } | |
285484e2 | 1705 | if (!r600_fmt_is_valid_texture(format, p->family)) { |
961fb597 | 1706 | dev_warn(p->dev, "%s:%d texture invalid format %d\n", |
60b212f8 | 1707 | __func__, __LINE__, format); |
961fb597 JG |
1708 | return -EINVAL; |
1709 | } | |
40e2a5c1 | 1710 | |
16790569 AD |
1711 | if (r600_get_array_mode_alignment(&array_check, |
1712 | &pitch_align, &height_align, &depth_align, &base_align)) { | |
1713 | dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n", | |
1714 | __func__, __LINE__, G_038000_TILE_MODE(word0)); | |
1715 | return -EINVAL; | |
1716 | } | |
1717 | ||
1718 | /* XXX check height as well... */ | |
1719 | ||
1720 | if (!IS_ALIGNED(pitch, pitch_align)) { | |
c2049b3d AD |
1721 | dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n", |
1722 | __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0)); | |
16790569 AD |
1723 | return -EINVAL; |
1724 | } | |
1725 | if (!IS_ALIGNED(base_offset, base_align)) { | |
c2049b3d AD |
1726 | dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n", |
1727 | __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0)); | |
16790569 AD |
1728 | return -EINVAL; |
1729 | } | |
1730 | if (!IS_ALIGNED(mip_offset, base_align)) { | |
c2049b3d AD |
1731 | dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n", |
1732 | __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0)); | |
40e2a5c1 AD |
1733 | return -EINVAL; |
1734 | } | |
40e2a5c1 | 1735 | |
285484e2 JG |
1736 | if (blevel > llevel) { |
1737 | dev_warn(p->dev, "texture blevel %d > llevel %d\n", | |
1738 | blevel, llevel); | |
1739 | } | |
f00245f1 MO |
1740 | if (is_array) { |
1741 | barray = G_038014_BASE_ARRAY(word5); | |
1742 | larray = G_038014_LAST_ARRAY(word5); | |
60b212f8 DA |
1743 | |
1744 | nfaces = larray - barray + 1; | |
1745 | } | |
fcdeefe4 | 1746 | r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, array_check.nsamples, format, |
60b212f8 | 1747 | pitch_align, height_align, base_align, |
40e2a5c1 | 1748 | &l0_size, &mipmap_size); |
961fb597 | 1749 | /* using get ib will give us the offset into the texture bo */ |
af50621a | 1750 | if ((l0_size + word2) > radeon_bo_size(texture)) { |
285484e2 JG |
1751 | dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n", |
1752 | w0, h0, pitch_align, height_align, | |
1753 | array_check.array_mode, format, word2, | |
1754 | l0_size, radeon_bo_size(texture)); | |
60b212f8 | 1755 | dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align); |
961fb597 JG |
1756 | return -EINVAL; |
1757 | } | |
1758 | /* using get ib will give us the offset into the mipmap bo */ | |
af50621a | 1759 | if ((mipmap_size + word3) > radeon_bo_size(mipmap)) { |
fe725d4f | 1760 | /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n", |
af50621a | 1761 | w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/ |
961fb597 JG |
1762 | } |
1763 | return 0; | |
1764 | } | |
1765 | ||
dd220a00 MO |
1766 | static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) |
1767 | { | |
1768 | u32 m, i; | |
1769 | ||
1770 | i = (reg >> 7); | |
1771 | if (i >= ARRAY_SIZE(r600_reg_safe_bm)) { | |
1772 | dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); | |
1773 | return false; | |
1774 | } | |
1775 | m = 1 << ((reg >> 2) & 31); | |
1776 | if (!(r600_reg_safe_bm[i] & m)) | |
1777 | return true; | |
1778 | dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); | |
1779 | return false; | |
1780 | } | |
1781 | ||
3ce0a23d JG |
1782 | static int r600_packet3_check(struct radeon_cs_parser *p, |
1783 | struct radeon_cs_packet *pkt) | |
1784 | { | |
3ce0a23d | 1785 | struct radeon_cs_reloc *reloc; |
c8c15ff1 | 1786 | struct r600_cs_track *track; |
3ce0a23d JG |
1787 | volatile u32 *ib; |
1788 | unsigned idx; | |
1789 | unsigned i; | |
1790 | unsigned start_reg, end_reg, reg; | |
1791 | int r; | |
adea4796 | 1792 | u32 idx_value; |
3ce0a23d | 1793 | |
c8c15ff1 | 1794 | track = (struct r600_cs_track *)p->track; |
f2e39221 | 1795 | ib = p->ib.ptr; |
3ce0a23d | 1796 | idx = pkt->idx + 1; |
adea4796 | 1797 | idx_value = radeon_get_ib_value(p, idx); |
513bcb46 | 1798 | |
3ce0a23d | 1799 | switch (pkt->opcode) { |
2a19cac8 DA |
1800 | case PACKET3_SET_PREDICATION: |
1801 | { | |
1802 | int pred_op; | |
1803 | int tmp; | |
6333003b MO |
1804 | uint64_t offset; |
1805 | ||
2a19cac8 DA |
1806 | if (pkt->count != 1) { |
1807 | DRM_ERROR("bad SET PREDICATION\n"); | |
1808 | return -EINVAL; | |
1809 | } | |
1810 | ||
1811 | tmp = radeon_get_ib_value(p, idx + 1); | |
1812 | pred_op = (tmp >> 16) & 0x7; | |
1813 | ||
1814 | /* for the clear predicate operation */ | |
1815 | if (pred_op == 0) | |
1816 | return 0; | |
1817 | ||
1818 | if (pred_op > 2) { | |
1819 | DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op); | |
1820 | return -EINVAL; | |
1821 | } | |
1822 | ||
1823 | r = r600_cs_packet_next_reloc(p, &reloc); | |
1824 | if (r) { | |
1825 | DRM_ERROR("bad SET PREDICATION\n"); | |
1826 | return -EINVAL; | |
1827 | } | |
1828 | ||
6333003b MO |
1829 | offset = reloc->lobj.gpu_offset + |
1830 | (idx_value & 0xfffffff0) + | |
1831 | ((u64)(tmp & 0xff) << 32); | |
1832 | ||
1833 | ib[idx + 0] = offset; | |
1834 | ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); | |
2a19cac8 DA |
1835 | } |
1836 | break; | |
1837 | ||
3ce0a23d JG |
1838 | case PACKET3_START_3D_CMDBUF: |
1839 | if (p->family >= CHIP_RV770 || pkt->count) { | |
1840 | DRM_ERROR("bad START_3D\n"); | |
1841 | return -EINVAL; | |
1842 | } | |
1843 | break; | |
1844 | case PACKET3_CONTEXT_CONTROL: | |
1845 | if (pkt->count != 1) { | |
1846 | DRM_ERROR("bad CONTEXT_CONTROL\n"); | |
1847 | return -EINVAL; | |
1848 | } | |
1849 | break; | |
1850 | case PACKET3_INDEX_TYPE: | |
1851 | case PACKET3_NUM_INSTANCES: | |
1852 | if (pkt->count) { | |
1853 | DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n"); | |
1854 | return -EINVAL; | |
1855 | } | |
1856 | break; | |
1857 | case PACKET3_DRAW_INDEX: | |
6333003b MO |
1858 | { |
1859 | uint64_t offset; | |
3ce0a23d JG |
1860 | if (pkt->count != 3) { |
1861 | DRM_ERROR("bad DRAW_INDEX\n"); | |
1862 | return -EINVAL; | |
1863 | } | |
1864 | r = r600_cs_packet_next_reloc(p, &reloc); | |
1865 | if (r) { | |
1866 | DRM_ERROR("bad DRAW_INDEX\n"); | |
1867 | return -EINVAL; | |
1868 | } | |
6333003b MO |
1869 | |
1870 | offset = reloc->lobj.gpu_offset + | |
1871 | idx_value + | |
1872 | ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); | |
1873 | ||
1874 | ib[idx+0] = offset; | |
1875 | ib[idx+1] = upper_32_bits(offset) & 0xff; | |
1876 | ||
961fb597 JG |
1877 | r = r600_cs_track_check(p); |
1878 | if (r) { | |
1879 | dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); | |
1880 | return r; | |
1881 | } | |
3ce0a23d | 1882 | break; |
6333003b | 1883 | } |
3ce0a23d JG |
1884 | case PACKET3_DRAW_INDEX_AUTO: |
1885 | if (pkt->count != 1) { | |
1886 | DRM_ERROR("bad DRAW_INDEX_AUTO\n"); | |
1887 | return -EINVAL; | |
1888 | } | |
961fb597 JG |
1889 | r = r600_cs_track_check(p); |
1890 | if (r) { | |
1891 | dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); | |
1892 | return r; | |
1893 | } | |
3ce0a23d JG |
1894 | break; |
1895 | case PACKET3_DRAW_INDEX_IMMD_BE: | |
1896 | case PACKET3_DRAW_INDEX_IMMD: | |
1897 | if (pkt->count < 2) { | |
1898 | DRM_ERROR("bad DRAW_INDEX_IMMD\n"); | |
1899 | return -EINVAL; | |
1900 | } | |
961fb597 JG |
1901 | r = r600_cs_track_check(p); |
1902 | if (r) { | |
1903 | dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); | |
1904 | return r; | |
1905 | } | |
3ce0a23d JG |
1906 | break; |
1907 | case PACKET3_WAIT_REG_MEM: | |
1908 | if (pkt->count != 5) { | |
1909 | DRM_ERROR("bad WAIT_REG_MEM\n"); | |
1910 | return -EINVAL; | |
1911 | } | |
1912 | /* bit 4 is reg (0) or mem (1) */ | |
adea4796 | 1913 | if (idx_value & 0x10) { |
6333003b MO |
1914 | uint64_t offset; |
1915 | ||
3ce0a23d JG |
1916 | r = r600_cs_packet_next_reloc(p, &reloc); |
1917 | if (r) { | |
1918 | DRM_ERROR("bad WAIT_REG_MEM\n"); | |
1919 | return -EINVAL; | |
1920 | } | |
6333003b MO |
1921 | |
1922 | offset = reloc->lobj.gpu_offset + | |
1923 | (radeon_get_ib_value(p, idx+1) & 0xfffffff0) + | |
1924 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); | |
1925 | ||
1926 | ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0); | |
1927 | ib[idx+2] = upper_32_bits(offset) & 0xff; | |
3ce0a23d JG |
1928 | } |
1929 | break; | |
1930 | case PACKET3_SURFACE_SYNC: | |
1931 | if (pkt->count != 3) { | |
1932 | DRM_ERROR("bad SURFACE_SYNC\n"); | |
1933 | return -EINVAL; | |
1934 | } | |
1935 | /* 0xffffffff/0x0 is flush all cache flag */ | |
513bcb46 DA |
1936 | if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || |
1937 | radeon_get_ib_value(p, idx + 2) != 0) { | |
3ce0a23d JG |
1938 | r = r600_cs_packet_next_reloc(p, &reloc); |
1939 | if (r) { | |
1940 | DRM_ERROR("bad SURFACE_SYNC\n"); | |
1941 | return -EINVAL; | |
1942 | } | |
1943 | ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1944 | } | |
1945 | break; | |
1946 | case PACKET3_EVENT_WRITE: | |
1947 | if (pkt->count != 2 && pkt->count != 0) { | |
1948 | DRM_ERROR("bad EVENT_WRITE\n"); | |
1949 | return -EINVAL; | |
1950 | } | |
1951 | if (pkt->count) { | |
6333003b MO |
1952 | uint64_t offset; |
1953 | ||
3ce0a23d JG |
1954 | r = r600_cs_packet_next_reloc(p, &reloc); |
1955 | if (r) { | |
1956 | DRM_ERROR("bad EVENT_WRITE\n"); | |
1957 | return -EINVAL; | |
1958 | } | |
6333003b MO |
1959 | offset = reloc->lobj.gpu_offset + |
1960 | (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + | |
1961 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); | |
1962 | ||
1963 | ib[idx+1] = offset & 0xfffffff8; | |
1964 | ib[idx+2] = upper_32_bits(offset) & 0xff; | |
3ce0a23d JG |
1965 | } |
1966 | break; | |
1967 | case PACKET3_EVENT_WRITE_EOP: | |
6333003b MO |
1968 | { |
1969 | uint64_t offset; | |
1970 | ||
3ce0a23d JG |
1971 | if (pkt->count != 4) { |
1972 | DRM_ERROR("bad EVENT_WRITE_EOP\n"); | |
1973 | return -EINVAL; | |
1974 | } | |
1975 | r = r600_cs_packet_next_reloc(p, &reloc); | |
1976 | if (r) { | |
1977 | DRM_ERROR("bad EVENT_WRITE\n"); | |
1978 | return -EINVAL; | |
1979 | } | |
6333003b MO |
1980 | |
1981 | offset = reloc->lobj.gpu_offset + | |
1982 | (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + | |
1983 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); | |
1984 | ||
1985 | ib[idx+1] = offset & 0xfffffffc; | |
1986 | ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); | |
3ce0a23d | 1987 | break; |
6333003b | 1988 | } |
3ce0a23d | 1989 | case PACKET3_SET_CONFIG_REG: |
adea4796 | 1990 | start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; |
3ce0a23d JG |
1991 | end_reg = 4 * pkt->count + start_reg - 4; |
1992 | if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) || | |
1993 | (start_reg >= PACKET3_SET_CONFIG_REG_END) || | |
1994 | (end_reg >= PACKET3_SET_CONFIG_REG_END)) { | |
1995 | DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); | |
1996 | return -EINVAL; | |
1997 | } | |
1998 | for (i = 0; i < pkt->count; i++) { | |
1999 | reg = start_reg + (4 * i); | |
961fb597 JG |
2000 | r = r600_cs_check_reg(p, reg, idx+1+i); |
2001 | if (r) | |
2002 | return r; | |
3ce0a23d JG |
2003 | } |
2004 | break; | |
2005 | case PACKET3_SET_CONTEXT_REG: | |
adea4796 | 2006 | start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET; |
3ce0a23d JG |
2007 | end_reg = 4 * pkt->count + start_reg - 4; |
2008 | if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) || | |
2009 | (start_reg >= PACKET3_SET_CONTEXT_REG_END) || | |
2010 | (end_reg >= PACKET3_SET_CONTEXT_REG_END)) { | |
2011 | DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n"); | |
2012 | return -EINVAL; | |
2013 | } | |
2014 | for (i = 0; i < pkt->count; i++) { | |
2015 | reg = start_reg + (4 * i); | |
961fb597 JG |
2016 | r = r600_cs_check_reg(p, reg, idx+1+i); |
2017 | if (r) | |
2018 | return r; | |
3ce0a23d JG |
2019 | } |
2020 | break; | |
2021 | case PACKET3_SET_RESOURCE: | |
2022 | if (pkt->count % 7) { | |
2023 | DRM_ERROR("bad SET_RESOURCE\n"); | |
2024 | return -EINVAL; | |
2025 | } | |
adea4796 | 2026 | start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET; |
3ce0a23d JG |
2027 | end_reg = 4 * pkt->count + start_reg - 4; |
2028 | if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) || | |
2029 | (start_reg >= PACKET3_SET_RESOURCE_END) || | |
2030 | (end_reg >= PACKET3_SET_RESOURCE_END)) { | |
2031 | DRM_ERROR("bad SET_RESOURCE\n"); | |
2032 | return -EINVAL; | |
2033 | } | |
2034 | for (i = 0; i < (pkt->count / 7); i++) { | |
961fb597 | 2035 | struct radeon_bo *texture, *mipmap; |
1729dd33 | 2036 | u32 size, offset, base_offset, mip_offset; |
961fb597 | 2037 | |
adea4796 | 2038 | switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) { |
3ce0a23d JG |
2039 | case SQ_TEX_VTX_VALID_TEXTURE: |
2040 | /* tex base */ | |
2041 | r = r600_cs_packet_next_reloc(p, &reloc); | |
2042 | if (r) { | |
2043 | DRM_ERROR("bad SET_RESOURCE\n"); | |
2044 | return -EINVAL; | |
2045 | } | |
1729dd33 | 2046 | base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); |
721604a1 | 2047 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
e70f224c MO |
2048 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
2049 | ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); | |
2050 | else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | |
2051 | ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); | |
2052 | } | |
961fb597 | 2053 | texture = reloc->robj; |
3ce0a23d JG |
2054 | /* tex mip base */ |
2055 | r = r600_cs_packet_next_reloc(p, &reloc); | |
2056 | if (r) { | |
2057 | DRM_ERROR("bad SET_RESOURCE\n"); | |
2058 | return -EINVAL; | |
2059 | } | |
1729dd33 | 2060 | mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); |
961fb597 JG |
2061 | mipmap = reloc->robj; |
2062 | r = r600_check_texture_resource(p, idx+(i*7)+1, | |
16790569 AD |
2063 | texture, mipmap, |
2064 | base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2), | |
2065 | mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3), | |
2066 | reloc->lobj.tiling_flags); | |
961fb597 JG |
2067 | if (r) |
2068 | return r; | |
1729dd33 AD |
2069 | ib[idx+1+(i*7)+2] += base_offset; |
2070 | ib[idx+1+(i*7)+3] += mip_offset; | |
3ce0a23d JG |
2071 | break; |
2072 | case SQ_TEX_VTX_VALID_BUFFER: | |
6333003b MO |
2073 | { |
2074 | uint64_t offset64; | |
3ce0a23d JG |
2075 | /* vtx base */ |
2076 | r = r600_cs_packet_next_reloc(p, &reloc); | |
2077 | if (r) { | |
2078 | DRM_ERROR("bad SET_RESOURCE\n"); | |
2079 | return -EINVAL; | |
2080 | } | |
961fb597 | 2081 | offset = radeon_get_ib_value(p, idx+1+(i*7)+0); |
1729dd33 | 2082 | size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1; |
961fb597 JG |
2083 | if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { |
2084 | /* force size to size of the buffer */ | |
1729dd33 AD |
2085 | dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n", |
2086 | size + offset, radeon_bo_size(reloc->robj)); | |
6333003b | 2087 | ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset; |
961fb597 | 2088 | } |
6333003b MO |
2089 | |
2090 | offset64 = reloc->lobj.gpu_offset + offset; | |
2091 | ib[idx+1+(i*8)+0] = offset64; | |
2092 | ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | | |
2093 | (upper_32_bits(offset64) & 0xff); | |
3ce0a23d | 2094 | break; |
6333003b | 2095 | } |
3ce0a23d JG |
2096 | case SQ_TEX_VTX_INVALID_TEXTURE: |
2097 | case SQ_TEX_VTX_INVALID_BUFFER: | |
2098 | default: | |
2099 | DRM_ERROR("bad SET_RESOURCE\n"); | |
2100 | return -EINVAL; | |
2101 | } | |
2102 | } | |
2103 | break; | |
2104 | case PACKET3_SET_ALU_CONST: | |
5f77df36 AD |
2105 | if (track->sq_config & DX9_CONSTS) { |
2106 | start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET; | |
2107 | end_reg = 4 * pkt->count + start_reg - 4; | |
2108 | if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) || | |
2109 | (start_reg >= PACKET3_SET_ALU_CONST_END) || | |
2110 | (end_reg >= PACKET3_SET_ALU_CONST_END)) { | |
2111 | DRM_ERROR("bad SET_ALU_CONST\n"); | |
2112 | return -EINVAL; | |
2113 | } | |
3ce0a23d JG |
2114 | } |
2115 | break; | |
2116 | case PACKET3_SET_BOOL_CONST: | |
adea4796 | 2117 | start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET; |
3ce0a23d JG |
2118 | end_reg = 4 * pkt->count + start_reg - 4; |
2119 | if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) || | |
2120 | (start_reg >= PACKET3_SET_BOOL_CONST_END) || | |
2121 | (end_reg >= PACKET3_SET_BOOL_CONST_END)) { | |
2122 | DRM_ERROR("bad SET_BOOL_CONST\n"); | |
2123 | return -EINVAL; | |
2124 | } | |
2125 | break; | |
2126 | case PACKET3_SET_LOOP_CONST: | |
adea4796 | 2127 | start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET; |
3ce0a23d JG |
2128 | end_reg = 4 * pkt->count + start_reg - 4; |
2129 | if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) || | |
2130 | (start_reg >= PACKET3_SET_LOOP_CONST_END) || | |
2131 | (end_reg >= PACKET3_SET_LOOP_CONST_END)) { | |
2132 | DRM_ERROR("bad SET_LOOP_CONST\n"); | |
2133 | return -EINVAL; | |
2134 | } | |
2135 | break; | |
2136 | case PACKET3_SET_CTL_CONST: | |
adea4796 | 2137 | start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET; |
3ce0a23d JG |
2138 | end_reg = 4 * pkt->count + start_reg - 4; |
2139 | if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) || | |
2140 | (start_reg >= PACKET3_SET_CTL_CONST_END) || | |
2141 | (end_reg >= PACKET3_SET_CTL_CONST_END)) { | |
2142 | DRM_ERROR("bad SET_CTL_CONST\n"); | |
2143 | return -EINVAL; | |
2144 | } | |
2145 | break; | |
2146 | case PACKET3_SET_SAMPLER: | |
2147 | if (pkt->count % 3) { | |
2148 | DRM_ERROR("bad SET_SAMPLER\n"); | |
2149 | return -EINVAL; | |
2150 | } | |
adea4796 | 2151 | start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET; |
3ce0a23d JG |
2152 | end_reg = 4 * pkt->count + start_reg - 4; |
2153 | if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) || | |
2154 | (start_reg >= PACKET3_SET_SAMPLER_END) || | |
2155 | (end_reg >= PACKET3_SET_SAMPLER_END)) { | |
2156 | DRM_ERROR("bad SET_SAMPLER\n"); | |
2157 | return -EINVAL; | |
2158 | } | |
2159 | break; | |
7c77bf2a AD |
2160 | case PACKET3_STRMOUT_BASE_UPDATE: |
2161 | if (p->family < CHIP_RV770) { | |
2162 | DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n"); | |
2163 | return -EINVAL; | |
2164 | } | |
2165 | if (pkt->count != 1) { | |
2166 | DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n"); | |
2167 | return -EINVAL; | |
2168 | } | |
2169 | if (idx_value > 3) { | |
2170 | DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n"); | |
2171 | return -EINVAL; | |
2172 | } | |
2173 | { | |
2174 | u64 offset; | |
2175 | ||
2176 | r = r600_cs_packet_next_reloc(p, &reloc); | |
2177 | if (r) { | |
2178 | DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n"); | |
2179 | return -EINVAL; | |
2180 | } | |
2181 | ||
2182 | if (reloc->robj != track->vgt_strmout_bo[idx_value]) { | |
2183 | DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n"); | |
2184 | return -EINVAL; | |
2185 | } | |
2186 | ||
2187 | offset = radeon_get_ib_value(p, idx+1) << 8; | |
2188 | if (offset != track->vgt_strmout_bo_offset[idx_value]) { | |
2189 | DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n", | |
2190 | offset, track->vgt_strmout_bo_offset[idx_value]); | |
2191 | return -EINVAL; | |
2192 | } | |
2193 | ||
2194 | if ((offset + 4) > radeon_bo_size(reloc->robj)) { | |
2195 | DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n", | |
2196 | offset + 4, radeon_bo_size(reloc->robj)); | |
2197 | return -EINVAL; | |
2198 | } | |
2199 | ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
2200 | } | |
2201 | break; | |
3ce0a23d JG |
2202 | case PACKET3_SURFACE_BASE_UPDATE: |
2203 | if (p->family >= CHIP_RV770 || p->family == CHIP_R600) { | |
2204 | DRM_ERROR("bad SURFACE_BASE_UPDATE\n"); | |
2205 | return -EINVAL; | |
2206 | } | |
2207 | if (pkt->count) { | |
2208 | DRM_ERROR("bad SURFACE_BASE_UPDATE\n"); | |
2209 | return -EINVAL; | |
2210 | } | |
2211 | break; | |
dd220a00 MO |
2212 | case PACKET3_STRMOUT_BUFFER_UPDATE: |
2213 | if (pkt->count != 4) { | |
2214 | DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n"); | |
2215 | return -EINVAL; | |
2216 | } | |
2217 | /* Updating memory at DST_ADDRESS. */ | |
2218 | if (idx_value & 0x1) { | |
2219 | u64 offset; | |
2220 | r = r600_cs_packet_next_reloc(p, &reloc); | |
2221 | if (r) { | |
2222 | DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n"); | |
2223 | return -EINVAL; | |
2224 | } | |
2225 | offset = radeon_get_ib_value(p, idx+1); | |
2226 | offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; | |
2227 | if ((offset + 4) > radeon_bo_size(reloc->robj)) { | |
2228 | DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n", | |
2229 | offset + 4, radeon_bo_size(reloc->robj)); | |
2230 | return -EINVAL; | |
2231 | } | |
6333003b MO |
2232 | offset += reloc->lobj.gpu_offset; |
2233 | ib[idx+1] = offset; | |
2234 | ib[idx+2] = upper_32_bits(offset) & 0xff; | |
dd220a00 MO |
2235 | } |
2236 | /* Reading data from SRC_ADDRESS. */ | |
2237 | if (((idx_value >> 1) & 0x3) == 2) { | |
2238 | u64 offset; | |
2239 | r = r600_cs_packet_next_reloc(p, &reloc); | |
2240 | if (r) { | |
2241 | DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n"); | |
2242 | return -EINVAL; | |
2243 | } | |
2244 | offset = radeon_get_ib_value(p, idx+3); | |
2245 | offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; | |
2246 | if ((offset + 4) > radeon_bo_size(reloc->robj)) { | |
2247 | DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n", | |
2248 | offset + 4, radeon_bo_size(reloc->robj)); | |
2249 | return -EINVAL; | |
2250 | } | |
6333003b MO |
2251 | offset += reloc->lobj.gpu_offset; |
2252 | ib[idx+3] = offset; | |
2253 | ib[idx+4] = upper_32_bits(offset) & 0xff; | |
dd220a00 MO |
2254 | } |
2255 | break; | |
2256 | case PACKET3_COPY_DW: | |
2257 | if (pkt->count != 4) { | |
2258 | DRM_ERROR("bad COPY_DW (invalid count)\n"); | |
2259 | return -EINVAL; | |
2260 | } | |
2261 | if (idx_value & 0x1) { | |
2262 | u64 offset; | |
2263 | /* SRC is memory. */ | |
2264 | r = r600_cs_packet_next_reloc(p, &reloc); | |
2265 | if (r) { | |
2266 | DRM_ERROR("bad COPY_DW (missing src reloc)\n"); | |
2267 | return -EINVAL; | |
2268 | } | |
2269 | offset = radeon_get_ib_value(p, idx+1); | |
2270 | offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; | |
2271 | if ((offset + 4) > radeon_bo_size(reloc->robj)) { | |
2272 | DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n", | |
2273 | offset + 4, radeon_bo_size(reloc->robj)); | |
2274 | return -EINVAL; | |
2275 | } | |
6333003b MO |
2276 | offset += reloc->lobj.gpu_offset; |
2277 | ib[idx+1] = offset; | |
2278 | ib[idx+2] = upper_32_bits(offset) & 0xff; | |
dd220a00 MO |
2279 | } else { |
2280 | /* SRC is a reg. */ | |
2281 | reg = radeon_get_ib_value(p, idx+1) << 2; | |
2282 | if (!r600_is_safe_reg(p, reg, idx+1)) | |
2283 | return -EINVAL; | |
2284 | } | |
2285 | if (idx_value & 0x2) { | |
2286 | u64 offset; | |
2287 | /* DST is memory. */ | |
2288 | r = r600_cs_packet_next_reloc(p, &reloc); | |
2289 | if (r) { | |
2290 | DRM_ERROR("bad COPY_DW (missing dst reloc)\n"); | |
2291 | return -EINVAL; | |
2292 | } | |
2293 | offset = radeon_get_ib_value(p, idx+3); | |
2294 | offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; | |
2295 | if ((offset + 4) > radeon_bo_size(reloc->robj)) { | |
2296 | DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n", | |
2297 | offset + 4, radeon_bo_size(reloc->robj)); | |
2298 | return -EINVAL; | |
2299 | } | |
6333003b MO |
2300 | offset += reloc->lobj.gpu_offset; |
2301 | ib[idx+3] = offset; | |
2302 | ib[idx+4] = upper_32_bits(offset) & 0xff; | |
dd220a00 MO |
2303 | } else { |
2304 | /* DST is a reg. */ | |
2305 | reg = radeon_get_ib_value(p, idx+3) << 2; | |
2306 | if (!r600_is_safe_reg(p, reg, idx+3)) | |
2307 | return -EINVAL; | |
2308 | } | |
2309 | break; | |
3ce0a23d JG |
2310 | case PACKET3_NOP: |
2311 | break; | |
2312 | default: | |
2313 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); | |
2314 | return -EINVAL; | |
2315 | } | |
2316 | return 0; | |
2317 | } | |
2318 | ||
2319 | int r600_cs_parse(struct radeon_cs_parser *p) | |
2320 | { | |
2321 | struct radeon_cs_packet pkt; | |
c8c15ff1 | 2322 | struct r600_cs_track *track; |
3ce0a23d JG |
2323 | int r; |
2324 | ||
961fb597 JG |
2325 | if (p->track == NULL) { |
2326 | /* initialize tracker, we are in kms */ | |
2327 | track = kzalloc(sizeof(*track), GFP_KERNEL); | |
2328 | if (track == NULL) | |
2329 | return -ENOMEM; | |
2330 | r600_cs_track_init(track); | |
2331 | if (p->rdev->family < CHIP_RV770) { | |
2332 | track->npipes = p->rdev->config.r600.tiling_npipes; | |
2333 | track->nbanks = p->rdev->config.r600.tiling_nbanks; | |
2334 | track->group_size = p->rdev->config.r600.tiling_group_size; | |
2335 | } else if (p->rdev->family <= CHIP_RV740) { | |
2336 | track->npipes = p->rdev->config.rv770.tiling_npipes; | |
2337 | track->nbanks = p->rdev->config.rv770.tiling_nbanks; | |
2338 | track->group_size = p->rdev->config.rv770.tiling_group_size; | |
2339 | } | |
2340 | p->track = track; | |
2341 | } | |
3ce0a23d JG |
2342 | do { |
2343 | r = r600_cs_packet_parse(p, &pkt, p->idx); | |
2344 | if (r) { | |
7cb72ef4 JG |
2345 | kfree(p->track); |
2346 | p->track = NULL; | |
3ce0a23d JG |
2347 | return r; |
2348 | } | |
2349 | p->idx += pkt.count + 2; | |
2350 | switch (pkt.type) { | |
2351 | case PACKET_TYPE0: | |
2352 | r = r600_cs_parse_packet0(p, &pkt); | |
2353 | break; | |
2354 | case PACKET_TYPE2: | |
2355 | break; | |
2356 | case PACKET_TYPE3: | |
2357 | r = r600_packet3_check(p, &pkt); | |
2358 | break; | |
2359 | default: | |
2360 | DRM_ERROR("Unknown packet type %d !\n", pkt.type); | |
961fb597 | 2361 | kfree(p->track); |
7cb72ef4 | 2362 | p->track = NULL; |
3ce0a23d JG |
2363 | return -EINVAL; |
2364 | } | |
2365 | if (r) { | |
961fb597 | 2366 | kfree(p->track); |
7cb72ef4 | 2367 | p->track = NULL; |
3ce0a23d JG |
2368 | return r; |
2369 | } | |
2370 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); | |
2371 | #if 0 | |
f2e39221 JG |
2372 | for (r = 0; r < p->ib.length_dw; r++) { |
2373 | printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]); | |
3ce0a23d JG |
2374 | mdelay(1); |
2375 | } | |
2376 | #endif | |
961fb597 | 2377 | kfree(p->track); |
7cb72ef4 | 2378 | p->track = NULL; |
3ce0a23d JG |
2379 | return 0; |
2380 | } | |
2381 | ||
2382 | static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p) | |
2383 | { | |
2384 | if (p->chunk_relocs_idx == -1) { | |
2385 | return 0; | |
2386 | } | |
e265f39e | 2387 | p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL); |
3ce0a23d JG |
2388 | if (p->relocs == NULL) { |
2389 | return -ENOMEM; | |
2390 | } | |
2391 | return 0; | |
2392 | } | |
2393 | ||
2394 | /** | |
2395 | * cs_parser_fini() - clean parser states | |
2396 | * @parser: parser structure holding parsing context. | |
2397 | * @error: error number | |
2398 | * | |
2399 | * If error is set than unvalidate buffer, otherwise just free memory | |
2400 | * used by parsing context. | |
2401 | **/ | |
2402 | static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error) | |
2403 | { | |
2404 | unsigned i; | |
2405 | ||
2406 | kfree(parser->relocs); | |
2407 | for (i = 0; i < parser->nchunks; i++) { | |
2408 | kfree(parser->chunks[i].kdata); | |
4c57edba DA |
2409 | kfree(parser->chunks[i].kpage[0]); |
2410 | kfree(parser->chunks[i].kpage[1]); | |
3ce0a23d JG |
2411 | } |
2412 | kfree(parser->chunks); | |
2413 | kfree(parser->chunks_array); | |
2414 | } | |
2415 | ||
2416 | int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, | |
2417 | unsigned family, u32 *ib, int *l) | |
2418 | { | |
2419 | struct radeon_cs_parser parser; | |
2420 | struct radeon_cs_chunk *ib_chunk; | |
961fb597 | 2421 | struct r600_cs_track *track; |
3ce0a23d JG |
2422 | int r; |
2423 | ||
961fb597 JG |
2424 | /* initialize tracker */ |
2425 | track = kzalloc(sizeof(*track), GFP_KERNEL); | |
2426 | if (track == NULL) | |
2427 | return -ENOMEM; | |
2428 | r600_cs_track_init(track); | |
2429 | r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size); | |
3ce0a23d JG |
2430 | /* initialize parser */ |
2431 | memset(&parser, 0, sizeof(struct radeon_cs_parser)); | |
2432 | parser.filp = filp; | |
c8c15ff1 | 2433 | parser.dev = &dev->pdev->dev; |
3ce0a23d JG |
2434 | parser.rdev = NULL; |
2435 | parser.family = family; | |
961fb597 | 2436 | parser.track = track; |
f2e39221 | 2437 | parser.ib.ptr = ib; |
3ce0a23d JG |
2438 | r = radeon_cs_parser_init(&parser, data); |
2439 | if (r) { | |
2440 | DRM_ERROR("Failed to initialize parser !\n"); | |
2441 | r600_cs_parser_fini(&parser, r); | |
2442 | return r; | |
2443 | } | |
2444 | r = r600_cs_parser_relocs_legacy(&parser); | |
2445 | if (r) { | |
2446 | DRM_ERROR("Failed to parse relocation !\n"); | |
2447 | r600_cs_parser_fini(&parser, r); | |
2448 | return r; | |
2449 | } | |
2450 | /* Copy the packet into the IB, the parser will read from the | |
2451 | * input memory (cached) and write to the IB (which can be | |
2452 | * uncached). */ | |
2453 | ib_chunk = &parser.chunks[parser.chunk_ib_idx]; | |
f2e39221 JG |
2454 | parser.ib.length_dw = ib_chunk->length_dw; |
2455 | *l = parser.ib.length_dw; | |
3ce0a23d JG |
2456 | r = r600_cs_parse(&parser); |
2457 | if (r) { | |
2458 | DRM_ERROR("Invalid command stream !\n"); | |
2459 | r600_cs_parser_fini(&parser, r); | |
2460 | return r; | |
2461 | } | |
513bcb46 DA |
2462 | r = radeon_cs_finish_pages(&parser); |
2463 | if (r) { | |
2464 | DRM_ERROR("Invalid command stream !\n"); | |
2465 | r600_cs_parser_fini(&parser, r); | |
2466 | return r; | |
2467 | } | |
3ce0a23d JG |
2468 | r600_cs_parser_fini(&parser, r); |
2469 | return r; | |
2470 | } | |
2471 | ||
2472 | void r600_cs_legacy_init(void) | |
2473 | { | |
2474 | r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm; | |
2475 | } |