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drm/radeon: initialize tracked CS state
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / r600_cs.c
CommitLineData
3ce0a23d
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
40e2a5c1 28#include <linux/kernel.h>
3ce0a23d
JG		 29#include "drmP.h"
30#include "radeon.h"
3ce0a23d 31#include "r600d.h"
961fb597 32#include "r600_reg_safe.h"
3ce0a23d
JG		 33
34static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
35 struct radeon_cs_reloc **cs_reloc);
36static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
37 struct radeon_cs_reloc **cs_reloc);
38typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
39static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
961fb597
JG		 40extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
41
3ce0a23d 42
c8c15ff1 43struct r600_cs_track {
961fb597
JG		 44 /* configuration we miror so that we use same code btw kms/ums */
45 u32 group_size;
46 u32 nbanks;
47 u32 npipes;
48 /* value we track */
5f77df36 49 u32 sq_config;
c116cc94 50 u32 log_nsamples;
961fb597
JG		 51 u32 nsamples;
52 u32 cb_color_base_last[8];
53 struct radeon_bo *cb_color_bo[8];
16790569 54 u64 cb_color_bo_mc[8];
c116cc94
MO		 55 u64 cb_color_bo_offset[8];
56 struct radeon_bo *cb_color_frag_bo[8];
57 u64 cb_color_frag_offset[8];
58 struct radeon_bo *cb_color_tile_bo[8];
59 u64 cb_color_tile_offset[8];
60 u32 cb_color_mask[8];
961fb597 61 u32 cb_color_info[8];
285484e2 62 u32 cb_color_view[8];
3c12513d 63 u32 cb_color_size_idx[8]; /* unused */
961fb597 64 u32 cb_target_mask;
3c12513d 65 u32 cb_shader_mask; /* unused */
961fb597
JG		 66 u32 cb_color_size[8];
67 u32 vgt_strmout_en;
68 u32 vgt_strmout_buffer_en;
dd220a00 69 struct radeon_bo *vgt_strmout_bo[4];
3c12513d 70 u64 vgt_strmout_bo_mc[4]; /* unused */
dd220a00
MO		 71 u32 vgt_strmout_bo_offset[4];
72 u32 vgt_strmout_size[4];
961fb597
JG		 73 u32 db_depth_control;
74 u32 db_depth_info;
75 u32 db_depth_size_idx;
76 u32 db_depth_view;
77 u32 db_depth_size;
78 u32 db_offset;
79 struct radeon_bo *db_bo;
16790569 80 u64 db_bo_mc;
779923bc 81 bool sx_misc_kill_all_prims;
3c12513d
MO		 82 bool cb_dirty;
83 bool db_dirty;
84 bool streamout_dirty;
88f50c80
JG		 85 struct radeon_bo *htile_bo;
86 u64 htile_offset;
87 u32 htile_surface;
c8c15ff1
JG		 88};
89
fe6f0bd0
MO		 90#define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }
91#define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 }
285484e2 92#define FMT_24_BIT(fmt) [fmt] = { 1, 1, 4, 0, CHIP_R600 }
fe6f0bd0 93#define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 }
285484e2 94#define FMT_48_BIT(fmt) [fmt] = { 1, 1, 8, 0, CHIP_R600 }
fe6f0bd0
MO		 95#define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 }
96#define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 }
97#define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
60b212f8
DA		 98
99struct gpu_formats {
100 unsigned blockwidth;
101 unsigned blockheight;
102 unsigned blocksize;
103 unsigned valid_color;
fe6f0bd0 104 enum radeon_family min_family;
60b212f8
DA		 105};
106
107static const struct gpu_formats color_formats_table[] = {
108 /* 8 bit */
109 FMT_8_BIT(V_038004_COLOR_8, 1),
110 FMT_8_BIT(V_038004_COLOR_4_4, 1),
111 FMT_8_BIT(V_038004_COLOR_3_3_2, 1),
112 FMT_8_BIT(V_038004_FMT_1, 0),
113
114 /* 16-bit */
115 FMT_16_BIT(V_038004_COLOR_16, 1),
116 FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),
117 FMT_16_BIT(V_038004_COLOR_8_8, 1),
118 FMT_16_BIT(V_038004_COLOR_5_6_5, 1),
119 FMT_16_BIT(V_038004_COLOR_6_5_5, 1),
120 FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),
121 FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),
122 FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),
123
124 /* 24-bit */
125 FMT_24_BIT(V_038004_FMT_8_8_8),
285484e2 126
60b212f8
DA		 127 /* 32-bit */
128 FMT_32_BIT(V_038004_COLOR_32, 1),
129 FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
130 FMT_32_BIT(V_038004_COLOR_16_16, 1),
131 FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),
132 FMT_32_BIT(V_038004_COLOR_8_24, 1),
133 FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),
134 FMT_32_BIT(V_038004_COLOR_24_8, 1),
135 FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),
136 FMT_32_BIT(V_038004_COLOR_10_11_11, 1),
137 FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),
138 FMT_32_BIT(V_038004_COLOR_11_11_10, 1),
139 FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),
140 FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),
141 FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),
142 FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),
143 FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),
144 FMT_32_BIT(V_038004_FMT_32_AS_8, 0),
145 FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),
146
147 /* 48-bit */
148 FMT_48_BIT(V_038004_FMT_16_16_16),
149 FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),
150
151 /* 64-bit */
152 FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),
153 FMT_64_BIT(V_038004_COLOR_32_32, 1),
154 FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),
155 FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),
156 FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),
157
158 FMT_96_BIT(V_038004_FMT_32_32_32),
159 FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),
160
161 /* 128-bit */
162 FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),
163 FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),
164
165 [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },
166 [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },
167
168 /* block compressed formats */
169 [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
170 [V_038004_FMT_BC2] = { 4, 4, 16, 0 },
171 [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
172 [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
173 [V_038004_FMT_BC5] = { 4, 4, 16, 0},
fe6f0bd0
MO		 174 [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
175 [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
60b212f8 176
fe6f0bd0
MO		 177 /* The other Evergreen formats */
178 [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
60b212f8
DA		 179};
180
285484e2 181bool r600_fmt_is_valid_color(u32 format)
60b212f8 182{
cf8a47d1 183 if (format >= ARRAY_SIZE(color_formats_table))
60b212f8 184 return false;
285484e2 185
60b212f8
DA		 186 if (color_formats_table[format].valid_color)
187 return true;
188
189 return false;
190}
191
285484e2 192bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)
60b212f8 193{
cf8a47d1 194 if (format >= ARRAY_SIZE(color_formats_table))
60b212f8 195 return false;
285484e2 196
fe6f0bd0
MO		 197 if (family < color_formats_table[format].min_family)
198 return false;
199
60b212f8
DA		 200 if (color_formats_table[format].blockwidth > 0)
201 return true;
202
203 return false;
204}
205
285484e2 206int r600_fmt_get_blocksize(u32 format)
60b212f8 207{
cf8a47d1 208 if (format >= ARRAY_SIZE(color_formats_table))
60b212f8
DA		 209 return 0;
210
211 return color_formats_table[format].blocksize;
212}
213
285484e2 214int r600_fmt_get_nblocksx(u32 format, u32 w)
60b212f8
DA		 215{
216 unsigned bw;
cf8a47d1
DC		 217
218 if (format >= ARRAY_SIZE(color_formats_table))
60b212f8
DA		 219 return 0;
220
221 bw = color_formats_table[format].blockwidth;
222 if (bw == 0)
223 return 0;
224
225 return (w + bw - 1) / bw;
226}
227
285484e2 228int r600_fmt_get_nblocksy(u32 format, u32 h)
60b212f8
DA		 229{
230 unsigned bh;
cf8a47d1
DC		 231
232 if (format >= ARRAY_SIZE(color_formats_table))
60b212f8
DA		 233 return 0;
234
235 bh = color_formats_table[format].blockheight;
236 if (bh == 0)
237 return 0;
238
239 return (h + bh - 1) / bh;
240}
241
16790569
AD		 242struct array_mode_checker {
243 int array_mode;
244 u32 group_size;
245 u32 nbanks;
246 u32 npipes;
247 u32 nsamples;
60b212f8 248 u32 blocksize;
16790569
AD		 249};
250
251/* returns alignment in pixels for pitch/height/depth and bytes for base */
488479eb 252static int r600_get_array_mode_alignment(struct array_mode_checker *values,
16790569
AD		 253 u32 *pitch_align,
254 u32 *height_align,
255 u32 *depth_align,
256 u64 *base_align)
257{
258 u32 tile_width = 8;
259 u32 tile_height = 8;
260 u32 macro_tile_width = values->nbanks;
261 u32 macro_tile_height = values->npipes;
60b212f8 262 u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;
16790569
AD		 263 u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
264
265 switch (values->array_mode) {
266 case ARRAY_LINEAR_GENERAL:
267 /* technically tile_width/_height for pitch/height */
268 *pitch_align = 1; /* tile_width */
269 *height_align = 1; /* tile_height */
270 *depth_align = 1;
271 *base_align = 1;
272 break;
273 case ARRAY_LINEAR_ALIGNED:
60b212f8 274 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
285484e2 275 *height_align = 1;
16790569
AD		 276 *depth_align = 1;
277 *base_align = values->group_size;
278 break;
279 case ARRAY_1D_TILED_THIN1:
280 *pitch_align = max((u32)tile_width,
281 (u32)(values->group_size /
60b212f8 282 (tile_height * values->blocksize * values->nsamples)));
16790569
AD		 283 *height_align = tile_height;
284 *depth_align = 1;
285 *base_align = values->group_size;
286 break;
287 case ARRAY_2D_TILED_THIN1:
285484e2
JG		 288 *pitch_align = max((u32)macro_tile_width * tile_width,
289 (u32)((values->group_size * values->nbanks) /
290 (values->blocksize * values->nsamples * tile_width)));
16790569
AD		 291 *height_align = macro_tile_height * tile_height;
292 *depth_align = 1;
293 *base_align = max(macro_tile_bytes,
60b212f8 294 (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);
16790569
AD		 295 break;
296 default:
297 return -EINVAL;
298 }
299
300 return 0;
301}
302
961fb597
JG		 303static void r600_cs_track_init(struct r600_cs_track *track)
304{
305 int i;
306
5f77df36
AD		 307 /* assume DX9 mode */
308 track->sq_config = DX9_CONSTS;
961fb597
JG		 309 for (i = 0; i < 8; i++) {
310 track->cb_color_base_last[i] = 0;
311 track->cb_color_size[i] = 0;
312 track->cb_color_size_idx[i] = 0;
313 track->cb_color_info[i] = 0;
285484e2 314 track->cb_color_view[i] = 0xFFFFFFFF;
961fb597
JG		 315 track->cb_color_bo[i] = NULL;
316 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
16790569 317 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
3b5ef597
MO		 318 track->cb_color_frag_bo[i] = NULL;
319 track->cb_color_frag_offset[i] = 0xFFFFFFFF;
320 track->cb_color_tile_bo[i] = NULL;
321 track->cb_color_tile_offset[i] = 0xFFFFFFFF;
322 track->cb_color_mask[i] = 0xFFFFFFFF;
961fb597 323 }
3b5ef597
MO		 324 track->nsamples = 16;
325 track->log_nsamples = 4;
961fb597
JG		 326 track->cb_target_mask = 0xFFFFFFFF;
327 track->cb_shader_mask = 0xFFFFFFFF;
3c12513d 328 track->cb_dirty = true;
961fb597 329 track->db_bo = NULL;
16790569 330 track->db_bo_mc = 0xFFFFFFFF;
961fb597
JG		 331 /* assume the biggest format and that htile is enabled */
332 track->db_depth_info = 7 | (1 << 25);
333 track->db_depth_view = 0xFFFFC000;
334 track->db_depth_size = 0xFFFFFFFF;
335 track->db_depth_size_idx = 0;
336 track->db_depth_control = 0xFFFFFFFF;
3c12513d 337 track->db_dirty = true;
88f50c80
JG		 338 track->htile_bo = NULL;
339 track->htile_offset = 0xFFFFFFFF;
340 track->htile_surface = 0;
dd220a00
MO		 341
342 for (i = 0; i < 4; i++) {
343 track->vgt_strmout_size[i] = 0;
344 track->vgt_strmout_bo[i] = NULL;
345 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
346 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
347 }
3c12513d 348 track->streamout_dirty = true;
779923bc 349 track->sx_misc_kill_all_prims = false;
961fb597
JG		 350}
351
488479eb 352static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
961fb597
JG		 353{
354 struct r600_cs_track *track = p->track;
60b212f8 355 u32 slice_tile_max, size, tmp;
16790569
AD		 356 u32 height, height_align, pitch, pitch_align, depth_align;
357 u64 base_offset, base_align;
358 struct array_mode_checker array_check;
f2e39221 359 volatile u32 *ib = p->ib.ptr;
f30df2fa 360 unsigned array_mode;
60b212f8 361 u32 format;
285484e2 362
1729dd33 363 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
60b212f8 364 format = G_0280A0_FORMAT(track->cb_color_info[i]);
285484e2 365 if (!r600_fmt_is_valid_color(format)) {
961fb597 366 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
60b212f8 367 __func__, __LINE__, format,
961fb597
JG		 368 i, track->cb_color_info[i]);
369 return -EINVAL;
370 }
16790569
AD		 371 /* pitch in pixels */
372 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
961fb597 373 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
f30df2fa 374 slice_tile_max *= 64;
16790569 375 height = slice_tile_max / pitch;
961fb597
JG		 376 if (height > 8192)
377 height = 8192;
f30df2fa 378 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
16790569
AD		 379
380 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
381 array_check.array_mode = array_mode;
382 array_check.group_size = track->group_size;
383 array_check.nbanks = track->nbanks;
384 array_check.npipes = track->npipes;
385 array_check.nsamples = track->nsamples;
285484e2 386 array_check.blocksize = r600_fmt_get_blocksize(format);
16790569
AD		 387 if (r600_get_array_mode_alignment(&array_check,
388 &pitch_align, &height_align, &depth_align, &base_align)) {
389 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
390 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
391 track->cb_color_info[i]);
392 return -EINVAL;
393 }
f30df2fa 394 switch (array_mode) {
961fb597 395 case V_0280A0_ARRAY_LINEAR_GENERAL:
40e2a5c1 396 break;
961fb597 397 case V_0280A0_ARRAY_LINEAR_ALIGNED:
961fb597
JG		 398 break;
399 case V_0280A0_ARRAY_1D_TILED_THIN1:
8f895da5
AD		 400 /* avoid breaking userspace */
401 if (height > 7)
402 height &= ~0x7;
961fb597
JG		 403 break;
404 case V_0280A0_ARRAY_2D_TILED_THIN1:
961fb597
JG		 405 break;
406 default:
407 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
408 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
409 track->cb_color_info[i]);
410 return -EINVAL;
411 }
16790569
AD		 412
413 if (!IS_ALIGNED(pitch, pitch_align)) {
c2049b3d
AD		 414 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
415 __func__, __LINE__, pitch, pitch_align, array_mode);
16790569
AD		 416 return -EINVAL;
417 }
418 if (!IS_ALIGNED(height, height_align)) {
c2049b3d
AD		 419 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
420 __func__, __LINE__, height, height_align, array_mode);
16790569
AD		 421 return -EINVAL;
422 }
423 if (!IS_ALIGNED(base_offset, base_align)) {
c2049b3d
AD		 424 dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i,
425 base_offset, base_align, array_mode);
16790569
AD		 426 return -EINVAL;
427 }
428
961fb597 429 /* check offset */
fcdeefe4
MO		 430 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
431 r600_fmt_get_blocksize(format) * track->nsamples;
285484e2
JG		 432 switch (array_mode) {
433 default:
434 case V_0280A0_ARRAY_LINEAR_GENERAL:
435 case V_0280A0_ARRAY_LINEAR_ALIGNED:
436 tmp += track->cb_color_view[i] & 0xFF;
437 break;
438 case V_0280A0_ARRAY_1D_TILED_THIN1:
439 case V_0280A0_ARRAY_2D_TILED_THIN1:
440 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
441 break;
442 }
961fb597 443 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
f30df2fa
DA		 444 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
445 /* the initial DDX does bad things with the CB size occasionally */
446 /* it rounds up height too far for slice tile max but the BO is smaller */
a1a82133
AD		 447 /* r600c,g also seem to flush at bad times in some apps resulting in
448 * bogus values here. So for linear just allow anything to avoid breaking
449 * broken userspace.
450 */
f30df2fa 451 } else {
c116cc94 452 dev_warn(p->dev, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n",
285484e2 453 __func__, i, array_mode,
c2049b3d 454 track->cb_color_bo_offset[i], tmp,
285484e2
JG		 455 radeon_bo_size(track->cb_color_bo[i]),
456 pitch, height, r600_fmt_get_nblocksx(format, pitch),
457 r600_fmt_get_nblocksy(format, height),
458 r600_fmt_get_blocksize(format));
f30df2fa
DA		 459 return -EINVAL;
460 }
40e2a5c1 461 }
961fb597 462 /* limit max tile */
16790569 463 tmp = (height * pitch) >> 6;
961fb597
JG		 464 if (tmp < slice_tile_max)
465 slice_tile_max = tmp;
16790569 466 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
961fb597
JG		 467 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
468 ib[track->cb_color_size_idx[i]] = tmp;
c116cc94
MO		 469
470 /* FMASK/CMASK */
471 switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
472 case V_0280A0_TILE_DISABLE:
473 break;
474 case V_0280A0_FRAG_ENABLE:
475 if (track->nsamples > 1) {
476 uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);
477 /* the tile size is 8x8, but the size is in units of bits.
478 * for bytes, do just * 8. */
479 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);
480
481 if (bytes + track->cb_color_frag_offset[i] >
482 radeon_bo_size(track->cb_color_frag_bo[i])) {
483 dev_warn(p->dev, "%s FMASK_TILE_MAX too large "
484 "(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
485 __func__, tile_max, bytes,
486 track->cb_color_frag_offset[i],
487 radeon_bo_size(track->cb_color_frag_bo[i]));
488 return -EINVAL;
489 }
490 }
491 /* fall through */
492 case V_0280A0_CLEAR_ENABLE:
493 {
494 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
495 /* One block = 128x128 pixels, one 8x8 tile has 4 bits..
496 * (128*128) / (8*8) / 2 = 128 bytes per block. */
497 uint32_t bytes = (block_max + 1) * 128;
498
499 if (bytes + track->cb_color_tile_offset[i] >
500 radeon_bo_size(track->cb_color_tile_bo[i])) {
501 dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large "
502 "(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
503 __func__, block_max, bytes,
504 track->cb_color_tile_offset[i],
505 radeon_bo_size(track->cb_color_tile_bo[i]));
506 return -EINVAL;
507 }
508 break;
509 }
510 default:
511 dev_warn(p->dev, "%s invalid tile mode\n", __func__);
512 return -EINVAL;
513 }
961fb597
JG		 514 return 0;
515}
516
88f50c80
JG		 517static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
518{
519 struct r600_cs_track *track = p->track;
520 u32 nviews, bpe, ntiles, size, slice_tile_max, tmp;
521 u32 height_align, pitch_align, depth_align;
522 u32 pitch = 8192;
523 u32 height = 8192;
524 u64 base_offset, base_align;
525 struct array_mode_checker array_check;
526 int array_mode;
f2e39221 527 volatile u32 *ib = p->ib.ptr;
88f50c80
JG		 528
529
530 if (track->db_bo == NULL) {
531 dev_warn(p->dev, "z/stencil with no depth buffer\n");
532 return -EINVAL;
533 }
534 switch (G_028010_FORMAT(track->db_depth_info)) {
535 case V_028010_DEPTH_16:
536 bpe = 2;
537 break;
538 case V_028010_DEPTH_X8_24:
539 case V_028010_DEPTH_8_24:
540 case V_028010_DEPTH_X8_24_FLOAT:
541 case V_028010_DEPTH_8_24_FLOAT:
542 case V_028010_DEPTH_32_FLOAT:
543 bpe = 4;
544 break;
545 case V_028010_DEPTH_X24_8_32_FLOAT:
546 bpe = 8;
547 break;
548 default:
549 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
550 return -EINVAL;
551 }
552 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
553 if (!track->db_depth_size_idx) {
554 dev_warn(p->dev, "z/stencil buffer size not set\n");
555 return -EINVAL;
556 }
557 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
558 tmp = (tmp / bpe) >> 6;
559 if (!tmp) {
560 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
561 track->db_depth_size, bpe, track->db_offset,
562 radeon_bo_size(track->db_bo));
563 return -EINVAL;
564 }
565 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
566 } else {
567 size = radeon_bo_size(track->db_bo);
568 /* pitch in pixels */
569 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
570 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
571 slice_tile_max *= 64;
572 height = slice_tile_max / pitch;
573 if (height > 8192)
574 height = 8192;
575 base_offset = track->db_bo_mc + track->db_offset;
576 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
577 array_check.array_mode = array_mode;
578 array_check.group_size = track->group_size;
579 array_check.nbanks = track->nbanks;
580 array_check.npipes = track->npipes;
581 array_check.nsamples = track->nsamples;
582 array_check.blocksize = bpe;
583 if (r600_get_array_mode_alignment(&array_check,
584 &pitch_align, &height_align, &depth_align, &base_align)) {
585 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
586 G_028010_ARRAY_MODE(track->db_depth_info),
587 track->db_depth_info);
588 return -EINVAL;
589 }
590 switch (array_mode) {
591 case V_028010_ARRAY_1D_TILED_THIN1:
592 /* don't break userspace */
593 height &= ~0x7;
594 break;
595 case V_028010_ARRAY_2D_TILED_THIN1:
596 break;
597 default:
598 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
599 G_028010_ARRAY_MODE(track->db_depth_info),
600 track->db_depth_info);
601 return -EINVAL;
602 }
603
604 if (!IS_ALIGNED(pitch, pitch_align)) {
605 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
606 __func__, __LINE__, pitch, pitch_align, array_mode);
607 return -EINVAL;
608 }
609 if (!IS_ALIGNED(height, height_align)) {
610 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
611 __func__, __LINE__, height, height_align, array_mode);
612 return -EINVAL;
613 }
614 if (!IS_ALIGNED(base_offset, base_align)) {
615 dev_warn(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__,
616 base_offset, base_align, array_mode);
617 return -EINVAL;
618 }
619
620 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
621 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
fcdeefe4 622 tmp = ntiles * bpe * 64 * nviews * track->nsamples;
88f50c80
JG		 623 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
624 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
625 array_mode,
626 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
627 radeon_bo_size(track->db_bo));
628 return -EINVAL;
629 }
630 }
631
632 /* hyperz */
633 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
634 unsigned long size;
635 unsigned nbx, nby;
636
637 if (track->htile_bo == NULL) {
638 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
639 __func__, __LINE__, track->db_depth_info);
640 return -EINVAL;
641 }
642 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
643 dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n",
644 __func__, __LINE__, track->db_depth_size);
645 return -EINVAL;
646 }
647
648 nbx = pitch;
649 nby = height;
650 if (G_028D24_LINEAR(track->htile_surface)) {
651 /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */
652 nbx = round_up(nbx, 16 * 8);
653 /* nby is npipes htiles aligned == npipes * 8 pixel aligned */
654 nby = round_up(nby, track->npipes * 8);
655 } else {
656 /* htile widht & nby (8 or 4) make 2 bits number */
657 tmp = track->htile_surface & 3;
658 /* align is htile align * 8, htile align vary according to
659 * number of pipe and tile width and nby
660 */
661 switch (track->npipes) {
662 case 8:
663 switch (tmp) {
664 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
665 nbx = round_up(nbx, 64 * 8);
666 nby = round_up(nby, 64 * 8);
667 break;
668 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
669 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
670 nbx = round_up(nbx, 64 * 8);
671 nby = round_up(nby, 32 * 8);
672 break;
673 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
674 nbx = round_up(nbx, 32 * 8);
675 nby = round_up(nby, 32 * 8);
676 break;
677 default:
678 return -EINVAL;
679 }
680 break;
681 case 4:
682 switch (tmp) {
683 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
684 nbx = round_up(nbx, 64 * 8);
685 nby = round_up(nby, 32 * 8);
686 break;
687 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
688 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
689 nbx = round_up(nbx, 32 * 8);
690 nby = round_up(nby, 32 * 8);
691 break;
692 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
693 nbx = round_up(nbx, 32 * 8);
694 nby = round_up(nby, 16 * 8);
695 break;
696 default:
697 return -EINVAL;
698 }
699 break;
700 case 2:
701 switch (tmp) {
702 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
703 nbx = round_up(nbx, 32 * 8);
704 nby = round_up(nby, 32 * 8);
705 break;
706 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
707 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
708 nbx = round_up(nbx, 32 * 8);
709 nby = round_up(nby, 16 * 8);
710 break;
711 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
712 nbx = round_up(nbx, 16 * 8);
713 nby = round_up(nby, 16 * 8);
714 break;
715 default:
716 return -EINVAL;
717 }
718 break;
719 case 1:
720 switch (tmp) {
721 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
722 nbx = round_up(nbx, 32 * 8);
723 nby = round_up(nby, 16 * 8);
724 break;
725 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
726 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
727 nbx = round_up(nbx, 16 * 8);
728 nby = round_up(nby, 16 * 8);
729 break;
730 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
731 nbx = round_up(nbx, 16 * 8);
732 nby = round_up(nby, 8 * 8);
733 break;
734 default:
735 return -EINVAL;
736 }
737 break;
738 default:
739 dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
740 __func__, __LINE__, track->npipes);
741 return -EINVAL;
742 }
743 }
744 /* compute number of htile */
745 nbx = G_028D24_HTILE_WIDTH(track->htile_surface) ? nbx / 8 : nbx / 4;
746 nby = G_028D24_HTILE_HEIGHT(track->htile_surface) ? nby / 8 : nby / 4;
747 size = nbx * nby * 4;
748 size += track->htile_offset;
749
750 if (size > radeon_bo_size(track->htile_bo)) {
751 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
752 __func__, __LINE__, radeon_bo_size(track->htile_bo),
753 size, nbx, nby);
754 return -EINVAL;
755 }
756 }
757
758 track->db_dirty = false;
759 return 0;
760}
761
961fb597
JG		 762static int r600_cs_track_check(struct radeon_cs_parser *p)
763{
764 struct r600_cs_track *track = p->track;
765 u32 tmp;
766 int r, i;
961fb597
JG		 767
768 /* on legacy kernel we don't perform advanced check */
769 if (p->rdev == NULL)
770 return 0;
dd220a00
MO		 771
772 /* check streamout */
3c12513d 773 if (track->streamout_dirty && track->vgt_strmout_en) {
dd220a00
MO		 774 for (i = 0; i < 4; i++) {
775 if (track->vgt_strmout_buffer_en & (1 << i)) {
776 if (track->vgt_strmout_bo[i]) {
777 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
778 (u64)track->vgt_strmout_size[i];
779 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
780 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
781 i, offset,
782 radeon_bo_size(track->vgt_strmout_bo[i]));
783 return -EINVAL;
784 }
785 } else {
786 dev_warn(p->dev, "No buffer for streamout %d\n", i);
787 return -EINVAL;
788 }
789 }
790 }
3c12513d 791 track->streamout_dirty = false;
961fb597 792 }
dd220a00 793
779923bc
MO		 794 if (track->sx_misc_kill_all_prims)
795 return 0;
796
961fb597
JG		 797 /* check that we have a cb for each enabled target, we don't check
798 * shader_mask because it seems mesa isn't always setting it :(
799 */
3c12513d
MO		 800 if (track->cb_dirty) {
801 tmp = track->cb_target_mask;
802 for (i = 0; i < 8; i++) {
803 if ((tmp >> (i * 4)) & 0xF) {
804 /* at least one component is enabled */
805 if (track->cb_color_bo[i] == NULL) {
806 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
807 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
808 return -EINVAL;
809 }
810 /* perform rewrite of CB_COLOR[0-7]_SIZE */
811 r = r600_cs_track_validate_cb(p, i);
812 if (r)
813 return r;
961fb597 814 }
961fb597 815 }
3c12513d 816 track->cb_dirty = false;
961fb597 817 }
3c12513d 818
88f50c80 819 /* Check depth buffer */
0f457e48
MO		 820 if (track->db_dirty &&
821 G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID &&
822 (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
823 G_028800_Z_ENABLE(track->db_depth_control))) {
88f50c80
JG		 824 r = r600_cs_track_validate_db(p);
825 if (r)
826 return r;
961fb597 827 }
88f50c80 828
961fb597
JG		 829 return 0;
830}
831
3ce0a23d
JG		 832/**
833 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
834 * @parser: parser structure holding parsing context.
835 * @pkt: where to store packet informations
836 *
837 * Assume that chunk_ib_index is properly set. Will return -EINVAL
838 * if packet is bigger than remaining ib size. or if packets is unknown.
839 **/
840int r600_cs_packet_parse(struct radeon_cs_parser *p,
841 struct radeon_cs_packet *pkt,
842 unsigned idx)
843{
844 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
845 uint32_t header;
846
847 if (idx >= ib_chunk->length_dw) {
848 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
849 idx, ib_chunk->length_dw);
850 return -EINVAL;
851 }
513bcb46 852 header = radeon_get_ib_value(p, idx);
3ce0a23d
JG		 853 pkt->idx = idx;
854 pkt->type = CP_PACKET_GET_TYPE(header);
855 pkt->count = CP_PACKET_GET_COUNT(header);
856 pkt->one_reg_wr = 0;
857 switch (pkt->type) {
858 case PACKET_TYPE0:
859 pkt->reg = CP_PACKET0_GET_REG(header);
860 break;
861 case PACKET_TYPE3:
862 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
863 break;
864 case PACKET_TYPE2:
865 pkt->count = -1;
866 break;
867 default:
868 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
869 return -EINVAL;
870 }
871 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
872 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
873 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
874 return -EINVAL;
875 }
876 return 0;
877}
878
879/**
880 * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
881 * @parser: parser structure holding parsing context.
882 * @data: pointer to relocation data
883 * @offset_start: starting offset
884 * @offset_mask: offset mask (to align start offset on)
885 * @reloc: reloc informations
886 *
887 * Check next packet is relocation packet3, do bo validation and compute
888 * GPU offset using the provided start.
889 **/
890static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
891 struct radeon_cs_reloc **cs_reloc)
892{
3ce0a23d
JG		 893 struct radeon_cs_chunk *relocs_chunk;
894 struct radeon_cs_packet p3reloc;
895 unsigned idx;
896 int r;
897
898 if (p->chunk_relocs_idx == -1) {
899 DRM_ERROR("No relocation chunk !\n");
900 return -EINVAL;
901 }
902 *cs_reloc = NULL;
3ce0a23d
JG		 903 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
904 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
905 if (r) {
906 return r;
907 }
908 p->idx += p3reloc.count + 2;
909 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
910 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
911 p3reloc.idx);
912 return -EINVAL;
913 }
513bcb46 914 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
3ce0a23d
JG		 915 if (idx >= relocs_chunk->length_dw) {
916 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
917 idx, relocs_chunk->length_dw);
918 return -EINVAL;
919 }
920 /* FIXME: we assume reloc size is 4 dwords */
921 *cs_reloc = p->relocs_ptr[(idx / 4)];
922 return 0;
923}
924
925/**
926 * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
927 * @parser: parser structure holding parsing context.
928 * @data: pointer to relocation data
929 * @offset_start: starting offset
930 * @offset_mask: offset mask (to align start offset on)
931 * @reloc: reloc informations
932 *
933 * Check next packet is relocation packet3, do bo validation and compute
934 * GPU offset using the provided start.
935 **/
936static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
937 struct radeon_cs_reloc **cs_reloc)
938{
3ce0a23d
JG		 939 struct radeon_cs_chunk *relocs_chunk;
940 struct radeon_cs_packet p3reloc;
941 unsigned idx;
942 int r;
943
944 if (p->chunk_relocs_idx == -1) {
945 DRM_ERROR("No relocation chunk !\n");
946 return -EINVAL;
947 }
948 *cs_reloc = NULL;
3ce0a23d
JG		 949 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
950 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
951 if (r) {
952 return r;
953 }
954 p->idx += p3reloc.count + 2;
955 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
956 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
957 p3reloc.idx);
958 return -EINVAL;
959 }
513bcb46 960 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
3ce0a23d
JG		 961 if (idx >= relocs_chunk->length_dw) {
962 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
963 idx, relocs_chunk->length_dw);
964 return -EINVAL;
965 }
e265f39e 966 *cs_reloc = p->relocs;
3ce0a23d
JG		 967 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
968 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
969 return 0;
970}
971
c8c15ff1
JG		 972/**
973 * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
974 * @parser: parser structure holding parsing context.
975 *
976 * Check next packet is relocation packet3, do bo validation and compute
977 * GPU offset using the provided start.
978 **/
488479eb 979static int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
c8c15ff1
JG		 980{
981 struct radeon_cs_packet p3reloc;
982 int r;
983
984 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
985 if (r) {
986 return 0;
987 }
988 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
989 return 0;
990 }
991 return 1;
992}
993
2f67c6e0
AD		 994/**
995 * r600_cs_packet_next_vline() - parse userspace VLINE packet
996 * @parser: parser structure holding parsing context.
997 *
998 * Userspace sends a special sequence for VLINE waits.
999 * PACKET0 - VLINE_START_END + value
1000 * PACKET3 - WAIT_REG_MEM poll vline status reg
1001 * RELOC (P3) - crtc_id in reloc.
1002 *
1003 * This function parses this and relocates the VLINE START END
1004 * and WAIT_REG_MEM packets to the correct crtc.
1005 * It also detects a switched off crtc and nulls out the
1006 * wait in that case.
1007 */
1008static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
1009{
1010 struct drm_mode_object *obj;
1011 struct drm_crtc *crtc;
1012 struct radeon_crtc *radeon_crtc;
1013 struct radeon_cs_packet p3reloc, wait_reg_mem;
1014 int crtc_id;
1015 int r;
1016 uint32_t header, h_idx, reg, wait_reg_mem_info;
1017 volatile uint32_t *ib;
1018
f2e39221 1019 ib = p->ib.ptr;
2f67c6e0
AD		 1020
1021 /* parse the WAIT_REG_MEM */
1022 r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
1023 if (r)
1024 return r;
1025
1026 /* check its a WAIT_REG_MEM */
1027 if (wait_reg_mem.type != PACKET_TYPE3 ||
1028 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
1029 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
a3a88a66 1030 return -EINVAL;
2f67c6e0
AD		 1031 }
1032
1033 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
1034 /* bit 4 is reg (0) or mem (1) */
1035 if (wait_reg_mem_info & 0x10) {
1036 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
a3a88a66 1037 return -EINVAL;
2f67c6e0
AD		 1038 }
1039 /* waiting for value to be equal */
1040 if ((wait_reg_mem_info & 0x7) != 0x3) {
1041 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
a3a88a66 1042 return -EINVAL;
2f67c6e0
AD		 1043 }
1044 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
1045 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
a3a88a66 1046 return -EINVAL;
2f67c6e0
AD		 1047 }
1048
1049 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
1050 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
a3a88a66 1051 return -EINVAL;
2f67c6e0
AD		 1052 }
1053
1054 /* jump over the NOP */
1055 r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
1056 if (r)
1057 return r;
1058
1059 h_idx = p->idx - 2;
1060 p->idx += wait_reg_mem.count + 2;
1061 p->idx += p3reloc.count + 2;
1062
1063 header = radeon_get_ib_value(p, h_idx);
1064 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
d4ac6a05 1065 reg = CP_PACKET0_GET_REG(header);
29508eb6 1066
2f67c6e0
AD		 1067 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1068 if (!obj) {
1069 DRM_ERROR("cannot find crtc %d\n", crtc_id);
a3a88a66 1070 return -EINVAL;
2f67c6e0
AD		 1071 }
1072 crtc = obj_to_crtc(obj);
1073 radeon_crtc = to_radeon_crtc(crtc);
1074 crtc_id = radeon_crtc->crtc_id;
1075
1076 if (!crtc->enabled) {
1077 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
1078 ib[h_idx + 2] = PACKET2(0);
1079 ib[h_idx + 3] = PACKET2(0);
1080 ib[h_idx + 4] = PACKET2(0);
1081 ib[h_idx + 5] = PACKET2(0);
1082 ib[h_idx + 6] = PACKET2(0);
1083 ib[h_idx + 7] = PACKET2(0);
1084 ib[h_idx + 8] = PACKET2(0);
1085 } else if (crtc_id == 1) {
1086 switch (reg) {
1087 case AVIVO_D1MODE_VLINE_START_END:
1088 header &= ~R600_CP_PACKET0_REG_MASK;
1089 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1090 break;
1091 default:
1092 DRM_ERROR("unknown crtc reloc\n");
a3a88a66 1093 return -EINVAL;
2f67c6e0
AD		 1094 }
1095 ib[h_idx] = header;
1096 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
1097 }
a3a88a66
PB		 1098
1099 return 0;
2f67c6e0
AD		 1100}
1101
3ce0a23d
JG		 1102static int r600_packet0_check(struct radeon_cs_parser *p,
1103 struct radeon_cs_packet *pkt,
1104 unsigned idx, unsigned reg)
1105{
2f67c6e0
AD		 1106 int r;
1107
3ce0a23d
JG		 1108 switch (reg) {
1109 case AVIVO_D1MODE_VLINE_START_END:
2f67c6e0
AD		 1110 r = r600_cs_packet_parse_vline(p);
1111 if (r) {
1112 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1113 idx, reg);
1114 return r;
1115 }
3ce0a23d
JG		 1116 break;
1117 default:
1118 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1119 reg, idx);
1120 return -EINVAL;
1121 }
1122 return 0;
1123}
1124
1125static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
1126 struct radeon_cs_packet *pkt)
1127{
1128 unsigned reg, i;
1129 unsigned idx;
1130 int r;
1131
1132 idx = pkt->idx + 1;
1133 reg = pkt->reg;
1134 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
1135 r = r600_packet0_check(p, pkt, idx, reg);
1136 if (r) {
1137 return r;
1138 }
1139 }
1140 return 0;
1141}
1142
961fb597
JG		 1143/**
1144 * r600_cs_check_reg() - check if register is authorized or not
1145 * @parser: parser structure holding parsing context
1146 * @reg: register we are testing
1147 * @idx: index into the cs buffer
1148 *
1149 * This function will test against r600_reg_safe_bm and return 0
1150 * if register is safe. If register is not flag as safe this function
1151 * will test it against a list of register needind special handling.
1152 */
488479eb 1153static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
961fb597
JG		 1154{
1155 struct r600_cs_track *track = (struct r600_cs_track *)p->track;
1156 struct radeon_cs_reloc *reloc;
961fb597
JG		 1157 u32 m, i, tmp, *ib;
1158 int r;
1159
1160 i = (reg >> 7);
88498839 1161 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
961fb597
JG		 1162 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1163 return -EINVAL;
1164 }
1165 m = 1 << ((reg >> 2) & 31);
1166 if (!(r600_reg_safe_bm[i] & m))
1167 return 0;
f2e39221 1168 ib = p->ib.ptr;
961fb597 1169 switch (reg) {
25985edc 1170 /* force following reg to 0 in an attempt to disable out buffer
961fb597
JG		 1171 * which will need us to better understand how it works to perform
1172 * security check on it (Jerome)
1173 */
1174 case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
1175 case R_008C44_SQ_ESGS_RING_SIZE:
1176 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
1177 case R_008C54_SQ_ESTMP_RING_SIZE:
1178 case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
1179 case R_008C74_SQ_FBUF_RING_SIZE:
1180 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
1181 case R_008C5C_SQ_GSTMP_RING_SIZE:
1182 case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
1183 case R_008C4C_SQ_GSVS_RING_SIZE:
1184 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
1185 case R_008C6C_SQ_PSTMP_RING_SIZE:
1186 case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
1187 case R_008C7C_SQ_REDUC_RING_SIZE:
1188 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
1189 case R_008C64_SQ_VSTMP_RING_SIZE:
1190 case R_0288C8_SQ_GS_VERT_ITEMSIZE:
1191 /* get value to populate the IB don't remove */
1192 tmp =radeon_get_ib_value(p, idx);
1193 ib[idx] = 0;
1194 break;
5f77df36
AD		 1195 case SQ_CONFIG:
1196 track->sq_config = radeon_get_ib_value(p, idx);
1197 break;
961fb597
JG		 1198 case R_028800_DB_DEPTH_CONTROL:
1199 track->db_depth_control = radeon_get_ib_value(p, idx);
3c12513d 1200 track->db_dirty = true;
961fb597
JG		 1201 break;
1202 case R_028010_DB_DEPTH_INFO:
721604a1 1203 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
e70f224c 1204 r600_cs_packet_next_is_pkt3_nop(p)) {
7f813377
AD		 1205 r = r600_cs_packet_next_reloc(p, &reloc);
1206 if (r) {
1207 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1208 "0x%04X\n", reg);
1209 return -EINVAL;
1210 }
1211 track->db_depth_info = radeon_get_ib_value(p, idx);
1212 ib[idx] &= C_028010_ARRAY_MODE;
1213 track->db_depth_info &= C_028010_ARRAY_MODE;
1214 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1215 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1216 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1217 } else {
1218 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1219 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1220 }
3c12513d 1221 } else {
7f813377 1222 track->db_depth_info = radeon_get_ib_value(p, idx);
3c12513d
MO		 1223 }
1224 track->db_dirty = true;
961fb597
JG		 1225 break;
1226 case R_028004_DB_DEPTH_VIEW:
1227 track->db_depth_view = radeon_get_ib_value(p, idx);
3c12513d 1228 track->db_dirty = true;
961fb597
JG		 1229 break;
1230 case R_028000_DB_DEPTH_SIZE:
1231 track->db_depth_size = radeon_get_ib_value(p, idx);
1232 track->db_depth_size_idx = idx;
3c12513d 1233 track->db_dirty = true;
961fb597
JG		 1234 break;
1235 case R_028AB0_VGT_STRMOUT_EN:
1236 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
3c12513d 1237 track->streamout_dirty = true;
961fb597
JG		 1238 break;
1239 case R_028B20_VGT_STRMOUT_BUFFER_EN:
1240 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
3c12513d 1241 track->streamout_dirty = true;
961fb597 1242 break;
dd220a00
MO		 1243 case VGT_STRMOUT_BUFFER_BASE_0:
1244 case VGT_STRMOUT_BUFFER_BASE_1:
1245 case VGT_STRMOUT_BUFFER_BASE_2:
1246 case VGT_STRMOUT_BUFFER_BASE_3:
1247 r = r600_cs_packet_next_reloc(p, &reloc);
1248 if (r) {
1249 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1250 "0x%04X\n", reg);
1251 return -EINVAL;
1252 }
1253 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1254 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1255 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1256 track->vgt_strmout_bo[tmp] = reloc->robj;
1257 track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset;
3c12513d 1258 track->streamout_dirty = true;
dd220a00
MO		 1259 break;
1260 case VGT_STRMOUT_BUFFER_SIZE_0:
1261 case VGT_STRMOUT_BUFFER_SIZE_1:
1262 case VGT_STRMOUT_BUFFER_SIZE_2:
1263 case VGT_STRMOUT_BUFFER_SIZE_3:
1264 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1265 /* size in register is DWs, convert to bytes */
1266 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
3c12513d 1267 track->streamout_dirty = true;
dd220a00
MO		 1268 break;
1269 case CP_COHER_BASE:
1270 r = r600_cs_packet_next_reloc(p, &reloc);
1271 if (r) {
1272 dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1273 "0x%04X\n", reg);
1274 return -EINVAL;
1275 }
1276 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1277 break;
961fb597
JG		 1278 case R_028238_CB_TARGET_MASK:
1279 track->cb_target_mask = radeon_get_ib_value(p, idx);
3c12513d 1280 track->cb_dirty = true;
961fb597
JG		 1281 break;
1282 case R_02823C_CB_SHADER_MASK:
1283 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1284 break;
1285 case R_028C04_PA_SC_AA_CONFIG:
1286 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
c116cc94 1287 track->log_nsamples = tmp;
961fb597 1288 track->nsamples = 1 << tmp;
3c12513d 1289 track->cb_dirty = true;
961fb597
JG		 1290 break;
1291 case R_0280A0_CB_COLOR0_INFO:
1292 case R_0280A4_CB_COLOR1_INFO:
1293 case R_0280A8_CB_COLOR2_INFO:
1294 case R_0280AC_CB_COLOR3_INFO:
1295 case R_0280B0_CB_COLOR4_INFO:
1296 case R_0280B4_CB_COLOR5_INFO:
1297 case R_0280B8_CB_COLOR6_INFO:
1298 case R_0280BC_CB_COLOR7_INFO:
721604a1 1299 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
e70f224c 1300 r600_cs_packet_next_is_pkt3_nop(p)) {
7f813377
AD		 1301 r = r600_cs_packet_next_reloc(p, &reloc);
1302 if (r) {
1303 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1304 return -EINVAL;
1305 }
1306 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1307 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1308 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1309 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1310 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1311 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1312 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1313 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1314 }
1315 } else {
1316 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1317 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1318 }
3c12513d 1319 track->cb_dirty = true;
961fb597 1320 break;
285484e2
JG		 1321 case R_028080_CB_COLOR0_VIEW:
1322 case R_028084_CB_COLOR1_VIEW:
1323 case R_028088_CB_COLOR2_VIEW:
1324 case R_02808C_CB_COLOR3_VIEW:
1325 case R_028090_CB_COLOR4_VIEW:
1326 case R_028094_CB_COLOR5_VIEW:
1327 case R_028098_CB_COLOR6_VIEW:
1328 case R_02809C_CB_COLOR7_VIEW:
1329 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
1330 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
3c12513d 1331 track->cb_dirty = true;
285484e2 1332 break;
961fb597
JG		 1333 case R_028060_CB_COLOR0_SIZE:
1334 case R_028064_CB_COLOR1_SIZE:
1335 case R_028068_CB_COLOR2_SIZE:
1336 case R_02806C_CB_COLOR3_SIZE:
1337 case R_028070_CB_COLOR4_SIZE:
1338 case R_028074_CB_COLOR5_SIZE:
1339 case R_028078_CB_COLOR6_SIZE:
1340 case R_02807C_CB_COLOR7_SIZE:
1341 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1342 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1343 track->cb_color_size_idx[tmp] = idx;
3c12513d 1344 track->cb_dirty = true;
961fb597
JG		 1345 break;
1346 /* This register were added late, there is userspace
1347 * which does provide relocation for those but set
1348 * 0 offset. In order to avoid breaking old userspace
1349 * we detect this and set address to point to last
1350 * CB_COLOR0_BASE, note that if userspace doesn't set
1351 * CB_COLOR0_BASE before this register we will report
1352 * error. Old userspace always set CB_COLOR0_BASE
1353 * before any of this.
1354 */
1355 case R_0280E0_CB_COLOR0_FRAG:
1356 case R_0280E4_CB_COLOR1_FRAG:
1357 case R_0280E8_CB_COLOR2_FRAG:
1358 case R_0280EC_CB_COLOR3_FRAG:
1359 case R_0280F0_CB_COLOR4_FRAG:
1360 case R_0280F4_CB_COLOR5_FRAG:
1361 case R_0280F8_CB_COLOR6_FRAG:
1362 case R_0280FC_CB_COLOR7_FRAG:
1363 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
1364 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1365 if (!track->cb_color_base_last[tmp]) {
1366 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1367 return -EINVAL;
1368 }
961fb597 1369 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
c116cc94
MO		 1370 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
1371 ib[idx] = track->cb_color_base_last[tmp];
961fb597
JG		 1372 } else {
1373 r = r600_cs_packet_next_reloc(p, &reloc);
1374 if (r) {
1375 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1376 return -EINVAL;
1377 }
961fb597 1378 track->cb_color_frag_bo[tmp] = reloc->robj;
c116cc94
MO		 1379 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
1380 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1381 }
1382 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1383 track->cb_dirty = true;
961fb597
JG		 1384 }
1385 break;
1386 case R_0280C0_CB_COLOR0_TILE:
1387 case R_0280C4_CB_COLOR1_TILE:
1388 case R_0280C8_CB_COLOR2_TILE:
1389 case R_0280CC_CB_COLOR3_TILE:
1390 case R_0280D0_CB_COLOR4_TILE:
1391 case R_0280D4_CB_COLOR5_TILE:
1392 case R_0280D8_CB_COLOR6_TILE:
1393 case R_0280DC_CB_COLOR7_TILE:
1394 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
1395 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1396 if (!track->cb_color_base_last[tmp]) {
1397 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1398 return -EINVAL;
1399 }
961fb597 1400 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
c116cc94
MO		 1401 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
1402 ib[idx] = track->cb_color_base_last[tmp];
961fb597
JG		 1403 } else {
1404 r = r600_cs_packet_next_reloc(p, &reloc);
1405 if (r) {
1406 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1407 return -EINVAL;
1408 }
961fb597 1409 track->cb_color_tile_bo[tmp] = reloc->robj;
c116cc94
MO		 1410 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
1411 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1412 }
1413 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1414 track->cb_dirty = true;
1415 }
1416 break;
1417 case R_028100_CB_COLOR0_MASK:
1418 case R_028104_CB_COLOR1_MASK:
1419 case R_028108_CB_COLOR2_MASK:
1420 case R_02810C_CB_COLOR3_MASK:
1421 case R_028110_CB_COLOR4_MASK:
1422 case R_028114_CB_COLOR5_MASK:
1423 case R_028118_CB_COLOR6_MASK:
1424 case R_02811C_CB_COLOR7_MASK:
1425 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
305a3d20 1426 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
c116cc94
MO		 1427 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1428 track->cb_dirty = true;
961fb597
JG		 1429 }
1430 break;
1431 case CB_COLOR0_BASE:
1432 case CB_COLOR1_BASE:
1433 case CB_COLOR2_BASE:
1434 case CB_COLOR3_BASE:
1435 case CB_COLOR4_BASE:
1436 case CB_COLOR5_BASE:
1437 case CB_COLOR6_BASE:
1438 case CB_COLOR7_BASE:
1439 r = r600_cs_packet_next_reloc(p, &reloc);
1440 if (r) {
1441 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1442 "0x%04X\n", reg);
1443 return -EINVAL;
1444 }
7cb72ef4 1445 tmp = (reg - CB_COLOR0_BASE) / 4;
1729dd33 1446 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
961fb597 1447 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
961fb597
JG		 1448 track->cb_color_base_last[tmp] = ib[idx];
1449 track->cb_color_bo[tmp] = reloc->robj;
16790569 1450 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
3c12513d 1451 track->cb_dirty = true;
961fb597
JG		 1452 break;
1453 case DB_DEPTH_BASE:
1454 r = r600_cs_packet_next_reloc(p, &reloc);
1455 if (r) {
1456 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1457 "0x%04X\n", reg);
1458 return -EINVAL;
1459 }
1729dd33 1460 track->db_offset = radeon_get_ib_value(p, idx) << 8;
961fb597
JG		 1461 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1462 track->db_bo = reloc->robj;
16790569 1463 track->db_bo_mc = reloc->lobj.gpu_offset;
3c12513d 1464 track->db_dirty = true;
961fb597
JG		 1465 break;
1466 case DB_HTILE_DATA_BASE:
88f50c80
JG		 1467 r = r600_cs_packet_next_reloc(p, &reloc);
1468 if (r) {
1469 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1470 "0x%04X\n", reg);
1471 return -EINVAL;
1472 }
1473 track->htile_offset = radeon_get_ib_value(p, idx) << 8;
1474 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1475 track->htile_bo = reloc->robj;
1476 track->db_dirty = true;
1477 break;
1478 case DB_HTILE_SURFACE:
1479 track->htile_surface = radeon_get_ib_value(p, idx);
1480 track->db_dirty = true;
1481 break;
961fb597
JG		 1482 case SQ_PGM_START_FS:
1483 case SQ_PGM_START_ES:
1484 case SQ_PGM_START_VS:
1485 case SQ_PGM_START_GS:
1486 case SQ_PGM_START_PS:
5f77df36
AD		 1487 case SQ_ALU_CONST_CACHE_GS_0:
1488 case SQ_ALU_CONST_CACHE_GS_1:
1489 case SQ_ALU_CONST_CACHE_GS_2:
1490 case SQ_ALU_CONST_CACHE_GS_3:
1491 case SQ_ALU_CONST_CACHE_GS_4:
1492 case SQ_ALU_CONST_CACHE_GS_5:
1493 case SQ_ALU_CONST_CACHE_GS_6:
1494 case SQ_ALU_CONST_CACHE_GS_7:
1495 case SQ_ALU_CONST_CACHE_GS_8:
1496 case SQ_ALU_CONST_CACHE_GS_9:
1497 case SQ_ALU_CONST_CACHE_GS_10:
1498 case SQ_ALU_CONST_CACHE_GS_11:
1499 case SQ_ALU_CONST_CACHE_GS_12:
1500 case SQ_ALU_CONST_CACHE_GS_13:
1501 case SQ_ALU_CONST_CACHE_GS_14:
1502 case SQ_ALU_CONST_CACHE_GS_15:
1503 case SQ_ALU_CONST_CACHE_PS_0:
1504 case SQ_ALU_CONST_CACHE_PS_1:
1505 case SQ_ALU_CONST_CACHE_PS_2:
1506 case SQ_ALU_CONST_CACHE_PS_3:
1507 case SQ_ALU_CONST_CACHE_PS_4:
1508 case SQ_ALU_CONST_CACHE_PS_5:
1509 case SQ_ALU_CONST_CACHE_PS_6:
1510 case SQ_ALU_CONST_CACHE_PS_7:
1511 case SQ_ALU_CONST_CACHE_PS_8:
1512 case SQ_ALU_CONST_CACHE_PS_9:
1513 case SQ_ALU_CONST_CACHE_PS_10:
1514 case SQ_ALU_CONST_CACHE_PS_11:
1515 case SQ_ALU_CONST_CACHE_PS_12:
1516 case SQ_ALU_CONST_CACHE_PS_13:
1517 case SQ_ALU_CONST_CACHE_PS_14:
1518 case SQ_ALU_CONST_CACHE_PS_15:
1519 case SQ_ALU_CONST_CACHE_VS_0:
1520 case SQ_ALU_CONST_CACHE_VS_1:
1521 case SQ_ALU_CONST_CACHE_VS_2:
1522 case SQ_ALU_CONST_CACHE_VS_3:
1523 case SQ_ALU_CONST_CACHE_VS_4:
1524 case SQ_ALU_CONST_CACHE_VS_5:
1525 case SQ_ALU_CONST_CACHE_VS_6:
1526 case SQ_ALU_CONST_CACHE_VS_7:
1527 case SQ_ALU_CONST_CACHE_VS_8:
1528 case SQ_ALU_CONST_CACHE_VS_9:
1529 case SQ_ALU_CONST_CACHE_VS_10:
1530 case SQ_ALU_CONST_CACHE_VS_11:
1531 case SQ_ALU_CONST_CACHE_VS_12:
1532 case SQ_ALU_CONST_CACHE_VS_13:
1533 case SQ_ALU_CONST_CACHE_VS_14:
1534 case SQ_ALU_CONST_CACHE_VS_15:
961fb597
JG		 1535 r = r600_cs_packet_next_reloc(p, &reloc);
1536 if (r) {
1537 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1538 "0x%04X\n", reg);
1539 return -EINVAL;
033b5650
AD		 1540 }
1541 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1542 break;
1543 case SX_MEMORY_EXPORT_BASE:
1544 r = r600_cs_packet_next_reloc(p, &reloc);
1545 if (r) {
1546 dev_warn(p->dev, "bad SET_CONFIG_REG "
1547 "0x%04X\n", reg);
1548 return -EINVAL;
961fb597
JG		 1549 }
1550 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1551 break;
779923bc
MO		 1552 case SX_MISC:
1553 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1554 break;
961fb597
JG		 1555 default:
1556 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1557 return -EINVAL;
1558 }
1559 return 0;
1560}
1561
285484e2 1562unsigned r600_mip_minify(unsigned size, unsigned level)
961fb597 1563{
60b212f8
DA		 1564 unsigned val;
1565
1566 val = max(1U, size >> level);
1567 if (level > 0)
1568 val = roundup_pow_of_two(val);
1569 return val;
961fb597
JG		 1570}
1571
60b212f8 1572static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
fcdeefe4 1573 unsigned w0, unsigned h0, unsigned d0, unsigned nsamples, unsigned format,
60b212f8 1574 unsigned block_align, unsigned height_align, unsigned base_align,
40e2a5c1 1575 unsigned *l0_size, unsigned *mipmap_size)
961fb597 1576{
60b212f8
DA		 1577 unsigned offset, i, level;
1578 unsigned width, height, depth, size;
1579 unsigned blocksize;
1580 unsigned nbx, nby;
1581 unsigned nlevels = llevel - blevel + 1;
961fb597 1582
60b212f8 1583 *l0_size = -1;
285484e2 1584 blocksize = r600_fmt_get_blocksize(format);
60b212f8 1585
285484e2
JG		 1586 w0 = r600_mip_minify(w0, 0);
1587 h0 = r600_mip_minify(h0, 0);
1588 d0 = r600_mip_minify(d0, 0);
961fb597 1589 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
285484e2
JG		 1590 width = r600_mip_minify(w0, i);
1591 nbx = r600_fmt_get_nblocksx(format, width);
60b212f8
DA		 1592
1593 nbx = round_up(nbx, block_align);
1594
285484e2
JG		 1595 height = r600_mip_minify(h0, i);
1596 nby = r600_fmt_get_nblocksy(format, height);
60b212f8
DA		 1597 nby = round_up(nby, height_align);
1598
285484e2 1599 depth = r600_mip_minify(d0, i);
60b212f8 1600
fcdeefe4 1601 size = nbx * nby * blocksize * nsamples;
60b212f8
DA		 1602 if (nfaces)
1603 size *= nfaces;
1604 else
1605 size *= depth;
1606
1607 if (i == 0)
1608 *l0_size = size;
1609
1610 if (i == 0 || i == 1)
1611 offset = round_up(offset, base_align);
1612
1613 offset += size;
961fb597 1614 }
961fb597 1615 *mipmap_size = offset;
60b212f8 1616 if (llevel == 0)
961fb597 1617 *mipmap_size = *l0_size;
1729dd33
AD		 1618 if (!blevel)
1619 *mipmap_size -= *l0_size;
961fb597
JG		 1620}
1621
1622/**
1623 * r600_check_texture_resource() - check if register is authorized or not
1624 * @p: parser structure holding parsing context
1625 * @idx: index into the cs buffer
1626 * @texture: texture's bo structure
1627 * @mipmap: mipmap's bo structure
1628 *
1629 * This function will check that the resource has valid field and that
1630 * the texture and mipmap bo object are big enough to cover this resource.
1631 */
488479eb 1632static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
7f813377
AD		 1633 struct radeon_bo *texture,
1634 struct radeon_bo *mipmap,
16790569
AD		 1635 u64 base_offset,
1636 u64 mip_offset,
7f813377 1637 u32 tiling_flags)
961fb597 1638{
40e2a5c1 1639 struct r600_cs_track *track = p->track;
f00245f1
MO		 1640 u32 dim, nfaces, llevel, blevel, w0, h0, d0;
1641 u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5;
16790569 1642 u32 height_align, pitch, pitch_align, depth_align;
f00245f1 1643 u32 barray, larray;
16790569
AD		 1644 u64 base_align;
1645 struct array_mode_checker array_check;
60b212f8 1646 u32 format;
f00245f1 1647 bool is_array;
961fb597
JG		 1648
1649 /* on legacy kernel we don't perform advanced check */
1650 if (p->rdev == NULL)
1651 return 0;
7f813377 1652
16790569
AD		 1653 /* convert to bytes */
1654 base_offset <<= 8;
1655 mip_offset <<= 8;
1656
961fb597 1657 word0 = radeon_get_ib_value(p, idx + 0);
721604a1 1658 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
e70f224c
MO		 1659 if (tiling_flags & RADEON_TILING_MACRO)
1660 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1661 else if (tiling_flags & RADEON_TILING_MICRO)
1662 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1663 }
961fb597 1664 word1 = radeon_get_ib_value(p, idx + 1);
f00245f1
MO		 1665 word2 = radeon_get_ib_value(p, idx + 2) << 8;
1666 word3 = radeon_get_ib_value(p, idx + 3) << 8;
1667 word4 = radeon_get_ib_value(p, idx + 4);
1668 word5 = radeon_get_ib_value(p, idx + 5);
1669 dim = G_038000_DIM(word0);
961fb597 1670 w0 = G_038000_TEX_WIDTH(word0) + 1;
f00245f1 1671 pitch = (G_038000_PITCH(word0) + 1) * 8;
961fb597
JG		 1672 h0 = G_038004_TEX_HEIGHT(word1) + 1;
1673 d0 = G_038004_TEX_DEPTH(word1);
f00245f1
MO		 1674 format = G_038004_DATA_FORMAT(word1);
1675 blevel = G_038010_BASE_LEVEL(word4);
1676 llevel = G_038014_LAST_LEVEL(word5);
1677 /* pitch in texels */
1678 array_check.array_mode = G_038000_TILE_MODE(word0);
1679 array_check.group_size = track->group_size;
1680 array_check.nbanks = track->nbanks;
1681 array_check.npipes = track->npipes;
1682 array_check.nsamples = 1;
1683 array_check.blocksize = r600_fmt_get_blocksize(format);
961fb597 1684 nfaces = 1;
f00245f1
MO		 1685 is_array = false;
1686 switch (dim) {
961fb597
JG		 1687 case V_038000_SQ_TEX_DIM_1D:
1688 case V_038000_SQ_TEX_DIM_2D:
1689 case V_038000_SQ_TEX_DIM_3D:
1690 break;
1691 case V_038000_SQ_TEX_DIM_CUBEMAP:
60b212f8
DA		 1692 if (p->family >= CHIP_RV770)
1693 nfaces = 8;
1694 else
1695 nfaces = 6;
961fb597
JG		 1696 break;
1697 case V_038000_SQ_TEX_DIM_1D_ARRAY:
1698 case V_038000_SQ_TEX_DIM_2D_ARRAY:
f00245f1 1699 is_array = true;
60b212f8 1700 break;
961fb597 1701 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
b51ad12a
MO		 1702 is_array = true;
1703 /* fall through */
1704 case V_038000_SQ_TEX_DIM_2D_MSAA:
1705 array_check.nsamples = 1 << llevel;
1706 llevel = 0;
1707 break;
961fb597
JG		 1708 default:
1709 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1710 return -EINVAL;
1711 }
285484e2 1712 if (!r600_fmt_is_valid_texture(format, p->family)) {
961fb597 1713 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
60b212f8 1714 __func__, __LINE__, format);
961fb597
JG		 1715 return -EINVAL;
1716 }
40e2a5c1 1717
16790569
AD		 1718 if (r600_get_array_mode_alignment(&array_check,
1719 &pitch_align, &height_align, &depth_align, &base_align)) {
1720 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
1721 __func__, __LINE__, G_038000_TILE_MODE(word0));
1722 return -EINVAL;
1723 }
1724
1725 /* XXX check height as well... */
1726
1727 if (!IS_ALIGNED(pitch, pitch_align)) {
c2049b3d
AD		 1728 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
1729 __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0));
16790569
AD		 1730 return -EINVAL;
1731 }
1732 if (!IS_ALIGNED(base_offset, base_align)) {
c2049b3d
AD		 1733 dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",
1734 __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0));
16790569
AD		 1735 return -EINVAL;
1736 }
1737 if (!IS_ALIGNED(mip_offset, base_align)) {
c2049b3d
AD		 1738 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",
1739 __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0));
40e2a5c1
AD		 1740 return -EINVAL;
1741 }
40e2a5c1 1742
285484e2
JG		 1743 if (blevel > llevel) {
1744 dev_warn(p->dev, "texture blevel %d > llevel %d\n",
1745 blevel, llevel);
1746 }
f00245f1
MO		 1747 if (is_array) {
1748 barray = G_038014_BASE_ARRAY(word5);
1749 larray = G_038014_LAST_ARRAY(word5);
60b212f8
DA		 1750
1751 nfaces = larray - barray + 1;
1752 }
fcdeefe4 1753 r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, array_check.nsamples, format,
60b212f8 1754 pitch_align, height_align, base_align,
40e2a5c1 1755 &l0_size, &mipmap_size);
961fb597 1756 /* using get ib will give us the offset into the texture bo */
af50621a 1757 if ((l0_size + word2) > radeon_bo_size(texture)) {
285484e2
JG		 1758 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n",
1759 w0, h0, pitch_align, height_align,
1760 array_check.array_mode, format, word2,
1761 l0_size, radeon_bo_size(texture));
60b212f8 1762 dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
961fb597
JG		 1763 return -EINVAL;
1764 }
1765 /* using get ib will give us the offset into the mipmap bo */
af50621a 1766 if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
fe725d4f 1767 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
af50621a 1768 w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
961fb597
JG		 1769 }
1770 return 0;
1771}
1772
dd220a00
MO		 1773static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1774{
1775 u32 m, i;
1776
1777 i = (reg >> 7);
1778 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
1779 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1780 return false;
1781 }
1782 m = 1 << ((reg >> 2) & 31);
1783 if (!(r600_reg_safe_bm[i] & m))
1784 return true;
1785 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1786 return false;
1787}
1788
3ce0a23d
JG		 1789static int r600_packet3_check(struct radeon_cs_parser *p,
1790 struct radeon_cs_packet *pkt)
1791{
3ce0a23d 1792 struct radeon_cs_reloc *reloc;
c8c15ff1 1793 struct r600_cs_track *track;
3ce0a23d
JG		 1794 volatile u32 *ib;
1795 unsigned idx;
1796 unsigned i;
1797 unsigned start_reg, end_reg, reg;
1798 int r;
adea4796 1799 u32 idx_value;
3ce0a23d 1800
c8c15ff1 1801 track = (struct r600_cs_track *)p->track;
f2e39221 1802 ib = p->ib.ptr;
3ce0a23d 1803 idx = pkt->idx + 1;
adea4796 1804 idx_value = radeon_get_ib_value(p, idx);
513bcb46 1805
3ce0a23d 1806 switch (pkt->opcode) {
2a19cac8
DA		 1807 case PACKET3_SET_PREDICATION:
1808 {
1809 int pred_op;
1810 int tmp;
6333003b
MO		 1811 uint64_t offset;
1812
2a19cac8
DA		 1813 if (pkt->count != 1) {
1814 DRM_ERROR("bad SET PREDICATION\n");
1815 return -EINVAL;
1816 }
1817
1818 tmp = radeon_get_ib_value(p, idx + 1);
1819 pred_op = (tmp >> 16) & 0x7;
1820
1821 /* for the clear predicate operation */
1822 if (pred_op == 0)
1823 return 0;
1824
1825 if (pred_op > 2) {
1826 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1827 return -EINVAL;
1828 }
1829
1830 r = r600_cs_packet_next_reloc(p, &reloc);
1831 if (r) {
1832 DRM_ERROR("bad SET PREDICATION\n");
1833 return -EINVAL;
1834 }
1835
6333003b
MO		 1836 offset = reloc->lobj.gpu_offset +
1837 (idx_value & 0xfffffff0) +
1838 ((u64)(tmp & 0xff) << 32);
1839
1840 ib[idx + 0] = offset;
1841 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2a19cac8
DA		 1842 }
1843 break;
1844
3ce0a23d
JG		 1845 case PACKET3_START_3D_CMDBUF:
1846 if (p->family >= CHIP_RV770 || pkt->count) {
1847 DRM_ERROR("bad START_3D\n");
1848 return -EINVAL;
1849 }
1850 break;
1851 case PACKET3_CONTEXT_CONTROL:
1852 if (pkt->count != 1) {
1853 DRM_ERROR("bad CONTEXT_CONTROL\n");
1854 return -EINVAL;
1855 }
1856 break;
1857 case PACKET3_INDEX_TYPE:
1858 case PACKET3_NUM_INSTANCES:
1859 if (pkt->count) {
1860 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1861 return -EINVAL;
1862 }
1863 break;
1864 case PACKET3_DRAW_INDEX:
6333003b
MO		 1865 {
1866 uint64_t offset;
3ce0a23d
JG		 1867 if (pkt->count != 3) {
1868 DRM_ERROR("bad DRAW_INDEX\n");
1869 return -EINVAL;
1870 }
1871 r = r600_cs_packet_next_reloc(p, &reloc);
1872 if (r) {
1873 DRM_ERROR("bad DRAW_INDEX\n");
1874 return -EINVAL;
1875 }
6333003b
MO		 1876
1877 offset = reloc->lobj.gpu_offset +
1878 idx_value +
1879 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1880
1881 ib[idx+0] = offset;
1882 ib[idx+1] = upper_32_bits(offset) & 0xff;
1883
961fb597
JG		 1884 r = r600_cs_track_check(p);
1885 if (r) {
1886 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1887 return r;
1888 }
3ce0a23d 1889 break;
6333003b 1890 }
3ce0a23d
JG		 1891 case PACKET3_DRAW_INDEX_AUTO:
1892 if (pkt->count != 1) {
1893 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1894 return -EINVAL;
1895 }
961fb597
JG		 1896 r = r600_cs_track_check(p);
1897 if (r) {
1898 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1899 return r;
1900 }
3ce0a23d
JG		 1901 break;
1902 case PACKET3_DRAW_INDEX_IMMD_BE:
1903 case PACKET3_DRAW_INDEX_IMMD:
1904 if (pkt->count < 2) {
1905 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1906 return -EINVAL;
1907 }
961fb597
JG		 1908 r = r600_cs_track_check(p);
1909 if (r) {
1910 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1911 return r;
1912 }
3ce0a23d
JG		 1913 break;
1914 case PACKET3_WAIT_REG_MEM:
1915 if (pkt->count != 5) {
1916 DRM_ERROR("bad WAIT_REG_MEM\n");
1917 return -EINVAL;
1918 }
1919 /* bit 4 is reg (0) or mem (1) */
adea4796 1920 if (idx_value & 0x10) {
6333003b
MO		 1921 uint64_t offset;
1922
3ce0a23d
JG		 1923 r = r600_cs_packet_next_reloc(p, &reloc);
1924 if (r) {
1925 DRM_ERROR("bad WAIT_REG_MEM\n");
1926 return -EINVAL;
1927 }
6333003b
MO		 1928
1929 offset = reloc->lobj.gpu_offset +
1930 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +
1931 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1932
1933 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);
1934 ib[idx+2] = upper_32_bits(offset) & 0xff;
3ce0a23d
JG		 1935 }
1936 break;
1937 case PACKET3_SURFACE_SYNC:
1938 if (pkt->count != 3) {
1939 DRM_ERROR("bad SURFACE_SYNC\n");
1940 return -EINVAL;
1941 }
1942 /* 0xffffffff/0x0 is flush all cache flag */
513bcb46
DA		 1943 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1944 radeon_get_ib_value(p, idx + 2) != 0) {
3ce0a23d
JG		 1945 r = r600_cs_packet_next_reloc(p, &reloc);
1946 if (r) {
1947 DRM_ERROR("bad SURFACE_SYNC\n");
1948 return -EINVAL;
1949 }
1950 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1951 }
1952 break;
1953 case PACKET3_EVENT_WRITE:
1954 if (pkt->count != 2 && pkt->count != 0) {
1955 DRM_ERROR("bad EVENT_WRITE\n");
1956 return -EINVAL;
1957 }
1958 if (pkt->count) {
6333003b
MO		 1959 uint64_t offset;
1960
3ce0a23d
JG		 1961 r = r600_cs_packet_next_reloc(p, &reloc);
1962 if (r) {
1963 DRM_ERROR("bad EVENT_WRITE\n");
1964 return -EINVAL;
1965 }
6333003b
MO		 1966 offset = reloc->lobj.gpu_offset +
1967 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
1968 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1969
1970 ib[idx+1] = offset & 0xfffffff8;
1971 ib[idx+2] = upper_32_bits(offset) & 0xff;
3ce0a23d
JG		 1972 }
1973 break;
1974 case PACKET3_EVENT_WRITE_EOP:
6333003b
MO		 1975 {
1976 uint64_t offset;
1977
3ce0a23d
JG		 1978 if (pkt->count != 4) {
1979 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1980 return -EINVAL;
1981 }
1982 r = r600_cs_packet_next_reloc(p, &reloc);
1983 if (r) {
1984 DRM_ERROR("bad EVENT_WRITE\n");
1985 return -EINVAL;
1986 }
6333003b
MO		 1987
1988 offset = reloc->lobj.gpu_offset +
1989 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
1990 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1991
1992 ib[idx+1] = offset & 0xfffffffc;
1993 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
3ce0a23d 1994 break;
6333003b 1995 }
3ce0a23d 1996 case PACKET3_SET_CONFIG_REG:
adea4796 1997 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
3ce0a23d
JG		 1998 end_reg = 4 * pkt->count + start_reg - 4;
1999 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
2000 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2001 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2002 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2003 return -EINVAL;
2004 }
2005 for (i = 0; i < pkt->count; i++) {
2006 reg = start_reg + (4 * i);
961fb597
JG		 2007 r = r600_cs_check_reg(p, reg, idx+1+i);
2008 if (r)
2009 return r;
3ce0a23d
JG		 2010 }
2011 break;
2012 case PACKET3_SET_CONTEXT_REG:
adea4796 2013 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
3ce0a23d
JG		 2014 end_reg = 4 * pkt->count + start_reg - 4;
2015 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
2016 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
2017 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
2018 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
2019 return -EINVAL;
2020 }
2021 for (i = 0; i < pkt->count; i++) {
2022 reg = start_reg + (4 * i);
961fb597
JG		 2023 r = r600_cs_check_reg(p, reg, idx+1+i);
2024 if (r)
2025 return r;
3ce0a23d
JG		 2026 }
2027 break;
2028 case PACKET3_SET_RESOURCE:
2029 if (pkt->count % 7) {
2030 DRM_ERROR("bad SET_RESOURCE\n");
2031 return -EINVAL;
2032 }
adea4796 2033 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
3ce0a23d
JG		 2034 end_reg = 4 * pkt->count + start_reg - 4;
2035 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
2036 (start_reg >= PACKET3_SET_RESOURCE_END) ||
2037 (end_reg >= PACKET3_SET_RESOURCE_END)) {
2038 DRM_ERROR("bad SET_RESOURCE\n");
2039 return -EINVAL;
2040 }
2041 for (i = 0; i < (pkt->count / 7); i++) {
961fb597 2042 struct radeon_bo *texture, *mipmap;
1729dd33 2043 u32 size, offset, base_offset, mip_offset;
961fb597 2044
adea4796 2045 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
3ce0a23d
JG		 2046 case SQ_TEX_VTX_VALID_TEXTURE:
2047 /* tex base */
2048 r = r600_cs_packet_next_reloc(p, &reloc);
2049 if (r) {
2050 DRM_ERROR("bad SET_RESOURCE\n");
2051 return -EINVAL;
2052 }
1729dd33 2053 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
721604a1 2054 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
e70f224c
MO		 2055 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
2056 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
2057 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
2058 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
2059 }
961fb597 2060 texture = reloc->robj;
3ce0a23d
JG		 2061 /* tex mip base */
2062 r = r600_cs_packet_next_reloc(p, &reloc);
2063 if (r) {
2064 DRM_ERROR("bad SET_RESOURCE\n");
2065 return -EINVAL;
2066 }
1729dd33 2067 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
961fb597
JG		 2068 mipmap = reloc->robj;
2069 r = r600_check_texture_resource(p, idx+(i*7)+1,
16790569
AD		 2070 texture, mipmap,
2071 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
2072 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
2073 reloc->lobj.tiling_flags);
961fb597
JG		 2074 if (r)
2075 return r;
1729dd33
AD		 2076 ib[idx+1+(i*7)+2] += base_offset;
2077 ib[idx+1+(i*7)+3] += mip_offset;
3ce0a23d
JG		 2078 break;
2079 case SQ_TEX_VTX_VALID_BUFFER:
6333003b
MO		 2080 {
2081 uint64_t offset64;
3ce0a23d
JG		 2082 /* vtx base */
2083 r = r600_cs_packet_next_reloc(p, &reloc);
2084 if (r) {
2085 DRM_ERROR("bad SET_RESOURCE\n");
2086 return -EINVAL;
2087 }
961fb597 2088 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1729dd33 2089 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
961fb597
JG		 2090 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2091 /* force size to size of the buffer */
1729dd33
AD		 2092 dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
2093 size + offset, radeon_bo_size(reloc->robj));
6333003b 2094 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;
961fb597 2095 }
6333003b
MO		 2096
2097 offset64 = reloc->lobj.gpu_offset + offset;
2098 ib[idx+1+(i*8)+0] = offset64;
2099 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2100 (upper_32_bits(offset64) & 0xff);
3ce0a23d 2101 break;
6333003b 2102 }
3ce0a23d
JG		 2103 case SQ_TEX_VTX_INVALID_TEXTURE:
2104 case SQ_TEX_VTX_INVALID_BUFFER:
2105 default:
2106 DRM_ERROR("bad SET_RESOURCE\n");
2107 return -EINVAL;
2108 }
2109 }
2110 break;
2111 case PACKET3_SET_ALU_CONST:
5f77df36
AD		 2112 if (track->sq_config & DX9_CONSTS) {
2113 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
2114 end_reg = 4 * pkt->count + start_reg - 4;
2115 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
2116 (start_reg >= PACKET3_SET_ALU_CONST_END) ||
2117 (end_reg >= PACKET3_SET_ALU_CONST_END)) {
2118 DRM_ERROR("bad SET_ALU_CONST\n");
2119 return -EINVAL;
2120 }
3ce0a23d
JG		 2121 }
2122 break;
2123 case PACKET3_SET_BOOL_CONST:
adea4796 2124 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
3ce0a23d
JG		 2125 end_reg = 4 * pkt->count + start_reg - 4;
2126 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
2127 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
2128 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
2129 DRM_ERROR("bad SET_BOOL_CONST\n");
2130 return -EINVAL;
2131 }
2132 break;
2133 case PACKET3_SET_LOOP_CONST:
adea4796 2134 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
3ce0a23d
JG		 2135 end_reg = 4 * pkt->count + start_reg - 4;
2136 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
2137 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
2138 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
2139 DRM_ERROR("bad SET_LOOP_CONST\n");
2140 return -EINVAL;
2141 }
2142 break;
2143 case PACKET3_SET_CTL_CONST:
adea4796 2144 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
3ce0a23d
JG		 2145 end_reg = 4 * pkt->count + start_reg - 4;
2146 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
2147 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
2148 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
2149 DRM_ERROR("bad SET_CTL_CONST\n");
2150 return -EINVAL;
2151 }
2152 break;
2153 case PACKET3_SET_SAMPLER:
2154 if (pkt->count % 3) {
2155 DRM_ERROR("bad SET_SAMPLER\n");
2156 return -EINVAL;
2157 }
adea4796 2158 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
3ce0a23d
JG		 2159 end_reg = 4 * pkt->count + start_reg - 4;
2160 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
2161 (start_reg >= PACKET3_SET_SAMPLER_END) ||
2162 (end_reg >= PACKET3_SET_SAMPLER_END)) {
2163 DRM_ERROR("bad SET_SAMPLER\n");
2164 return -EINVAL;
2165 }
2166 break;
7c77bf2a
AD		 2167 case PACKET3_STRMOUT_BASE_UPDATE:
2168 if (p->family < CHIP_RV770) {
2169 DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n");
2170 return -EINVAL;
2171 }
2172 if (pkt->count != 1) {
2173 DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n");
2174 return -EINVAL;
2175 }
2176 if (idx_value > 3) {
2177 DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n");
2178 return -EINVAL;
2179 }
2180 {
2181 u64 offset;
2182
2183 r = r600_cs_packet_next_reloc(p, &reloc);
2184 if (r) {
2185 DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");
2186 return -EINVAL;
2187 }
2188
2189 if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
2190 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n");
2191 return -EINVAL;
2192 }
2193
2194 offset = radeon_get_ib_value(p, idx+1) << 8;
2195 if (offset != track->vgt_strmout_bo_offset[idx_value]) {
2196 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n",
2197 offset, track->vgt_strmout_bo_offset[idx_value]);
2198 return -EINVAL;
2199 }
2200
2201 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2202 DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n",
2203 offset + 4, radeon_bo_size(reloc->robj));
2204 return -EINVAL;
2205 }
2206 ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2207 }
2208 break;
3ce0a23d
JG		 2209 case PACKET3_SURFACE_BASE_UPDATE:
2210 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
2211 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2212 return -EINVAL;
2213 }
2214 if (pkt->count) {
2215 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2216 return -EINVAL;
2217 }
2218 break;
dd220a00
MO		 2219 case PACKET3_STRMOUT_BUFFER_UPDATE:
2220 if (pkt->count != 4) {
2221 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2222 return -EINVAL;
2223 }
2224 /* Updating memory at DST_ADDRESS. */
2225 if (idx_value & 0x1) {
2226 u64 offset;
2227 r = r600_cs_packet_next_reloc(p, &reloc);
2228 if (r) {
2229 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2230 return -EINVAL;
2231 }
2232 offset = radeon_get_ib_value(p, idx+1);
2233 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2234 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2235 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
2236 offset + 4, radeon_bo_size(reloc->robj));
2237 return -EINVAL;
2238 }
6333003b
MO		 2239 offset += reloc->lobj.gpu_offset;
2240 ib[idx+1] = offset;
2241 ib[idx+2] = upper_32_bits(offset) & 0xff;
dd220a00
MO		 2242 }
2243 /* Reading data from SRC_ADDRESS. */
2244 if (((idx_value >> 1) & 0x3) == 2) {
2245 u64 offset;
2246 r = r600_cs_packet_next_reloc(p, &reloc);
2247 if (r) {
2248 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2249 return -EINVAL;
2250 }
2251 offset = radeon_get_ib_value(p, idx+3);
2252 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2253 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2254 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
2255 offset + 4, radeon_bo_size(reloc->robj));
2256 return -EINVAL;
2257 }
6333003b
MO		 2258 offset += reloc->lobj.gpu_offset;
2259 ib[idx+3] = offset;
2260 ib[idx+4] = upper_32_bits(offset) & 0xff;
dd220a00
MO		 2261 }
2262 break;
2263 case PACKET3_COPY_DW:
2264 if (pkt->count != 4) {
2265 DRM_ERROR("bad COPY_DW (invalid count)\n");
2266 return -EINVAL;
2267 }
2268 if (idx_value & 0x1) {
2269 u64 offset;
2270 /* SRC is memory. */
2271 r = r600_cs_packet_next_reloc(p, &reloc);
2272 if (r) {
2273 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2274 return -EINVAL;
2275 }
2276 offset = radeon_get_ib_value(p, idx+1);
2277 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2278 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2279 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
2280 offset + 4, radeon_bo_size(reloc->robj));
2281 return -EINVAL;
2282 }
6333003b
MO		 2283 offset += reloc->lobj.gpu_offset;
2284 ib[idx+1] = offset;
2285 ib[idx+2] = upper_32_bits(offset) & 0xff;
dd220a00
MO		 2286 } else {
2287 /* SRC is a reg. */
2288 reg = radeon_get_ib_value(p, idx+1) << 2;
2289 if (!r600_is_safe_reg(p, reg, idx+1))
2290 return -EINVAL;
2291 }
2292 if (idx_value & 0x2) {
2293 u64 offset;
2294 /* DST is memory. */
2295 r = r600_cs_packet_next_reloc(p, &reloc);
2296 if (r) {
2297 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2298 return -EINVAL;
2299 }
2300 offset = radeon_get_ib_value(p, idx+3);
2301 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2302 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2303 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2304 offset + 4, radeon_bo_size(reloc->robj));
2305 return -EINVAL;
2306 }
6333003b
MO		 2307 offset += reloc->lobj.gpu_offset;
2308 ib[idx+3] = offset;
2309 ib[idx+4] = upper_32_bits(offset) & 0xff;
dd220a00
MO		 2310 } else {
2311 /* DST is a reg. */
2312 reg = radeon_get_ib_value(p, idx+3) << 2;
2313 if (!r600_is_safe_reg(p, reg, idx+3))
2314 return -EINVAL;
2315 }
2316 break;
3ce0a23d
JG		 2317 case PACKET3_NOP:
2318 break;
2319 default:
2320 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2321 return -EINVAL;
2322 }
2323 return 0;
2324}
2325
2326int r600_cs_parse(struct radeon_cs_parser *p)
2327{
2328 struct radeon_cs_packet pkt;
c8c15ff1 2329 struct r600_cs_track *track;
3ce0a23d
JG		 2330 int r;
2331
961fb597
JG		 2332 if (p->track == NULL) {
2333 /* initialize tracker, we are in kms */
2334 track = kzalloc(sizeof(*track), GFP_KERNEL);
2335 if (track == NULL)
2336 return -ENOMEM;
2337 r600_cs_track_init(track);
2338 if (p->rdev->family < CHIP_RV770) {
2339 track->npipes = p->rdev->config.r600.tiling_npipes;
2340 track->nbanks = p->rdev->config.r600.tiling_nbanks;
2341 track->group_size = p->rdev->config.r600.tiling_group_size;
2342 } else if (p->rdev->family <= CHIP_RV740) {
2343 track->npipes = p->rdev->config.rv770.tiling_npipes;
2344 track->nbanks = p->rdev->config.rv770.tiling_nbanks;
2345 track->group_size = p->rdev->config.rv770.tiling_group_size;
2346 }
2347 p->track = track;
2348 }
3ce0a23d
JG		 2349 do {
2350 r = r600_cs_packet_parse(p, &pkt, p->idx);
2351 if (r) {
7cb72ef4
JG		 2352 kfree(p->track);
2353 p->track = NULL;
3ce0a23d
JG		 2354 return r;
2355 }
2356 p->idx += pkt.count + 2;
2357 switch (pkt.type) {
2358 case PACKET_TYPE0:
2359 r = r600_cs_parse_packet0(p, &pkt);
2360 break;
2361 case PACKET_TYPE2:
2362 break;
2363 case PACKET_TYPE3:
2364 r = r600_packet3_check(p, &pkt);
2365 break;
2366 default:
2367 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
961fb597 2368 kfree(p->track);
7cb72ef4 2369 p->track = NULL;
3ce0a23d
JG		 2370 return -EINVAL;
2371 }
2372 if (r) {
961fb597 2373 kfree(p->track);
7cb72ef4 2374 p->track = NULL;
3ce0a23d
JG		 2375 return r;
2376 }
2377 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2378#if 0
f2e39221
JG		 2379 for (r = 0; r < p->ib.length_dw; r++) {
2380 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]);
3ce0a23d
JG		 2381 mdelay(1);
2382 }
2383#endif
961fb597 2384 kfree(p->track);
7cb72ef4 2385 p->track = NULL;
3ce0a23d
JG		 2386 return 0;
2387}
2388
2389static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
2390{
2391 if (p->chunk_relocs_idx == -1) {
2392 return 0;
2393 }
e265f39e 2394 p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
3ce0a23d
JG		 2395 if (p->relocs == NULL) {
2396 return -ENOMEM;
2397 }
2398 return 0;
2399}
2400
2401/**
2402 * cs_parser_fini() - clean parser states
2403 * @parser: parser structure holding parsing context.
2404 * @error: error number
2405 *
2406 * If error is set than unvalidate buffer, otherwise just free memory
2407 * used by parsing context.
2408 **/
2409static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
2410{
2411 unsigned i;
2412
2413 kfree(parser->relocs);
2414 for (i = 0; i < parser->nchunks; i++) {
2415 kfree(parser->chunks[i].kdata);
4c57edba
DA		 2416 kfree(parser->chunks[i].kpage[0]);
2417 kfree(parser->chunks[i].kpage[1]);
3ce0a23d
JG		 2418 }
2419 kfree(parser->chunks);
2420 kfree(parser->chunks_array);
2421}
2422
2423int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
2424 unsigned family, u32 *ib, int *l)
2425{
2426 struct radeon_cs_parser parser;
2427 struct radeon_cs_chunk *ib_chunk;
961fb597 2428 struct r600_cs_track *track;
3ce0a23d
JG		 2429 int r;
2430
961fb597
JG		 2431 /* initialize tracker */
2432 track = kzalloc(sizeof(*track), GFP_KERNEL);
2433 if (track == NULL)
2434 return -ENOMEM;
2435 r600_cs_track_init(track);
2436 r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
3ce0a23d
JG		 2437 /* initialize parser */
2438 memset(&parser, 0, sizeof(struct radeon_cs_parser));
2439 parser.filp = filp;
c8c15ff1 2440 parser.dev = &dev->pdev->dev;
3ce0a23d
JG		 2441 parser.rdev = NULL;
2442 parser.family = family;
961fb597 2443 parser.track = track;
f2e39221 2444 parser.ib.ptr = ib;
3ce0a23d
JG		 2445 r = radeon_cs_parser_init(&parser, data);
2446 if (r) {
2447 DRM_ERROR("Failed to initialize parser !\n");
2448 r600_cs_parser_fini(&parser, r);
2449 return r;
2450 }
2451 r = r600_cs_parser_relocs_legacy(&parser);
2452 if (r) {
2453 DRM_ERROR("Failed to parse relocation !\n");
2454 r600_cs_parser_fini(&parser, r);
2455 return r;
2456 }
2457 /* Copy the packet into the IB, the parser will read from the
2458 * input memory (cached) and write to the IB (which can be
2459 * uncached). */
2460 ib_chunk = &parser.chunks[parser.chunk_ib_idx];
f2e39221
JG		 2461 parser.ib.length_dw = ib_chunk->length_dw;
2462 *l = parser.ib.length_dw;
3ce0a23d
JG		 2463 r = r600_cs_parse(&parser);
2464 if (r) {
2465 DRM_ERROR("Invalid command stream !\n");
2466 r600_cs_parser_fini(&parser, r);
2467 return r;
2468 }
513bcb46
DA		 2469 r = radeon_cs_finish_pages(&parser);
2470 if (r) {
2471 DRM_ERROR("Invalid command stream !\n");
2472 r600_cs_parser_fini(&parser, r);
2473 return r;
2474 }
3ce0a23d
JG		 2475 r600_cs_parser_fini(&parser, r);
2476 return r;
2477}
2478
2479void r600_cs_legacy_init(void)
2480{
2481 r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
2482}
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