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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __RADEON_H__ | |
29 | #define __RADEON_H__ | |
30 | ||
771fe6b9 JG |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should | |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings | |
34 | * related to surface | |
35 | * - WB : write back stuff (do it bit like scratch reg things) | |
36 | * - Vblank : look at Jesse's rework and what we should do | |
37 | * - r600/r700: gart & cp | |
38 | * - cs : clean cs ioctl use bitmap & things like that. | |
39 | * - power management stuff | |
40 | * - Barrier in gart code | |
41 | * - Unmappabled vram ? | |
42 | * - TESTING, TESTING, TESTING | |
43 | */ | |
44 | ||
d39c3b89 JG |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various | |
47 | * reasons even thought we work hard to make it works on most | |
48 | * configurations. In order to still have a working userspace in such | |
49 | * situation the init path must succeed up to the memory controller | |
50 | * initialization point. Failure before this point are considered as | |
51 | * fatal error. Here is the init callchain : | |
52 | * radeon_device_init perform common structure, mutex initialization | |
53 | * asic_init setup the GPU memory layout and perform all | |
54 | * one time initialization (failure in this | |
55 | * function are considered fatal) | |
56 | * asic_startup setup the GPU acceleration, in order to | |
57 | * follow guideline the first thing this | |
58 | * function should do is setting the GPU | |
59 | * memory controller (only MC setup failure | |
60 | * are considered as fatal) | |
61 | */ | |
62 | ||
771fe6b9 JG |
63 | #include <asm/atomic.h> |
64 | #include <linux/wait.h> | |
65 | #include <linux/list.h> | |
66 | #include <linux/kref.h> | |
67 | ||
4c788679 JG |
68 | #include <ttm/ttm_bo_api.h> |
69 | #include <ttm/ttm_bo_driver.h> | |
70 | #include <ttm/ttm_placement.h> | |
71 | #include <ttm/ttm_module.h> | |
72 | ||
c2142715 | 73 | #include "radeon_family.h" |
771fe6b9 JG |
74 | #include "radeon_mode.h" |
75 | #include "radeon_reg.h" | |
771fe6b9 JG |
76 | |
77 | /* | |
78 | * Modules parameters. | |
79 | */ | |
80 | extern int radeon_no_wb; | |
81 | extern int radeon_modeset; | |
82 | extern int radeon_dynclks; | |
83 | extern int radeon_r4xx_atom; | |
84 | extern int radeon_agpmode; | |
85 | extern int radeon_vram_limit; | |
86 | extern int radeon_gart_size; | |
87 | extern int radeon_benchmarking; | |
ecc0b326 | 88 | extern int radeon_testing; |
771fe6b9 | 89 | extern int radeon_connector_table; |
4ce001ab | 90 | extern int radeon_tv; |
b27b6375 | 91 | extern int radeon_new_pll; |
c913e23a | 92 | extern int radeon_dynpm; |
dafc3bd5 | 93 | extern int radeon_audio; |
771fe6b9 JG |
94 | |
95 | /* | |
96 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | |
97 | * symbol; | |
98 | */ | |
99 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ | |
100 | #define RADEON_IB_POOL_SIZE 16 | |
101 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 | |
102 | #define RADEONFB_CONN_LIMIT 4 | |
f657c2a7 | 103 | #define RADEON_BIOS_NUM_SCRATCH 8 |
771fe6b9 | 104 | |
771fe6b9 JG |
105 | /* |
106 | * Errata workarounds. | |
107 | */ | |
108 | enum radeon_pll_errata { | |
109 | CHIP_ERRATA_R300_CG = 0x00000001, | |
110 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, | |
111 | CHIP_ERRATA_PLL_DELAY = 0x00000004 | |
112 | }; | |
113 | ||
114 | ||
115 | struct radeon_device; | |
116 | ||
117 | ||
118 | /* | |
119 | * BIOS. | |
120 | */ | |
121 | bool radeon_get_bios(struct radeon_device *rdev); | |
122 | ||
3ce0a23d | 123 | |
771fe6b9 | 124 | /* |
3ce0a23d | 125 | * Dummy page |
771fe6b9 | 126 | */ |
3ce0a23d JG |
127 | struct radeon_dummy_page { |
128 | struct page *page; | |
129 | dma_addr_t addr; | |
130 | }; | |
131 | int radeon_dummy_page_init(struct radeon_device *rdev); | |
132 | void radeon_dummy_page_fini(struct radeon_device *rdev); | |
133 | ||
771fe6b9 | 134 | |
3ce0a23d JG |
135 | /* |
136 | * Clocks | |
137 | */ | |
771fe6b9 JG |
138 | struct radeon_clock { |
139 | struct radeon_pll p1pll; | |
140 | struct radeon_pll p2pll; | |
141 | struct radeon_pll spll; | |
142 | struct radeon_pll mpll; | |
143 | /* 10 Khz units */ | |
144 | uint32_t default_mclk; | |
145 | uint32_t default_sclk; | |
146 | }; | |
147 | ||
7433874e RM |
148 | /* |
149 | * Power management | |
150 | */ | |
151 | int radeon_pm_init(struct radeon_device *rdev); | |
c913e23a | 152 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
56278a8e AD |
153 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
154 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); | |
3ce0a23d | 155 | |
771fe6b9 JG |
156 | /* |
157 | * Fences. | |
158 | */ | |
159 | struct radeon_fence_driver { | |
160 | uint32_t scratch_reg; | |
161 | atomic_t seq; | |
162 | uint32_t last_seq; | |
163 | unsigned long count_timeout; | |
164 | wait_queue_head_t queue; | |
165 | rwlock_t lock; | |
166 | struct list_head created; | |
167 | struct list_head emited; | |
168 | struct list_head signaled; | |
0a0c7596 | 169 | bool initialized; |
771fe6b9 JG |
170 | }; |
171 | ||
172 | struct radeon_fence { | |
173 | struct radeon_device *rdev; | |
174 | struct kref kref; | |
175 | struct list_head list; | |
176 | /* protected by radeon_fence.lock */ | |
177 | uint32_t seq; | |
178 | unsigned long timeout; | |
179 | bool emited; | |
180 | bool signaled; | |
181 | }; | |
182 | ||
183 | int radeon_fence_driver_init(struct radeon_device *rdev); | |
184 | void radeon_fence_driver_fini(struct radeon_device *rdev); | |
185 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); | |
186 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); | |
187 | void radeon_fence_process(struct radeon_device *rdev); | |
188 | bool radeon_fence_signaled(struct radeon_fence *fence); | |
189 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); | |
190 | int radeon_fence_wait_next(struct radeon_device *rdev); | |
191 | int radeon_fence_wait_last(struct radeon_device *rdev); | |
192 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); | |
193 | void radeon_fence_unref(struct radeon_fence **fence); | |
194 | ||
e024e110 DA |
195 | /* |
196 | * Tiling registers | |
197 | */ | |
198 | struct radeon_surface_reg { | |
4c788679 | 199 | struct radeon_bo *bo; |
e024e110 DA |
200 | }; |
201 | ||
202 | #define RADEON_GEM_MAX_SURFACES 8 | |
771fe6b9 JG |
203 | |
204 | /* | |
4c788679 | 205 | * TTM. |
771fe6b9 | 206 | */ |
4c788679 JG |
207 | struct radeon_mman { |
208 | struct ttm_bo_global_ref bo_global_ref; | |
209 | struct ttm_global_reference mem_global_ref; | |
4c788679 | 210 | struct ttm_bo_device bdev; |
0a0c7596 JG |
211 | bool mem_global_referenced; |
212 | bool initialized; | |
4c788679 JG |
213 | }; |
214 | ||
215 | struct radeon_bo { | |
216 | /* Protected by gem.mutex */ | |
217 | struct list_head list; | |
218 | /* Protected by tbo.reserved */ | |
312ea8da JG |
219 | u32 placements[3]; |
220 | struct ttm_placement placement; | |
4c788679 JG |
221 | struct ttm_buffer_object tbo; |
222 | struct ttm_bo_kmap_obj kmap; | |
223 | unsigned pin_count; | |
224 | void *kptr; | |
225 | u32 tiling_flags; | |
226 | u32 pitch; | |
227 | int surface_reg; | |
228 | /* Constant after initialization */ | |
229 | struct radeon_device *rdev; | |
230 | struct drm_gem_object *gobj; | |
231 | }; | |
771fe6b9 | 232 | |
4c788679 | 233 | struct radeon_bo_list { |
771fe6b9 | 234 | struct list_head list; |
4c788679 | 235 | struct radeon_bo *bo; |
771fe6b9 JG |
236 | uint64_t gpu_offset; |
237 | unsigned rdomain; | |
238 | unsigned wdomain; | |
4c788679 | 239 | u32 tiling_flags; |
771fe6b9 JG |
240 | }; |
241 | ||
771fe6b9 JG |
242 | /* |
243 | * GEM objects. | |
244 | */ | |
245 | struct radeon_gem { | |
4c788679 | 246 | struct mutex mutex; |
771fe6b9 JG |
247 | struct list_head objects; |
248 | }; | |
249 | ||
250 | int radeon_gem_init(struct radeon_device *rdev); | |
251 | void radeon_gem_fini(struct radeon_device *rdev); | |
252 | int radeon_gem_object_create(struct radeon_device *rdev, int size, | |
4c788679 JG |
253 | int alignment, int initial_domain, |
254 | bool discardable, bool kernel, | |
255 | struct drm_gem_object **obj); | |
771fe6b9 JG |
256 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
257 | uint64_t *gpu_addr); | |
258 | void radeon_gem_object_unpin(struct drm_gem_object *obj); | |
259 | ||
260 | ||
261 | /* | |
262 | * GART structures, functions & helpers | |
263 | */ | |
264 | struct radeon_mc; | |
265 | ||
266 | struct radeon_gart_table_ram { | |
267 | volatile uint32_t *ptr; | |
268 | }; | |
269 | ||
270 | struct radeon_gart_table_vram { | |
4c788679 | 271 | struct radeon_bo *robj; |
771fe6b9 JG |
272 | volatile uint32_t *ptr; |
273 | }; | |
274 | ||
275 | union radeon_gart_table { | |
276 | struct radeon_gart_table_ram ram; | |
277 | struct radeon_gart_table_vram vram; | |
278 | }; | |
279 | ||
a77f1718 MT |
280 | #define RADEON_GPU_PAGE_SIZE 4096 |
281 | ||
771fe6b9 JG |
282 | struct radeon_gart { |
283 | dma_addr_t table_addr; | |
284 | unsigned num_gpu_pages; | |
285 | unsigned num_cpu_pages; | |
286 | unsigned table_size; | |
287 | union radeon_gart_table table; | |
288 | struct page **pages; | |
289 | dma_addr_t *pages_addr; | |
290 | bool ready; | |
291 | }; | |
292 | ||
293 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); | |
294 | void radeon_gart_table_ram_free(struct radeon_device *rdev); | |
295 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); | |
296 | void radeon_gart_table_vram_free(struct radeon_device *rdev); | |
297 | int radeon_gart_init(struct radeon_device *rdev); | |
298 | void radeon_gart_fini(struct radeon_device *rdev); | |
299 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |
300 | int pages); | |
301 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |
302 | int pages, struct page **pagelist); | |
303 | ||
304 | ||
305 | /* | |
306 | * GPU MC structures, functions & helpers | |
307 | */ | |
308 | struct radeon_mc { | |
309 | resource_size_t aper_size; | |
310 | resource_size_t aper_base; | |
311 | resource_size_t agp_base; | |
7a50f01a DA |
312 | /* for some chips with <= 32MB we need to lie |
313 | * about vram size near mc fb location */ | |
3ce0a23d JG |
314 | u64 mc_vram_size; |
315 | u64 gtt_location; | |
316 | u64 gtt_size; | |
317 | u64 gtt_start; | |
318 | u64 gtt_end; | |
319 | u64 vram_location; | |
320 | u64 vram_start; | |
321 | u64 vram_end; | |
771fe6b9 | 322 | unsigned vram_width; |
3ce0a23d | 323 | u64 real_vram_size; |
771fe6b9 JG |
324 | int vram_mtrr; |
325 | bool vram_is_ddr; | |
06b6476d | 326 | bool igp_sideport_enabled; |
771fe6b9 JG |
327 | }; |
328 | ||
329 | int radeon_mc_setup(struct radeon_device *rdev); | |
06b6476d AD |
330 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
331 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); | |
771fe6b9 JG |
332 | |
333 | /* | |
334 | * GPU scratch registers structures, functions & helpers | |
335 | */ | |
336 | struct radeon_scratch { | |
337 | unsigned num_reg; | |
338 | bool free[32]; | |
339 | uint32_t reg[32]; | |
340 | }; | |
341 | ||
342 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); | |
343 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); | |
344 | ||
345 | ||
346 | /* | |
347 | * IRQS. | |
348 | */ | |
349 | struct radeon_irq { | |
350 | bool installed; | |
351 | bool sw_int; | |
352 | /* FIXME: use a define max crtc rather than hardcode it */ | |
353 | bool crtc_vblank_int[2]; | |
b500f680 AD |
354 | /* FIXME: use defines for max hpd/dacs */ |
355 | bool hpd[6]; | |
1614f8b1 DA |
356 | spinlock_t sw_lock; |
357 | int sw_refcount; | |
771fe6b9 JG |
358 | }; |
359 | ||
360 | int radeon_irq_kms_init(struct radeon_device *rdev); | |
361 | void radeon_irq_kms_fini(struct radeon_device *rdev); | |
1614f8b1 DA |
362 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); |
363 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); | |
771fe6b9 JG |
364 | |
365 | /* | |
366 | * CP & ring. | |
367 | */ | |
368 | struct radeon_ib { | |
369 | struct list_head list; | |
370 | unsigned long idx; | |
371 | uint64_t gpu_addr; | |
372 | struct radeon_fence *fence; | |
513bcb46 | 373 | uint32_t *ptr; |
771fe6b9 JG |
374 | uint32_t length_dw; |
375 | }; | |
376 | ||
ecb114a1 DA |
377 | /* |
378 | * locking - | |
379 | * mutex protects scheduled_ibs, ready, alloc_bm | |
380 | */ | |
771fe6b9 JG |
381 | struct radeon_ib_pool { |
382 | struct mutex mutex; | |
4c788679 | 383 | struct radeon_bo *robj; |
771fe6b9 JG |
384 | struct list_head scheduled_ibs; |
385 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; | |
386 | bool ready; | |
387 | DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); | |
388 | }; | |
389 | ||
390 | struct radeon_cp { | |
4c788679 | 391 | struct radeon_bo *ring_obj; |
771fe6b9 JG |
392 | volatile uint32_t *ring; |
393 | unsigned rptr; | |
394 | unsigned wptr; | |
395 | unsigned wptr_old; | |
396 | unsigned ring_size; | |
397 | unsigned ring_free_dw; | |
398 | int count_dw; | |
399 | uint64_t gpu_addr; | |
400 | uint32_t align_mask; | |
401 | uint32_t ptr_mask; | |
402 | struct mutex mutex; | |
403 | bool ready; | |
404 | }; | |
405 | ||
d8f60cfc AD |
406 | /* |
407 | * R6xx+ IH ring | |
408 | */ | |
409 | struct r600_ih { | |
4c788679 | 410 | struct radeon_bo *ring_obj; |
d8f60cfc AD |
411 | volatile uint32_t *ring; |
412 | unsigned rptr; | |
413 | unsigned wptr; | |
414 | unsigned wptr_old; | |
415 | unsigned ring_size; | |
416 | uint64_t gpu_addr; | |
d8f60cfc AD |
417 | uint32_t ptr_mask; |
418 | spinlock_t lock; | |
419 | bool enabled; | |
420 | }; | |
421 | ||
3ce0a23d | 422 | struct r600_blit { |
ff82f052 | 423 | struct mutex mutex; |
4c788679 | 424 | struct radeon_bo *shader_obj; |
3ce0a23d JG |
425 | u64 shader_gpu_addr; |
426 | u32 vs_offset, ps_offset; | |
427 | u32 state_offset; | |
428 | u32 state_len; | |
429 | u32 vb_used, vb_total; | |
430 | struct radeon_ib *vb_ib; | |
431 | }; | |
432 | ||
771fe6b9 JG |
433 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
434 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); | |
435 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); | |
436 | int radeon_ib_pool_init(struct radeon_device *rdev); | |
437 | void radeon_ib_pool_fini(struct radeon_device *rdev); | |
438 | int radeon_ib_test(struct radeon_device *rdev); | |
439 | /* Ring access between begin & end cannot sleep */ | |
440 | void radeon_ring_free_size(struct radeon_device *rdev); | |
441 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); | |
442 | void radeon_ring_unlock_commit(struct radeon_device *rdev); | |
443 | void radeon_ring_unlock_undo(struct radeon_device *rdev); | |
444 | int radeon_ring_test(struct radeon_device *rdev); | |
445 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
446 | void radeon_ring_fini(struct radeon_device *rdev); | |
447 | ||
448 | ||
449 | /* | |
450 | * CS. | |
451 | */ | |
452 | struct radeon_cs_reloc { | |
453 | struct drm_gem_object *gobj; | |
4c788679 JG |
454 | struct radeon_bo *robj; |
455 | struct radeon_bo_list lobj; | |
771fe6b9 JG |
456 | uint32_t handle; |
457 | uint32_t flags; | |
458 | }; | |
459 | ||
460 | struct radeon_cs_chunk { | |
461 | uint32_t chunk_id; | |
462 | uint32_t length_dw; | |
513bcb46 DA |
463 | int kpage_idx[2]; |
464 | uint32_t *kpage[2]; | |
771fe6b9 | 465 | uint32_t *kdata; |
513bcb46 DA |
466 | void __user *user_ptr; |
467 | int last_copied_page; | |
468 | int last_page_index; | |
771fe6b9 JG |
469 | }; |
470 | ||
471 | struct radeon_cs_parser { | |
c8c15ff1 | 472 | struct device *dev; |
771fe6b9 JG |
473 | struct radeon_device *rdev; |
474 | struct drm_file *filp; | |
475 | /* chunks */ | |
476 | unsigned nchunks; | |
477 | struct radeon_cs_chunk *chunks; | |
478 | uint64_t *chunks_array; | |
479 | /* IB */ | |
480 | unsigned idx; | |
481 | /* relocations */ | |
482 | unsigned nrelocs; | |
483 | struct radeon_cs_reloc *relocs; | |
484 | struct radeon_cs_reloc **relocs_ptr; | |
485 | struct list_head validated; | |
486 | /* indices of various chunks */ | |
487 | int chunk_ib_idx; | |
488 | int chunk_relocs_idx; | |
489 | struct radeon_ib *ib; | |
490 | void *track; | |
3ce0a23d | 491 | unsigned family; |
513bcb46 | 492 | int parser_error; |
771fe6b9 JG |
493 | }; |
494 | ||
513bcb46 DA |
495 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
496 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); | |
497 | ||
498 | ||
499 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) | |
500 | { | |
501 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
502 | u32 pg_idx, pg_offset; | |
503 | u32 idx_value = 0; | |
504 | int new_page; | |
505 | ||
506 | pg_idx = (idx * 4) / PAGE_SIZE; | |
507 | pg_offset = (idx * 4) % PAGE_SIZE; | |
508 | ||
509 | if (ibc->kpage_idx[0] == pg_idx) | |
510 | return ibc->kpage[0][pg_offset/4]; | |
511 | if (ibc->kpage_idx[1] == pg_idx) | |
512 | return ibc->kpage[1][pg_offset/4]; | |
513 | ||
514 | new_page = radeon_cs_update_pages(p, pg_idx); | |
515 | if (new_page < 0) { | |
516 | p->parser_error = new_page; | |
517 | return 0; | |
518 | } | |
519 | ||
520 | idx_value = ibc->kpage[new_page][pg_offset/4]; | |
521 | return idx_value; | |
522 | } | |
523 | ||
771fe6b9 JG |
524 | struct radeon_cs_packet { |
525 | unsigned idx; | |
526 | unsigned type; | |
527 | unsigned reg; | |
528 | unsigned opcode; | |
529 | int count; | |
530 | unsigned one_reg_wr; | |
531 | }; | |
532 | ||
533 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, | |
534 | struct radeon_cs_packet *pkt, | |
535 | unsigned idx, unsigned reg); | |
536 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, | |
537 | struct radeon_cs_packet *pkt); | |
538 | ||
539 | ||
540 | /* | |
541 | * AGP | |
542 | */ | |
543 | int radeon_agp_init(struct radeon_device *rdev); | |
0ebf1717 | 544 | void radeon_agp_resume(struct radeon_device *rdev); |
771fe6b9 JG |
545 | void radeon_agp_fini(struct radeon_device *rdev); |
546 | ||
547 | ||
548 | /* | |
549 | * Writeback | |
550 | */ | |
551 | struct radeon_wb { | |
4c788679 | 552 | struct radeon_bo *wb_obj; |
771fe6b9 JG |
553 | volatile uint32_t *wb; |
554 | uint64_t gpu_addr; | |
555 | }; | |
556 | ||
c93bb85b JG |
557 | /** |
558 | * struct radeon_pm - power management datas | |
559 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) | |
560 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) | |
561 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) | |
562 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) | |
563 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) | |
564 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) | |
565 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) | |
566 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) | |
567 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) | |
568 | * @sclk: GPU clock Mhz (core bandwith depends of this clock) | |
569 | * @needed_bandwidth: current bandwidth needs | |
570 | * | |
571 | * It keeps track of various data needed to take powermanagement decision. | |
572 | * Bandwith need is used to determine minimun clock of the GPU and memory. | |
573 | * Equation between gpu/memory clock and available bandwidth is hw dependent | |
574 | * (type of memory, bus size, efficiency, ...) | |
575 | */ | |
c913e23a RM |
576 | enum radeon_pm_state { |
577 | PM_STATE_DISABLED, | |
578 | PM_STATE_MINIMUM, | |
579 | PM_STATE_PAUSED, | |
580 | PM_STATE_ACTIVE | |
581 | }; | |
582 | enum radeon_pm_action { | |
583 | PM_ACTION_NONE, | |
584 | PM_ACTION_MINIMUM, | |
585 | PM_ACTION_DOWNCLOCK, | |
586 | PM_ACTION_UPCLOCK | |
587 | }; | |
56278a8e AD |
588 | |
589 | enum radeon_voltage_type { | |
590 | VOLTAGE_NONE = 0, | |
591 | VOLTAGE_GPIO, | |
592 | VOLTAGE_VDDC, | |
593 | VOLTAGE_SW | |
594 | }; | |
595 | ||
0ec0e74f AD |
596 | enum radeon_pm_state_type { |
597 | POWER_STATE_TYPE_DEFAULT, | |
598 | POWER_STATE_TYPE_POWERSAVE, | |
599 | POWER_STATE_TYPE_BATTERY, | |
600 | POWER_STATE_TYPE_BALANCED, | |
601 | POWER_STATE_TYPE_PERFORMANCE, | |
602 | }; | |
603 | ||
516d0e46 AD |
604 | enum radeon_pm_clock_mode_type { |
605 | POWER_MODE_TYPE_DEFAULT, | |
606 | POWER_MODE_TYPE_LOW, | |
607 | POWER_MODE_TYPE_MID, | |
608 | POWER_MODE_TYPE_HIGH, | |
609 | }; | |
610 | ||
56278a8e AD |
611 | struct radeon_voltage { |
612 | enum radeon_voltage_type type; | |
613 | /* gpio voltage */ | |
614 | struct radeon_gpio_rec gpio; | |
615 | u32 delay; /* delay in usec from voltage drop to sclk change */ | |
616 | bool active_high; /* voltage drop is active when bit is high */ | |
617 | /* VDDC voltage */ | |
618 | u8 vddc_id; /* index into vddc voltage table */ | |
619 | u8 vddci_id; /* index into vddci voltage table */ | |
620 | bool vddci_enabled; | |
621 | /* r6xx+ sw */ | |
622 | u32 voltage; | |
623 | }; | |
624 | ||
625 | struct radeon_pm_non_clock_info { | |
626 | /* pcie lanes */ | |
627 | int pcie_lanes; | |
628 | /* standardized non-clock flags */ | |
629 | u32 flags; | |
630 | }; | |
631 | ||
632 | struct radeon_pm_clock_info { | |
633 | /* memory clock */ | |
634 | u32 mclk; | |
635 | /* engine clock */ | |
636 | u32 sclk; | |
637 | /* voltage info */ | |
638 | struct radeon_voltage voltage; | |
639 | /* standardized clock flags - not sure we'll need these */ | |
640 | u32 flags; | |
641 | }; | |
642 | ||
643 | struct radeon_power_state { | |
0ec0e74f | 644 | enum radeon_pm_state_type type; |
56278a8e AD |
645 | /* XXX: use a define for num clock modes */ |
646 | struct radeon_pm_clock_info clock_info[8]; | |
647 | /* number of valid clock modes in this power state */ | |
648 | int num_clock_modes; | |
649 | /* currently selected clock mode */ | |
650 | struct radeon_pm_clock_info *current_clock_mode; | |
516d0e46 | 651 | struct radeon_pm_clock_info *requested_clock_mode; |
56278a8e AD |
652 | struct radeon_pm_clock_info *default_clock_mode; |
653 | /* non clock info about this state */ | |
654 | struct radeon_pm_non_clock_info non_clock_info; | |
655 | bool voltage_drop_active; | |
656 | }; | |
657 | ||
c93bb85b | 658 | struct radeon_pm { |
c913e23a RM |
659 | struct mutex mutex; |
660 | struct work_struct reclock_work; | |
661 | struct delayed_work idle_work; | |
662 | enum radeon_pm_state state; | |
663 | enum radeon_pm_action planned_action; | |
664 | unsigned long action_timeout; | |
665 | bool downclocked; | |
666 | bool vblank_callback; | |
667 | int active_crtcs; | |
668 | int req_vblank; | |
669 | uint32_t min_gpu_engine_clock; | |
670 | uint32_t min_gpu_memory_clock; | |
671 | uint32_t min_mode_engine_clock; | |
672 | uint32_t min_mode_memory_clock; | |
c93bb85b JG |
673 | fixed20_12 max_bandwidth; |
674 | fixed20_12 igp_sideport_mclk; | |
675 | fixed20_12 igp_system_mclk; | |
676 | fixed20_12 igp_ht_link_clk; | |
677 | fixed20_12 igp_ht_link_width; | |
678 | fixed20_12 k8_bandwidth; | |
679 | fixed20_12 sideport_bandwidth; | |
680 | fixed20_12 ht_bandwidth; | |
681 | fixed20_12 core_bandwidth; | |
682 | fixed20_12 sclk; | |
683 | fixed20_12 needed_bandwidth; | |
56278a8e AD |
684 | /* XXX: use a define for num power modes */ |
685 | struct radeon_power_state power_state[8]; | |
686 | /* number of valid power states */ | |
687 | int num_power_states; | |
688 | struct radeon_power_state *current_power_state; | |
516d0e46 | 689 | struct radeon_power_state *requested_power_state; |
56278a8e | 690 | struct radeon_power_state *default_power_state; |
c93bb85b JG |
691 | }; |
692 | ||
771fe6b9 JG |
693 | |
694 | /* | |
695 | * Benchmarking | |
696 | */ | |
697 | void radeon_benchmark(struct radeon_device *rdev); | |
698 | ||
699 | ||
ecc0b326 MD |
700 | /* |
701 | * Testing | |
702 | */ | |
703 | void radeon_test_moves(struct radeon_device *rdev); | |
704 | ||
705 | ||
771fe6b9 JG |
706 | /* |
707 | * Debugfs | |
708 | */ | |
709 | int radeon_debugfs_add_files(struct radeon_device *rdev, | |
710 | struct drm_info_list *files, | |
711 | unsigned nfiles); | |
712 | int radeon_debugfs_fence_init(struct radeon_device *rdev); | |
713 | int r100_debugfs_rbbm_init(struct radeon_device *rdev); | |
714 | int r100_debugfs_cp_init(struct radeon_device *rdev); | |
715 | ||
716 | ||
717 | /* | |
718 | * ASIC specific functions. | |
719 | */ | |
720 | struct radeon_asic { | |
068a117c | 721 | int (*init)(struct radeon_device *rdev); |
3ce0a23d JG |
722 | void (*fini)(struct radeon_device *rdev); |
723 | int (*resume)(struct radeon_device *rdev); | |
724 | int (*suspend)(struct radeon_device *rdev); | |
28d52043 | 725 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
771fe6b9 | 726 | int (*gpu_reset)(struct radeon_device *rdev); |
771fe6b9 JG |
727 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
728 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); | |
729 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); | |
730 | void (*cp_fini)(struct radeon_device *rdev); | |
731 | void (*cp_disable)(struct radeon_device *rdev); | |
3ce0a23d | 732 | void (*cp_commit)(struct radeon_device *rdev); |
771fe6b9 | 733 | void (*ring_start)(struct radeon_device *rdev); |
3ce0a23d JG |
734 | int (*ring_test)(struct radeon_device *rdev); |
735 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); | |
771fe6b9 JG |
736 | int (*irq_set)(struct radeon_device *rdev); |
737 | int (*irq_process)(struct radeon_device *rdev); | |
7ed220d7 | 738 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
771fe6b9 JG |
739 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
740 | int (*cs_parse)(struct radeon_cs_parser *p); | |
741 | int (*copy_blit)(struct radeon_device *rdev, | |
742 | uint64_t src_offset, | |
743 | uint64_t dst_offset, | |
744 | unsigned num_pages, | |
745 | struct radeon_fence *fence); | |
746 | int (*copy_dma)(struct radeon_device *rdev, | |
747 | uint64_t src_offset, | |
748 | uint64_t dst_offset, | |
749 | unsigned num_pages, | |
750 | struct radeon_fence *fence); | |
751 | int (*copy)(struct radeon_device *rdev, | |
752 | uint64_t src_offset, | |
753 | uint64_t dst_offset, | |
754 | unsigned num_pages, | |
755 | struct radeon_fence *fence); | |
7433874e | 756 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
771fe6b9 | 757 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
7433874e | 758 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
771fe6b9 | 759 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
c836a412 | 760 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
771fe6b9 JG |
761 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
762 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); | |
e024e110 DA |
763 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
764 | uint32_t tiling_flags, uint32_t pitch, | |
765 | uint32_t offset, uint32_t obj_size); | |
766 | int (*clear_surface_reg)(struct radeon_device *rdev, int reg); | |
c93bb85b | 767 | void (*bandwidth_update)(struct radeon_device *rdev); |
429770b3 AD |
768 | void (*hpd_init)(struct radeon_device *rdev); |
769 | void (*hpd_fini)(struct radeon_device *rdev); | |
770 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
771 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
062b389c JG |
772 | /* ioctl hw specific callback. Some hw might want to perform special |
773 | * operation on specific ioctl. For instance on wait idle some hw | |
774 | * might want to perform and HDP flush through MMIO as it seems that | |
775 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed | |
776 | * through ring. | |
777 | */ | |
778 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); | |
771fe6b9 JG |
779 | }; |
780 | ||
21f9a437 JG |
781 | /* |
782 | * Asic structures | |
783 | */ | |
551ebd83 DA |
784 | struct r100_asic { |
785 | const unsigned *reg_safe_bm; | |
786 | unsigned reg_safe_bm_size; | |
cafe6609 | 787 | u32 hdp_cntl; |
551ebd83 DA |
788 | }; |
789 | ||
21f9a437 JG |
790 | struct r300_asic { |
791 | const unsigned *reg_safe_bm; | |
792 | unsigned reg_safe_bm_size; | |
62cdc0c2 | 793 | u32 resync_scratch; |
cafe6609 | 794 | u32 hdp_cntl; |
21f9a437 JG |
795 | }; |
796 | ||
797 | struct r600_asic { | |
798 | unsigned max_pipes; | |
799 | unsigned max_tile_pipes; | |
800 | unsigned max_simds; | |
801 | unsigned max_backends; | |
802 | unsigned max_gprs; | |
803 | unsigned max_threads; | |
804 | unsigned max_stack_entries; | |
805 | unsigned max_hw_contexts; | |
806 | unsigned max_gs_threads; | |
807 | unsigned sx_max_export_size; | |
808 | unsigned sx_max_export_pos_size; | |
809 | unsigned sx_max_export_smx_size; | |
810 | unsigned sq_num_cf_insts; | |
811 | }; | |
812 | ||
813 | struct rv770_asic { | |
814 | unsigned max_pipes; | |
815 | unsigned max_tile_pipes; | |
816 | unsigned max_simds; | |
817 | unsigned max_backends; | |
818 | unsigned max_gprs; | |
819 | unsigned max_threads; | |
820 | unsigned max_stack_entries; | |
821 | unsigned max_hw_contexts; | |
822 | unsigned max_gs_threads; | |
823 | unsigned sx_max_export_size; | |
824 | unsigned sx_max_export_pos_size; | |
825 | unsigned sx_max_export_smx_size; | |
826 | unsigned sq_num_cf_insts; | |
827 | unsigned sx_num_of_sets; | |
828 | unsigned sc_prim_fifo_size; | |
829 | unsigned sc_hiz_tile_fifo_size; | |
830 | unsigned sc_earlyz_tile_fifo_fize; | |
831 | }; | |
832 | ||
068a117c JG |
833 | union radeon_asic_config { |
834 | struct r300_asic r300; | |
551ebd83 | 835 | struct r100_asic r100; |
3ce0a23d JG |
836 | struct r600_asic r600; |
837 | struct rv770_asic rv770; | |
068a117c JG |
838 | }; |
839 | ||
771fe6b9 JG |
840 | |
841 | /* | |
842 | * IOCTL. | |
843 | */ | |
844 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |
845 | struct drm_file *filp); | |
846 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, | |
847 | struct drm_file *filp); | |
848 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, | |
849 | struct drm_file *file_priv); | |
850 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
851 | struct drm_file *file_priv); | |
852 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
853 | struct drm_file *file_priv); | |
854 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, | |
855 | struct drm_file *file_priv); | |
856 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
857 | struct drm_file *filp); | |
858 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
859 | struct drm_file *filp); | |
860 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, | |
861 | struct drm_file *filp); | |
862 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
863 | struct drm_file *filp); | |
864 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); | |
e024e110 DA |
865 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
866 | struct drm_file *filp); | |
867 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
868 | struct drm_file *filp); | |
771fe6b9 JG |
869 | |
870 | ||
871 | /* | |
872 | * Core structure, functions and helpers. | |
873 | */ | |
874 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); | |
875 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); | |
876 | ||
877 | struct radeon_device { | |
9f022ddf | 878 | struct device *dev; |
771fe6b9 JG |
879 | struct drm_device *ddev; |
880 | struct pci_dev *pdev; | |
881 | /* ASIC */ | |
068a117c | 882 | union radeon_asic_config config; |
771fe6b9 JG |
883 | enum radeon_family family; |
884 | unsigned long flags; | |
885 | int usec_timeout; | |
886 | enum radeon_pll_errata pll_errata; | |
887 | int num_gb_pipes; | |
f779b3e5 | 888 | int num_z_pipes; |
771fe6b9 JG |
889 | int disp_priority; |
890 | /* BIOS */ | |
891 | uint8_t *bios; | |
892 | bool is_atom_bios; | |
893 | uint16_t bios_header_start; | |
4c788679 | 894 | struct radeon_bo *stollen_vga_memory; |
771fe6b9 | 895 | struct fb_info *fbdev_info; |
4c788679 | 896 | struct radeon_bo *fbdev_rbo; |
771fe6b9 JG |
897 | struct radeon_framebuffer *fbdev_rfb; |
898 | /* Register mmio */ | |
4c9bc75c DA |
899 | resource_size_t rmmio_base; |
900 | resource_size_t rmmio_size; | |
771fe6b9 | 901 | void *rmmio; |
771fe6b9 JG |
902 | radeon_rreg_t mc_rreg; |
903 | radeon_wreg_t mc_wreg; | |
904 | radeon_rreg_t pll_rreg; | |
905 | radeon_wreg_t pll_wreg; | |
de1b2898 | 906 | uint32_t pcie_reg_mask; |
771fe6b9 JG |
907 | radeon_rreg_t pciep_rreg; |
908 | radeon_wreg_t pciep_wreg; | |
909 | struct radeon_clock clock; | |
910 | struct radeon_mc mc; | |
911 | struct radeon_gart gart; | |
912 | struct radeon_mode_info mode_info; | |
913 | struct radeon_scratch scratch; | |
914 | struct radeon_mman mman; | |
915 | struct radeon_fence_driver fence_drv; | |
916 | struct radeon_cp cp; | |
917 | struct radeon_ib_pool ib_pool; | |
918 | struct radeon_irq irq; | |
919 | struct radeon_asic *asic; | |
920 | struct radeon_gem gem; | |
c93bb85b | 921 | struct radeon_pm pm; |
f657c2a7 | 922 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
771fe6b9 JG |
923 | struct mutex cs_mutex; |
924 | struct radeon_wb wb; | |
3ce0a23d | 925 | struct radeon_dummy_page dummy_page; |
771fe6b9 JG |
926 | bool gpu_lockup; |
927 | bool shutdown; | |
928 | bool suspend; | |
ad49f501 | 929 | bool need_dma32; |
733289c2 | 930 | bool accel_working; |
e024e110 | 931 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
3ce0a23d JG |
932 | const struct firmware *me_fw; /* all family ME firmware */ |
933 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ | |
d8f60cfc | 934 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
3ce0a23d | 935 | struct r600_blit r600_blit; |
3e5cb98d | 936 | int msi_enabled; /* msi enabled */ |
d8f60cfc | 937 | struct r600_ih ih; /* r6/700 interrupt ring */ |
d4877cf2 AD |
938 | struct workqueue_struct *wq; |
939 | struct work_struct hotplug_work; | |
18917b60 | 940 | int num_crtc; /* number of crtcs */ |
40bacf16 | 941 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
dafc3bd5 CK |
942 | |
943 | /* audio stuff */ | |
944 | struct timer_list audio_timer; | |
945 | int audio_channels; | |
946 | int audio_rate; | |
947 | int audio_bits_per_sample; | |
948 | uint8_t audio_status_bits; | |
949 | uint8_t audio_category_code; | |
771fe6b9 JG |
950 | }; |
951 | ||
952 | int radeon_device_init(struct radeon_device *rdev, | |
953 | struct drm_device *ddev, | |
954 | struct pci_dev *pdev, | |
955 | uint32_t flags); | |
956 | void radeon_device_fini(struct radeon_device *rdev); | |
957 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); | |
958 | ||
3ce0a23d JG |
959 | /* r600 blit */ |
960 | int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); | |
961 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); | |
962 | void r600_kms_blit_copy(struct radeon_device *rdev, | |
963 | u64 src_gpu_addr, u64 dst_gpu_addr, | |
964 | int size_bytes); | |
965 | ||
de1b2898 DA |
966 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
967 | { | |
07bec2df | 968 | if (reg < rdev->rmmio_size) |
de1b2898 DA |
969 | return readl(((void __iomem *)rdev->rmmio) + reg); |
970 | else { | |
971 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | |
972 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
973 | } | |
974 | } | |
975 | ||
976 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
977 | { | |
07bec2df | 978 | if (reg < rdev->rmmio_size) |
de1b2898 DA |
979 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
980 | else { | |
981 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | |
982 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
983 | } | |
984 | } | |
985 | ||
4c788679 JG |
986 | /* |
987 | * Cast helper | |
988 | */ | |
989 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) | |
771fe6b9 JG |
990 | |
991 | /* | |
992 | * Registers read & write functions. | |
993 | */ | |
994 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) | |
995 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) | |
de1b2898 | 996 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
3ce0a23d | 997 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
de1b2898 | 998 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
771fe6b9 JG |
999 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1000 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
1001 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) | |
1002 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) | |
1003 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) | |
1004 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) | |
de1b2898 DA |
1005 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
1006 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) | |
771fe6b9 JG |
1007 | #define WREG32_P(reg, val, mask) \ |
1008 | do { \ | |
1009 | uint32_t tmp_ = RREG32(reg); \ | |
1010 | tmp_ &= (mask); \ | |
1011 | tmp_ |= ((val) & ~(mask)); \ | |
1012 | WREG32(reg, tmp_); \ | |
1013 | } while (0) | |
1014 | #define WREG32_PLL_P(reg, val, mask) \ | |
1015 | do { \ | |
1016 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
1017 | tmp_ &= (mask); \ | |
1018 | tmp_ |= ((val) & ~(mask)); \ | |
1019 | WREG32_PLL(reg, tmp_); \ | |
1020 | } while (0) | |
3ce0a23d | 1021 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) |
771fe6b9 | 1022 | |
de1b2898 DA |
1023 | /* |
1024 | * Indirect registers accessor | |
1025 | */ | |
1026 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | |
1027 | { | |
1028 | uint32_t r; | |
1029 | ||
1030 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1031 | r = RREG32(RADEON_PCIE_DATA); | |
1032 | return r; | |
1033 | } | |
1034 | ||
1035 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
1036 | { | |
1037 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1038 | WREG32(RADEON_PCIE_DATA, (v)); | |
1039 | } | |
1040 | ||
771fe6b9 JG |
1041 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
1042 | ||
1043 | ||
1044 | /* | |
1045 | * ASICs helpers. | |
1046 | */ | |
b995e433 DA |
1047 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
1048 | (rdev->pdev->device == 0x5969)) | |
771fe6b9 JG |
1049 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1050 | (rdev->family == CHIP_RV200) || \ | |
1051 | (rdev->family == CHIP_RS100) || \ | |
1052 | (rdev->family == CHIP_RS200) || \ | |
1053 | (rdev->family == CHIP_RV250) || \ | |
1054 | (rdev->family == CHIP_RV280) || \ | |
1055 | (rdev->family == CHIP_RS300)) | |
1056 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ | |
1057 | (rdev->family == CHIP_RV350) || \ | |
1058 | (rdev->family == CHIP_R350) || \ | |
1059 | (rdev->family == CHIP_RV380) || \ | |
1060 | (rdev->family == CHIP_R420) || \ | |
1061 | (rdev->family == CHIP_R423) || \ | |
1062 | (rdev->family == CHIP_RV410) || \ | |
1063 | (rdev->family == CHIP_RS400) || \ | |
1064 | (rdev->family == CHIP_RS480)) | |
1065 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) | |
1066 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) | |
1067 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) | |
1068 | ||
1069 | ||
1070 | /* | |
1071 | * BIOS helpers. | |
1072 | */ | |
1073 | #define RBIOS8(i) (rdev->bios[i]) | |
1074 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
1075 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
1076 | ||
1077 | int radeon_combios_init(struct radeon_device *rdev); | |
1078 | void radeon_combios_fini(struct radeon_device *rdev); | |
1079 | int radeon_atombios_init(struct radeon_device *rdev); | |
1080 | void radeon_atombios_fini(struct radeon_device *rdev); | |
1081 | ||
1082 | ||
1083 | /* | |
1084 | * RING helpers. | |
1085 | */ | |
771fe6b9 JG |
1086 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
1087 | { | |
1088 | #if DRM_DEBUG_CODE | |
1089 | if (rdev->cp.count_dw <= 0) { | |
1090 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); | |
1091 | } | |
1092 | #endif | |
1093 | rdev->cp.ring[rdev->cp.wptr++] = v; | |
1094 | rdev->cp.wptr &= rdev->cp.ptr_mask; | |
1095 | rdev->cp.count_dw--; | |
1096 | rdev->cp.ring_free_dw--; | |
1097 | } | |
1098 | ||
1099 | ||
1100 | /* | |
1101 | * ASICs macro. | |
1102 | */ | |
068a117c | 1103 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
3ce0a23d JG |
1104 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1105 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) | |
1106 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) | |
771fe6b9 | 1107 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
28d52043 | 1108 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
771fe6b9 | 1109 | #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
771fe6b9 JG |
1110 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
1111 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) | |
3ce0a23d | 1112 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
771fe6b9 | 1113 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
3ce0a23d JG |
1114 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
1115 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) | |
771fe6b9 JG |
1116 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
1117 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) | |
7ed220d7 | 1118 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
771fe6b9 JG |
1119 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
1120 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) | |
1121 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) | |
1122 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) | |
7433874e | 1123 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
771fe6b9 | 1124 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
7433874e | 1125 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
93e7de7b | 1126 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) |
c836a412 | 1127 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) |
771fe6b9 JG |
1128 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
1129 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) | |
e024e110 DA |
1130 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
1131 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) | |
c93bb85b | 1132 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
429770b3 AD |
1133 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) |
1134 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) | |
1135 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) | |
1136 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) | |
771fe6b9 | 1137 | |
6cf8a3f5 | 1138 | /* Common functions */ |
700a0cc0 JG |
1139 | /* AGP */ |
1140 | extern void radeon_agp_disable(struct radeon_device *rdev); | |
4aac0473 | 1141 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
21f9a437 JG |
1142 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1143 | extern void radeon_modeset_fini(struct radeon_device *rdev); | |
9f022ddf | 1144 | extern bool radeon_card_posted(struct radeon_device *rdev); |
72542d77 | 1145 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
21f9a437 JG |
1146 | extern int radeon_clocks_init(struct radeon_device *rdev); |
1147 | extern void radeon_clocks_fini(struct radeon_device *rdev); | |
1148 | extern void radeon_scratch_init(struct radeon_device *rdev); | |
1149 | extern void radeon_surface_init(struct radeon_device *rdev); | |
1150 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); | |
ca6ffc64 | 1151 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
d39c3b89 | 1152 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
312ea8da | 1153 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
d03d8589 | 1154 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
6cf8a3f5 | 1155 | |
a18d7ea1 | 1156 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
9f022ddf JG |
1157 | struct r100_mc_save { |
1158 | u32 GENMO_WT; | |
1159 | u32 CRTC_EXT_CNTL; | |
1160 | u32 CRTC_GEN_CNTL; | |
1161 | u32 CRTC2_GEN_CNTL; | |
1162 | u32 CUR_OFFSET; | |
1163 | u32 CUR2_OFFSET; | |
1164 | }; | |
1165 | extern void r100_cp_disable(struct radeon_device *rdev); | |
1166 | extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); | |
1167 | extern void r100_cp_fini(struct radeon_device *rdev); | |
21f9a437 | 1168 | extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
4aac0473 JG |
1169 | extern int r100_pci_gart_init(struct radeon_device *rdev); |
1170 | extern void r100_pci_gart_fini(struct radeon_device *rdev); | |
21f9a437 JG |
1171 | extern int r100_pci_gart_enable(struct radeon_device *rdev); |
1172 | extern void r100_pci_gart_disable(struct radeon_device *rdev); | |
1173 | extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
9f022ddf JG |
1174 | extern int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
1175 | extern int r100_gui_wait_for_idle(struct radeon_device *rdev); | |
1176 | extern void r100_ib_fini(struct radeon_device *rdev); | |
1177 | extern int r100_ib_init(struct radeon_device *rdev); | |
1178 | extern void r100_irq_disable(struct radeon_device *rdev); | |
1179 | extern int r100_irq_set(struct radeon_device *rdev); | |
1180 | extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); | |
1181 | extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); | |
21f9a437 | 1182 | extern void r100_vram_init_sizes(struct radeon_device *rdev); |
9f022ddf JG |
1183 | extern void r100_wb_disable(struct radeon_device *rdev); |
1184 | extern void r100_wb_fini(struct radeon_device *rdev); | |
1185 | extern int r100_wb_init(struct radeon_device *rdev); | |
d39c3b89 JG |
1186 | extern void r100_hdp_reset(struct radeon_device *rdev); |
1187 | extern int r100_rb2d_reset(struct radeon_device *rdev); | |
1188 | extern int r100_cp_reset(struct radeon_device *rdev); | |
ca6ffc64 | 1189 | extern void r100_vga_render_disable(struct radeon_device *rdev); |
207bf9e9 JG |
1190 | extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
1191 | struct radeon_cs_packet *pkt, | |
4c788679 | 1192 | struct radeon_bo *robj); |
207bf9e9 JG |
1193 | extern int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
1194 | struct radeon_cs_packet *pkt, | |
1195 | const unsigned *auth, unsigned n, | |
1196 | radeon_packet0_check_t check); | |
1197 | extern int r100_cs_packet_parse(struct radeon_cs_parser *p, | |
1198 | struct radeon_cs_packet *pkt, | |
1199 | unsigned idx); | |
17e15b0c | 1200 | extern void r100_enable_bm(struct radeon_device *rdev); |
92cde00c | 1201 | extern void r100_set_common_regs(struct radeon_device *rdev); |
9f022ddf | 1202 | |
d4550907 JG |
1203 | /* rv200,rv250,rv280 */ |
1204 | extern void r200_set_safe_registers(struct radeon_device *rdev); | |
9f022ddf JG |
1205 | |
1206 | /* r300,r350,rv350,rv370,rv380 */ | |
1207 | extern void r300_set_reg_safe(struct radeon_device *rdev); | |
1208 | extern void r300_mc_program(struct radeon_device *rdev); | |
1209 | extern void r300_vram_info(struct radeon_device *rdev); | |
ca6ffc64 JG |
1210 | extern void r300_clock_startup(struct radeon_device *rdev); |
1211 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); | |
4aac0473 JG |
1212 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
1213 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); | |
1214 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); | |
9f022ddf | 1215 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
a18d7ea1 | 1216 | |
905b6822 | 1217 | /* r420,r423,rv410 */ |
d39c3b89 | 1218 | extern int r420_mc_init(struct radeon_device *rdev); |
21f9a437 JG |
1219 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
1220 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
9f022ddf | 1221 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
d39c3b89 | 1222 | extern void r420_pipes_init(struct radeon_device *rdev); |
905b6822 | 1223 | |
21f9a437 | 1224 | /* rv515 */ |
d39c3b89 JG |
1225 | struct rv515_mc_save { |
1226 | u32 d1vga_control; | |
1227 | u32 d2vga_control; | |
1228 | u32 vga_render_control; | |
1229 | u32 vga_hdp_control; | |
1230 | u32 d1crtc_control; | |
1231 | u32 d2crtc_control; | |
1232 | }; | |
21f9a437 | 1233 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
d39c3b89 JG |
1234 | extern void rv515_vga_render_disable(struct radeon_device *rdev); |
1235 | extern void rv515_set_safe_registers(struct radeon_device *rdev); | |
f0ed1f65 JG |
1236 | extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
1237 | extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); | |
1238 | extern void rv515_clock_startup(struct radeon_device *rdev); | |
1239 | extern void rv515_debugfs(struct radeon_device *rdev); | |
1240 | extern int rv515_suspend(struct radeon_device *rdev); | |
21f9a437 | 1241 | |
3bc68535 JG |
1242 | /* rs400 */ |
1243 | extern int rs400_gart_init(struct radeon_device *rdev); | |
1244 | extern int rs400_gart_enable(struct radeon_device *rdev); | |
1245 | extern void rs400_gart_adjust_size(struct radeon_device *rdev); | |
1246 | extern void rs400_gart_disable(struct radeon_device *rdev); | |
1247 | extern void rs400_gart_fini(struct radeon_device *rdev); | |
1248 | ||
1249 | /* rs600 */ | |
1250 | extern void rs600_set_safe_registers(struct radeon_device *rdev); | |
ac447df4 JG |
1251 | extern int rs600_irq_set(struct radeon_device *rdev); |
1252 | extern void rs600_irq_disable(struct radeon_device *rdev); | |
3bc68535 | 1253 | |
21f9a437 JG |
1254 | /* rs690, rs740 */ |
1255 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, | |
1256 | struct drm_display_mode *mode1, | |
1257 | struct drm_display_mode *mode2); | |
1258 | ||
1259 | /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ | |
1260 | extern bool r600_card_posted(struct radeon_device *rdev); | |
1261 | extern void r600_cp_stop(struct radeon_device *rdev); | |
1262 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
1263 | extern int r600_cp_resume(struct radeon_device *rdev); | |
655efd3d | 1264 | extern void r600_cp_fini(struct radeon_device *rdev); |
21f9a437 JG |
1265 | extern int r600_count_pipe_bits(uint32_t val); |
1266 | extern int r600_gart_clear_page(struct radeon_device *rdev, int i); | |
1267 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); | |
4aac0473 | 1268 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
21f9a437 JG |
1269 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
1270 | extern int r600_ib_test(struct radeon_device *rdev); | |
1271 | extern int r600_ring_test(struct radeon_device *rdev); | |
21f9a437 | 1272 | extern void r600_wb_fini(struct radeon_device *rdev); |
81cc35bf JG |
1273 | extern int r600_wb_enable(struct radeon_device *rdev); |
1274 | extern void r600_wb_disable(struct radeon_device *rdev); | |
21f9a437 JG |
1275 | extern void r600_scratch_init(struct radeon_device *rdev); |
1276 | extern int r600_blit_init(struct radeon_device *rdev); | |
1277 | extern void r600_blit_fini(struct radeon_device *rdev); | |
d8f60cfc | 1278 | extern int r600_init_microcode(struct radeon_device *rdev); |
fe62e1a4 | 1279 | extern int r600_gpu_reset(struct radeon_device *rdev); |
d8f60cfc AD |
1280 | /* r600 irq */ |
1281 | extern int r600_irq_init(struct radeon_device *rdev); | |
1282 | extern void r600_irq_fini(struct radeon_device *rdev); | |
1283 | extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
1284 | extern int r600_irq_set(struct radeon_device *rdev); | |
0c45249f JG |
1285 | extern void r600_irq_suspend(struct radeon_device *rdev); |
1286 | /* r600 audio */ | |
dafc3bd5 CK |
1287 | extern int r600_audio_init(struct radeon_device *rdev); |
1288 | extern int r600_audio_tmds_index(struct drm_encoder *encoder); | |
1289 | extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); | |
1290 | extern void r600_audio_fini(struct radeon_device *rdev); | |
1291 | extern void r600_hdmi_init(struct drm_encoder *encoder); | |
1292 | extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable); | |
1293 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); | |
1294 | extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); | |
1295 | extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder, | |
1296 | int channels, | |
1297 | int rate, | |
1298 | int bps, | |
1299 | uint8_t status_bits, | |
1300 | uint8_t category_code); | |
1301 | ||
4c788679 JG |
1302 | #include "radeon_object.h" |
1303 | ||
771fe6b9 | 1304 | #endif |