]>
Commit | Line | Data |
---|---|---|
771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __RADEON_H__ | |
29 | #define __RADEON_H__ | |
30 | ||
771fe6b9 JG |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should | |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings | |
34 | * related to surface | |
35 | * - WB : write back stuff (do it bit like scratch reg things) | |
36 | * - Vblank : look at Jesse's rework and what we should do | |
37 | * - r600/r700: gart & cp | |
38 | * - cs : clean cs ioctl use bitmap & things like that. | |
39 | * - power management stuff | |
40 | * - Barrier in gart code | |
41 | * - Unmappabled vram ? | |
42 | * - TESTING, TESTING, TESTING | |
43 | */ | |
44 | ||
d39c3b89 JG |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various | |
47 | * reasons even thought we work hard to make it works on most | |
48 | * configurations. In order to still have a working userspace in such | |
49 | * situation the init path must succeed up to the memory controller | |
50 | * initialization point. Failure before this point are considered as | |
51 | * fatal error. Here is the init callchain : | |
52 | * radeon_device_init perform common structure, mutex initialization | |
53 | * asic_init setup the GPU memory layout and perform all | |
54 | * one time initialization (failure in this | |
55 | * function are considered fatal) | |
56 | * asic_startup setup the GPU acceleration, in order to | |
57 | * follow guideline the first thing this | |
58 | * function should do is setting the GPU | |
59 | * memory controller (only MC setup failure | |
60 | * are considered as fatal) | |
61 | */ | |
62 | ||
60063497 | 63 | #include <linux/atomic.h> |
771fe6b9 JG |
64 | #include <linux/wait.h> |
65 | #include <linux/list.h> | |
66 | #include <linux/kref.h> | |
67 | ||
4c788679 JG |
68 | #include <ttm/ttm_bo_api.h> |
69 | #include <ttm/ttm_bo_driver.h> | |
70 | #include <ttm/ttm_placement.h> | |
71 | #include <ttm/ttm_module.h> | |
147666fb | 72 | #include <ttm/ttm_execbuf_util.h> |
4c788679 | 73 | |
c2142715 | 74 | #include "radeon_family.h" |
771fe6b9 JG |
75 | #include "radeon_mode.h" |
76 | #include "radeon_reg.h" | |
771fe6b9 JG |
77 | |
78 | /* | |
79 | * Modules parameters. | |
80 | */ | |
81 | extern int radeon_no_wb; | |
82 | extern int radeon_modeset; | |
83 | extern int radeon_dynclks; | |
84 | extern int radeon_r4xx_atom; | |
85 | extern int radeon_agpmode; | |
86 | extern int radeon_vram_limit; | |
87 | extern int radeon_gart_size; | |
88 | extern int radeon_benchmarking; | |
ecc0b326 | 89 | extern int radeon_testing; |
771fe6b9 | 90 | extern int radeon_connector_table; |
4ce001ab | 91 | extern int radeon_tv; |
dafc3bd5 | 92 | extern int radeon_audio; |
f46c0120 | 93 | extern int radeon_disp_priority; |
e2b0a8e1 | 94 | extern int radeon_hw_i2c; |
d42dd579 | 95 | extern int radeon_pcie_gen2; |
a18cee15 | 96 | extern int radeon_msi; |
3368ff0c | 97 | extern int radeon_lockup_timeout; |
a0a53aa8 | 98 | extern int radeon_fastfb; |
771fe6b9 JG |
99 | |
100 | /* | |
101 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | |
102 | * symbol; | |
103 | */ | |
bb635567 JG |
104 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
105 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) | |
e821767b | 106 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
bb635567 JG |
107 | #define RADEON_IB_POOL_SIZE 16 |
108 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 | |
109 | #define RADEONFB_CONN_LIMIT 4 | |
110 | #define RADEON_BIOS_NUM_SCRATCH 8 | |
771fe6b9 | 111 | |
1b37078b | 112 | /* max number of rings */ |
f2ba57b5 | 113 | #define RADEON_NUM_RINGS 6 |
bb635567 JG |
114 | |
115 | /* fence seq are set to this number when signaled */ | |
116 | #define RADEON_FENCE_SIGNALED_SEQ 0LL | |
1b37078b AD |
117 | |
118 | /* internal ring indices */ | |
119 | /* r1xx+ has gfx CP ring */ | |
f2ba57b5 | 120 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
1b37078b AD |
121 | |
122 | /* cayman has 2 compute CP rings */ | |
f2ba57b5 CK |
123 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
124 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 | |
1b37078b | 125 | |
4d75658b AD |
126 | /* R600+ has an async dma ring */ |
127 | #define R600_RING_TYPE_DMA_INDEX 3 | |
f60cbd11 AD |
128 | /* cayman add a second async dma ring */ |
129 | #define CAYMAN_RING_TYPE_DMA1_INDEX 4 | |
4d75658b | 130 | |
f2ba57b5 CK |
131 | /* R600+ */ |
132 | #define R600_RING_TYPE_UVD_INDEX 5 | |
133 | ||
721604a1 | 134 | /* hardcode those limit for now */ |
ca19f21e | 135 | #define RADEON_VA_IB_OFFSET (1 << 20) |
bb635567 JG |
136 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
137 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) | |
721604a1 | 138 | |
ec46c76d AD |
139 | /* reset flags */ |
140 | #define RADEON_RESET_GFX (1 << 0) | |
141 | #define RADEON_RESET_COMPUTE (1 << 1) | |
142 | #define RADEON_RESET_DMA (1 << 2) | |
9ff0744c AD |
143 | #define RADEON_RESET_CP (1 << 3) |
144 | #define RADEON_RESET_GRBM (1 << 4) | |
145 | #define RADEON_RESET_DMA1 (1 << 5) | |
146 | #define RADEON_RESET_RLC (1 << 6) | |
147 | #define RADEON_RESET_SEM (1 << 7) | |
148 | #define RADEON_RESET_IH (1 << 8) | |
149 | #define RADEON_RESET_VMC (1 << 9) | |
150 | #define RADEON_RESET_MC (1 << 10) | |
151 | #define RADEON_RESET_DISPLAY (1 << 11) | |
ec46c76d | 152 | |
771fe6b9 JG |
153 | /* |
154 | * Errata workarounds. | |
155 | */ | |
156 | enum radeon_pll_errata { | |
157 | CHIP_ERRATA_R300_CG = 0x00000001, | |
158 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, | |
159 | CHIP_ERRATA_PLL_DELAY = 0x00000004 | |
160 | }; | |
161 | ||
162 | ||
163 | struct radeon_device; | |
164 | ||
165 | ||
166 | /* | |
167 | * BIOS. | |
168 | */ | |
169 | bool radeon_get_bios(struct radeon_device *rdev); | |
170 | ||
171 | /* | |
3ce0a23d | 172 | * Dummy page |
771fe6b9 | 173 | */ |
3ce0a23d JG |
174 | struct radeon_dummy_page { |
175 | struct page *page; | |
176 | dma_addr_t addr; | |
177 | }; | |
178 | int radeon_dummy_page_init(struct radeon_device *rdev); | |
179 | void radeon_dummy_page_fini(struct radeon_device *rdev); | |
180 | ||
771fe6b9 | 181 | |
3ce0a23d JG |
182 | /* |
183 | * Clocks | |
184 | */ | |
771fe6b9 JG |
185 | struct radeon_clock { |
186 | struct radeon_pll p1pll; | |
187 | struct radeon_pll p2pll; | |
bcc1c2a1 | 188 | struct radeon_pll dcpll; |
771fe6b9 JG |
189 | struct radeon_pll spll; |
190 | struct radeon_pll mpll; | |
191 | /* 10 Khz units */ | |
192 | uint32_t default_mclk; | |
193 | uint32_t default_sclk; | |
bcc1c2a1 AD |
194 | uint32_t default_dispclk; |
195 | uint32_t dp_extclk; | |
b20f9bef | 196 | uint32_t max_pixel_clock; |
771fe6b9 JG |
197 | }; |
198 | ||
7433874e RM |
199 | /* |
200 | * Power management | |
201 | */ | |
202 | int radeon_pm_init(struct radeon_device *rdev); | |
29fb52ca | 203 | void radeon_pm_fini(struct radeon_device *rdev); |
c913e23a | 204 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
ce8f5370 AD |
205 | void radeon_pm_suspend(struct radeon_device *rdev); |
206 | void radeon_pm_resume(struct radeon_device *rdev); | |
56278a8e AD |
207 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
208 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); | |
7062ab67 CK |
209 | int radeon_atom_get_clock_dividers(struct radeon_device *rdev, |
210 | u8 clock_type, | |
211 | u32 clock, | |
212 | bool strobe_mode, | |
213 | struct atom_clock_dividers *dividers); | |
8a83ec5e | 214 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
f892034a | 215 | void rs690_pm_info(struct radeon_device *rdev); |
20d391d7 AD |
216 | extern int rv6xx_get_temp(struct radeon_device *rdev); |
217 | extern int rv770_get_temp(struct radeon_device *rdev); | |
218 | extern int evergreen_get_temp(struct radeon_device *rdev); | |
219 | extern int sumo_get_temp(struct radeon_device *rdev); | |
1bd47d2e | 220 | extern int si_get_temp(struct radeon_device *rdev); |
285484e2 JG |
221 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
222 | unsigned *bankh, unsigned *mtaspect, | |
223 | unsigned *tile_split); | |
3ce0a23d | 224 | |
771fe6b9 JG |
225 | /* |
226 | * Fences. | |
227 | */ | |
228 | struct radeon_fence_driver { | |
229 | uint32_t scratch_reg; | |
30eb77f4 JG |
230 | uint64_t gpu_addr; |
231 | volatile uint32_t *cpu_addr; | |
68e250b7 CK |
232 | /* sync_seq is protected by ring emission lock */ |
233 | uint64_t sync_seq[RADEON_NUM_RINGS]; | |
bb635567 | 234 | atomic64_t last_seq; |
36abacae | 235 | unsigned long last_activity; |
0a0c7596 | 236 | bool initialized; |
771fe6b9 JG |
237 | }; |
238 | ||
239 | struct radeon_fence { | |
240 | struct radeon_device *rdev; | |
241 | struct kref kref; | |
771fe6b9 | 242 | /* protected by radeon_fence.lock */ |
bb635567 | 243 | uint64_t seq; |
7465280c | 244 | /* RB, DMA, etc. */ |
bb635567 | 245 | unsigned ring; |
771fe6b9 JG |
246 | }; |
247 | ||
30eb77f4 JG |
248 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
249 | int radeon_fence_driver_init(struct radeon_device *rdev); | |
771fe6b9 | 250 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
76903b96 | 251 | void radeon_fence_driver_force_completion(struct radeon_device *rdev); |
876dc9f3 | 252 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
7465280c | 253 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
771fe6b9 JG |
254 | bool radeon_fence_signaled(struct radeon_fence *fence); |
255 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); | |
8a47cc9e | 256 | int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); |
5f8f635e | 257 | int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); |
0085c950 JG |
258 | int radeon_fence_wait_any(struct radeon_device *rdev, |
259 | struct radeon_fence **fences, | |
260 | bool intr); | |
771fe6b9 JG |
261 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
262 | void radeon_fence_unref(struct radeon_fence **fence); | |
3b7a2b24 | 263 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
68e250b7 CK |
264 | bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); |
265 | void radeon_fence_note_sync(struct radeon_fence *fence, int ring); | |
266 | static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, | |
267 | struct radeon_fence *b) | |
268 | { | |
269 | if (!a) { | |
270 | return b; | |
271 | } | |
272 | ||
273 | if (!b) { | |
274 | return a; | |
275 | } | |
276 | ||
277 | BUG_ON(a->ring != b->ring); | |
278 | ||
279 | if (a->seq > b->seq) { | |
280 | return a; | |
281 | } else { | |
282 | return b; | |
283 | } | |
284 | } | |
771fe6b9 | 285 | |
ee60e29f CK |
286 | static inline bool radeon_fence_is_earlier(struct radeon_fence *a, |
287 | struct radeon_fence *b) | |
288 | { | |
289 | if (!a) { | |
290 | return false; | |
291 | } | |
292 | ||
293 | if (!b) { | |
294 | return true; | |
295 | } | |
296 | ||
297 | BUG_ON(a->ring != b->ring); | |
298 | ||
299 | return a->seq < b->seq; | |
300 | } | |
301 | ||
e024e110 DA |
302 | /* |
303 | * Tiling registers | |
304 | */ | |
305 | struct radeon_surface_reg { | |
4c788679 | 306 | struct radeon_bo *bo; |
e024e110 DA |
307 | }; |
308 | ||
309 | #define RADEON_GEM_MAX_SURFACES 8 | |
771fe6b9 JG |
310 | |
311 | /* | |
4c788679 | 312 | * TTM. |
771fe6b9 | 313 | */ |
4c788679 JG |
314 | struct radeon_mman { |
315 | struct ttm_bo_global_ref bo_global_ref; | |
ba4420c2 | 316 | struct drm_global_reference mem_global_ref; |
4c788679 | 317 | struct ttm_bo_device bdev; |
0a0c7596 JG |
318 | bool mem_global_referenced; |
319 | bool initialized; | |
4c788679 JG |
320 | }; |
321 | ||
721604a1 JG |
322 | /* bo virtual address in a specific vm */ |
323 | struct radeon_bo_va { | |
e971bd5e | 324 | /* protected by bo being reserved */ |
721604a1 | 325 | struct list_head bo_list; |
721604a1 JG |
326 | uint64_t soffset; |
327 | uint64_t eoffset; | |
328 | uint32_t flags; | |
329 | bool valid; | |
e971bd5e CK |
330 | unsigned ref_count; |
331 | ||
332 | /* protected by vm mutex */ | |
333 | struct list_head vm_list; | |
334 | ||
335 | /* constant after initialization */ | |
336 | struct radeon_vm *vm; | |
337 | struct radeon_bo *bo; | |
721604a1 JG |
338 | }; |
339 | ||
4c788679 JG |
340 | struct radeon_bo { |
341 | /* Protected by gem.mutex */ | |
342 | struct list_head list; | |
343 | /* Protected by tbo.reserved */ | |
312ea8da JG |
344 | u32 placements[3]; |
345 | struct ttm_placement placement; | |
4c788679 JG |
346 | struct ttm_buffer_object tbo; |
347 | struct ttm_bo_kmap_obj kmap; | |
348 | unsigned pin_count; | |
349 | void *kptr; | |
350 | u32 tiling_flags; | |
351 | u32 pitch; | |
352 | int surface_reg; | |
721604a1 JG |
353 | /* list of all virtual address to which this bo |
354 | * is associated to | |
355 | */ | |
356 | struct list_head va; | |
4c788679 JG |
357 | /* Constant after initialization */ |
358 | struct radeon_device *rdev; | |
441921d5 | 359 | struct drm_gem_object gem_base; |
63bc620b | 360 | |
409851f4 JG |
361 | struct ttm_bo_kmap_obj dma_buf_vmap; |
362 | pid_t pid; | |
4c788679 | 363 | }; |
7e4d15d9 | 364 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
771fe6b9 | 365 | |
4c788679 | 366 | struct radeon_bo_list { |
147666fb | 367 | struct ttm_validate_buffer tv; |
4c788679 | 368 | struct radeon_bo *bo; |
771fe6b9 | 369 | uint64_t gpu_offset; |
4474f3a9 CK |
370 | bool written; |
371 | unsigned domain; | |
372 | unsigned alt_domain; | |
4c788679 | 373 | u32 tiling_flags; |
771fe6b9 JG |
374 | }; |
375 | ||
409851f4 JG |
376 | int radeon_gem_debugfs_init(struct radeon_device *rdev); |
377 | ||
b15ba512 JG |
378 | /* sub-allocation manager, it has to be protected by another lock. |
379 | * By conception this is an helper for other part of the driver | |
380 | * like the indirect buffer or semaphore, which both have their | |
381 | * locking. | |
382 | * | |
383 | * Principe is simple, we keep a list of sub allocation in offset | |
384 | * order (first entry has offset == 0, last entry has the highest | |
385 | * offset). | |
386 | * | |
387 | * When allocating new object we first check if there is room at | |
388 | * the end total_size - (last_object_offset + last_object_size) >= | |
389 | * alloc_size. If so we allocate new object there. | |
390 | * | |
391 | * When there is not enough room at the end, we start waiting for | |
392 | * each sub object until we reach object_offset+object_size >= | |
393 | * alloc_size, this object then become the sub object we return. | |
394 | * | |
395 | * Alignment can't be bigger than page size. | |
396 | * | |
397 | * Hole are not considered for allocation to keep things simple. | |
398 | * Assumption is that there won't be hole (all object on same | |
399 | * alignment). | |
400 | */ | |
401 | struct radeon_sa_manager { | |
bfb38d35 | 402 | wait_queue_head_t wq; |
b15ba512 | 403 | struct radeon_bo *bo; |
c3b7fe8b CK |
404 | struct list_head *hole; |
405 | struct list_head flist[RADEON_NUM_RINGS]; | |
406 | struct list_head olist; | |
b15ba512 JG |
407 | unsigned size; |
408 | uint64_t gpu_addr; | |
409 | void *cpu_ptr; | |
410 | uint32_t domain; | |
411 | }; | |
412 | ||
413 | struct radeon_sa_bo; | |
414 | ||
415 | /* sub-allocation buffer */ | |
416 | struct radeon_sa_bo { | |
c3b7fe8b CK |
417 | struct list_head olist; |
418 | struct list_head flist; | |
b15ba512 | 419 | struct radeon_sa_manager *manager; |
e6661a96 CK |
420 | unsigned soffset; |
421 | unsigned eoffset; | |
557017a0 | 422 | struct radeon_fence *fence; |
b15ba512 JG |
423 | }; |
424 | ||
771fe6b9 JG |
425 | /* |
426 | * GEM objects. | |
427 | */ | |
428 | struct radeon_gem { | |
4c788679 | 429 | struct mutex mutex; |
771fe6b9 JG |
430 | struct list_head objects; |
431 | }; | |
432 | ||
433 | int radeon_gem_init(struct radeon_device *rdev); | |
434 | void radeon_gem_fini(struct radeon_device *rdev); | |
435 | int radeon_gem_object_create(struct radeon_device *rdev, int size, | |
4c788679 JG |
436 | int alignment, int initial_domain, |
437 | bool discardable, bool kernel, | |
438 | struct drm_gem_object **obj); | |
771fe6b9 | 439 | |
ff72145b DA |
440 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
441 | struct drm_device *dev, | |
442 | struct drm_mode_create_dumb *args); | |
443 | int radeon_mode_dumb_mmap(struct drm_file *filp, | |
444 | struct drm_device *dev, | |
445 | uint32_t handle, uint64_t *offset_p); | |
446 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, | |
447 | struct drm_device *dev, | |
448 | uint32_t handle); | |
771fe6b9 | 449 | |
c1341e52 JG |
450 | /* |
451 | * Semaphores. | |
452 | */ | |
c1341e52 JG |
453 | /* everything here is constant */ |
454 | struct radeon_semaphore { | |
a8c05940 JG |
455 | struct radeon_sa_bo *sa_bo; |
456 | signed waiters; | |
c1341e52 | 457 | uint64_t gpu_addr; |
c1341e52 JG |
458 | }; |
459 | ||
c1341e52 JG |
460 | int radeon_semaphore_create(struct radeon_device *rdev, |
461 | struct radeon_semaphore **semaphore); | |
462 | void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, | |
463 | struct radeon_semaphore *semaphore); | |
464 | void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, | |
465 | struct radeon_semaphore *semaphore); | |
8f676c4c CK |
466 | int radeon_semaphore_sync_rings(struct radeon_device *rdev, |
467 | struct radeon_semaphore *semaphore, | |
220907d9 | 468 | int signaler, int waiter); |
c1341e52 | 469 | void radeon_semaphore_free(struct radeon_device *rdev, |
220907d9 | 470 | struct radeon_semaphore **semaphore, |
a8c05940 | 471 | struct radeon_fence *fence); |
c1341e52 | 472 | |
771fe6b9 JG |
473 | /* |
474 | * GART structures, functions & helpers | |
475 | */ | |
476 | struct radeon_mc; | |
477 | ||
a77f1718 | 478 | #define RADEON_GPU_PAGE_SIZE 4096 |
d594e46a | 479 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
003cefe0 | 480 | #define RADEON_GPU_PAGE_SHIFT 12 |
721604a1 | 481 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
a77f1718 | 482 | |
771fe6b9 JG |
483 | struct radeon_gart { |
484 | dma_addr_t table_addr; | |
c9a1be96 JG |
485 | struct radeon_bo *robj; |
486 | void *ptr; | |
771fe6b9 JG |
487 | unsigned num_gpu_pages; |
488 | unsigned num_cpu_pages; | |
489 | unsigned table_size; | |
771fe6b9 JG |
490 | struct page **pages; |
491 | dma_addr_t *pages_addr; | |
492 | bool ready; | |
493 | }; | |
494 | ||
495 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); | |
496 | void radeon_gart_table_ram_free(struct radeon_device *rdev); | |
497 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); | |
498 | void radeon_gart_table_vram_free(struct radeon_device *rdev); | |
c9a1be96 JG |
499 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
500 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); | |
771fe6b9 JG |
501 | int radeon_gart_init(struct radeon_device *rdev); |
502 | void radeon_gart_fini(struct radeon_device *rdev); | |
503 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |
504 | int pages); | |
505 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |
c39d3516 KRW |
506 | int pages, struct page **pagelist, |
507 | dma_addr_t *dma_addr); | |
c9a1be96 | 508 | void radeon_gart_restore(struct radeon_device *rdev); |
771fe6b9 JG |
509 | |
510 | ||
511 | /* | |
512 | * GPU MC structures, functions & helpers | |
513 | */ | |
514 | struct radeon_mc { | |
515 | resource_size_t aper_size; | |
516 | resource_size_t aper_base; | |
517 | resource_size_t agp_base; | |
7a50f01a DA |
518 | /* for some chips with <= 32MB we need to lie |
519 | * about vram size near mc fb location */ | |
3ce0a23d | 520 | u64 mc_vram_size; |
d594e46a | 521 | u64 visible_vram_size; |
3ce0a23d JG |
522 | u64 gtt_size; |
523 | u64 gtt_start; | |
524 | u64 gtt_end; | |
3ce0a23d JG |
525 | u64 vram_start; |
526 | u64 vram_end; | |
771fe6b9 | 527 | unsigned vram_width; |
3ce0a23d | 528 | u64 real_vram_size; |
771fe6b9 JG |
529 | int vram_mtrr; |
530 | bool vram_is_ddr; | |
d594e46a | 531 | bool igp_sideport_enabled; |
8d369bb1 | 532 | u64 gtt_base_align; |
9ed8b1f9 | 533 | u64 mc_mask; |
771fe6b9 JG |
534 | }; |
535 | ||
06b6476d AD |
536 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
537 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); | |
771fe6b9 JG |
538 | |
539 | /* | |
540 | * GPU scratch registers structures, functions & helpers | |
541 | */ | |
542 | struct radeon_scratch { | |
543 | unsigned num_reg; | |
724c80e1 | 544 | uint32_t reg_base; |
771fe6b9 JG |
545 | bool free[32]; |
546 | uint32_t reg[32]; | |
547 | }; | |
548 | ||
549 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); | |
550 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); | |
551 | ||
552 | ||
553 | /* | |
554 | * IRQS. | |
555 | */ | |
6f34be50 AD |
556 | |
557 | struct radeon_unpin_work { | |
558 | struct work_struct work; | |
559 | struct radeon_device *rdev; | |
560 | int crtc_id; | |
561 | struct radeon_fence *fence; | |
562 | struct drm_pending_vblank_event *event; | |
563 | struct radeon_bo *old_rbo; | |
564 | u64 new_crtc_base; | |
565 | }; | |
566 | ||
567 | struct r500_irq_stat_regs { | |
568 | u32 disp_int; | |
f122c610 | 569 | u32 hdmi0_status; |
6f34be50 AD |
570 | }; |
571 | ||
572 | struct r600_irq_stat_regs { | |
573 | u32 disp_int; | |
574 | u32 disp_int_cont; | |
575 | u32 disp_int_cont2; | |
576 | u32 d1grph_int; | |
577 | u32 d2grph_int; | |
f122c610 AD |
578 | u32 hdmi0_status; |
579 | u32 hdmi1_status; | |
6f34be50 AD |
580 | }; |
581 | ||
582 | struct evergreen_irq_stat_regs { | |
583 | u32 disp_int; | |
584 | u32 disp_int_cont; | |
585 | u32 disp_int_cont2; | |
586 | u32 disp_int_cont3; | |
587 | u32 disp_int_cont4; | |
588 | u32 disp_int_cont5; | |
589 | u32 d1grph_int; | |
590 | u32 d2grph_int; | |
591 | u32 d3grph_int; | |
592 | u32 d4grph_int; | |
593 | u32 d5grph_int; | |
594 | u32 d6grph_int; | |
f122c610 AD |
595 | u32 afmt_status1; |
596 | u32 afmt_status2; | |
597 | u32 afmt_status3; | |
598 | u32 afmt_status4; | |
599 | u32 afmt_status5; | |
600 | u32 afmt_status6; | |
6f34be50 AD |
601 | }; |
602 | ||
603 | union radeon_irq_stat_regs { | |
604 | struct r500_irq_stat_regs r500; | |
605 | struct r600_irq_stat_regs r600; | |
606 | struct evergreen_irq_stat_regs evergreen; | |
607 | }; | |
608 | ||
54bd5206 IH |
609 | #define RADEON_MAX_HPD_PINS 6 |
610 | #define RADEON_MAX_CRTCS 6 | |
f122c610 | 611 | #define RADEON_MAX_AFMT_BLOCKS 6 |
54bd5206 | 612 | |
771fe6b9 | 613 | struct radeon_irq { |
fb98257a CK |
614 | bool installed; |
615 | spinlock_t lock; | |
736fc37f | 616 | atomic_t ring_int[RADEON_NUM_RINGS]; |
fb98257a | 617 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
736fc37f | 618 | atomic_t pflip[RADEON_MAX_CRTCS]; |
fb98257a CK |
619 | wait_queue_head_t vblank_queue; |
620 | bool hpd[RADEON_MAX_HPD_PINS]; | |
fb98257a CK |
621 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
622 | union radeon_irq_stat_regs stat_regs; | |
771fe6b9 JG |
623 | }; |
624 | ||
625 | int radeon_irq_kms_init(struct radeon_device *rdev); | |
626 | void radeon_irq_kms_fini(struct radeon_device *rdev); | |
1b37078b AD |
627 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
628 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); | |
6f34be50 AD |
629 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
630 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); | |
fb98257a CK |
631 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); |
632 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); | |
633 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); | |
634 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); | |
771fe6b9 JG |
635 | |
636 | /* | |
e32eb50d | 637 | * CP & rings. |
771fe6b9 | 638 | */ |
7465280c | 639 | |
771fe6b9 | 640 | struct radeon_ib { |
68470ae7 JG |
641 | struct radeon_sa_bo *sa_bo; |
642 | uint32_t length_dw; | |
643 | uint64_t gpu_addr; | |
644 | uint32_t *ptr; | |
876dc9f3 | 645 | int ring; |
68470ae7 | 646 | struct radeon_fence *fence; |
4bf3dd92 | 647 | struct radeon_vm *vm; |
68470ae7 | 648 | bool is_const_ib; |
220907d9 | 649 | struct radeon_fence *sync_to[RADEON_NUM_RINGS]; |
68470ae7 | 650 | struct radeon_semaphore *semaphore; |
771fe6b9 JG |
651 | }; |
652 | ||
e32eb50d | 653 | struct radeon_ring { |
4c788679 | 654 | struct radeon_bo *ring_obj; |
771fe6b9 JG |
655 | volatile uint32_t *ring; |
656 | unsigned rptr; | |
5596a9db CK |
657 | unsigned rptr_offs; |
658 | unsigned rptr_reg; | |
45df6803 | 659 | unsigned rptr_save_reg; |
89d35807 AD |
660 | u64 next_rptr_gpu_addr; |
661 | volatile u32 *next_rptr_cpu_addr; | |
771fe6b9 JG |
662 | unsigned wptr; |
663 | unsigned wptr_old; | |
5596a9db | 664 | unsigned wptr_reg; |
771fe6b9 JG |
665 | unsigned ring_size; |
666 | unsigned ring_free_dw; | |
667 | int count_dw; | |
069211e5 CK |
668 | unsigned long last_activity; |
669 | unsigned last_rptr; | |
771fe6b9 JG |
670 | uint64_t gpu_addr; |
671 | uint32_t align_mask; | |
672 | uint32_t ptr_mask; | |
771fe6b9 | 673 | bool ready; |
78c5560a AD |
674 | u32 ptr_reg_shift; |
675 | u32 ptr_reg_mask; | |
676 | u32 nop; | |
8b25ed34 | 677 | u32 idx; |
5f0839c1 JG |
678 | u64 last_semaphore_signal_addr; |
679 | u64 last_semaphore_wait_addr; | |
771fe6b9 JG |
680 | }; |
681 | ||
721604a1 JG |
682 | /* |
683 | * VM | |
684 | */ | |
ee60e29f | 685 | |
fa87e62d | 686 | /* maximum number of VMIDs */ |
ee60e29f CK |
687 | #define RADEON_NUM_VM 16 |
688 | ||
fa87e62d DC |
689 | /* defines number of bits in page table versus page directory, |
690 | * a page is 4KB so we have 12 bits offset, 9 bits in the page | |
691 | * table and the remaining 19 bits are in the page directory */ | |
692 | #define RADEON_VM_BLOCK_SIZE 9 | |
693 | ||
694 | /* number of entries in page table */ | |
695 | #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) | |
696 | ||
721604a1 JG |
697 | struct radeon_vm { |
698 | struct list_head list; | |
699 | struct list_head va; | |
ee60e29f | 700 | unsigned id; |
90a51a32 CK |
701 | |
702 | /* contains the page directory */ | |
703 | struct radeon_sa_bo *page_directory; | |
704 | uint64_t pd_gpu_addr; | |
705 | ||
706 | /* array of page tables, one for each page directory entry */ | |
707 | struct radeon_sa_bo **page_tables; | |
708 | ||
721604a1 JG |
709 | struct mutex mutex; |
710 | /* last fence for cs using this vm */ | |
711 | struct radeon_fence *fence; | |
9b40e5d8 CK |
712 | /* last flush or NULL if we still need to flush */ |
713 | struct radeon_fence *last_flush; | |
721604a1 JG |
714 | }; |
715 | ||
721604a1 | 716 | struct radeon_vm_manager { |
36ff39c4 | 717 | struct mutex lock; |
721604a1 | 718 | struct list_head lru_vm; |
ee60e29f | 719 | struct radeon_fence *active[RADEON_NUM_VM]; |
721604a1 JG |
720 | struct radeon_sa_manager sa_manager; |
721 | uint32_t max_pfn; | |
721604a1 JG |
722 | /* number of VMIDs */ |
723 | unsigned nvm; | |
724 | /* vram base address for page table entry */ | |
725 | u64 vram_base_offset; | |
67e915e4 AD |
726 | /* is vm enabled? */ |
727 | bool enabled; | |
721604a1 JG |
728 | }; |
729 | ||
730 | /* | |
731 | * file private structure | |
732 | */ | |
733 | struct radeon_fpriv { | |
734 | struct radeon_vm vm; | |
735 | }; | |
736 | ||
d8f60cfc AD |
737 | /* |
738 | * R6xx+ IH ring | |
739 | */ | |
740 | struct r600_ih { | |
4c788679 | 741 | struct radeon_bo *ring_obj; |
d8f60cfc AD |
742 | volatile uint32_t *ring; |
743 | unsigned rptr; | |
d8f60cfc AD |
744 | unsigned ring_size; |
745 | uint64_t gpu_addr; | |
d8f60cfc | 746 | uint32_t ptr_mask; |
c20dc369 | 747 | atomic_t lock; |
d8f60cfc AD |
748 | bool enabled; |
749 | }; | |
750 | ||
8eec9d6f IH |
751 | struct r600_blit_cp_primitives { |
752 | void (*set_render_target)(struct radeon_device *rdev, int format, | |
753 | int w, int h, u64 gpu_addr); | |
754 | void (*cp_set_surface_sync)(struct radeon_device *rdev, | |
755 | u32 sync_type, u32 size, | |
756 | u64 mc_addr); | |
757 | void (*set_shaders)(struct radeon_device *rdev); | |
758 | void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); | |
759 | void (*set_tex_resource)(struct radeon_device *rdev, | |
760 | int format, int w, int h, int pitch, | |
9bb7703c | 761 | u64 gpu_addr, u32 size); |
8eec9d6f IH |
762 | void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, |
763 | int x2, int y2); | |
764 | void (*draw_auto)(struct radeon_device *rdev); | |
765 | void (*set_default_state)(struct radeon_device *rdev); | |
766 | }; | |
767 | ||
3ce0a23d | 768 | struct r600_blit { |
4c788679 | 769 | struct radeon_bo *shader_obj; |
8eec9d6f IH |
770 | struct r600_blit_cp_primitives primitives; |
771 | int max_dim; | |
772 | int ring_size_common; | |
773 | int ring_size_per_loop; | |
3ce0a23d JG |
774 | u64 shader_gpu_addr; |
775 | u32 vs_offset, ps_offset; | |
776 | u32 state_offset; | |
777 | u32 state_len; | |
3ce0a23d JG |
778 | }; |
779 | ||
347e7592 AD |
780 | /* |
781 | * SI RLC stuff | |
782 | */ | |
783 | struct si_rlc { | |
784 | /* for power gating */ | |
785 | struct radeon_bo *save_restore_obj; | |
786 | uint64_t save_restore_gpu_addr; | |
787 | /* for clear state */ | |
788 | struct radeon_bo *clear_state_obj; | |
789 | uint64_t clear_state_gpu_addr; | |
790 | }; | |
791 | ||
69e130a6 | 792 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
4bf3dd92 CK |
793 | struct radeon_ib *ib, struct radeon_vm *vm, |
794 | unsigned size); | |
f2e39221 | 795 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
43f1214a | 796 | void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence); |
4ef72566 CK |
797 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
798 | struct radeon_ib *const_ib); | |
771fe6b9 JG |
799 | int radeon_ib_pool_init(struct radeon_device *rdev); |
800 | void radeon_ib_pool_fini(struct radeon_device *rdev); | |
7bd560e8 | 801 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
771fe6b9 | 802 | /* Ring access between begin & end cannot sleep */ |
89d35807 AD |
803 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
804 | struct radeon_ring *ring); | |
e32eb50d CK |
805 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
806 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); | |
807 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); | |
808 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); | |
809 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); | |
d6999bc7 | 810 | void radeon_ring_undo(struct radeon_ring *ring); |
e32eb50d CK |
811 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
812 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); | |
7b9ef16b | 813 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); |
069211e5 CK |
814 | void radeon_ring_lockup_update(struct radeon_ring *ring); |
815 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); | |
55d7c221 CK |
816 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
817 | uint32_t **data); | |
818 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, | |
819 | unsigned size, uint32_t *data); | |
e32eb50d | 820 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
78c5560a AD |
821 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
822 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); | |
e32eb50d | 823 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
771fe6b9 JG |
824 | |
825 | ||
4d75658b AD |
826 | /* r600 async dma */ |
827 | void r600_dma_stop(struct radeon_device *rdev); | |
828 | int r600_dma_resume(struct radeon_device *rdev); | |
829 | void r600_dma_fini(struct radeon_device *rdev); | |
830 | ||
8c5fd7ef AD |
831 | void cayman_dma_stop(struct radeon_device *rdev); |
832 | int cayman_dma_resume(struct radeon_device *rdev); | |
833 | void cayman_dma_fini(struct radeon_device *rdev); | |
834 | ||
771fe6b9 JG |
835 | /* |
836 | * CS. | |
837 | */ | |
838 | struct radeon_cs_reloc { | |
839 | struct drm_gem_object *gobj; | |
4c788679 JG |
840 | struct radeon_bo *robj; |
841 | struct radeon_bo_list lobj; | |
771fe6b9 JG |
842 | uint32_t handle; |
843 | uint32_t flags; | |
844 | }; | |
845 | ||
846 | struct radeon_cs_chunk { | |
847 | uint32_t chunk_id; | |
848 | uint32_t length_dw; | |
721604a1 JG |
849 | int kpage_idx[2]; |
850 | uint32_t *kpage[2]; | |
771fe6b9 | 851 | uint32_t *kdata; |
721604a1 JG |
852 | void __user *user_ptr; |
853 | int last_copied_page; | |
854 | int last_page_index; | |
771fe6b9 JG |
855 | }; |
856 | ||
857 | struct radeon_cs_parser { | |
c8c15ff1 | 858 | struct device *dev; |
771fe6b9 JG |
859 | struct radeon_device *rdev; |
860 | struct drm_file *filp; | |
861 | /* chunks */ | |
862 | unsigned nchunks; | |
863 | struct radeon_cs_chunk *chunks; | |
864 | uint64_t *chunks_array; | |
865 | /* IB */ | |
866 | unsigned idx; | |
867 | /* relocations */ | |
868 | unsigned nrelocs; | |
869 | struct radeon_cs_reloc *relocs; | |
870 | struct radeon_cs_reloc **relocs_ptr; | |
871 | struct list_head validated; | |
cf4ccd01 | 872 | unsigned dma_reloc_idx; |
771fe6b9 JG |
873 | /* indices of various chunks */ |
874 | int chunk_ib_idx; | |
875 | int chunk_relocs_idx; | |
721604a1 | 876 | int chunk_flags_idx; |
dfcf5f36 | 877 | int chunk_const_ib_idx; |
f2e39221 JG |
878 | struct radeon_ib ib; |
879 | struct radeon_ib const_ib; | |
771fe6b9 | 880 | void *track; |
3ce0a23d | 881 | unsigned family; |
e70f224c | 882 | int parser_error; |
721604a1 JG |
883 | u32 cs_flags; |
884 | u32 ring; | |
885 | s32 priority; | |
771fe6b9 JG |
886 | }; |
887 | ||
513bcb46 | 888 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
ce580fab | 889 | extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); |
513bcb46 | 890 | |
771fe6b9 JG |
891 | struct radeon_cs_packet { |
892 | unsigned idx; | |
893 | unsigned type; | |
894 | unsigned reg; | |
895 | unsigned opcode; | |
896 | int count; | |
897 | unsigned one_reg_wr; | |
898 | }; | |
899 | ||
900 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, | |
901 | struct radeon_cs_packet *pkt, | |
902 | unsigned idx, unsigned reg); | |
903 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, | |
904 | struct radeon_cs_packet *pkt); | |
905 | ||
906 | ||
907 | /* | |
908 | * AGP | |
909 | */ | |
910 | int radeon_agp_init(struct radeon_device *rdev); | |
0ebf1717 | 911 | void radeon_agp_resume(struct radeon_device *rdev); |
10b06122 | 912 | void radeon_agp_suspend(struct radeon_device *rdev); |
771fe6b9 JG |
913 | void radeon_agp_fini(struct radeon_device *rdev); |
914 | ||
915 | ||
916 | /* | |
917 | * Writeback | |
918 | */ | |
919 | struct radeon_wb { | |
4c788679 | 920 | struct radeon_bo *wb_obj; |
771fe6b9 JG |
921 | volatile uint32_t *wb; |
922 | uint64_t gpu_addr; | |
724c80e1 | 923 | bool enabled; |
d0f8a854 | 924 | bool use_event; |
771fe6b9 JG |
925 | }; |
926 | ||
724c80e1 | 927 | #define RADEON_WB_SCRATCH_OFFSET 0 |
89d35807 | 928 | #define RADEON_WB_RING0_NEXT_RPTR 256 |
724c80e1 | 929 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
0c88a02e AD |
930 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
931 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 | |
4d75658b | 932 | #define R600_WB_DMA_RPTR_OFFSET 1792 |
724c80e1 | 933 | #define R600_WB_IH_WPTR_OFFSET 2048 |
f60cbd11 | 934 | #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 |
f2ba57b5 | 935 | #define R600_WB_UVD_RPTR_OFFSET 2560 |
d0f8a854 | 936 | #define R600_WB_EVENT_OFFSET 3072 |
724c80e1 | 937 | |
c93bb85b JG |
938 | /** |
939 | * struct radeon_pm - power management datas | |
940 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) | |
941 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) | |
942 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) | |
943 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) | |
944 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) | |
945 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) | |
946 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) | |
947 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) | |
948 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) | |
25985edc | 949 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
c93bb85b JG |
950 | * @needed_bandwidth: current bandwidth needs |
951 | * | |
952 | * It keeps track of various data needed to take powermanagement decision. | |
25985edc | 953 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
c93bb85b JG |
954 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
955 | * (type of memory, bus size, efficiency, ...) | |
956 | */ | |
ce8f5370 AD |
957 | |
958 | enum radeon_pm_method { | |
959 | PM_METHOD_PROFILE, | |
960 | PM_METHOD_DYNPM, | |
961 | }; | |
962 | ||
963 | enum radeon_dynpm_state { | |
964 | DYNPM_STATE_DISABLED, | |
965 | DYNPM_STATE_MINIMUM, | |
966 | DYNPM_STATE_PAUSED, | |
3f53eb6f RW |
967 | DYNPM_STATE_ACTIVE, |
968 | DYNPM_STATE_SUSPENDED, | |
c913e23a | 969 | }; |
ce8f5370 AD |
970 | enum radeon_dynpm_action { |
971 | DYNPM_ACTION_NONE, | |
972 | DYNPM_ACTION_MINIMUM, | |
973 | DYNPM_ACTION_DOWNCLOCK, | |
974 | DYNPM_ACTION_UPCLOCK, | |
975 | DYNPM_ACTION_DEFAULT | |
c913e23a | 976 | }; |
56278a8e AD |
977 | |
978 | enum radeon_voltage_type { | |
979 | VOLTAGE_NONE = 0, | |
980 | VOLTAGE_GPIO, | |
981 | VOLTAGE_VDDC, | |
982 | VOLTAGE_SW | |
983 | }; | |
984 | ||
0ec0e74f AD |
985 | enum radeon_pm_state_type { |
986 | POWER_STATE_TYPE_DEFAULT, | |
987 | POWER_STATE_TYPE_POWERSAVE, | |
988 | POWER_STATE_TYPE_BATTERY, | |
989 | POWER_STATE_TYPE_BALANCED, | |
990 | POWER_STATE_TYPE_PERFORMANCE, | |
991 | }; | |
992 | ||
ce8f5370 AD |
993 | enum radeon_pm_profile_type { |
994 | PM_PROFILE_DEFAULT, | |
995 | PM_PROFILE_AUTO, | |
996 | PM_PROFILE_LOW, | |
c9e75b21 | 997 | PM_PROFILE_MID, |
ce8f5370 AD |
998 | PM_PROFILE_HIGH, |
999 | }; | |
1000 | ||
1001 | #define PM_PROFILE_DEFAULT_IDX 0 | |
1002 | #define PM_PROFILE_LOW_SH_IDX 1 | |
c9e75b21 AD |
1003 | #define PM_PROFILE_MID_SH_IDX 2 |
1004 | #define PM_PROFILE_HIGH_SH_IDX 3 | |
1005 | #define PM_PROFILE_LOW_MH_IDX 4 | |
1006 | #define PM_PROFILE_MID_MH_IDX 5 | |
1007 | #define PM_PROFILE_HIGH_MH_IDX 6 | |
1008 | #define PM_PROFILE_MAX 7 | |
ce8f5370 AD |
1009 | |
1010 | struct radeon_pm_profile { | |
1011 | int dpms_off_ps_idx; | |
1012 | int dpms_on_ps_idx; | |
1013 | int dpms_off_cm_idx; | |
1014 | int dpms_on_cm_idx; | |
516d0e46 AD |
1015 | }; |
1016 | ||
21a8122a AD |
1017 | enum radeon_int_thermal_type { |
1018 | THERMAL_TYPE_NONE, | |
1019 | THERMAL_TYPE_RV6XX, | |
1020 | THERMAL_TYPE_RV770, | |
1021 | THERMAL_TYPE_EVERGREEN, | |
e33df25f | 1022 | THERMAL_TYPE_SUMO, |
4fddba1f | 1023 | THERMAL_TYPE_NI, |
14607d08 | 1024 | THERMAL_TYPE_SI, |
21a8122a AD |
1025 | }; |
1026 | ||
56278a8e AD |
1027 | struct radeon_voltage { |
1028 | enum radeon_voltage_type type; | |
1029 | /* gpio voltage */ | |
1030 | struct radeon_gpio_rec gpio; | |
1031 | u32 delay; /* delay in usec from voltage drop to sclk change */ | |
1032 | bool active_high; /* voltage drop is active when bit is high */ | |
1033 | /* VDDC voltage */ | |
1034 | u8 vddc_id; /* index into vddc voltage table */ | |
1035 | u8 vddci_id; /* index into vddci voltage table */ | |
1036 | bool vddci_enabled; | |
1037 | /* r6xx+ sw */ | |
2feea49a AD |
1038 | u16 voltage; |
1039 | /* evergreen+ vddci */ | |
1040 | u16 vddci; | |
56278a8e AD |
1041 | }; |
1042 | ||
d7311171 AD |
1043 | /* clock mode flags */ |
1044 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) | |
1045 | ||
56278a8e AD |
1046 | struct radeon_pm_clock_info { |
1047 | /* memory clock */ | |
1048 | u32 mclk; | |
1049 | /* engine clock */ | |
1050 | u32 sclk; | |
1051 | /* voltage info */ | |
1052 | struct radeon_voltage voltage; | |
d7311171 | 1053 | /* standardized clock flags */ |
56278a8e AD |
1054 | u32 flags; |
1055 | }; | |
1056 | ||
a48b9b4e | 1057 | /* state flags */ |
d7311171 | 1058 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
a48b9b4e | 1059 | |
56278a8e | 1060 | struct radeon_power_state { |
0ec0e74f | 1061 | enum radeon_pm_state_type type; |
8f3f1c9a | 1062 | struct radeon_pm_clock_info *clock_info; |
56278a8e AD |
1063 | /* number of valid clock modes in this power state */ |
1064 | int num_clock_modes; | |
56278a8e | 1065 | struct radeon_pm_clock_info *default_clock_mode; |
a48b9b4e AD |
1066 | /* standardized state flags */ |
1067 | u32 flags; | |
79daedc9 AD |
1068 | u32 misc; /* vbios specific flags */ |
1069 | u32 misc2; /* vbios specific flags */ | |
1070 | int pcie_lanes; /* pcie lanes */ | |
56278a8e AD |
1071 | }; |
1072 | ||
27459324 RM |
1073 | /* |
1074 | * Some modes are overclocked by very low value, accept them | |
1075 | */ | |
1076 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ | |
1077 | ||
c93bb85b | 1078 | struct radeon_pm { |
c913e23a | 1079 | struct mutex mutex; |
db7fce39 CK |
1080 | /* write locked while reprogramming mclk */ |
1081 | struct rw_semaphore mclk_lock; | |
a48b9b4e AD |
1082 | u32 active_crtcs; |
1083 | int active_crtc_count; | |
c913e23a | 1084 | int req_vblank; |
839461d3 | 1085 | bool vblank_sync; |
c93bb85b JG |
1086 | fixed20_12 max_bandwidth; |
1087 | fixed20_12 igp_sideport_mclk; | |
1088 | fixed20_12 igp_system_mclk; | |
1089 | fixed20_12 igp_ht_link_clk; | |
1090 | fixed20_12 igp_ht_link_width; | |
1091 | fixed20_12 k8_bandwidth; | |
1092 | fixed20_12 sideport_bandwidth; | |
1093 | fixed20_12 ht_bandwidth; | |
1094 | fixed20_12 core_bandwidth; | |
1095 | fixed20_12 sclk; | |
f47299c5 | 1096 | fixed20_12 mclk; |
c93bb85b | 1097 | fixed20_12 needed_bandwidth; |
0975b162 | 1098 | struct radeon_power_state *power_state; |
56278a8e AD |
1099 | /* number of valid power states */ |
1100 | int num_power_states; | |
a48b9b4e AD |
1101 | int current_power_state_index; |
1102 | int current_clock_mode_index; | |
1103 | int requested_power_state_index; | |
1104 | int requested_clock_mode_index; | |
1105 | int default_power_state_index; | |
1106 | u32 current_sclk; | |
1107 | u32 current_mclk; | |
2feea49a AD |
1108 | u16 current_vddc; |
1109 | u16 current_vddci; | |
9ace9f7b AD |
1110 | u32 default_sclk; |
1111 | u32 default_mclk; | |
2feea49a AD |
1112 | u16 default_vddc; |
1113 | u16 default_vddci; | |
29fb52ca | 1114 | struct radeon_i2c_chan *i2c_bus; |
ce8f5370 AD |
1115 | /* selected pm method */ |
1116 | enum radeon_pm_method pm_method; | |
1117 | /* dynpm power management */ | |
1118 | struct delayed_work dynpm_idle_work; | |
1119 | enum radeon_dynpm_state dynpm_state; | |
1120 | enum radeon_dynpm_action dynpm_planned_action; | |
1121 | unsigned long dynpm_action_timeout; | |
1122 | bool dynpm_can_upclock; | |
1123 | bool dynpm_can_downclock; | |
1124 | /* profile-based power management */ | |
1125 | enum radeon_pm_profile_type profile; | |
1126 | int profile_index; | |
1127 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; | |
21a8122a AD |
1128 | /* internal thermal controller on rv6xx+ */ |
1129 | enum radeon_int_thermal_type int_thermal_type; | |
1130 | struct device *int_hwmon_dev; | |
c93bb85b JG |
1131 | }; |
1132 | ||
a4c9e2ee AD |
1133 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
1134 | enum radeon_pm_state_type ps_type, | |
1135 | int instance); | |
f2ba57b5 CK |
1136 | /* |
1137 | * UVD | |
1138 | */ | |
1139 | #define RADEON_MAX_UVD_HANDLES 10 | |
1140 | #define RADEON_UVD_STACK_SIZE (1024*1024) | |
1141 | #define RADEON_UVD_HEAP_SIZE (1024*1024) | |
1142 | ||
1143 | struct radeon_uvd { | |
1144 | struct radeon_bo *vcpu_bo; | |
1145 | void *cpu_addr; | |
1146 | uint64_t gpu_addr; | |
1147 | atomic_t handles[RADEON_MAX_UVD_HANDLES]; | |
1148 | struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; | |
55b51c88 | 1149 | struct delayed_work idle_work; |
f2ba57b5 CK |
1150 | }; |
1151 | ||
1152 | int radeon_uvd_init(struct radeon_device *rdev); | |
1153 | void radeon_uvd_fini(struct radeon_device *rdev); | |
1154 | int radeon_uvd_suspend(struct radeon_device *rdev); | |
1155 | int radeon_uvd_resume(struct radeon_device *rdev); | |
1156 | int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, | |
1157 | uint32_t handle, struct radeon_fence **fence); | |
1158 | int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, | |
1159 | uint32_t handle, struct radeon_fence **fence); | |
1160 | void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo); | |
1161 | void radeon_uvd_free_handles(struct radeon_device *rdev, | |
1162 | struct drm_file *filp); | |
1163 | int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); | |
55b51c88 | 1164 | void radeon_uvd_note_usage(struct radeon_device *rdev); |
facd112d CK |
1165 | int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, |
1166 | unsigned vclk, unsigned dclk, | |
1167 | unsigned vco_min, unsigned vco_max, | |
1168 | unsigned fb_factor, unsigned fb_mask, | |
1169 | unsigned pd_min, unsigned pd_max, | |
1170 | unsigned pd_even, | |
1171 | unsigned *optimal_fb_div, | |
1172 | unsigned *optimal_vclk_div, | |
1173 | unsigned *optimal_dclk_div); | |
1174 | int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, | |
1175 | unsigned cg_upll_func_cntl); | |
771fe6b9 | 1176 | |
a92553ab | 1177 | struct r600_audio { |
a92553ab RM |
1178 | int channels; |
1179 | int rate; | |
1180 | int bits_per_sample; | |
1181 | u8 status_bits; | |
1182 | u8 category_code; | |
1183 | }; | |
1184 | ||
771fe6b9 JG |
1185 | /* |
1186 | * Benchmarking | |
1187 | */ | |
638dd7db | 1188 | void radeon_benchmark(struct radeon_device *rdev, int test_number); |
771fe6b9 JG |
1189 | |
1190 | ||
ecc0b326 MD |
1191 | /* |
1192 | * Testing | |
1193 | */ | |
1194 | void radeon_test_moves(struct radeon_device *rdev); | |
60a7e396 | 1195 | void radeon_test_ring_sync(struct radeon_device *rdev, |
e32eb50d CK |
1196 | struct radeon_ring *cpA, |
1197 | struct radeon_ring *cpB); | |
60a7e396 | 1198 | void radeon_test_syncing(struct radeon_device *rdev); |
ecc0b326 MD |
1199 | |
1200 | ||
771fe6b9 JG |
1201 | /* |
1202 | * Debugfs | |
1203 | */ | |
4d8bf9ae CK |
1204 | struct radeon_debugfs { |
1205 | struct drm_info_list *files; | |
1206 | unsigned num_files; | |
1207 | }; | |
1208 | ||
771fe6b9 JG |
1209 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
1210 | struct drm_info_list *files, | |
1211 | unsigned nfiles); | |
1212 | int radeon_debugfs_fence_init(struct radeon_device *rdev); | |
771fe6b9 JG |
1213 | |
1214 | ||
1215 | /* | |
1216 | * ASIC specific functions. | |
1217 | */ | |
1218 | struct radeon_asic { | |
068a117c | 1219 | int (*init)(struct radeon_device *rdev); |
3ce0a23d JG |
1220 | void (*fini)(struct radeon_device *rdev); |
1221 | int (*resume)(struct radeon_device *rdev); | |
1222 | int (*suspend)(struct radeon_device *rdev); | |
28d52043 | 1223 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
a2d07b74 | 1224 | int (*asic_reset)(struct radeon_device *rdev); |
54e88e06 AD |
1225 | /* ioctl hw specific callback. Some hw might want to perform special |
1226 | * operation on specific ioctl. For instance on wait idle some hw | |
1227 | * might want to perform and HDP flush through MMIO as it seems that | |
1228 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed | |
1229 | * through ring. | |
1230 | */ | |
1231 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); | |
1232 | /* check if 3D engine is idle */ | |
1233 | bool (*gui_idle)(struct radeon_device *rdev); | |
1234 | /* wait for mc_idle */ | |
1235 | int (*mc_wait_for_idle)(struct radeon_device *rdev); | |
454d2e2a AD |
1236 | /* get the reference clock */ |
1237 | u32 (*get_xclk)(struct radeon_device *rdev); | |
d0418894 AD |
1238 | /* get the gpu clock counter */ |
1239 | uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); | |
54e88e06 | 1240 | /* gart */ |
c5b3b850 AD |
1241 | struct { |
1242 | void (*tlb_flush)(struct radeon_device *rdev); | |
1243 | int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); | |
1244 | } gart; | |
05b07147 CK |
1245 | struct { |
1246 | int (*init)(struct radeon_device *rdev); | |
1247 | void (*fini)(struct radeon_device *rdev); | |
2a6f1abb CK |
1248 | |
1249 | u32 pt_ring_index; | |
43f1214a AD |
1250 | void (*set_page)(struct radeon_device *rdev, |
1251 | struct radeon_ib *ib, | |
1252 | uint64_t pe, | |
dce34bfd CK |
1253 | uint64_t addr, unsigned count, |
1254 | uint32_t incr, uint32_t flags); | |
05b07147 | 1255 | } vm; |
54e88e06 | 1256 | /* ring specific callbacks */ |
4c87bc26 CK |
1257 | struct { |
1258 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); | |
721604a1 | 1259 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); |
4c87bc26 | 1260 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); |
e32eb50d | 1261 | void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
4c87bc26 | 1262 | struct radeon_semaphore *semaphore, bool emit_wait); |
eb0c19c5 | 1263 | int (*cs_parse)(struct radeon_cs_parser *p); |
f712812e AD |
1264 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); |
1265 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); | |
1266 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); | |
312c4a8c | 1267 | bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); |
498522b4 | 1268 | void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
4c87bc26 | 1269 | } ring[RADEON_NUM_RINGS]; |
54e88e06 | 1270 | /* irqs */ |
b35ea4ab AD |
1271 | struct { |
1272 | int (*set)(struct radeon_device *rdev); | |
1273 | int (*process)(struct radeon_device *rdev); | |
1274 | } irq; | |
54e88e06 | 1275 | /* displays */ |
c79a49ca AD |
1276 | struct { |
1277 | /* display watermarks */ | |
1278 | void (*bandwidth_update)(struct radeon_device *rdev); | |
1279 | /* get frame count */ | |
1280 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); | |
1281 | /* wait for vblank */ | |
1282 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); | |
37e9b6a6 AD |
1283 | /* set backlight level */ |
1284 | void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); | |
6d92f81d AD |
1285 | /* get backlight level */ |
1286 | u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); | |
a973bea1 AD |
1287 | /* audio callbacks */ |
1288 | void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); | |
1289 | void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); | |
c79a49ca | 1290 | } display; |
54e88e06 | 1291 | /* copy functions for bo handling */ |
27cd7769 AD |
1292 | struct { |
1293 | int (*blit)(struct radeon_device *rdev, | |
1294 | uint64_t src_offset, | |
1295 | uint64_t dst_offset, | |
1296 | unsigned num_gpu_pages, | |
876dc9f3 | 1297 | struct radeon_fence **fence); |
27cd7769 AD |
1298 | u32 blit_ring_index; |
1299 | int (*dma)(struct radeon_device *rdev, | |
1300 | uint64_t src_offset, | |
1301 | uint64_t dst_offset, | |
1302 | unsigned num_gpu_pages, | |
876dc9f3 | 1303 | struct radeon_fence **fence); |
27cd7769 AD |
1304 | u32 dma_ring_index; |
1305 | /* method used for bo copy */ | |
1306 | int (*copy)(struct radeon_device *rdev, | |
1307 | uint64_t src_offset, | |
1308 | uint64_t dst_offset, | |
1309 | unsigned num_gpu_pages, | |
876dc9f3 | 1310 | struct radeon_fence **fence); |
27cd7769 AD |
1311 | /* ring used for bo copies */ |
1312 | u32 copy_ring_index; | |
1313 | } copy; | |
54e88e06 | 1314 | /* surfaces */ |
9e6f3d02 AD |
1315 | struct { |
1316 | int (*set_reg)(struct radeon_device *rdev, int reg, | |
1317 | uint32_t tiling_flags, uint32_t pitch, | |
1318 | uint32_t offset, uint32_t obj_size); | |
1319 | void (*clear_reg)(struct radeon_device *rdev, int reg); | |
1320 | } surface; | |
54e88e06 | 1321 | /* hotplug detect */ |
901ea57d AD |
1322 | struct { |
1323 | void (*init)(struct radeon_device *rdev); | |
1324 | void (*fini)(struct radeon_device *rdev); | |
1325 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
1326 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
1327 | } hpd; | |
ce8f5370 | 1328 | /* power management */ |
a02fa397 AD |
1329 | struct { |
1330 | void (*misc)(struct radeon_device *rdev); | |
1331 | void (*prepare)(struct radeon_device *rdev); | |
1332 | void (*finish)(struct radeon_device *rdev); | |
1333 | void (*init_profile)(struct radeon_device *rdev); | |
1334 | void (*get_dynpm_state)(struct radeon_device *rdev); | |
798bcf73 AD |
1335 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1336 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); | |
1337 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); | |
1338 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); | |
1339 | int (*get_pcie_lanes)(struct radeon_device *rdev); | |
1340 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); | |
1341 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); | |
73afc70d | 1342 | int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); |
a02fa397 | 1343 | } pm; |
6f34be50 | 1344 | /* pageflipping */ |
0f9e006c AD |
1345 | struct { |
1346 | void (*pre_page_flip)(struct radeon_device *rdev, int crtc); | |
1347 | u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
1348 | void (*post_page_flip)(struct radeon_device *rdev, int crtc); | |
1349 | } pflip; | |
771fe6b9 JG |
1350 | }; |
1351 | ||
21f9a437 JG |
1352 | /* |
1353 | * Asic structures | |
1354 | */ | |
551ebd83 | 1355 | struct r100_asic { |
225758d8 JG |
1356 | const unsigned *reg_safe_bm; |
1357 | unsigned reg_safe_bm_size; | |
1358 | u32 hdp_cntl; | |
551ebd83 DA |
1359 | }; |
1360 | ||
21f9a437 | 1361 | struct r300_asic { |
225758d8 JG |
1362 | const unsigned *reg_safe_bm; |
1363 | unsigned reg_safe_bm_size; | |
1364 | u32 resync_scratch; | |
1365 | u32 hdp_cntl; | |
21f9a437 JG |
1366 | }; |
1367 | ||
1368 | struct r600_asic { | |
225758d8 JG |
1369 | unsigned max_pipes; |
1370 | unsigned max_tile_pipes; | |
1371 | unsigned max_simds; | |
1372 | unsigned max_backends; | |
1373 | unsigned max_gprs; | |
1374 | unsigned max_threads; | |
1375 | unsigned max_stack_entries; | |
1376 | unsigned max_hw_contexts; | |
1377 | unsigned max_gs_threads; | |
1378 | unsigned sx_max_export_size; | |
1379 | unsigned sx_max_export_pos_size; | |
1380 | unsigned sx_max_export_smx_size; | |
1381 | unsigned sq_num_cf_insts; | |
1382 | unsigned tiling_nbanks; | |
1383 | unsigned tiling_npipes; | |
1384 | unsigned tiling_group_size; | |
e7aeeba6 | 1385 | unsigned tile_config; |
e55b9422 | 1386 | unsigned backend_map; |
21f9a437 JG |
1387 | }; |
1388 | ||
1389 | struct rv770_asic { | |
225758d8 JG |
1390 | unsigned max_pipes; |
1391 | unsigned max_tile_pipes; | |
1392 | unsigned max_simds; | |
1393 | unsigned max_backends; | |
1394 | unsigned max_gprs; | |
1395 | unsigned max_threads; | |
1396 | unsigned max_stack_entries; | |
1397 | unsigned max_hw_contexts; | |
1398 | unsigned max_gs_threads; | |
1399 | unsigned sx_max_export_size; | |
1400 | unsigned sx_max_export_pos_size; | |
1401 | unsigned sx_max_export_smx_size; | |
1402 | unsigned sq_num_cf_insts; | |
1403 | unsigned sx_num_of_sets; | |
1404 | unsigned sc_prim_fifo_size; | |
1405 | unsigned sc_hiz_tile_fifo_size; | |
1406 | unsigned sc_earlyz_tile_fifo_fize; | |
1407 | unsigned tiling_nbanks; | |
1408 | unsigned tiling_npipes; | |
1409 | unsigned tiling_group_size; | |
e7aeeba6 | 1410 | unsigned tile_config; |
e55b9422 | 1411 | unsigned backend_map; |
21f9a437 JG |
1412 | }; |
1413 | ||
32fcdbf4 AD |
1414 | struct evergreen_asic { |
1415 | unsigned num_ses; | |
1416 | unsigned max_pipes; | |
1417 | unsigned max_tile_pipes; | |
1418 | unsigned max_simds; | |
1419 | unsigned max_backends; | |
1420 | unsigned max_gprs; | |
1421 | unsigned max_threads; | |
1422 | unsigned max_stack_entries; | |
1423 | unsigned max_hw_contexts; | |
1424 | unsigned max_gs_threads; | |
1425 | unsigned sx_max_export_size; | |
1426 | unsigned sx_max_export_pos_size; | |
1427 | unsigned sx_max_export_smx_size; | |
1428 | unsigned sq_num_cf_insts; | |
1429 | unsigned sx_num_of_sets; | |
1430 | unsigned sc_prim_fifo_size; | |
1431 | unsigned sc_hiz_tile_fifo_size; | |
1432 | unsigned sc_earlyz_tile_fifo_size; | |
1433 | unsigned tiling_nbanks; | |
1434 | unsigned tiling_npipes; | |
1435 | unsigned tiling_group_size; | |
e7aeeba6 | 1436 | unsigned tile_config; |
e55b9422 | 1437 | unsigned backend_map; |
32fcdbf4 AD |
1438 | }; |
1439 | ||
fecf1d07 AD |
1440 | struct cayman_asic { |
1441 | unsigned max_shader_engines; | |
1442 | unsigned max_pipes_per_simd; | |
1443 | unsigned max_tile_pipes; | |
1444 | unsigned max_simds_per_se; | |
1445 | unsigned max_backends_per_se; | |
1446 | unsigned max_texture_channel_caches; | |
1447 | unsigned max_gprs; | |
1448 | unsigned max_threads; | |
1449 | unsigned max_gs_threads; | |
1450 | unsigned max_stack_entries; | |
1451 | unsigned sx_num_of_sets; | |
1452 | unsigned sx_max_export_size; | |
1453 | unsigned sx_max_export_pos_size; | |
1454 | unsigned sx_max_export_smx_size; | |
1455 | unsigned max_hw_contexts; | |
1456 | unsigned sq_num_cf_insts; | |
1457 | unsigned sc_prim_fifo_size; | |
1458 | unsigned sc_hiz_tile_fifo_size; | |
1459 | unsigned sc_earlyz_tile_fifo_size; | |
1460 | ||
1461 | unsigned num_shader_engines; | |
1462 | unsigned num_shader_pipes_per_simd; | |
1463 | unsigned num_tile_pipes; | |
1464 | unsigned num_simds_per_se; | |
1465 | unsigned num_backends_per_se; | |
1466 | unsigned backend_disable_mask_per_asic; | |
1467 | unsigned backend_map; | |
1468 | unsigned num_texture_channel_caches; | |
1469 | unsigned mem_max_burst_length_bytes; | |
1470 | unsigned mem_row_size_in_kb; | |
1471 | unsigned shader_engine_tile_size; | |
1472 | unsigned num_gpus; | |
1473 | unsigned multi_gpu_tile_size; | |
1474 | ||
1475 | unsigned tile_config; | |
fecf1d07 AD |
1476 | }; |
1477 | ||
0a96d72b AD |
1478 | struct si_asic { |
1479 | unsigned max_shader_engines; | |
0a96d72b | 1480 | unsigned max_tile_pipes; |
1a8ca750 AD |
1481 | unsigned max_cu_per_sh; |
1482 | unsigned max_sh_per_se; | |
0a96d72b AD |
1483 | unsigned max_backends_per_se; |
1484 | unsigned max_texture_channel_caches; | |
1485 | unsigned max_gprs; | |
1486 | unsigned max_gs_threads; | |
1487 | unsigned max_hw_contexts; | |
1488 | unsigned sc_prim_fifo_size_frontend; | |
1489 | unsigned sc_prim_fifo_size_backend; | |
1490 | unsigned sc_hiz_tile_fifo_size; | |
1491 | unsigned sc_earlyz_tile_fifo_size; | |
1492 | ||
0a96d72b AD |
1493 | unsigned num_tile_pipes; |
1494 | unsigned num_backends_per_se; | |
1495 | unsigned backend_disable_mask_per_asic; | |
1496 | unsigned backend_map; | |
1497 | unsigned num_texture_channel_caches; | |
1498 | unsigned mem_max_burst_length_bytes; | |
1499 | unsigned mem_row_size_in_kb; | |
1500 | unsigned shader_engine_tile_size; | |
1501 | unsigned num_gpus; | |
1502 | unsigned multi_gpu_tile_size; | |
1503 | ||
1504 | unsigned tile_config; | |
64d7b8be | 1505 | uint32_t tile_mode_array[32]; |
0a96d72b AD |
1506 | }; |
1507 | ||
8cc1a532 AD |
1508 | struct cik_asic { |
1509 | unsigned max_shader_engines; | |
1510 | unsigned max_tile_pipes; | |
1511 | unsigned max_cu_per_sh; | |
1512 | unsigned max_sh_per_se; | |
1513 | unsigned max_backends_per_se; | |
1514 | unsigned max_texture_channel_caches; | |
1515 | unsigned max_gprs; | |
1516 | unsigned max_gs_threads; | |
1517 | unsigned max_hw_contexts; | |
1518 | unsigned sc_prim_fifo_size_frontend; | |
1519 | unsigned sc_prim_fifo_size_backend; | |
1520 | unsigned sc_hiz_tile_fifo_size; | |
1521 | unsigned sc_earlyz_tile_fifo_size; | |
1522 | ||
1523 | unsigned num_tile_pipes; | |
1524 | unsigned num_backends_per_se; | |
1525 | unsigned backend_disable_mask_per_asic; | |
1526 | unsigned backend_map; | |
1527 | unsigned num_texture_channel_caches; | |
1528 | unsigned mem_max_burst_length_bytes; | |
1529 | unsigned mem_row_size_in_kb; | |
1530 | unsigned shader_engine_tile_size; | |
1531 | unsigned num_gpus; | |
1532 | unsigned multi_gpu_tile_size; | |
1533 | ||
1534 | unsigned tile_config; | |
1535 | }; | |
1536 | ||
068a117c JG |
1537 | union radeon_asic_config { |
1538 | struct r300_asic r300; | |
551ebd83 | 1539 | struct r100_asic r100; |
3ce0a23d JG |
1540 | struct r600_asic r600; |
1541 | struct rv770_asic rv770; | |
32fcdbf4 | 1542 | struct evergreen_asic evergreen; |
fecf1d07 | 1543 | struct cayman_asic cayman; |
0a96d72b | 1544 | struct si_asic si; |
8cc1a532 | 1545 | struct cik_asic cik; |
068a117c JG |
1546 | }; |
1547 | ||
0a10c851 DV |
1548 | /* |
1549 | * asic initizalization from radeon_asic.c | |
1550 | */ | |
1551 | void radeon_agp_disable(struct radeon_device *rdev); | |
1552 | int radeon_asic_init(struct radeon_device *rdev); | |
1553 | ||
771fe6b9 JG |
1554 | |
1555 | /* | |
1556 | * IOCTL. | |
1557 | */ | |
1558 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |
1559 | struct drm_file *filp); | |
1560 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, | |
1561 | struct drm_file *filp); | |
1562 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, | |
1563 | struct drm_file *file_priv); | |
1564 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1565 | struct drm_file *file_priv); | |
1566 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1567 | struct drm_file *file_priv); | |
1568 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1569 | struct drm_file *file_priv); | |
1570 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1571 | struct drm_file *filp); | |
1572 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1573 | struct drm_file *filp); | |
1574 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1575 | struct drm_file *filp); | |
1576 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
1577 | struct drm_file *filp); | |
721604a1 JG |
1578 | int radeon_gem_va_ioctl(struct drm_device *dev, void *data, |
1579 | struct drm_file *filp); | |
771fe6b9 | 1580 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
e024e110 DA |
1581 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
1582 | struct drm_file *filp); | |
1583 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
1584 | struct drm_file *filp); | |
771fe6b9 | 1585 | |
16cdf04d AD |
1586 | /* VRAM scratch page for HDP bug, default vram page */ |
1587 | struct r600_vram_scratch { | |
87cbf8f2 AD |
1588 | struct radeon_bo *robj; |
1589 | volatile uint32_t *ptr; | |
16cdf04d | 1590 | u64 gpu_addr; |
87cbf8f2 | 1591 | }; |
771fe6b9 | 1592 | |
fd64ca8a LT |
1593 | /* |
1594 | * ACPI | |
1595 | */ | |
1596 | struct radeon_atif_notification_cfg { | |
1597 | bool enabled; | |
1598 | int command_code; | |
1599 | }; | |
1600 | ||
1601 | struct radeon_atif_notifications { | |
1602 | bool display_switch; | |
1603 | bool expansion_mode_change; | |
1604 | bool thermal_state; | |
1605 | bool forced_power_state; | |
1606 | bool system_power_state; | |
1607 | bool display_conf_change; | |
1608 | bool px_gfx_switch; | |
1609 | bool brightness_change; | |
1610 | bool dgpu_display_event; | |
1611 | }; | |
1612 | ||
1613 | struct radeon_atif_functions { | |
1614 | bool system_params; | |
1615 | bool sbios_requests; | |
1616 | bool select_active_disp; | |
1617 | bool lid_state; | |
1618 | bool get_tv_standard; | |
1619 | bool set_tv_standard; | |
1620 | bool get_panel_expansion_mode; | |
1621 | bool set_panel_expansion_mode; | |
1622 | bool temperature_change; | |
1623 | bool graphics_device_types; | |
1624 | }; | |
1625 | ||
1626 | struct radeon_atif { | |
1627 | struct radeon_atif_notifications notifications; | |
1628 | struct radeon_atif_functions functions; | |
1629 | struct radeon_atif_notification_cfg notification_cfg; | |
37e9b6a6 | 1630 | struct radeon_encoder *encoder_for_bl; |
fd64ca8a | 1631 | }; |
7a1619b9 | 1632 | |
e3a15920 AD |
1633 | struct radeon_atcs_functions { |
1634 | bool get_ext_state; | |
1635 | bool pcie_perf_req; | |
1636 | bool pcie_dev_rdy; | |
1637 | bool pcie_bus_width; | |
1638 | }; | |
1639 | ||
1640 | struct radeon_atcs { | |
1641 | struct radeon_atcs_functions functions; | |
1642 | }; | |
1643 | ||
771fe6b9 JG |
1644 | /* |
1645 | * Core structure, functions and helpers. | |
1646 | */ | |
1647 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); | |
1648 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); | |
1649 | ||
1650 | struct radeon_device { | |
9f022ddf | 1651 | struct device *dev; |
771fe6b9 JG |
1652 | struct drm_device *ddev; |
1653 | struct pci_dev *pdev; | |
dee53e7f | 1654 | struct rw_semaphore exclusive_lock; |
771fe6b9 | 1655 | /* ASIC */ |
068a117c | 1656 | union radeon_asic_config config; |
771fe6b9 JG |
1657 | enum radeon_family family; |
1658 | unsigned long flags; | |
1659 | int usec_timeout; | |
1660 | enum radeon_pll_errata pll_errata; | |
1661 | int num_gb_pipes; | |
f779b3e5 | 1662 | int num_z_pipes; |
771fe6b9 JG |
1663 | int disp_priority; |
1664 | /* BIOS */ | |
1665 | uint8_t *bios; | |
1666 | bool is_atom_bios; | |
1667 | uint16_t bios_header_start; | |
4c788679 | 1668 | struct radeon_bo *stollen_vga_memory; |
771fe6b9 | 1669 | /* Register mmio */ |
4c9bc75c DA |
1670 | resource_size_t rmmio_base; |
1671 | resource_size_t rmmio_size; | |
2c385151 DV |
1672 | /* protects concurrent MM_INDEX/DATA based register access */ |
1673 | spinlock_t mmio_idx_lock; | |
a0533fbf | 1674 | void __iomem *rmmio; |
771fe6b9 JG |
1675 | radeon_rreg_t mc_rreg; |
1676 | radeon_wreg_t mc_wreg; | |
1677 | radeon_rreg_t pll_rreg; | |
1678 | radeon_wreg_t pll_wreg; | |
de1b2898 | 1679 | uint32_t pcie_reg_mask; |
771fe6b9 JG |
1680 | radeon_rreg_t pciep_rreg; |
1681 | radeon_wreg_t pciep_wreg; | |
351a52a2 AD |
1682 | /* io port */ |
1683 | void __iomem *rio_mem; | |
1684 | resource_size_t rio_mem_size; | |
771fe6b9 JG |
1685 | struct radeon_clock clock; |
1686 | struct radeon_mc mc; | |
1687 | struct radeon_gart gart; | |
1688 | struct radeon_mode_info mode_info; | |
1689 | struct radeon_scratch scratch; | |
1690 | struct radeon_mman mman; | |
7465280c | 1691 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
0085c950 | 1692 | wait_queue_head_t fence_queue; |
d6999bc7 | 1693 | struct mutex ring_lock; |
e32eb50d | 1694 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
c507f7ef JG |
1695 | bool ib_pool_ready; |
1696 | struct radeon_sa_manager ring_tmp_bo; | |
771fe6b9 JG |
1697 | struct radeon_irq irq; |
1698 | struct radeon_asic *asic; | |
1699 | struct radeon_gem gem; | |
c93bb85b | 1700 | struct radeon_pm pm; |
f2ba57b5 | 1701 | struct radeon_uvd uvd; |
f657c2a7 | 1702 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
771fe6b9 | 1703 | struct radeon_wb wb; |
3ce0a23d | 1704 | struct radeon_dummy_page dummy_page; |
771fe6b9 JG |
1705 | bool shutdown; |
1706 | bool suspend; | |
ad49f501 | 1707 | bool need_dma32; |
733289c2 | 1708 | bool accel_working; |
a0a53aa8 | 1709 | bool fastfb_working; /* IGP feature*/ |
e024e110 | 1710 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
3ce0a23d JG |
1711 | const struct firmware *me_fw; /* all family ME firmware */ |
1712 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ | |
d8f60cfc | 1713 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
0af62b01 | 1714 | const struct firmware *mc_fw; /* NI MC firmware */ |
0f0de06c | 1715 | const struct firmware *ce_fw; /* SI CE firmware */ |
f2ba57b5 | 1716 | const struct firmware *uvd_fw; /* UVD firmware */ |
02c81327 | 1717 | const struct firmware *mec_fw; /* CIK MEC firmware */ |
3ce0a23d | 1718 | struct r600_blit r600_blit; |
16cdf04d | 1719 | struct r600_vram_scratch vram_scratch; |
3e5cb98d | 1720 | int msi_enabled; /* msi enabled */ |
d8f60cfc | 1721 | struct r600_ih ih; /* r6/700 interrupt ring */ |
347e7592 | 1722 | struct si_rlc rlc; |
d4877cf2 | 1723 | struct work_struct hotplug_work; |
f122c610 | 1724 | struct work_struct audio_work; |
8f61b34c | 1725 | struct work_struct reset_work; |
18917b60 | 1726 | int num_crtc; /* number of crtcs */ |
40bacf16 | 1727 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
3299de95 | 1728 | bool audio_enabled; |
948bee3f | 1729 | bool has_uvd; |
3299de95 | 1730 | struct r600_audio audio_status; /* audio stuff */ |
ce8f5370 | 1731 | struct notifier_block acpi_nb; |
9eba4a93 | 1732 | /* only one userspace can use Hyperz features or CMASK at a time */ |
ab9e1f59 | 1733 | struct drm_file *hyperz_filp; |
9eba4a93 | 1734 | struct drm_file *cmask_filp; |
f376b94f AD |
1735 | /* i2c buses */ |
1736 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; | |
4d8bf9ae CK |
1737 | /* debugfs */ |
1738 | struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; | |
1739 | unsigned debugfs_count; | |
721604a1 JG |
1740 | /* virtual memory */ |
1741 | struct radeon_vm_manager vm_manager; | |
6759a0a7 | 1742 | struct mutex gpu_clock_mutex; |
fd64ca8a LT |
1743 | /* ACPI interface */ |
1744 | struct radeon_atif atif; | |
e3a15920 | 1745 | struct radeon_atcs atcs; |
771fe6b9 JG |
1746 | }; |
1747 | ||
1748 | int radeon_device_init(struct radeon_device *rdev, | |
1749 | struct drm_device *ddev, | |
1750 | struct pci_dev *pdev, | |
1751 | uint32_t flags); | |
1752 | void radeon_device_fini(struct radeon_device *rdev); | |
1753 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); | |
1754 | ||
2ef9bdfe DV |
1755 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, |
1756 | bool always_indirect); | |
1757 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, | |
1758 | bool always_indirect); | |
6fcbef7a AK |
1759 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); |
1760 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
351a52a2 | 1761 | |
4c788679 JG |
1762 | /* |
1763 | * Cast helper | |
1764 | */ | |
1765 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) | |
771fe6b9 JG |
1766 | |
1767 | /* | |
1768 | * Registers read & write functions. | |
1769 | */ | |
a0533fbf BH |
1770 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
1771 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) | |
1772 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) | |
1773 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) | |
2ef9bdfe DV |
1774 | #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) |
1775 | #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) | |
1776 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) | |
1777 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) | |
1778 | #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) | |
771fe6b9 JG |
1779 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1780 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
1781 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) | |
1782 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) | |
1783 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) | |
1784 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) | |
de1b2898 DA |
1785 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
1786 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) | |
492d2b61 AD |
1787 | #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) |
1788 | #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) | |
771fe6b9 JG |
1789 | #define WREG32_P(reg, val, mask) \ |
1790 | do { \ | |
1791 | uint32_t tmp_ = RREG32(reg); \ | |
1792 | tmp_ &= (mask); \ | |
1793 | tmp_ |= ((val) & ~(mask)); \ | |
1794 | WREG32(reg, tmp_); \ | |
1795 | } while (0) | |
d5169fc4 RM |
1796 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) |
1797 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~or) | |
771fe6b9 JG |
1798 | #define WREG32_PLL_P(reg, val, mask) \ |
1799 | do { \ | |
1800 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
1801 | tmp_ &= (mask); \ | |
1802 | tmp_ |= ((val) & ~(mask)); \ | |
1803 | WREG32_PLL(reg, tmp_); \ | |
1804 | } while (0) | |
2ef9bdfe | 1805 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) |
351a52a2 AD |
1806 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
1807 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) | |
771fe6b9 | 1808 | |
de1b2898 DA |
1809 | /* |
1810 | * Indirect registers accessor | |
1811 | */ | |
1812 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | |
1813 | { | |
1814 | uint32_t r; | |
1815 | ||
1816 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1817 | r = RREG32(RADEON_PCIE_DATA); | |
1818 | return r; | |
1819 | } | |
1820 | ||
1821 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
1822 | { | |
1823 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1824 | WREG32(RADEON_PCIE_DATA, (v)); | |
1825 | } | |
1826 | ||
771fe6b9 JG |
1827 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
1828 | ||
1829 | ||
1830 | /* | |
1831 | * ASICs helpers. | |
1832 | */ | |
b995e433 DA |
1833 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
1834 | (rdev->pdev->device == 0x5969)) | |
771fe6b9 JG |
1835 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1836 | (rdev->family == CHIP_RV200) || \ | |
1837 | (rdev->family == CHIP_RS100) || \ | |
1838 | (rdev->family == CHIP_RS200) || \ | |
1839 | (rdev->family == CHIP_RV250) || \ | |
1840 | (rdev->family == CHIP_RV280) || \ | |
1841 | (rdev->family == CHIP_RS300)) | |
1842 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ | |
1843 | (rdev->family == CHIP_RV350) || \ | |
1844 | (rdev->family == CHIP_R350) || \ | |
1845 | (rdev->family == CHIP_RV380) || \ | |
1846 | (rdev->family == CHIP_R420) || \ | |
1847 | (rdev->family == CHIP_R423) || \ | |
1848 | (rdev->family == CHIP_RV410) || \ | |
1849 | (rdev->family == CHIP_RS400) || \ | |
1850 | (rdev->family == CHIP_RS480)) | |
3313e3d4 AD |
1851 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
1852 | (rdev->ddev->pdev->device == 0x9443) || \ | |
1853 | (rdev->ddev->pdev->device == 0x944B) || \ | |
1854 | (rdev->ddev->pdev->device == 0x9506) || \ | |
1855 | (rdev->ddev->pdev->device == 0x9509) || \ | |
1856 | (rdev->ddev->pdev->device == 0x950F) || \ | |
1857 | (rdev->ddev->pdev->device == 0x689C) || \ | |
1858 | (rdev->ddev->pdev->device == 0x689D)) | |
771fe6b9 | 1859 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
99999aaa AD |
1860 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
1861 | (rdev->family == CHIP_RS690) || \ | |
1862 | (rdev->family == CHIP_RS740) || \ | |
1863 | (rdev->family >= CHIP_R600)) | |
771fe6b9 JG |
1864 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
1865 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) | |
bcc1c2a1 | 1866 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
633b9164 AD |
1867 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
1868 | (rdev->flags & RADEON_IS_IGP)) | |
1fe18305 | 1869 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
8848f759 AD |
1870 | #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) |
1871 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ | |
1872 | (rdev->flags & RADEON_IS_IGP)) | |
624d3524 | 1873 | #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) |
b5d9d726 | 1874 | #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) |
e282917c | 1875 | #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) |
771fe6b9 JG |
1876 | |
1877 | /* | |
1878 | * BIOS helpers. | |
1879 | */ | |
1880 | #define RBIOS8(i) (rdev->bios[i]) | |
1881 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
1882 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
1883 | ||
1884 | int radeon_combios_init(struct radeon_device *rdev); | |
1885 | void radeon_combios_fini(struct radeon_device *rdev); | |
1886 | int radeon_atombios_init(struct radeon_device *rdev); | |
1887 | void radeon_atombios_fini(struct radeon_device *rdev); | |
1888 | ||
1889 | ||
1890 | /* | |
1891 | * RING helpers. | |
1892 | */ | |
ce580fab | 1893 | #if DRM_DEBUG_CODE == 0 |
e32eb50d | 1894 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
771fe6b9 | 1895 | { |
e32eb50d CK |
1896 | ring->ring[ring->wptr++] = v; |
1897 | ring->wptr &= ring->ptr_mask; | |
1898 | ring->count_dw--; | |
1899 | ring->ring_free_dw--; | |
771fe6b9 | 1900 | } |
ce580fab AK |
1901 | #else |
1902 | /* With debugging this is just too big to inline */ | |
e32eb50d | 1903 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v); |
ce580fab | 1904 | #endif |
771fe6b9 JG |
1905 | |
1906 | /* | |
1907 | * ASICs macro. | |
1908 | */ | |
068a117c | 1909 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
3ce0a23d JG |
1910 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1911 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) | |
1912 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) | |
eb0c19c5 | 1913 | #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) |
28d52043 | 1914 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
a2d07b74 | 1915 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
c5b3b850 AD |
1916 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
1917 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) | |
05b07147 CK |
1918 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
1919 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) | |
43f1214a | 1920 | #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags))) |
f712812e AD |
1921 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) |
1922 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) | |
1923 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) | |
4c87bc26 | 1924 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) |
721604a1 | 1925 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) |
312c4a8c | 1926 | #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) |
498522b4 | 1927 | #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) |
b35ea4ab AD |
1928 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
1929 | #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) | |
c79a49ca | 1930 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) |
37e9b6a6 | 1931 | #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) |
6d92f81d | 1932 | #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) |
a973bea1 AD |
1933 | #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) |
1934 | #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) | |
4c87bc26 CK |
1935 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) |
1936 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) | |
27cd7769 AD |
1937 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) |
1938 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) | |
1939 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) | |
1940 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index | |
1941 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index | |
1942 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index | |
798bcf73 AD |
1943 | #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) |
1944 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) | |
1945 | #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) | |
1946 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) | |
1947 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) | |
1948 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) | |
1949 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) | |
73afc70d | 1950 | #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) |
9e6f3d02 AD |
1951 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) |
1952 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) | |
c79a49ca | 1953 | #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) |
901ea57d AD |
1954 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
1955 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) | |
1956 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) | |
1957 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) | |
def9ba9c | 1958 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
a02fa397 AD |
1959 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
1960 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) | |
1961 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) | |
1962 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) | |
1963 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) | |
69b62ad8 AD |
1964 | #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) |
1965 | #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) | |
1966 | #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) | |
1967 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) | |
1968 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) | |
454d2e2a | 1969 | #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) |
d0418894 | 1970 | #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) |
771fe6b9 | 1971 | |
6cf8a3f5 | 1972 | /* Common functions */ |
700a0cc0 | 1973 | /* AGP */ |
90aca4d2 | 1974 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
410a3418 | 1975 | extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); |
700a0cc0 | 1976 | extern void radeon_agp_disable(struct radeon_device *rdev); |
21f9a437 JG |
1977 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1978 | extern void radeon_modeset_fini(struct radeon_device *rdev); | |
9f022ddf | 1979 | extern bool radeon_card_posted(struct radeon_device *rdev); |
f47299c5 | 1980 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
f46c0120 | 1981 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
72542d77 | 1982 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
21f9a437 | 1983 | extern void radeon_scratch_init(struct radeon_device *rdev); |
724c80e1 AD |
1984 | extern void radeon_wb_fini(struct radeon_device *rdev); |
1985 | extern int radeon_wb_init(struct radeon_device *rdev); | |
1986 | extern void radeon_wb_disable(struct radeon_device *rdev); | |
21f9a437 JG |
1987 | extern void radeon_surface_init(struct radeon_device *rdev); |
1988 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); | |
ca6ffc64 | 1989 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
d39c3b89 | 1990 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
312ea8da | 1991 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
d03d8589 | 1992 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
d594e46a JG |
1993 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
1994 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | |
6a9ee8af DA |
1995 | extern int radeon_resume_kms(struct drm_device *dev); |
1996 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); | |
53595338 | 1997 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
2e1b65f9 AD |
1998 | extern void radeon_program_register_sequence(struct radeon_device *rdev, |
1999 | const u32 *registers, | |
2000 | const u32 array_size); | |
6cf8a3f5 | 2001 | |
721604a1 JG |
2002 | /* |
2003 | * vm | |
2004 | */ | |
2005 | int radeon_vm_manager_init(struct radeon_device *rdev); | |
2006 | void radeon_vm_manager_fini(struct radeon_device *rdev); | |
d72d43cf | 2007 | void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
721604a1 | 2008 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); |
ddf03f5c | 2009 | int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); |
13e55c38 | 2010 | void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); |
ee60e29f CK |
2011 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
2012 | struct radeon_vm *vm, int ring); | |
2013 | void radeon_vm_fence(struct radeon_device *rdev, | |
2014 | struct radeon_vm *vm, | |
2015 | struct radeon_fence *fence); | |
dce34bfd | 2016 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); |
721604a1 JG |
2017 | int radeon_vm_bo_update_pte(struct radeon_device *rdev, |
2018 | struct radeon_vm *vm, | |
2019 | struct radeon_bo *bo, | |
2020 | struct ttm_mem_reg *mem); | |
2021 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, | |
2022 | struct radeon_bo *bo); | |
421ca7ab CK |
2023 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, |
2024 | struct radeon_bo *bo); | |
e971bd5e CK |
2025 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, |
2026 | struct radeon_vm *vm, | |
2027 | struct radeon_bo *bo); | |
2028 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, | |
2029 | struct radeon_bo_va *bo_va, | |
2030 | uint64_t offset, | |
2031 | uint32_t flags); | |
721604a1 | 2032 | int radeon_vm_bo_rmv(struct radeon_device *rdev, |
e971bd5e | 2033 | struct radeon_bo_va *bo_va); |
721604a1 | 2034 | |
f122c610 AD |
2035 | /* audio */ |
2036 | void r600_audio_update_hdmi(struct work_struct *work); | |
721604a1 | 2037 | |
16cdf04d AD |
2038 | /* |
2039 | * R600 vram scratch functions | |
2040 | */ | |
2041 | int r600_vram_scratch_init(struct radeon_device *rdev); | |
2042 | void r600_vram_scratch_fini(struct radeon_device *rdev); | |
2043 | ||
285484e2 JG |
2044 | /* |
2045 | * r600 cs checking helper | |
2046 | */ | |
2047 | unsigned r600_mip_minify(unsigned size, unsigned level); | |
2048 | bool r600_fmt_is_valid_color(u32 format); | |
2049 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); | |
2050 | int r600_fmt_get_blocksize(u32 format); | |
2051 | int r600_fmt_get_nblocksx(u32 format, u32 w); | |
2052 | int r600_fmt_get_nblocksy(u32 format, u32 h); | |
2053 | ||
3574dda4 DV |
2054 | /* |
2055 | * r600 functions used by radeon_encoder.c | |
2056 | */ | |
1b688d08 RM |
2057 | struct radeon_hdmi_acr { |
2058 | u32 clock; | |
2059 | ||
2060 | int n_32khz; | |
2061 | int cts_32khz; | |
2062 | ||
2063 | int n_44_1khz; | |
2064 | int cts_44_1khz; | |
2065 | ||
2066 | int n_48khz; | |
2067 | int cts_48khz; | |
2068 | ||
2069 | }; | |
2070 | ||
e55d3e6c RM |
2071 | extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); |
2072 | ||
416a2bd2 AD |
2073 | extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
2074 | u32 tiling_pipe_num, | |
2075 | u32 max_rb_num, | |
2076 | u32 total_max_rb_num, | |
2077 | u32 enabled_rb_mask); | |
fe251e2f | 2078 | |
e55d3e6c RM |
2079 | /* |
2080 | * evergreen functions used by radeon_encoder.c | |
2081 | */ | |
2082 | ||
0af62b01 | 2083 | extern int ni_init_microcode(struct radeon_device *rdev); |
755d819e | 2084 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
0af62b01 | 2085 | |
c4917074 AD |
2086 | /* radeon_acpi.c */ |
2087 | #if defined(CONFIG_ACPI) | |
2088 | extern int radeon_acpi_init(struct radeon_device *rdev); | |
2089 | extern void radeon_acpi_fini(struct radeon_device *rdev); | |
2090 | #else | |
2091 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } | |
2092 | static inline void radeon_acpi_fini(struct radeon_device *rdev) { } | |
2093 | #endif | |
d7a2952f | 2094 | |
c38f34b5 IH |
2095 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, |
2096 | struct radeon_cs_packet *pkt, | |
2097 | unsigned idx); | |
9ffb7a6d | 2098 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); |
c3ad63af IH |
2099 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, |
2100 | struct radeon_cs_packet *pkt); | |
e9716993 IH |
2101 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, |
2102 | struct radeon_cs_reloc **cs_reloc, | |
2103 | int nomm); | |
40592a17 IH |
2104 | int r600_cs_common_vline_parse(struct radeon_cs_parser *p, |
2105 | uint32_t *vline_start_end, | |
2106 | uint32_t *vline_status); | |
c38f34b5 | 2107 | |
4c788679 JG |
2108 | #include "radeon_object.h" |
2109 | ||
771fe6b9 | 2110 | #endif |