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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __RADEON_H__ | |
29 | #define __RADEON_H__ | |
30 | ||
771fe6b9 JG |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should | |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings | |
34 | * related to surface | |
35 | * - WB : write back stuff (do it bit like scratch reg things) | |
36 | * - Vblank : look at Jesse's rework and what we should do | |
37 | * - r600/r700: gart & cp | |
38 | * - cs : clean cs ioctl use bitmap & things like that. | |
39 | * - power management stuff | |
40 | * - Barrier in gart code | |
41 | * - Unmappabled vram ? | |
42 | * - TESTING, TESTING, TESTING | |
43 | */ | |
44 | ||
d39c3b89 JG |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various | |
47 | * reasons even thought we work hard to make it works on most | |
48 | * configurations. In order to still have a working userspace in such | |
49 | * situation the init path must succeed up to the memory controller | |
50 | * initialization point. Failure before this point are considered as | |
51 | * fatal error. Here is the init callchain : | |
52 | * radeon_device_init perform common structure, mutex initialization | |
53 | * asic_init setup the GPU memory layout and perform all | |
54 | * one time initialization (failure in this | |
55 | * function are considered fatal) | |
56 | * asic_startup setup the GPU acceleration, in order to | |
57 | * follow guideline the first thing this | |
58 | * function should do is setting the GPU | |
59 | * memory controller (only MC setup failure | |
60 | * are considered as fatal) | |
61 | */ | |
62 | ||
771fe6b9 JG |
63 | #include <asm/atomic.h> |
64 | #include <linux/wait.h> | |
65 | #include <linux/list.h> | |
66 | #include <linux/kref.h> | |
67 | ||
4c788679 JG |
68 | #include <ttm/ttm_bo_api.h> |
69 | #include <ttm/ttm_bo_driver.h> | |
70 | #include <ttm/ttm_placement.h> | |
71 | #include <ttm/ttm_module.h> | |
72 | ||
c2142715 | 73 | #include "radeon_family.h" |
771fe6b9 JG |
74 | #include "radeon_mode.h" |
75 | #include "radeon_reg.h" | |
771fe6b9 JG |
76 | |
77 | /* | |
78 | * Modules parameters. | |
79 | */ | |
80 | extern int radeon_no_wb; | |
81 | extern int radeon_modeset; | |
82 | extern int radeon_dynclks; | |
83 | extern int radeon_r4xx_atom; | |
84 | extern int radeon_agpmode; | |
85 | extern int radeon_vram_limit; | |
86 | extern int radeon_gart_size; | |
87 | extern int radeon_benchmarking; | |
ecc0b326 | 88 | extern int radeon_testing; |
771fe6b9 | 89 | extern int radeon_connector_table; |
4ce001ab | 90 | extern int radeon_tv; |
b27b6375 | 91 | extern int radeon_new_pll; |
dafc3bd5 | 92 | extern int radeon_audio; |
771fe6b9 JG |
93 | |
94 | /* | |
95 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | |
96 | * symbol; | |
97 | */ | |
98 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ | |
99 | #define RADEON_IB_POOL_SIZE 16 | |
100 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 | |
101 | #define RADEONFB_CONN_LIMIT 4 | |
f657c2a7 | 102 | #define RADEON_BIOS_NUM_SCRATCH 8 |
771fe6b9 | 103 | |
771fe6b9 JG |
104 | /* |
105 | * Errata workarounds. | |
106 | */ | |
107 | enum radeon_pll_errata { | |
108 | CHIP_ERRATA_R300_CG = 0x00000001, | |
109 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, | |
110 | CHIP_ERRATA_PLL_DELAY = 0x00000004 | |
111 | }; | |
112 | ||
113 | ||
114 | struct radeon_device; | |
115 | ||
116 | ||
117 | /* | |
118 | * BIOS. | |
119 | */ | |
120 | bool radeon_get_bios(struct radeon_device *rdev); | |
121 | ||
3ce0a23d | 122 | |
771fe6b9 | 123 | /* |
3ce0a23d | 124 | * Dummy page |
771fe6b9 | 125 | */ |
3ce0a23d JG |
126 | struct radeon_dummy_page { |
127 | struct page *page; | |
128 | dma_addr_t addr; | |
129 | }; | |
130 | int radeon_dummy_page_init(struct radeon_device *rdev); | |
131 | void radeon_dummy_page_fini(struct radeon_device *rdev); | |
132 | ||
771fe6b9 | 133 | |
3ce0a23d JG |
134 | /* |
135 | * Clocks | |
136 | */ | |
771fe6b9 JG |
137 | struct radeon_clock { |
138 | struct radeon_pll p1pll; | |
139 | struct radeon_pll p2pll; | |
140 | struct radeon_pll spll; | |
141 | struct radeon_pll mpll; | |
142 | /* 10 Khz units */ | |
143 | uint32_t default_mclk; | |
144 | uint32_t default_sclk; | |
145 | }; | |
146 | ||
7433874e RM |
147 | /* |
148 | * Power management | |
149 | */ | |
150 | int radeon_pm_init(struct radeon_device *rdev); | |
3ce0a23d | 151 | |
771fe6b9 JG |
152 | /* |
153 | * Fences. | |
154 | */ | |
155 | struct radeon_fence_driver { | |
156 | uint32_t scratch_reg; | |
157 | atomic_t seq; | |
158 | uint32_t last_seq; | |
159 | unsigned long count_timeout; | |
160 | wait_queue_head_t queue; | |
161 | rwlock_t lock; | |
162 | struct list_head created; | |
163 | struct list_head emited; | |
164 | struct list_head signaled; | |
0a0c7596 | 165 | bool initialized; |
771fe6b9 JG |
166 | }; |
167 | ||
168 | struct radeon_fence { | |
169 | struct radeon_device *rdev; | |
170 | struct kref kref; | |
171 | struct list_head list; | |
172 | /* protected by radeon_fence.lock */ | |
173 | uint32_t seq; | |
174 | unsigned long timeout; | |
175 | bool emited; | |
176 | bool signaled; | |
177 | }; | |
178 | ||
179 | int radeon_fence_driver_init(struct radeon_device *rdev); | |
180 | void radeon_fence_driver_fini(struct radeon_device *rdev); | |
181 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); | |
182 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); | |
183 | void radeon_fence_process(struct radeon_device *rdev); | |
184 | bool radeon_fence_signaled(struct radeon_fence *fence); | |
185 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); | |
186 | int radeon_fence_wait_next(struct radeon_device *rdev); | |
187 | int radeon_fence_wait_last(struct radeon_device *rdev); | |
188 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); | |
189 | void radeon_fence_unref(struct radeon_fence **fence); | |
190 | ||
e024e110 DA |
191 | /* |
192 | * Tiling registers | |
193 | */ | |
194 | struct radeon_surface_reg { | |
4c788679 | 195 | struct radeon_bo *bo; |
e024e110 DA |
196 | }; |
197 | ||
198 | #define RADEON_GEM_MAX_SURFACES 8 | |
771fe6b9 JG |
199 | |
200 | /* | |
4c788679 | 201 | * TTM. |
771fe6b9 | 202 | */ |
4c788679 JG |
203 | struct radeon_mman { |
204 | struct ttm_bo_global_ref bo_global_ref; | |
205 | struct ttm_global_reference mem_global_ref; | |
4c788679 | 206 | struct ttm_bo_device bdev; |
0a0c7596 JG |
207 | bool mem_global_referenced; |
208 | bool initialized; | |
4c788679 JG |
209 | }; |
210 | ||
211 | struct radeon_bo { | |
212 | /* Protected by gem.mutex */ | |
213 | struct list_head list; | |
214 | /* Protected by tbo.reserved */ | |
312ea8da JG |
215 | u32 placements[3]; |
216 | struct ttm_placement placement; | |
4c788679 JG |
217 | struct ttm_buffer_object tbo; |
218 | struct ttm_bo_kmap_obj kmap; | |
219 | unsigned pin_count; | |
220 | void *kptr; | |
221 | u32 tiling_flags; | |
222 | u32 pitch; | |
223 | int surface_reg; | |
224 | /* Constant after initialization */ | |
225 | struct radeon_device *rdev; | |
226 | struct drm_gem_object *gobj; | |
227 | }; | |
771fe6b9 | 228 | |
4c788679 | 229 | struct radeon_bo_list { |
771fe6b9 | 230 | struct list_head list; |
4c788679 | 231 | struct radeon_bo *bo; |
771fe6b9 JG |
232 | uint64_t gpu_offset; |
233 | unsigned rdomain; | |
234 | unsigned wdomain; | |
4c788679 | 235 | u32 tiling_flags; |
771fe6b9 JG |
236 | }; |
237 | ||
771fe6b9 JG |
238 | /* |
239 | * GEM objects. | |
240 | */ | |
241 | struct radeon_gem { | |
4c788679 | 242 | struct mutex mutex; |
771fe6b9 JG |
243 | struct list_head objects; |
244 | }; | |
245 | ||
246 | int radeon_gem_init(struct radeon_device *rdev); | |
247 | void radeon_gem_fini(struct radeon_device *rdev); | |
248 | int radeon_gem_object_create(struct radeon_device *rdev, int size, | |
4c788679 JG |
249 | int alignment, int initial_domain, |
250 | bool discardable, bool kernel, | |
251 | struct drm_gem_object **obj); | |
771fe6b9 JG |
252 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
253 | uint64_t *gpu_addr); | |
254 | void radeon_gem_object_unpin(struct drm_gem_object *obj); | |
255 | ||
256 | ||
257 | /* | |
258 | * GART structures, functions & helpers | |
259 | */ | |
260 | struct radeon_mc; | |
261 | ||
262 | struct radeon_gart_table_ram { | |
263 | volatile uint32_t *ptr; | |
264 | }; | |
265 | ||
266 | struct radeon_gart_table_vram { | |
4c788679 | 267 | struct radeon_bo *robj; |
771fe6b9 JG |
268 | volatile uint32_t *ptr; |
269 | }; | |
270 | ||
271 | union radeon_gart_table { | |
272 | struct radeon_gart_table_ram ram; | |
273 | struct radeon_gart_table_vram vram; | |
274 | }; | |
275 | ||
a77f1718 MT |
276 | #define RADEON_GPU_PAGE_SIZE 4096 |
277 | ||
771fe6b9 JG |
278 | struct radeon_gart { |
279 | dma_addr_t table_addr; | |
280 | unsigned num_gpu_pages; | |
281 | unsigned num_cpu_pages; | |
282 | unsigned table_size; | |
283 | union radeon_gart_table table; | |
284 | struct page **pages; | |
285 | dma_addr_t *pages_addr; | |
286 | bool ready; | |
287 | }; | |
288 | ||
289 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); | |
290 | void radeon_gart_table_ram_free(struct radeon_device *rdev); | |
291 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); | |
292 | void radeon_gart_table_vram_free(struct radeon_device *rdev); | |
293 | int radeon_gart_init(struct radeon_device *rdev); | |
294 | void radeon_gart_fini(struct radeon_device *rdev); | |
295 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |
296 | int pages); | |
297 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |
298 | int pages, struct page **pagelist); | |
299 | ||
300 | ||
301 | /* | |
302 | * GPU MC structures, functions & helpers | |
303 | */ | |
304 | struct radeon_mc { | |
305 | resource_size_t aper_size; | |
306 | resource_size_t aper_base; | |
307 | resource_size_t agp_base; | |
7a50f01a DA |
308 | /* for some chips with <= 32MB we need to lie |
309 | * about vram size near mc fb location */ | |
3ce0a23d JG |
310 | u64 mc_vram_size; |
311 | u64 gtt_location; | |
312 | u64 gtt_size; | |
313 | u64 gtt_start; | |
314 | u64 gtt_end; | |
315 | u64 vram_location; | |
316 | u64 vram_start; | |
317 | u64 vram_end; | |
771fe6b9 | 318 | unsigned vram_width; |
3ce0a23d | 319 | u64 real_vram_size; |
771fe6b9 JG |
320 | int vram_mtrr; |
321 | bool vram_is_ddr; | |
322 | }; | |
323 | ||
324 | int radeon_mc_setup(struct radeon_device *rdev); | |
325 | ||
326 | ||
327 | /* | |
328 | * GPU scratch registers structures, functions & helpers | |
329 | */ | |
330 | struct radeon_scratch { | |
331 | unsigned num_reg; | |
332 | bool free[32]; | |
333 | uint32_t reg[32]; | |
334 | }; | |
335 | ||
336 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); | |
337 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); | |
338 | ||
339 | ||
340 | /* | |
341 | * IRQS. | |
342 | */ | |
343 | struct radeon_irq { | |
344 | bool installed; | |
345 | bool sw_int; | |
346 | /* FIXME: use a define max crtc rather than hardcode it */ | |
347 | bool crtc_vblank_int[2]; | |
b500f680 AD |
348 | /* FIXME: use defines for max hpd/dacs */ |
349 | bool hpd[6]; | |
1614f8b1 DA |
350 | spinlock_t sw_lock; |
351 | int sw_refcount; | |
771fe6b9 JG |
352 | }; |
353 | ||
354 | int radeon_irq_kms_init(struct radeon_device *rdev); | |
355 | void radeon_irq_kms_fini(struct radeon_device *rdev); | |
1614f8b1 DA |
356 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); |
357 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); | |
771fe6b9 JG |
358 | |
359 | /* | |
360 | * CP & ring. | |
361 | */ | |
362 | struct radeon_ib { | |
363 | struct list_head list; | |
364 | unsigned long idx; | |
365 | uint64_t gpu_addr; | |
366 | struct radeon_fence *fence; | |
513bcb46 | 367 | uint32_t *ptr; |
771fe6b9 JG |
368 | uint32_t length_dw; |
369 | }; | |
370 | ||
ecb114a1 DA |
371 | /* |
372 | * locking - | |
373 | * mutex protects scheduled_ibs, ready, alloc_bm | |
374 | */ | |
771fe6b9 JG |
375 | struct radeon_ib_pool { |
376 | struct mutex mutex; | |
4c788679 | 377 | struct radeon_bo *robj; |
771fe6b9 JG |
378 | struct list_head scheduled_ibs; |
379 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; | |
380 | bool ready; | |
381 | DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); | |
382 | }; | |
383 | ||
384 | struct radeon_cp { | |
4c788679 | 385 | struct radeon_bo *ring_obj; |
771fe6b9 JG |
386 | volatile uint32_t *ring; |
387 | unsigned rptr; | |
388 | unsigned wptr; | |
389 | unsigned wptr_old; | |
390 | unsigned ring_size; | |
391 | unsigned ring_free_dw; | |
392 | int count_dw; | |
393 | uint64_t gpu_addr; | |
394 | uint32_t align_mask; | |
395 | uint32_t ptr_mask; | |
396 | struct mutex mutex; | |
397 | bool ready; | |
398 | }; | |
399 | ||
d8f60cfc AD |
400 | /* |
401 | * R6xx+ IH ring | |
402 | */ | |
403 | struct r600_ih { | |
4c788679 | 404 | struct radeon_bo *ring_obj; |
d8f60cfc AD |
405 | volatile uint32_t *ring; |
406 | unsigned rptr; | |
407 | unsigned wptr; | |
408 | unsigned wptr_old; | |
409 | unsigned ring_size; | |
410 | uint64_t gpu_addr; | |
411 | uint32_t align_mask; | |
412 | uint32_t ptr_mask; | |
413 | spinlock_t lock; | |
414 | bool enabled; | |
415 | }; | |
416 | ||
3ce0a23d | 417 | struct r600_blit { |
4c788679 | 418 | struct radeon_bo *shader_obj; |
3ce0a23d JG |
419 | u64 shader_gpu_addr; |
420 | u32 vs_offset, ps_offset; | |
421 | u32 state_offset; | |
422 | u32 state_len; | |
423 | u32 vb_used, vb_total; | |
424 | struct radeon_ib *vb_ib; | |
425 | }; | |
426 | ||
771fe6b9 JG |
427 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
428 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); | |
429 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); | |
430 | int radeon_ib_pool_init(struct radeon_device *rdev); | |
431 | void radeon_ib_pool_fini(struct radeon_device *rdev); | |
432 | int radeon_ib_test(struct radeon_device *rdev); | |
433 | /* Ring access between begin & end cannot sleep */ | |
434 | void radeon_ring_free_size(struct radeon_device *rdev); | |
435 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); | |
436 | void radeon_ring_unlock_commit(struct radeon_device *rdev); | |
437 | void radeon_ring_unlock_undo(struct radeon_device *rdev); | |
438 | int radeon_ring_test(struct radeon_device *rdev); | |
439 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
440 | void radeon_ring_fini(struct radeon_device *rdev); | |
441 | ||
442 | ||
443 | /* | |
444 | * CS. | |
445 | */ | |
446 | struct radeon_cs_reloc { | |
447 | struct drm_gem_object *gobj; | |
4c788679 JG |
448 | struct radeon_bo *robj; |
449 | struct radeon_bo_list lobj; | |
771fe6b9 JG |
450 | uint32_t handle; |
451 | uint32_t flags; | |
452 | }; | |
453 | ||
454 | struct radeon_cs_chunk { | |
455 | uint32_t chunk_id; | |
456 | uint32_t length_dw; | |
513bcb46 DA |
457 | int kpage_idx[2]; |
458 | uint32_t *kpage[2]; | |
771fe6b9 | 459 | uint32_t *kdata; |
513bcb46 DA |
460 | void __user *user_ptr; |
461 | int last_copied_page; | |
462 | int last_page_index; | |
771fe6b9 JG |
463 | }; |
464 | ||
465 | struct radeon_cs_parser { | |
466 | struct radeon_device *rdev; | |
467 | struct drm_file *filp; | |
468 | /* chunks */ | |
469 | unsigned nchunks; | |
470 | struct radeon_cs_chunk *chunks; | |
471 | uint64_t *chunks_array; | |
472 | /* IB */ | |
473 | unsigned idx; | |
474 | /* relocations */ | |
475 | unsigned nrelocs; | |
476 | struct radeon_cs_reloc *relocs; | |
477 | struct radeon_cs_reloc **relocs_ptr; | |
478 | struct list_head validated; | |
479 | /* indices of various chunks */ | |
480 | int chunk_ib_idx; | |
481 | int chunk_relocs_idx; | |
482 | struct radeon_ib *ib; | |
483 | void *track; | |
3ce0a23d | 484 | unsigned family; |
513bcb46 | 485 | int parser_error; |
771fe6b9 JG |
486 | }; |
487 | ||
513bcb46 DA |
488 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
489 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); | |
490 | ||
491 | ||
492 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) | |
493 | { | |
494 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
495 | u32 pg_idx, pg_offset; | |
496 | u32 idx_value = 0; | |
497 | int new_page; | |
498 | ||
499 | pg_idx = (idx * 4) / PAGE_SIZE; | |
500 | pg_offset = (idx * 4) % PAGE_SIZE; | |
501 | ||
502 | if (ibc->kpage_idx[0] == pg_idx) | |
503 | return ibc->kpage[0][pg_offset/4]; | |
504 | if (ibc->kpage_idx[1] == pg_idx) | |
505 | return ibc->kpage[1][pg_offset/4]; | |
506 | ||
507 | new_page = radeon_cs_update_pages(p, pg_idx); | |
508 | if (new_page < 0) { | |
509 | p->parser_error = new_page; | |
510 | return 0; | |
511 | } | |
512 | ||
513 | idx_value = ibc->kpage[new_page][pg_offset/4]; | |
514 | return idx_value; | |
515 | } | |
516 | ||
771fe6b9 JG |
517 | struct radeon_cs_packet { |
518 | unsigned idx; | |
519 | unsigned type; | |
520 | unsigned reg; | |
521 | unsigned opcode; | |
522 | int count; | |
523 | unsigned one_reg_wr; | |
524 | }; | |
525 | ||
526 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, | |
527 | struct radeon_cs_packet *pkt, | |
528 | unsigned idx, unsigned reg); | |
529 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, | |
530 | struct radeon_cs_packet *pkt); | |
531 | ||
532 | ||
533 | /* | |
534 | * AGP | |
535 | */ | |
536 | int radeon_agp_init(struct radeon_device *rdev); | |
0ebf1717 | 537 | void radeon_agp_resume(struct radeon_device *rdev); |
771fe6b9 JG |
538 | void radeon_agp_fini(struct radeon_device *rdev); |
539 | ||
540 | ||
541 | /* | |
542 | * Writeback | |
543 | */ | |
544 | struct radeon_wb { | |
4c788679 | 545 | struct radeon_bo *wb_obj; |
771fe6b9 JG |
546 | volatile uint32_t *wb; |
547 | uint64_t gpu_addr; | |
548 | }; | |
549 | ||
c93bb85b JG |
550 | /** |
551 | * struct radeon_pm - power management datas | |
552 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) | |
553 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) | |
554 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) | |
555 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) | |
556 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) | |
557 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) | |
558 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) | |
559 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) | |
560 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) | |
561 | * @sclk: GPU clock Mhz (core bandwith depends of this clock) | |
562 | * @needed_bandwidth: current bandwidth needs | |
563 | * | |
564 | * It keeps track of various data needed to take powermanagement decision. | |
565 | * Bandwith need is used to determine minimun clock of the GPU and memory. | |
566 | * Equation between gpu/memory clock and available bandwidth is hw dependent | |
567 | * (type of memory, bus size, efficiency, ...) | |
568 | */ | |
569 | struct radeon_pm { | |
570 | fixed20_12 max_bandwidth; | |
571 | fixed20_12 igp_sideport_mclk; | |
572 | fixed20_12 igp_system_mclk; | |
573 | fixed20_12 igp_ht_link_clk; | |
574 | fixed20_12 igp_ht_link_width; | |
575 | fixed20_12 k8_bandwidth; | |
576 | fixed20_12 sideport_bandwidth; | |
577 | fixed20_12 ht_bandwidth; | |
578 | fixed20_12 core_bandwidth; | |
579 | fixed20_12 sclk; | |
580 | fixed20_12 needed_bandwidth; | |
581 | }; | |
582 | ||
771fe6b9 JG |
583 | |
584 | /* | |
585 | * Benchmarking | |
586 | */ | |
587 | void radeon_benchmark(struct radeon_device *rdev); | |
588 | ||
589 | ||
ecc0b326 MD |
590 | /* |
591 | * Testing | |
592 | */ | |
593 | void radeon_test_moves(struct radeon_device *rdev); | |
594 | ||
595 | ||
771fe6b9 JG |
596 | /* |
597 | * Debugfs | |
598 | */ | |
599 | int radeon_debugfs_add_files(struct radeon_device *rdev, | |
600 | struct drm_info_list *files, | |
601 | unsigned nfiles); | |
602 | int radeon_debugfs_fence_init(struct radeon_device *rdev); | |
603 | int r100_debugfs_rbbm_init(struct radeon_device *rdev); | |
604 | int r100_debugfs_cp_init(struct radeon_device *rdev); | |
605 | ||
606 | ||
607 | /* | |
608 | * ASIC specific functions. | |
609 | */ | |
610 | struct radeon_asic { | |
068a117c | 611 | int (*init)(struct radeon_device *rdev); |
3ce0a23d JG |
612 | void (*fini)(struct radeon_device *rdev); |
613 | int (*resume)(struct radeon_device *rdev); | |
614 | int (*suspend)(struct radeon_device *rdev); | |
28d52043 | 615 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
771fe6b9 | 616 | int (*gpu_reset)(struct radeon_device *rdev); |
771fe6b9 JG |
617 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
618 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); | |
619 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); | |
620 | void (*cp_fini)(struct radeon_device *rdev); | |
621 | void (*cp_disable)(struct radeon_device *rdev); | |
3ce0a23d | 622 | void (*cp_commit)(struct radeon_device *rdev); |
771fe6b9 | 623 | void (*ring_start)(struct radeon_device *rdev); |
3ce0a23d JG |
624 | int (*ring_test)(struct radeon_device *rdev); |
625 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); | |
771fe6b9 JG |
626 | int (*irq_set)(struct radeon_device *rdev); |
627 | int (*irq_process)(struct radeon_device *rdev); | |
7ed220d7 | 628 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
771fe6b9 JG |
629 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
630 | int (*cs_parse)(struct radeon_cs_parser *p); | |
631 | int (*copy_blit)(struct radeon_device *rdev, | |
632 | uint64_t src_offset, | |
633 | uint64_t dst_offset, | |
634 | unsigned num_pages, | |
635 | struct radeon_fence *fence); | |
636 | int (*copy_dma)(struct radeon_device *rdev, | |
637 | uint64_t src_offset, | |
638 | uint64_t dst_offset, | |
639 | unsigned num_pages, | |
640 | struct radeon_fence *fence); | |
641 | int (*copy)(struct radeon_device *rdev, | |
642 | uint64_t src_offset, | |
643 | uint64_t dst_offset, | |
644 | unsigned num_pages, | |
645 | struct radeon_fence *fence); | |
7433874e | 646 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
771fe6b9 | 647 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
7433874e | 648 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
771fe6b9 JG |
649 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
650 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); | |
651 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); | |
e024e110 DA |
652 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
653 | uint32_t tiling_flags, uint32_t pitch, | |
654 | uint32_t offset, uint32_t obj_size); | |
655 | int (*clear_surface_reg)(struct radeon_device *rdev, int reg); | |
c93bb85b | 656 | void (*bandwidth_update)(struct radeon_device *rdev); |
23956dfa | 657 | void (*hdp_flush)(struct radeon_device *rdev); |
429770b3 AD |
658 | void (*hpd_init)(struct radeon_device *rdev); |
659 | void (*hpd_fini)(struct radeon_device *rdev); | |
660 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
661 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
771fe6b9 JG |
662 | }; |
663 | ||
21f9a437 JG |
664 | /* |
665 | * Asic structures | |
666 | */ | |
551ebd83 DA |
667 | struct r100_asic { |
668 | const unsigned *reg_safe_bm; | |
669 | unsigned reg_safe_bm_size; | |
670 | }; | |
671 | ||
21f9a437 JG |
672 | struct r300_asic { |
673 | const unsigned *reg_safe_bm; | |
674 | unsigned reg_safe_bm_size; | |
675 | }; | |
676 | ||
677 | struct r600_asic { | |
678 | unsigned max_pipes; | |
679 | unsigned max_tile_pipes; | |
680 | unsigned max_simds; | |
681 | unsigned max_backends; | |
682 | unsigned max_gprs; | |
683 | unsigned max_threads; | |
684 | unsigned max_stack_entries; | |
685 | unsigned max_hw_contexts; | |
686 | unsigned max_gs_threads; | |
687 | unsigned sx_max_export_size; | |
688 | unsigned sx_max_export_pos_size; | |
689 | unsigned sx_max_export_smx_size; | |
690 | unsigned sq_num_cf_insts; | |
691 | }; | |
692 | ||
693 | struct rv770_asic { | |
694 | unsigned max_pipes; | |
695 | unsigned max_tile_pipes; | |
696 | unsigned max_simds; | |
697 | unsigned max_backends; | |
698 | unsigned max_gprs; | |
699 | unsigned max_threads; | |
700 | unsigned max_stack_entries; | |
701 | unsigned max_hw_contexts; | |
702 | unsigned max_gs_threads; | |
703 | unsigned sx_max_export_size; | |
704 | unsigned sx_max_export_pos_size; | |
705 | unsigned sx_max_export_smx_size; | |
706 | unsigned sq_num_cf_insts; | |
707 | unsigned sx_num_of_sets; | |
708 | unsigned sc_prim_fifo_size; | |
709 | unsigned sc_hiz_tile_fifo_size; | |
710 | unsigned sc_earlyz_tile_fifo_fize; | |
711 | }; | |
712 | ||
068a117c JG |
713 | union radeon_asic_config { |
714 | struct r300_asic r300; | |
551ebd83 | 715 | struct r100_asic r100; |
3ce0a23d JG |
716 | struct r600_asic r600; |
717 | struct rv770_asic rv770; | |
068a117c JG |
718 | }; |
719 | ||
771fe6b9 JG |
720 | |
721 | /* | |
722 | * IOCTL. | |
723 | */ | |
724 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |
725 | struct drm_file *filp); | |
726 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, | |
727 | struct drm_file *filp); | |
728 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, | |
729 | struct drm_file *file_priv); | |
730 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
731 | struct drm_file *file_priv); | |
732 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
733 | struct drm_file *file_priv); | |
734 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, | |
735 | struct drm_file *file_priv); | |
736 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
737 | struct drm_file *filp); | |
738 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
739 | struct drm_file *filp); | |
740 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, | |
741 | struct drm_file *filp); | |
742 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
743 | struct drm_file *filp); | |
744 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); | |
e024e110 DA |
745 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
746 | struct drm_file *filp); | |
747 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
748 | struct drm_file *filp); | |
771fe6b9 JG |
749 | |
750 | ||
751 | /* | |
752 | * Core structure, functions and helpers. | |
753 | */ | |
754 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); | |
755 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); | |
756 | ||
757 | struct radeon_device { | |
9f022ddf | 758 | struct device *dev; |
771fe6b9 JG |
759 | struct drm_device *ddev; |
760 | struct pci_dev *pdev; | |
761 | /* ASIC */ | |
068a117c | 762 | union radeon_asic_config config; |
771fe6b9 JG |
763 | enum radeon_family family; |
764 | unsigned long flags; | |
765 | int usec_timeout; | |
766 | enum radeon_pll_errata pll_errata; | |
767 | int num_gb_pipes; | |
f779b3e5 | 768 | int num_z_pipes; |
771fe6b9 JG |
769 | int disp_priority; |
770 | /* BIOS */ | |
771 | uint8_t *bios; | |
772 | bool is_atom_bios; | |
773 | uint16_t bios_header_start; | |
4c788679 | 774 | struct radeon_bo *stollen_vga_memory; |
771fe6b9 | 775 | struct fb_info *fbdev_info; |
4c788679 | 776 | struct radeon_bo *fbdev_rbo; |
771fe6b9 JG |
777 | struct radeon_framebuffer *fbdev_rfb; |
778 | /* Register mmio */ | |
4c9bc75c DA |
779 | resource_size_t rmmio_base; |
780 | resource_size_t rmmio_size; | |
771fe6b9 | 781 | void *rmmio; |
771fe6b9 JG |
782 | radeon_rreg_t mc_rreg; |
783 | radeon_wreg_t mc_wreg; | |
784 | radeon_rreg_t pll_rreg; | |
785 | radeon_wreg_t pll_wreg; | |
de1b2898 | 786 | uint32_t pcie_reg_mask; |
771fe6b9 JG |
787 | radeon_rreg_t pciep_rreg; |
788 | radeon_wreg_t pciep_wreg; | |
789 | struct radeon_clock clock; | |
790 | struct radeon_mc mc; | |
791 | struct radeon_gart gart; | |
792 | struct radeon_mode_info mode_info; | |
793 | struct radeon_scratch scratch; | |
794 | struct radeon_mman mman; | |
795 | struct radeon_fence_driver fence_drv; | |
796 | struct radeon_cp cp; | |
797 | struct radeon_ib_pool ib_pool; | |
798 | struct radeon_irq irq; | |
799 | struct radeon_asic *asic; | |
800 | struct radeon_gem gem; | |
c93bb85b | 801 | struct radeon_pm pm; |
f657c2a7 | 802 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
771fe6b9 JG |
803 | struct mutex cs_mutex; |
804 | struct radeon_wb wb; | |
3ce0a23d | 805 | struct radeon_dummy_page dummy_page; |
771fe6b9 JG |
806 | bool gpu_lockup; |
807 | bool shutdown; | |
808 | bool suspend; | |
ad49f501 | 809 | bool need_dma32; |
733289c2 | 810 | bool accel_working; |
e024e110 | 811 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
3ce0a23d JG |
812 | const struct firmware *me_fw; /* all family ME firmware */ |
813 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ | |
d8f60cfc | 814 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
3ce0a23d | 815 | struct r600_blit r600_blit; |
3e5cb98d | 816 | int msi_enabled; /* msi enabled */ |
d8f60cfc | 817 | struct r600_ih ih; /* r6/700 interrupt ring */ |
d4877cf2 AD |
818 | struct workqueue_struct *wq; |
819 | struct work_struct hotplug_work; | |
dafc3bd5 CK |
820 | |
821 | /* audio stuff */ | |
822 | struct timer_list audio_timer; | |
823 | int audio_channels; | |
824 | int audio_rate; | |
825 | int audio_bits_per_sample; | |
826 | uint8_t audio_status_bits; | |
827 | uint8_t audio_category_code; | |
771fe6b9 JG |
828 | }; |
829 | ||
830 | int radeon_device_init(struct radeon_device *rdev, | |
831 | struct drm_device *ddev, | |
832 | struct pci_dev *pdev, | |
833 | uint32_t flags); | |
834 | void radeon_device_fini(struct radeon_device *rdev); | |
835 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); | |
836 | ||
3ce0a23d JG |
837 | /* r600 blit */ |
838 | int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); | |
839 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); | |
840 | void r600_kms_blit_copy(struct radeon_device *rdev, | |
841 | u64 src_gpu_addr, u64 dst_gpu_addr, | |
842 | int size_bytes); | |
843 | ||
de1b2898 DA |
844 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
845 | { | |
846 | if (reg < 0x10000) | |
847 | return readl(((void __iomem *)rdev->rmmio) + reg); | |
848 | else { | |
849 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | |
850 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
851 | } | |
852 | } | |
853 | ||
854 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
855 | { | |
856 | if (reg < 0x10000) | |
857 | writel(v, ((void __iomem *)rdev->rmmio) + reg); | |
858 | else { | |
859 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | |
860 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
861 | } | |
862 | } | |
863 | ||
4c788679 JG |
864 | /* |
865 | * Cast helper | |
866 | */ | |
867 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) | |
771fe6b9 JG |
868 | |
869 | /* | |
870 | * Registers read & write functions. | |
871 | */ | |
872 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) | |
873 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) | |
de1b2898 | 874 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
3ce0a23d | 875 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
de1b2898 | 876 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
771fe6b9 JG |
877 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
878 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
879 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) | |
880 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) | |
881 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) | |
882 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) | |
de1b2898 DA |
883 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
884 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) | |
771fe6b9 JG |
885 | #define WREG32_P(reg, val, mask) \ |
886 | do { \ | |
887 | uint32_t tmp_ = RREG32(reg); \ | |
888 | tmp_ &= (mask); \ | |
889 | tmp_ |= ((val) & ~(mask)); \ | |
890 | WREG32(reg, tmp_); \ | |
891 | } while (0) | |
892 | #define WREG32_PLL_P(reg, val, mask) \ | |
893 | do { \ | |
894 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
895 | tmp_ &= (mask); \ | |
896 | tmp_ |= ((val) & ~(mask)); \ | |
897 | WREG32_PLL(reg, tmp_); \ | |
898 | } while (0) | |
3ce0a23d | 899 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) |
771fe6b9 | 900 | |
de1b2898 DA |
901 | /* |
902 | * Indirect registers accessor | |
903 | */ | |
904 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | |
905 | { | |
906 | uint32_t r; | |
907 | ||
908 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
909 | r = RREG32(RADEON_PCIE_DATA); | |
910 | return r; | |
911 | } | |
912 | ||
913 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
914 | { | |
915 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
916 | WREG32(RADEON_PCIE_DATA, (v)); | |
917 | } | |
918 | ||
771fe6b9 JG |
919 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
920 | ||
921 | ||
922 | /* | |
923 | * ASICs helpers. | |
924 | */ | |
b995e433 DA |
925 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
926 | (rdev->pdev->device == 0x5969)) | |
771fe6b9 JG |
927 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
928 | (rdev->family == CHIP_RV200) || \ | |
929 | (rdev->family == CHIP_RS100) || \ | |
930 | (rdev->family == CHIP_RS200) || \ | |
931 | (rdev->family == CHIP_RV250) || \ | |
932 | (rdev->family == CHIP_RV280) || \ | |
933 | (rdev->family == CHIP_RS300)) | |
934 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ | |
935 | (rdev->family == CHIP_RV350) || \ | |
936 | (rdev->family == CHIP_R350) || \ | |
937 | (rdev->family == CHIP_RV380) || \ | |
938 | (rdev->family == CHIP_R420) || \ | |
939 | (rdev->family == CHIP_R423) || \ | |
940 | (rdev->family == CHIP_RV410) || \ | |
941 | (rdev->family == CHIP_RS400) || \ | |
942 | (rdev->family == CHIP_RS480)) | |
943 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) | |
944 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) | |
945 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) | |
946 | ||
947 | ||
948 | /* | |
949 | * BIOS helpers. | |
950 | */ | |
951 | #define RBIOS8(i) (rdev->bios[i]) | |
952 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
953 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
954 | ||
955 | int radeon_combios_init(struct radeon_device *rdev); | |
956 | void radeon_combios_fini(struct radeon_device *rdev); | |
957 | int radeon_atombios_init(struct radeon_device *rdev); | |
958 | void radeon_atombios_fini(struct radeon_device *rdev); | |
959 | ||
960 | ||
961 | /* | |
962 | * RING helpers. | |
963 | */ | |
771fe6b9 JG |
964 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
965 | { | |
966 | #if DRM_DEBUG_CODE | |
967 | if (rdev->cp.count_dw <= 0) { | |
968 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); | |
969 | } | |
970 | #endif | |
971 | rdev->cp.ring[rdev->cp.wptr++] = v; | |
972 | rdev->cp.wptr &= rdev->cp.ptr_mask; | |
973 | rdev->cp.count_dw--; | |
974 | rdev->cp.ring_free_dw--; | |
975 | } | |
976 | ||
977 | ||
978 | /* | |
979 | * ASICs macro. | |
980 | */ | |
068a117c | 981 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
3ce0a23d JG |
982 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
983 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) | |
984 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) | |
771fe6b9 | 985 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
28d52043 | 986 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
771fe6b9 | 987 | #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
771fe6b9 JG |
988 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
989 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) | |
3ce0a23d | 990 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
771fe6b9 | 991 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
3ce0a23d JG |
992 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
993 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) | |
771fe6b9 JG |
994 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
995 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) | |
7ed220d7 | 996 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
771fe6b9 JG |
997 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
998 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) | |
999 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) | |
1000 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) | |
7433874e | 1001 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
771fe6b9 | 1002 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
7433874e | 1003 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
93e7de7b | 1004 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) |
771fe6b9 JG |
1005 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
1006 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) | |
e024e110 DA |
1007 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
1008 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) | |
c93bb85b | 1009 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
23956dfa | 1010 | #define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev)) |
429770b3 AD |
1011 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) |
1012 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) | |
1013 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) | |
1014 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) | |
771fe6b9 | 1015 | |
6cf8a3f5 | 1016 | /* Common functions */ |
4aac0473 | 1017 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
21f9a437 JG |
1018 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1019 | extern void radeon_modeset_fini(struct radeon_device *rdev); | |
9f022ddf | 1020 | extern bool radeon_card_posted(struct radeon_device *rdev); |
72542d77 | 1021 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
21f9a437 JG |
1022 | extern int radeon_clocks_init(struct radeon_device *rdev); |
1023 | extern void radeon_clocks_fini(struct radeon_device *rdev); | |
1024 | extern void radeon_scratch_init(struct radeon_device *rdev); | |
1025 | extern void radeon_surface_init(struct radeon_device *rdev); | |
1026 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); | |
ca6ffc64 | 1027 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
d39c3b89 | 1028 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
312ea8da | 1029 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
d03d8589 | 1030 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
6cf8a3f5 | 1031 | |
a18d7ea1 | 1032 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
9f022ddf JG |
1033 | struct r100_mc_save { |
1034 | u32 GENMO_WT; | |
1035 | u32 CRTC_EXT_CNTL; | |
1036 | u32 CRTC_GEN_CNTL; | |
1037 | u32 CRTC2_GEN_CNTL; | |
1038 | u32 CUR_OFFSET; | |
1039 | u32 CUR2_OFFSET; | |
1040 | }; | |
1041 | extern void r100_cp_disable(struct radeon_device *rdev); | |
1042 | extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); | |
1043 | extern void r100_cp_fini(struct radeon_device *rdev); | |
21f9a437 | 1044 | extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
4aac0473 JG |
1045 | extern int r100_pci_gart_init(struct radeon_device *rdev); |
1046 | extern void r100_pci_gart_fini(struct radeon_device *rdev); | |
21f9a437 JG |
1047 | extern int r100_pci_gart_enable(struct radeon_device *rdev); |
1048 | extern void r100_pci_gart_disable(struct radeon_device *rdev); | |
1049 | extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
9f022ddf JG |
1050 | extern int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
1051 | extern int r100_gui_wait_for_idle(struct radeon_device *rdev); | |
1052 | extern void r100_ib_fini(struct radeon_device *rdev); | |
1053 | extern int r100_ib_init(struct radeon_device *rdev); | |
1054 | extern void r100_irq_disable(struct radeon_device *rdev); | |
1055 | extern int r100_irq_set(struct radeon_device *rdev); | |
1056 | extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); | |
1057 | extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); | |
21f9a437 | 1058 | extern void r100_vram_init_sizes(struct radeon_device *rdev); |
9f022ddf JG |
1059 | extern void r100_wb_disable(struct radeon_device *rdev); |
1060 | extern void r100_wb_fini(struct radeon_device *rdev); | |
1061 | extern int r100_wb_init(struct radeon_device *rdev); | |
d39c3b89 JG |
1062 | extern void r100_hdp_reset(struct radeon_device *rdev); |
1063 | extern int r100_rb2d_reset(struct radeon_device *rdev); | |
1064 | extern int r100_cp_reset(struct radeon_device *rdev); | |
ca6ffc64 | 1065 | extern void r100_vga_render_disable(struct radeon_device *rdev); |
207bf9e9 JG |
1066 | extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
1067 | struct radeon_cs_packet *pkt, | |
4c788679 | 1068 | struct radeon_bo *robj); |
207bf9e9 JG |
1069 | extern int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
1070 | struct radeon_cs_packet *pkt, | |
1071 | const unsigned *auth, unsigned n, | |
1072 | radeon_packet0_check_t check); | |
1073 | extern int r100_cs_packet_parse(struct radeon_cs_parser *p, | |
1074 | struct radeon_cs_packet *pkt, | |
1075 | unsigned idx); | |
17e15b0c | 1076 | extern void r100_enable_bm(struct radeon_device *rdev); |
92cde00c | 1077 | extern void r100_set_common_regs(struct radeon_device *rdev); |
9f022ddf | 1078 | |
d4550907 JG |
1079 | /* rv200,rv250,rv280 */ |
1080 | extern void r200_set_safe_registers(struct radeon_device *rdev); | |
9f022ddf JG |
1081 | |
1082 | /* r300,r350,rv350,rv370,rv380 */ | |
1083 | extern void r300_set_reg_safe(struct radeon_device *rdev); | |
1084 | extern void r300_mc_program(struct radeon_device *rdev); | |
1085 | extern void r300_vram_info(struct radeon_device *rdev); | |
ca6ffc64 JG |
1086 | extern void r300_clock_startup(struct radeon_device *rdev); |
1087 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); | |
4aac0473 JG |
1088 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
1089 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); | |
1090 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); | |
9f022ddf | 1091 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
a18d7ea1 | 1092 | |
905b6822 | 1093 | /* r420,r423,rv410 */ |
d39c3b89 | 1094 | extern int r420_mc_init(struct radeon_device *rdev); |
21f9a437 JG |
1095 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
1096 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
9f022ddf | 1097 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
d39c3b89 | 1098 | extern void r420_pipes_init(struct radeon_device *rdev); |
905b6822 | 1099 | |
21f9a437 | 1100 | /* rv515 */ |
d39c3b89 JG |
1101 | struct rv515_mc_save { |
1102 | u32 d1vga_control; | |
1103 | u32 d2vga_control; | |
1104 | u32 vga_render_control; | |
1105 | u32 vga_hdp_control; | |
1106 | u32 d1crtc_control; | |
1107 | u32 d2crtc_control; | |
1108 | }; | |
21f9a437 | 1109 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
d39c3b89 JG |
1110 | extern void rv515_vga_render_disable(struct radeon_device *rdev); |
1111 | extern void rv515_set_safe_registers(struct radeon_device *rdev); | |
f0ed1f65 JG |
1112 | extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
1113 | extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); | |
1114 | extern void rv515_clock_startup(struct radeon_device *rdev); | |
1115 | extern void rv515_debugfs(struct radeon_device *rdev); | |
1116 | extern int rv515_suspend(struct radeon_device *rdev); | |
21f9a437 | 1117 | |
3bc68535 JG |
1118 | /* rs400 */ |
1119 | extern int rs400_gart_init(struct radeon_device *rdev); | |
1120 | extern int rs400_gart_enable(struct radeon_device *rdev); | |
1121 | extern void rs400_gart_adjust_size(struct radeon_device *rdev); | |
1122 | extern void rs400_gart_disable(struct radeon_device *rdev); | |
1123 | extern void rs400_gart_fini(struct radeon_device *rdev); | |
1124 | ||
1125 | /* rs600 */ | |
1126 | extern void rs600_set_safe_registers(struct radeon_device *rdev); | |
ac447df4 JG |
1127 | extern int rs600_irq_set(struct radeon_device *rdev); |
1128 | extern void rs600_irq_disable(struct radeon_device *rdev); | |
3bc68535 | 1129 | |
21f9a437 JG |
1130 | /* rs690, rs740 */ |
1131 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, | |
1132 | struct drm_display_mode *mode1, | |
1133 | struct drm_display_mode *mode2); | |
1134 | ||
1135 | /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ | |
1136 | extern bool r600_card_posted(struct radeon_device *rdev); | |
1137 | extern void r600_cp_stop(struct radeon_device *rdev); | |
1138 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
1139 | extern int r600_cp_resume(struct radeon_device *rdev); | |
1140 | extern int r600_count_pipe_bits(uint32_t val); | |
1141 | extern int r600_gart_clear_page(struct radeon_device *rdev, int i); | |
1142 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); | |
4aac0473 | 1143 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
21f9a437 JG |
1144 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
1145 | extern int r600_ib_test(struct radeon_device *rdev); | |
1146 | extern int r600_ring_test(struct radeon_device *rdev); | |
21f9a437 | 1147 | extern void r600_wb_fini(struct radeon_device *rdev); |
81cc35bf JG |
1148 | extern int r600_wb_enable(struct radeon_device *rdev); |
1149 | extern void r600_wb_disable(struct radeon_device *rdev); | |
21f9a437 JG |
1150 | extern void r600_scratch_init(struct radeon_device *rdev); |
1151 | extern int r600_blit_init(struct radeon_device *rdev); | |
1152 | extern void r600_blit_fini(struct radeon_device *rdev); | |
d8f60cfc | 1153 | extern int r600_init_microcode(struct radeon_device *rdev); |
fe62e1a4 | 1154 | extern int r600_gpu_reset(struct radeon_device *rdev); |
d8f60cfc AD |
1155 | /* r600 irq */ |
1156 | extern int r600_irq_init(struct radeon_device *rdev); | |
1157 | extern void r600_irq_fini(struct radeon_device *rdev); | |
1158 | extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
1159 | extern int r600_irq_set(struct radeon_device *rdev); | |
21f9a437 | 1160 | |
dafc3bd5 CK |
1161 | extern int r600_audio_init(struct radeon_device *rdev); |
1162 | extern int r600_audio_tmds_index(struct drm_encoder *encoder); | |
1163 | extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); | |
1164 | extern void r600_audio_fini(struct radeon_device *rdev); | |
1165 | extern void r600_hdmi_init(struct drm_encoder *encoder); | |
1166 | extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable); | |
1167 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); | |
1168 | extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); | |
1169 | extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder, | |
1170 | int channels, | |
1171 | int rate, | |
1172 | int bps, | |
1173 | uint8_t status_bits, | |
1174 | uint8_t category_code); | |
1175 | ||
4c788679 JG |
1176 | #include "radeon_object.h" |
1177 | ||
771fe6b9 | 1178 | #endif |