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drm: dereference of tmp in drm_proc_create_files()
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / radeon.h
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771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31#include "radeon_object.h"
32
33/* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
36 * related to surface
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
45 */
46
47#include <asm/atomic.h>
48#include <linux/wait.h>
49#include <linux/list.h>
50#include <linux/kref.h>
51
52#include "radeon_mode.h"
53#include "radeon_reg.h"
068a117c 54#include "r300.h"
771fe6b9
JG		 55
56/*
57 * Modules parameters.
58 */
59extern int radeon_no_wb;
60extern int radeon_modeset;
61extern int radeon_dynclks;
62extern int radeon_r4xx_atom;
63extern int radeon_agpmode;
64extern int radeon_vram_limit;
65extern int radeon_gart_size;
66extern int radeon_benchmarking;
ecc0b326 67extern int radeon_testing;
771fe6b9
JG		 68extern int radeon_connector_table;
69
70/*
71 * Copy from radeon_drv.h so we don't have to include both and have conflicting
72 * symbol;
73 */
74#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
75#define RADEON_IB_POOL_SIZE 16
76#define RADEON_DEBUGFS_MAX_NUM_FILES 32
77#define RADEONFB_CONN_LIMIT 4
78
79enum radeon_family {
80 CHIP_R100,
81 CHIP_RV100,
82 CHIP_RS100,
83 CHIP_RV200,
84 CHIP_RS200,
85 CHIP_R200,
86 CHIP_RV250,
87 CHIP_RS300,
88 CHIP_RV280,
89 CHIP_R300,
90 CHIP_R350,
91 CHIP_RV350,
92 CHIP_RV380,
93 CHIP_R420,
94 CHIP_R423,
95 CHIP_RV410,
96 CHIP_RS400,
97 CHIP_RS480,
98 CHIP_RS600,
99 CHIP_RS690,
100 CHIP_RS740,
101 CHIP_RV515,
102 CHIP_R520,
103 CHIP_RV530,
104 CHIP_RV560,
105 CHIP_RV570,
106 CHIP_R580,
107 CHIP_R600,
108 CHIP_RV610,
109 CHIP_RV630,
110 CHIP_RV620,
111 CHIP_RV635,
112 CHIP_RV670,
113 CHIP_RS780,
114 CHIP_RV770,
115 CHIP_RV730,
116 CHIP_RV710,
c93bb85b 117 CHIP_RS880,
771fe6b9
JG		 118 CHIP_LAST,
119};
120
121enum radeon_chip_flags {
122 RADEON_FAMILY_MASK = 0x0000ffffUL,
123 RADEON_FLAGS_MASK = 0xffff0000UL,
124 RADEON_IS_MOBILITY = 0x00010000UL,
125 RADEON_IS_IGP = 0x00020000UL,
126 RADEON_SINGLE_CRTC = 0x00040000UL,
127 RADEON_IS_AGP = 0x00080000UL,
128 RADEON_HAS_HIERZ = 0x00100000UL,
129 RADEON_IS_PCIE = 0x00200000UL,
130 RADEON_NEW_MEMMAP = 0x00400000UL,
131 RADEON_IS_PCI = 0x00800000UL,
132 RADEON_IS_IGPGART = 0x01000000UL,
133};
134
135
136/*
137 * Errata workarounds.
138 */
139enum radeon_pll_errata {
140 CHIP_ERRATA_R300_CG = 0x00000001,
141 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
142 CHIP_ERRATA_PLL_DELAY = 0x00000004
143};
144
145
146struct radeon_device;
147
148
149/*
150 * BIOS.
151 */
152bool radeon_get_bios(struct radeon_device *rdev);
153
154/*
155 * Clocks
156 */
157
158struct radeon_clock {
159 struct radeon_pll p1pll;
160 struct radeon_pll p2pll;
161 struct radeon_pll spll;
162 struct radeon_pll mpll;
163 /* 10 Khz units */
164 uint32_t default_mclk;
165 uint32_t default_sclk;
166};
167
168/*
169 * Fences.
170 */
171struct radeon_fence_driver {
172 uint32_t scratch_reg;
173 atomic_t seq;
174 uint32_t last_seq;
175 unsigned long count_timeout;
176 wait_queue_head_t queue;
177 rwlock_t lock;
178 struct list_head created;
179 struct list_head emited;
180 struct list_head signaled;
181};
182
183struct radeon_fence {
184 struct radeon_device *rdev;
185 struct kref kref;
186 struct list_head list;
187 /* protected by radeon_fence.lock */
188 uint32_t seq;
189 unsigned long timeout;
190 bool emited;
191 bool signaled;
192};
193
194int radeon_fence_driver_init(struct radeon_device *rdev);
195void radeon_fence_driver_fini(struct radeon_device *rdev);
196int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
197int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
198void radeon_fence_process(struct radeon_device *rdev);
199bool radeon_fence_signaled(struct radeon_fence *fence);
200int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
201int radeon_fence_wait_next(struct radeon_device *rdev);
202int radeon_fence_wait_last(struct radeon_device *rdev);
203struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
204void radeon_fence_unref(struct radeon_fence **fence);
205
e024e110
DA		 206/*
207 * Tiling registers
208 */
209struct radeon_surface_reg {
210 struct radeon_object *robj;
211};
212
213#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 214
215/*
216 * Radeon buffer.
217 */
218struct radeon_object;
219
220struct radeon_object_list {
221 struct list_head list;
222 struct radeon_object *robj;
223 uint64_t gpu_offset;
224 unsigned rdomain;
225 unsigned wdomain;
e024e110 226 uint32_t tiling_flags;
771fe6b9
JG		 227};
228
229int radeon_object_init(struct radeon_device *rdev);
230void radeon_object_fini(struct radeon_device *rdev);
231int radeon_object_create(struct radeon_device *rdev,
232 struct drm_gem_object *gobj,
233 unsigned long size,
234 bool kernel,
235 uint32_t domain,
236 bool interruptible,
237 struct radeon_object **robj_ptr);
238int radeon_object_kmap(struct radeon_object *robj, void **ptr);
239void radeon_object_kunmap(struct radeon_object *robj);
240void radeon_object_unref(struct radeon_object **robj);
241int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
242 uint64_t *gpu_addr);
243void radeon_object_unpin(struct radeon_object *robj);
244int radeon_object_wait(struct radeon_object *robj);
cefb87ef 245int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
771fe6b9
JG		 246int radeon_object_evict_vram(struct radeon_device *rdev);
247int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
248void radeon_object_force_delete(struct radeon_device *rdev);
249void radeon_object_list_add_object(struct radeon_object_list *lobj,
250 struct list_head *head);
251int radeon_object_list_validate(struct list_head *head, void *fence);
252void radeon_object_list_unvalidate(struct list_head *head);
253void radeon_object_list_clean(struct list_head *head);
254int radeon_object_fbdev_mmap(struct radeon_object *robj,
255 struct vm_area_struct *vma);
256unsigned long radeon_object_size(struct radeon_object *robj);
e024e110
DA		 257void radeon_object_clear_surface_reg(struct radeon_object *robj);
258int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
259 bool force_drop);
260void radeon_object_set_tiling_flags(struct radeon_object *robj,
261 uint32_t tiling_flags, uint32_t pitch);
262void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
263void radeon_bo_move_notify(struct ttm_buffer_object *bo,
264 struct ttm_mem_reg *mem);
265void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
771fe6b9
JG		 266/*
267 * GEM objects.
268 */
269struct radeon_gem {
270 struct list_head objects;
271};
272
273int radeon_gem_init(struct radeon_device *rdev);
274void radeon_gem_fini(struct radeon_device *rdev);
275int radeon_gem_object_create(struct radeon_device *rdev, int size,
276 int alignment, int initial_domain,
277 bool discardable, bool kernel,
278 bool interruptible,
279 struct drm_gem_object **obj);
280int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
281 uint64_t *gpu_addr);
282void radeon_gem_object_unpin(struct drm_gem_object *obj);
283
284
285/*
286 * GART structures, functions & helpers
287 */
288struct radeon_mc;
289
290struct radeon_gart_table_ram {
291 volatile uint32_t *ptr;
292};
293
294struct radeon_gart_table_vram {
295 struct radeon_object *robj;
296 volatile uint32_t *ptr;
297};
298
299union radeon_gart_table {
300 struct radeon_gart_table_ram ram;
301 struct radeon_gart_table_vram vram;
302};
303
304struct radeon_gart {
305 dma_addr_t table_addr;
306 unsigned num_gpu_pages;
307 unsigned num_cpu_pages;
308 unsigned table_size;
309 union radeon_gart_table table;
310 struct page **pages;
311 dma_addr_t *pages_addr;
312 bool ready;
313};
314
315int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
316void radeon_gart_table_ram_free(struct radeon_device *rdev);
317int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
318void radeon_gart_table_vram_free(struct radeon_device *rdev);
319int radeon_gart_init(struct radeon_device *rdev);
320void radeon_gart_fini(struct radeon_device *rdev);
321void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
322 int pages);
323int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
324 int pages, struct page **pagelist);
325
326
327/*
328 * GPU MC structures, functions & helpers
329 */
330struct radeon_mc {
331 resource_size_t aper_size;
332 resource_size_t aper_base;
333 resource_size_t agp_base;
334 unsigned gtt_location;
335 unsigned gtt_size;
336 unsigned vram_location;
7a50f01a
DA		 337 /* for some chips with <= 32MB we need to lie
338 * about vram size near mc fb location */
339 unsigned mc_vram_size;
771fe6b9 340 unsigned vram_width;
7a50f01a 341 unsigned real_vram_size;
771fe6b9
JG		 342 int vram_mtrr;
343 bool vram_is_ddr;
344};
345
346int radeon_mc_setup(struct radeon_device *rdev);
347
348
349/*
350 * GPU scratch registers structures, functions & helpers
351 */
352struct radeon_scratch {
353 unsigned num_reg;
354 bool free[32];
355 uint32_t reg[32];
356};
357
358int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
359void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
360
361
362/*
363 * IRQS.
364 */
365struct radeon_irq {
366 bool installed;
367 bool sw_int;
368 /* FIXME: use a define max crtc rather than hardcode it */
369 bool crtc_vblank_int[2];
370};
371
372int radeon_irq_kms_init(struct radeon_device *rdev);
373void radeon_irq_kms_fini(struct radeon_device *rdev);
374
375
376/*
377 * CP & ring.
378 */
379struct radeon_ib {
380 struct list_head list;
381 unsigned long idx;
382 uint64_t gpu_addr;
383 struct radeon_fence *fence;
384 volatile uint32_t *ptr;
385 uint32_t length_dw;
386};
387
388struct radeon_ib_pool {
389 struct mutex mutex;
390 struct radeon_object *robj;
391 struct list_head scheduled_ibs;
392 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
393 bool ready;
394 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
395};
396
397struct radeon_cp {
398 struct radeon_object *ring_obj;
399 volatile uint32_t *ring;
400 unsigned rptr;
401 unsigned wptr;
402 unsigned wptr_old;
403 unsigned ring_size;
404 unsigned ring_free_dw;
405 int count_dw;
406 uint64_t gpu_addr;
407 uint32_t align_mask;
408 uint32_t ptr_mask;
409 struct mutex mutex;
410 bool ready;
411};
412
413int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
414void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
415int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
416int radeon_ib_pool_init(struct radeon_device *rdev);
417void radeon_ib_pool_fini(struct radeon_device *rdev);
418int radeon_ib_test(struct radeon_device *rdev);
419/* Ring access between begin & end cannot sleep */
420void radeon_ring_free_size(struct radeon_device *rdev);
421int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
422void radeon_ring_unlock_commit(struct radeon_device *rdev);
423void radeon_ring_unlock_undo(struct radeon_device *rdev);
424int radeon_ring_test(struct radeon_device *rdev);
425int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
426void radeon_ring_fini(struct radeon_device *rdev);
427
428
429/*
430 * CS.
431 */
432struct radeon_cs_reloc {
433 struct drm_gem_object *gobj;
434 struct radeon_object *robj;
435 struct radeon_object_list lobj;
436 uint32_t handle;
437 uint32_t flags;
438};
439
440struct radeon_cs_chunk {
441 uint32_t chunk_id;
442 uint32_t length_dw;
443 uint32_t *kdata;
444};
445
446struct radeon_cs_parser {
447 struct radeon_device *rdev;
448 struct drm_file *filp;
449 /* chunks */
450 unsigned nchunks;
451 struct radeon_cs_chunk *chunks;
452 uint64_t *chunks_array;
453 /* IB */
454 unsigned idx;
455 /* relocations */
456 unsigned nrelocs;
457 struct radeon_cs_reloc *relocs;
458 struct radeon_cs_reloc **relocs_ptr;
459 struct list_head validated;
460 /* indices of various chunks */
461 int chunk_ib_idx;
462 int chunk_relocs_idx;
463 struct radeon_ib *ib;
464 void *track;
465};
466
467struct radeon_cs_packet {
468 unsigned idx;
469 unsigned type;
470 unsigned reg;
471 unsigned opcode;
472 int count;
473 unsigned one_reg_wr;
474};
475
476typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
477 struct radeon_cs_packet *pkt,
478 unsigned idx, unsigned reg);
479typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
480 struct radeon_cs_packet *pkt);
481
482
483/*
484 * AGP
485 */
486int radeon_agp_init(struct radeon_device *rdev);
487void radeon_agp_fini(struct radeon_device *rdev);
488
489
490/*
491 * Writeback
492 */
493struct radeon_wb {
494 struct radeon_object *wb_obj;
495 volatile uint32_t *wb;
496 uint64_t gpu_addr;
497};
498
c93bb85b
JG		 499/**
500 * struct radeon_pm - power management datas
501 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
502 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
503 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
504 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
505 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
506 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
507 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
508 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
509 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
510 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
511 * @needed_bandwidth: current bandwidth needs
512 *
513 * It keeps track of various data needed to take powermanagement decision.
514 * Bandwith need is used to determine minimun clock of the GPU and memory.
515 * Equation between gpu/memory clock and available bandwidth is hw dependent
516 * (type of memory, bus size, efficiency, ...)
517 */
518struct radeon_pm {
519 fixed20_12 max_bandwidth;
520 fixed20_12 igp_sideport_mclk;
521 fixed20_12 igp_system_mclk;
522 fixed20_12 igp_ht_link_clk;
523 fixed20_12 igp_ht_link_width;
524 fixed20_12 k8_bandwidth;
525 fixed20_12 sideport_bandwidth;
526 fixed20_12 ht_bandwidth;
527 fixed20_12 core_bandwidth;
528 fixed20_12 sclk;
529 fixed20_12 needed_bandwidth;
530};
531
771fe6b9
JG		 532
533/*
534 * Benchmarking
535 */
536void radeon_benchmark(struct radeon_device *rdev);
537
538
ecc0b326
MD		 539/*
540 * Testing
541 */
542void radeon_test_moves(struct radeon_device *rdev);
543
544
771fe6b9
JG		 545/*
546 * Debugfs
547 */
548int radeon_debugfs_add_files(struct radeon_device *rdev,
549 struct drm_info_list *files,
550 unsigned nfiles);
551int radeon_debugfs_fence_init(struct radeon_device *rdev);
552int r100_debugfs_rbbm_init(struct radeon_device *rdev);
553int r100_debugfs_cp_init(struct radeon_device *rdev);
554
555
556/*
557 * ASIC specific functions.
558 */
559struct radeon_asic {
068a117c 560 int (*init)(struct radeon_device *rdev);
771fe6b9
JG		 561 void (*errata)(struct radeon_device *rdev);
562 void (*vram_info)(struct radeon_device *rdev);
563 int (*gpu_reset)(struct radeon_device *rdev);
564 int (*mc_init)(struct radeon_device *rdev);
565 void (*mc_fini)(struct radeon_device *rdev);
566 int (*wb_init)(struct radeon_device *rdev);
567 void (*wb_fini)(struct radeon_device *rdev);
568 int (*gart_enable)(struct radeon_device *rdev);
569 void (*gart_disable)(struct radeon_device *rdev);
570 void (*gart_tlb_flush)(struct radeon_device *rdev);
571 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
572 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
573 void (*cp_fini)(struct radeon_device *rdev);
574 void (*cp_disable)(struct radeon_device *rdev);
575 void (*ring_start)(struct radeon_device *rdev);
576 int (*irq_set)(struct radeon_device *rdev);
577 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 578 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 579 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
580 int (*cs_parse)(struct radeon_cs_parser *p);
581 int (*copy_blit)(struct radeon_device *rdev,
582 uint64_t src_offset,
583 uint64_t dst_offset,
584 unsigned num_pages,
585 struct radeon_fence *fence);
586 int (*copy_dma)(struct radeon_device *rdev,
587 uint64_t src_offset,
588 uint64_t dst_offset,
589 unsigned num_pages,
590 struct radeon_fence *fence);
591 int (*copy)(struct radeon_device *rdev,
592 uint64_t src_offset,
593 uint64_t dst_offset,
594 unsigned num_pages,
595 struct radeon_fence *fence);
596 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
597 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
598 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
599 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 600 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
601 uint32_t tiling_flags, uint32_t pitch,
602 uint32_t offset, uint32_t obj_size);
603 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 604 void (*bandwidth_update)(struct radeon_device *rdev);
771fe6b9
JG		 605};
606
068a117c
JG		 607union radeon_asic_config {
608 struct r300_asic r300;
609};
610
771fe6b9
JG		 611
612/*
613 * IOCTL.
614 */
615int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
616 struct drm_file *filp);
617int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
618 struct drm_file *filp);
619int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
620 struct drm_file *file_priv);
621int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
622 struct drm_file *file_priv);
623int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
624 struct drm_file *file_priv);
625int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
626 struct drm_file *file_priv);
627int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
628 struct drm_file *filp);
629int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
630 struct drm_file *filp);
631int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
632 struct drm_file *filp);
633int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
634 struct drm_file *filp);
635int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 636int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
637 struct drm_file *filp);
638int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
639 struct drm_file *filp);
771fe6b9
JG		 640
641
642/*
643 * Core structure, functions and helpers.
644 */
645typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
646typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
647
648struct radeon_device {
649 struct drm_device *ddev;
650 struct pci_dev *pdev;
651 /* ASIC */
068a117c 652 union radeon_asic_config config;
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JG		 653 enum radeon_family family;
654 unsigned long flags;
655 int usec_timeout;
656 enum radeon_pll_errata pll_errata;
657 int num_gb_pipes;
658 int disp_priority;
659 /* BIOS */
660 uint8_t *bios;
661 bool is_atom_bios;
662 uint16_t bios_header_start;
663 struct radeon_object *stollen_vga_memory;
664 struct fb_info *fbdev_info;
665 struct radeon_object *fbdev_robj;
666 struct radeon_framebuffer *fbdev_rfb;
667 /* Register mmio */
4c9bc75c
DA		 668 resource_size_t rmmio_base;
669 resource_size_t rmmio_size;
771fe6b9 670 void *rmmio;
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JG		 671 radeon_rreg_t mc_rreg;
672 radeon_wreg_t mc_wreg;
673 radeon_rreg_t pll_rreg;
674 radeon_wreg_t pll_wreg;
de1b2898 675 uint32_t pcie_reg_mask;
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JG		 676 radeon_rreg_t pciep_rreg;
677 radeon_wreg_t pciep_wreg;
678 struct radeon_clock clock;
679 struct radeon_mc mc;
680 struct radeon_gart gart;
681 struct radeon_mode_info mode_info;
682 struct radeon_scratch scratch;
683 struct radeon_mman mman;
684 struct radeon_fence_driver fence_drv;
685 struct radeon_cp cp;
686 struct radeon_ib_pool ib_pool;
687 struct radeon_irq irq;
688 struct radeon_asic *asic;
689 struct radeon_gem gem;
c93bb85b 690 struct radeon_pm pm;
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JG		 691 struct mutex cs_mutex;
692 struct radeon_wb wb;
693 bool gpu_lockup;
694 bool shutdown;
695 bool suspend;
ad49f501 696 bool need_dma32;
e024e110 697 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
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JG		 698};
699
700int radeon_device_init(struct radeon_device *rdev,
701 struct drm_device *ddev,
702 struct pci_dev *pdev,
703 uint32_t flags);
704void radeon_device_fini(struct radeon_device *rdev);
705int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
706
de1b2898
DA		 707static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
708{
709 if (reg < 0x10000)
710 return readl(((void __iomem *)rdev->rmmio) + reg);
711 else {
712 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
713 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
714 }
715}
716
717static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
718{
719 if (reg < 0x10000)
720 writel(v, ((void __iomem *)rdev->rmmio) + reg);
721 else {
722 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
723 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
724 }
725}
726
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JG		 727
728/*
729 * Registers read & write functions.
730 */
731#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
732#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
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DA		 733#define RREG32(reg) r100_mm_rreg(rdev, (reg))
734#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
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JG		 735#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
736#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
737#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
738#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
739#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
740#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
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DA		 741#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
742#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
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JG		 743#define WREG32_P(reg, val, mask) \
744 do { \
745 uint32_t tmp_ = RREG32(reg); \
746 tmp_ &= (mask); \
747 tmp_ |= ((val) & ~(mask)); \
748 WREG32(reg, tmp_); \
749 } while (0)
750#define WREG32_PLL_P(reg, val, mask) \
751 do { \
752 uint32_t tmp_ = RREG32_PLL(reg); \
753 tmp_ &= (mask); \
754 tmp_ |= ((val) & ~(mask)); \
755 WREG32_PLL(reg, tmp_); \
756 } while (0)
757
de1b2898
DA		 758/*
759 * Indirect registers accessor
760 */
761static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
762{
763 uint32_t r;
764
765 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
766 r = RREG32(RADEON_PCIE_DATA);
767 return r;
768}
769
770static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
771{
772 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
773 WREG32(RADEON_PCIE_DATA, (v));
774}
775
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JG		 776void r100_pll_errata_after_index(struct radeon_device *rdev);
777
778
779/*
780 * ASICs helpers.
781 */
b995e433
DA		 782#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
783 (rdev->pdev->device == 0x5969))
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JG		 784#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
785 (rdev->family == CHIP_RV200) || \
786 (rdev->family == CHIP_RS100) || \
787 (rdev->family == CHIP_RS200) || \
788 (rdev->family == CHIP_RV250) || \
789 (rdev->family == CHIP_RV280) || \
790 (rdev->family == CHIP_RS300))
791#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
792 (rdev->family == CHIP_RV350) || \
793 (rdev->family == CHIP_R350) || \
794 (rdev->family == CHIP_RV380) || \
795 (rdev->family == CHIP_R420) || \
796 (rdev->family == CHIP_R423) || \
797 (rdev->family == CHIP_RV410) || \
798 (rdev->family == CHIP_RS400) || \
799 (rdev->family == CHIP_RS480))
800#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
801#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
802#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
803
804
805/*
806 * BIOS helpers.
807 */
808#define RBIOS8(i) (rdev->bios[i])
809#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
810#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
811
812int radeon_combios_init(struct radeon_device *rdev);
813void radeon_combios_fini(struct radeon_device *rdev);
814int radeon_atombios_init(struct radeon_device *rdev);
815void radeon_atombios_fini(struct radeon_device *rdev);
816
817
818/*
819 * RING helpers.
820 */
821#define CP_PACKET0 0x00000000
822#define PACKET0_BASE_INDEX_SHIFT 0
823#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
824#define PACKET0_COUNT_SHIFT 16
825#define PACKET0_COUNT_MASK (0x3fff << 16)
826#define CP_PACKET1 0x40000000
827#define CP_PACKET2 0x80000000
828#define PACKET2_PAD_SHIFT 0
829#define PACKET2_PAD_MASK (0x3fffffff << 0)
830#define CP_PACKET3 0xC0000000
831#define PACKET3_IT_OPCODE_SHIFT 8
832#define PACKET3_IT_OPCODE_MASK (0xff << 8)
833#define PACKET3_COUNT_SHIFT 16
834#define PACKET3_COUNT_MASK (0x3fff << 16)
835/* PACKET3 op code */
836#define PACKET3_NOP 0x10
837#define PACKET3_3D_DRAW_VBUF 0x28
838#define PACKET3_3D_DRAW_IMMD 0x29
839#define PACKET3_3D_DRAW_INDX 0x2A
840#define PACKET3_3D_LOAD_VBPNTR 0x2F
841#define PACKET3_INDX_BUFFER 0x33
842#define PACKET3_3D_DRAW_VBUF_2 0x34
843#define PACKET3_3D_DRAW_IMMD_2 0x35
844#define PACKET3_3D_DRAW_INDX_2 0x36
845#define PACKET3_BITBLT_MULTI 0x9B
846
847#define PACKET0(reg, n) (CP_PACKET0 | \
848 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
849 REG_SET(PACKET0_COUNT, (n)))
850#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
851#define PACKET3(op, n) (CP_PACKET3 | \
852 REG_SET(PACKET3_IT_OPCODE, (op)) | \
853 REG_SET(PACKET3_COUNT, (n)))
854
855#define PACKET_TYPE0 0
856#define PACKET_TYPE1 1
857#define PACKET_TYPE2 2
858#define PACKET_TYPE3 3
859
860#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
861#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
862#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
863#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
864#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
865
866static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
867{
868#if DRM_DEBUG_CODE
869 if (rdev->cp.count_dw <= 0) {
870 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
871 }
872#endif
873 rdev->cp.ring[rdev->cp.wptr++] = v;
874 rdev->cp.wptr &= rdev->cp.ptr_mask;
875 rdev->cp.count_dw--;
876 rdev->cp.ring_free_dw--;
877}
878
879
880/*
881 * ASICs macro.
882 */
068a117c 883#define radeon_init(rdev) (rdev)->asic->init((rdev))
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JG		 884#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
885#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
886#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
887#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
888#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
889#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
890#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
891#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
892#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
893#define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
894#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
895#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
896#define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
897#define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
898#define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
899#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
900#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
901#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 902#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
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JG		 903#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
904#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
905#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
906#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
907#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
908#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
909#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
910#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 911#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
912#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 913#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
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JG		 914
915#endif
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