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Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __RADEON_H__ | |
29 | #define __RADEON_H__ | |
30 | ||
771fe6b9 JG |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should | |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings | |
34 | * related to surface | |
35 | * - WB : write back stuff (do it bit like scratch reg things) | |
36 | * - Vblank : look at Jesse's rework and what we should do | |
37 | * - r600/r700: gart & cp | |
38 | * - cs : clean cs ioctl use bitmap & things like that. | |
39 | * - power management stuff | |
40 | * - Barrier in gart code | |
41 | * - Unmappabled vram ? | |
42 | * - TESTING, TESTING, TESTING | |
43 | */ | |
44 | ||
d39c3b89 JG |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various | |
47 | * reasons even thought we work hard to make it works on most | |
48 | * configurations. In order to still have a working userspace in such | |
49 | * situation the init path must succeed up to the memory controller | |
50 | * initialization point. Failure before this point are considered as | |
51 | * fatal error. Here is the init callchain : | |
52 | * radeon_device_init perform common structure, mutex initialization | |
53 | * asic_init setup the GPU memory layout and perform all | |
54 | * one time initialization (failure in this | |
55 | * function are considered fatal) | |
56 | * asic_startup setup the GPU acceleration, in order to | |
57 | * follow guideline the first thing this | |
58 | * function should do is setting the GPU | |
59 | * memory controller (only MC setup failure | |
60 | * are considered as fatal) | |
61 | */ | |
62 | ||
60063497 | 63 | #include <linux/atomic.h> |
771fe6b9 JG |
64 | #include <linux/wait.h> |
65 | #include <linux/list.h> | |
66 | #include <linux/kref.h> | |
67 | ||
4c788679 JG |
68 | #include <ttm/ttm_bo_api.h> |
69 | #include <ttm/ttm_bo_driver.h> | |
70 | #include <ttm/ttm_placement.h> | |
71 | #include <ttm/ttm_module.h> | |
147666fb | 72 | #include <ttm/ttm_execbuf_util.h> |
4c788679 | 73 | |
c2142715 | 74 | #include "radeon_family.h" |
771fe6b9 JG |
75 | #include "radeon_mode.h" |
76 | #include "radeon_reg.h" | |
771fe6b9 JG |
77 | |
78 | /* | |
79 | * Modules parameters. | |
80 | */ | |
81 | extern int radeon_no_wb; | |
82 | extern int radeon_modeset; | |
83 | extern int radeon_dynclks; | |
84 | extern int radeon_r4xx_atom; | |
85 | extern int radeon_agpmode; | |
86 | extern int radeon_vram_limit; | |
87 | extern int radeon_gart_size; | |
88 | extern int radeon_benchmarking; | |
ecc0b326 | 89 | extern int radeon_testing; |
771fe6b9 | 90 | extern int radeon_connector_table; |
4ce001ab | 91 | extern int radeon_tv; |
dafc3bd5 | 92 | extern int radeon_audio; |
f46c0120 | 93 | extern int radeon_disp_priority; |
e2b0a8e1 | 94 | extern int radeon_hw_i2c; |
d42dd579 | 95 | extern int radeon_pcie_gen2; |
a18cee15 | 96 | extern int radeon_msi; |
771fe6b9 JG |
97 | |
98 | /* | |
99 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | |
100 | * symbol; | |
101 | */ | |
102 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ | |
225758d8 | 103 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
e821767b | 104 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
771fe6b9 | 105 | #define RADEON_IB_POOL_SIZE 16 |
c245cb9e | 106 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 |
771fe6b9 | 107 | #define RADEONFB_CONN_LIMIT 4 |
f657c2a7 | 108 | #define RADEON_BIOS_NUM_SCRATCH 8 |
771fe6b9 | 109 | |
771fe6b9 JG |
110 | /* |
111 | * Errata workarounds. | |
112 | */ | |
113 | enum radeon_pll_errata { | |
114 | CHIP_ERRATA_R300_CG = 0x00000001, | |
115 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, | |
116 | CHIP_ERRATA_PLL_DELAY = 0x00000004 | |
117 | }; | |
118 | ||
119 | ||
120 | struct radeon_device; | |
121 | ||
122 | ||
123 | /* | |
124 | * BIOS. | |
125 | */ | |
6a9ee8af DA |
126 | #define ATRM_BIOS_PAGE 4096 |
127 | ||
8edb381d | 128 | #if defined(CONFIG_VGA_SWITCHEROO) |
6a9ee8af DA |
129 | bool radeon_atrm_supported(struct pci_dev *pdev); |
130 | int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); | |
8edb381d DA |
131 | #else |
132 | static inline bool radeon_atrm_supported(struct pci_dev *pdev) | |
133 | { | |
134 | return false; | |
135 | } | |
136 | ||
137 | static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){ | |
138 | return -EINVAL; | |
139 | } | |
140 | #endif | |
771fe6b9 JG |
141 | bool radeon_get_bios(struct radeon_device *rdev); |
142 | ||
3ce0a23d | 143 | |
771fe6b9 | 144 | /* |
3ce0a23d | 145 | * Dummy page |
771fe6b9 | 146 | */ |
3ce0a23d JG |
147 | struct radeon_dummy_page { |
148 | struct page *page; | |
149 | dma_addr_t addr; | |
150 | }; | |
151 | int radeon_dummy_page_init(struct radeon_device *rdev); | |
152 | void radeon_dummy_page_fini(struct radeon_device *rdev); | |
153 | ||
771fe6b9 | 154 | |
3ce0a23d JG |
155 | /* |
156 | * Clocks | |
157 | */ | |
771fe6b9 JG |
158 | struct radeon_clock { |
159 | struct radeon_pll p1pll; | |
160 | struct radeon_pll p2pll; | |
bcc1c2a1 | 161 | struct radeon_pll dcpll; |
771fe6b9 JG |
162 | struct radeon_pll spll; |
163 | struct radeon_pll mpll; | |
164 | /* 10 Khz units */ | |
165 | uint32_t default_mclk; | |
166 | uint32_t default_sclk; | |
bcc1c2a1 AD |
167 | uint32_t default_dispclk; |
168 | uint32_t dp_extclk; | |
b20f9bef | 169 | uint32_t max_pixel_clock; |
771fe6b9 JG |
170 | }; |
171 | ||
7433874e RM |
172 | /* |
173 | * Power management | |
174 | */ | |
175 | int radeon_pm_init(struct radeon_device *rdev); | |
29fb52ca | 176 | void radeon_pm_fini(struct radeon_device *rdev); |
c913e23a | 177 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
ce8f5370 AD |
178 | void radeon_pm_suspend(struct radeon_device *rdev); |
179 | void radeon_pm_resume(struct radeon_device *rdev); | |
56278a8e AD |
180 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
181 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); | |
8a83ec5e | 182 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
ee4017f4 | 183 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage); |
f892034a | 184 | void rs690_pm_info(struct radeon_device *rdev); |
20d391d7 AD |
185 | extern int rv6xx_get_temp(struct radeon_device *rdev); |
186 | extern int rv770_get_temp(struct radeon_device *rdev); | |
187 | extern int evergreen_get_temp(struct radeon_device *rdev); | |
188 | extern int sumo_get_temp(struct radeon_device *rdev); | |
3ce0a23d | 189 | |
771fe6b9 JG |
190 | /* |
191 | * Fences. | |
192 | */ | |
193 | struct radeon_fence_driver { | |
194 | uint32_t scratch_reg; | |
195 | atomic_t seq; | |
196 | uint32_t last_seq; | |
225758d8 JG |
197 | unsigned long last_jiffies; |
198 | unsigned long last_timeout; | |
771fe6b9 | 199 | wait_queue_head_t queue; |
771fe6b9 | 200 | struct list_head created; |
851a6bd9 | 201 | struct list_head emitted; |
771fe6b9 | 202 | struct list_head signaled; |
0a0c7596 | 203 | bool initialized; |
771fe6b9 JG |
204 | }; |
205 | ||
206 | struct radeon_fence { | |
207 | struct radeon_device *rdev; | |
208 | struct kref kref; | |
209 | struct list_head list; | |
210 | /* protected by radeon_fence.lock */ | |
211 | uint32_t seq; | |
851a6bd9 | 212 | bool emitted; |
771fe6b9 | 213 | bool signaled; |
7465280c AD |
214 | /* RB, DMA, etc. */ |
215 | int ring; | |
771fe6b9 JG |
216 | }; |
217 | ||
7465280c | 218 | int radeon_fence_driver_init(struct radeon_device *rdev, int num_rings); |
771fe6b9 | 219 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
7465280c | 220 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
771fe6b9 | 221 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); |
7465280c | 222 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
771fe6b9 JG |
223 | bool radeon_fence_signaled(struct radeon_fence *fence); |
224 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); | |
7465280c AD |
225 | int radeon_fence_wait_next(struct radeon_device *rdev, int ring); |
226 | int radeon_fence_wait_last(struct radeon_device *rdev, int ring); | |
771fe6b9 JG |
227 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
228 | void radeon_fence_unref(struct radeon_fence **fence); | |
229 | ||
15d3332f CK |
230 | /* |
231 | * Semaphores. | |
232 | */ | |
7b1f2485 CK |
233 | struct radeon_cp; |
234 | ||
15d3332f CK |
235 | struct radeon_semaphore_driver { |
236 | rwlock_t lock; | |
237 | struct list_head free; | |
238 | }; | |
239 | ||
240 | struct radeon_semaphore { | |
241 | struct radeon_bo *robj; | |
242 | struct list_head list; | |
243 | uint64_t gpu_addr; | |
244 | }; | |
245 | ||
246 | void radeon_semaphore_driver_fini(struct radeon_device *rdev); | |
247 | int radeon_semaphore_create(struct radeon_device *rdev, | |
248 | struct radeon_semaphore **semaphore); | |
249 | void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, | |
250 | struct radeon_semaphore *semaphore); | |
251 | void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, | |
252 | struct radeon_semaphore *semaphore); | |
253 | void radeon_semaphore_free(struct radeon_device *rdev, | |
254 | struct radeon_semaphore *semaphore); | |
255 | ||
e024e110 DA |
256 | /* |
257 | * Tiling registers | |
258 | */ | |
259 | struct radeon_surface_reg { | |
4c788679 | 260 | struct radeon_bo *bo; |
e024e110 DA |
261 | }; |
262 | ||
263 | #define RADEON_GEM_MAX_SURFACES 8 | |
771fe6b9 JG |
264 | |
265 | /* | |
4c788679 | 266 | * TTM. |
771fe6b9 | 267 | */ |
4c788679 JG |
268 | struct radeon_mman { |
269 | struct ttm_bo_global_ref bo_global_ref; | |
ba4420c2 | 270 | struct drm_global_reference mem_global_ref; |
4c788679 | 271 | struct ttm_bo_device bdev; |
0a0c7596 JG |
272 | bool mem_global_referenced; |
273 | bool initialized; | |
4c788679 JG |
274 | }; |
275 | ||
276 | struct radeon_bo { | |
277 | /* Protected by gem.mutex */ | |
278 | struct list_head list; | |
279 | /* Protected by tbo.reserved */ | |
312ea8da JG |
280 | u32 placements[3]; |
281 | struct ttm_placement placement; | |
4c788679 JG |
282 | struct ttm_buffer_object tbo; |
283 | struct ttm_bo_kmap_obj kmap; | |
284 | unsigned pin_count; | |
285 | void *kptr; | |
286 | u32 tiling_flags; | |
287 | u32 pitch; | |
288 | int surface_reg; | |
289 | /* Constant after initialization */ | |
290 | struct radeon_device *rdev; | |
441921d5 | 291 | struct drm_gem_object gem_base; |
4c788679 | 292 | }; |
7e4d15d9 | 293 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
771fe6b9 | 294 | |
4c788679 | 295 | struct radeon_bo_list { |
147666fb | 296 | struct ttm_validate_buffer tv; |
4c788679 | 297 | struct radeon_bo *bo; |
771fe6b9 JG |
298 | uint64_t gpu_offset; |
299 | unsigned rdomain; | |
300 | unsigned wdomain; | |
4c788679 | 301 | u32 tiling_flags; |
771fe6b9 JG |
302 | }; |
303 | ||
771fe6b9 JG |
304 | /* |
305 | * GEM objects. | |
306 | */ | |
307 | struct radeon_gem { | |
4c788679 | 308 | struct mutex mutex; |
771fe6b9 JG |
309 | struct list_head objects; |
310 | }; | |
311 | ||
312 | int radeon_gem_init(struct radeon_device *rdev); | |
313 | void radeon_gem_fini(struct radeon_device *rdev); | |
314 | int radeon_gem_object_create(struct radeon_device *rdev, int size, | |
4c788679 JG |
315 | int alignment, int initial_domain, |
316 | bool discardable, bool kernel, | |
317 | struct drm_gem_object **obj); | |
771fe6b9 JG |
318 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
319 | uint64_t *gpu_addr); | |
320 | void radeon_gem_object_unpin(struct drm_gem_object *obj); | |
321 | ||
ff72145b DA |
322 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
323 | struct drm_device *dev, | |
324 | struct drm_mode_create_dumb *args); | |
325 | int radeon_mode_dumb_mmap(struct drm_file *filp, | |
326 | struct drm_device *dev, | |
327 | uint32_t handle, uint64_t *offset_p); | |
328 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, | |
329 | struct drm_device *dev, | |
330 | uint32_t handle); | |
771fe6b9 JG |
331 | |
332 | /* | |
333 | * GART structures, functions & helpers | |
334 | */ | |
335 | struct radeon_mc; | |
336 | ||
a77f1718 | 337 | #define RADEON_GPU_PAGE_SIZE 4096 |
d594e46a | 338 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
003cefe0 | 339 | #define RADEON_GPU_PAGE_SHIFT 12 |
a77f1718 | 340 | |
771fe6b9 JG |
341 | struct radeon_gart { |
342 | dma_addr_t table_addr; | |
c9a1be96 JG |
343 | struct radeon_bo *robj; |
344 | void *ptr; | |
771fe6b9 JG |
345 | unsigned num_gpu_pages; |
346 | unsigned num_cpu_pages; | |
347 | unsigned table_size; | |
771fe6b9 JG |
348 | struct page **pages; |
349 | dma_addr_t *pages_addr; | |
350 | bool ready; | |
351 | }; | |
352 | ||
353 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); | |
354 | void radeon_gart_table_ram_free(struct radeon_device *rdev); | |
355 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); | |
356 | void radeon_gart_table_vram_free(struct radeon_device *rdev); | |
c9a1be96 JG |
357 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
358 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); | |
771fe6b9 JG |
359 | int radeon_gart_init(struct radeon_device *rdev); |
360 | void radeon_gart_fini(struct radeon_device *rdev); | |
361 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |
362 | int pages); | |
363 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |
c39d3516 KRW |
364 | int pages, struct page **pagelist, |
365 | dma_addr_t *dma_addr); | |
c9a1be96 | 366 | void radeon_gart_restore(struct radeon_device *rdev); |
771fe6b9 JG |
367 | |
368 | ||
369 | /* | |
370 | * GPU MC structures, functions & helpers | |
371 | */ | |
372 | struct radeon_mc { | |
373 | resource_size_t aper_size; | |
374 | resource_size_t aper_base; | |
375 | resource_size_t agp_base; | |
7a50f01a DA |
376 | /* for some chips with <= 32MB we need to lie |
377 | * about vram size near mc fb location */ | |
3ce0a23d | 378 | u64 mc_vram_size; |
d594e46a | 379 | u64 visible_vram_size; |
3ce0a23d JG |
380 | u64 gtt_size; |
381 | u64 gtt_start; | |
382 | u64 gtt_end; | |
3ce0a23d JG |
383 | u64 vram_start; |
384 | u64 vram_end; | |
771fe6b9 | 385 | unsigned vram_width; |
3ce0a23d | 386 | u64 real_vram_size; |
771fe6b9 JG |
387 | int vram_mtrr; |
388 | bool vram_is_ddr; | |
d594e46a | 389 | bool igp_sideport_enabled; |
8d369bb1 | 390 | u64 gtt_base_align; |
771fe6b9 JG |
391 | }; |
392 | ||
06b6476d AD |
393 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
394 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); | |
771fe6b9 JG |
395 | |
396 | /* | |
397 | * GPU scratch registers structures, functions & helpers | |
398 | */ | |
399 | struct radeon_scratch { | |
400 | unsigned num_reg; | |
724c80e1 | 401 | uint32_t reg_base; |
771fe6b9 JG |
402 | bool free[32]; |
403 | uint32_t reg[32]; | |
404 | }; | |
405 | ||
406 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); | |
407 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); | |
408 | ||
409 | ||
410 | /* | |
411 | * IRQS. | |
412 | */ | |
6f34be50 AD |
413 | |
414 | struct radeon_unpin_work { | |
415 | struct work_struct work; | |
416 | struct radeon_device *rdev; | |
417 | int crtc_id; | |
418 | struct radeon_fence *fence; | |
419 | struct drm_pending_vblank_event *event; | |
420 | struct radeon_bo *old_rbo; | |
421 | u64 new_crtc_base; | |
422 | }; | |
423 | ||
424 | struct r500_irq_stat_regs { | |
425 | u32 disp_int; | |
426 | }; | |
427 | ||
428 | struct r600_irq_stat_regs { | |
429 | u32 disp_int; | |
430 | u32 disp_int_cont; | |
431 | u32 disp_int_cont2; | |
432 | u32 d1grph_int; | |
433 | u32 d2grph_int; | |
434 | }; | |
435 | ||
436 | struct evergreen_irq_stat_regs { | |
437 | u32 disp_int; | |
438 | u32 disp_int_cont; | |
439 | u32 disp_int_cont2; | |
440 | u32 disp_int_cont3; | |
441 | u32 disp_int_cont4; | |
442 | u32 disp_int_cont5; | |
443 | u32 d1grph_int; | |
444 | u32 d2grph_int; | |
445 | u32 d3grph_int; | |
446 | u32 d4grph_int; | |
447 | u32 d5grph_int; | |
448 | u32 d6grph_int; | |
449 | }; | |
450 | ||
451 | union radeon_irq_stat_regs { | |
452 | struct r500_irq_stat_regs r500; | |
453 | struct r600_irq_stat_regs r600; | |
454 | struct evergreen_irq_stat_regs evergreen; | |
455 | }; | |
456 | ||
54bd5206 IH |
457 | #define RADEON_MAX_HPD_PINS 6 |
458 | #define RADEON_MAX_CRTCS 6 | |
459 | #define RADEON_MAX_HDMI_BLOCKS 2 | |
460 | ||
771fe6b9 JG |
461 | struct radeon_irq { |
462 | bool installed; | |
463 | bool sw_int; | |
54bd5206 IH |
464 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
465 | bool pflip[RADEON_MAX_CRTCS]; | |
73a6d3fc | 466 | wait_queue_head_t vblank_queue; |
54bd5206 | 467 | bool hpd[RADEON_MAX_HPD_PINS]; |
2031f77c AD |
468 | bool gui_idle; |
469 | bool gui_idle_acked; | |
470 | wait_queue_head_t idle_queue; | |
54bd5206 | 471 | bool hdmi[RADEON_MAX_HDMI_BLOCKS]; |
1614f8b1 DA |
472 | spinlock_t sw_lock; |
473 | int sw_refcount; | |
6f34be50 | 474 | union radeon_irq_stat_regs stat_regs; |
54bd5206 IH |
475 | spinlock_t pflip_lock[RADEON_MAX_CRTCS]; |
476 | int pflip_refcount[RADEON_MAX_CRTCS]; | |
771fe6b9 JG |
477 | }; |
478 | ||
479 | int radeon_irq_kms_init(struct radeon_device *rdev); | |
480 | void radeon_irq_kms_fini(struct radeon_device *rdev); | |
1614f8b1 DA |
481 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); |
482 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); | |
6f34be50 AD |
483 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
484 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); | |
771fe6b9 JG |
485 | |
486 | /* | |
487 | * CP & ring. | |
488 | */ | |
7465280c AD |
489 | |
490 | /* max number of rings */ | |
491 | #define RADEON_NUM_RINGS 3 | |
492 | ||
493 | /* internal ring indices */ | |
494 | /* r1xx+ has gfx CP ring */ | |
495 | #define RADEON_RING_TYPE_GFX_INDEX 0 | |
496 | ||
497 | /* cayman has 2 compute CP rings */ | |
498 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 | |
499 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 | |
500 | ||
771fe6b9 JG |
501 | struct radeon_ib { |
502 | struct list_head list; | |
e821767b | 503 | unsigned idx; |
771fe6b9 JG |
504 | uint64_t gpu_addr; |
505 | struct radeon_fence *fence; | |
e821767b | 506 | uint32_t *ptr; |
771fe6b9 | 507 | uint32_t length_dw; |
e821767b | 508 | bool free; |
771fe6b9 JG |
509 | }; |
510 | ||
ecb114a1 DA |
511 | /* |
512 | * locking - | |
513 | * mutex protects scheduled_ibs, ready, alloc_bm | |
514 | */ | |
771fe6b9 JG |
515 | struct radeon_ib_pool { |
516 | struct mutex mutex; | |
4c788679 | 517 | struct radeon_bo *robj; |
9f93ed39 | 518 | struct list_head bogus_ib; |
771fe6b9 JG |
519 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
520 | bool ready; | |
e821767b | 521 | unsigned head_id; |
771fe6b9 JG |
522 | }; |
523 | ||
524 | struct radeon_cp { | |
4c788679 | 525 | struct radeon_bo *ring_obj; |
771fe6b9 JG |
526 | volatile uint32_t *ring; |
527 | unsigned rptr; | |
5596a9db CK |
528 | unsigned rptr_offs; |
529 | unsigned rptr_reg; | |
771fe6b9 JG |
530 | unsigned wptr; |
531 | unsigned wptr_old; | |
5596a9db | 532 | unsigned wptr_reg; |
771fe6b9 JG |
533 | unsigned ring_size; |
534 | unsigned ring_free_dw; | |
535 | int count_dw; | |
536 | uint64_t gpu_addr; | |
537 | uint32_t align_mask; | |
538 | uint32_t ptr_mask; | |
539 | struct mutex mutex; | |
540 | bool ready; | |
541 | }; | |
542 | ||
d8f60cfc AD |
543 | /* |
544 | * R6xx+ IH ring | |
545 | */ | |
546 | struct r600_ih { | |
4c788679 | 547 | struct radeon_bo *ring_obj; |
d8f60cfc AD |
548 | volatile uint32_t *ring; |
549 | unsigned rptr; | |
550 | unsigned wptr; | |
551 | unsigned wptr_old; | |
552 | unsigned ring_size; | |
553 | uint64_t gpu_addr; | |
d8f60cfc AD |
554 | uint32_t ptr_mask; |
555 | spinlock_t lock; | |
556 | bool enabled; | |
557 | }; | |
558 | ||
8eec9d6f IH |
559 | struct r600_blit_cp_primitives { |
560 | void (*set_render_target)(struct radeon_device *rdev, int format, | |
561 | int w, int h, u64 gpu_addr); | |
562 | void (*cp_set_surface_sync)(struct radeon_device *rdev, | |
563 | u32 sync_type, u32 size, | |
564 | u64 mc_addr); | |
565 | void (*set_shaders)(struct radeon_device *rdev); | |
566 | void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); | |
567 | void (*set_tex_resource)(struct radeon_device *rdev, | |
568 | int format, int w, int h, int pitch, | |
9bb7703c | 569 | u64 gpu_addr, u32 size); |
8eec9d6f IH |
570 | void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, |
571 | int x2, int y2); | |
572 | void (*draw_auto)(struct radeon_device *rdev); | |
573 | void (*set_default_state)(struct radeon_device *rdev); | |
574 | }; | |
575 | ||
3ce0a23d | 576 | struct r600_blit { |
ff82f052 | 577 | struct mutex mutex; |
4c788679 | 578 | struct radeon_bo *shader_obj; |
8eec9d6f IH |
579 | struct r600_blit_cp_primitives primitives; |
580 | int max_dim; | |
581 | int ring_size_common; | |
582 | int ring_size_per_loop; | |
3ce0a23d JG |
583 | u64 shader_gpu_addr; |
584 | u32 vs_offset, ps_offset; | |
585 | u32 state_offset; | |
586 | u32 state_len; | |
587 | u32 vb_used, vb_total; | |
588 | struct radeon_ib *vb_ib; | |
589 | }; | |
590 | ||
6ddddfe7 AD |
591 | void r600_blit_suspend(struct radeon_device *rdev); |
592 | ||
7b1f2485 | 593 | int radeon_ib_get(struct radeon_device *rdev, int ring, struct radeon_ib **ib); |
771fe6b9 JG |
594 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
595 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); | |
596 | int radeon_ib_pool_init(struct radeon_device *rdev); | |
597 | void radeon_ib_pool_fini(struct radeon_device *rdev); | |
598 | int radeon_ib_test(struct radeon_device *rdev); | |
9f93ed39 | 599 | extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); |
771fe6b9 | 600 | /* Ring access between begin & end cannot sleep */ |
7b1f2485 CK |
601 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_cp *cp); |
602 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ndw); | |
603 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ndw); | |
604 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_cp *cp); | |
605 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_cp *cp); | |
606 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_cp *cp); | |
607 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_cp *cp); | |
5596a9db CK |
608 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ring_size, |
609 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg); | |
7b1f2485 | 610 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_cp *cp); |
771fe6b9 JG |
611 | |
612 | ||
613 | /* | |
614 | * CS. | |
615 | */ | |
616 | struct radeon_cs_reloc { | |
617 | struct drm_gem_object *gobj; | |
4c788679 JG |
618 | struct radeon_bo *robj; |
619 | struct radeon_bo_list lobj; | |
771fe6b9 JG |
620 | uint32_t handle; |
621 | uint32_t flags; | |
622 | }; | |
623 | ||
624 | struct radeon_cs_chunk { | |
625 | uint32_t chunk_id; | |
626 | uint32_t length_dw; | |
513bcb46 DA |
627 | int kpage_idx[2]; |
628 | uint32_t *kpage[2]; | |
771fe6b9 | 629 | uint32_t *kdata; |
513bcb46 DA |
630 | void __user *user_ptr; |
631 | int last_copied_page; | |
632 | int last_page_index; | |
771fe6b9 JG |
633 | }; |
634 | ||
635 | struct radeon_cs_parser { | |
c8c15ff1 | 636 | struct device *dev; |
771fe6b9 JG |
637 | struct radeon_device *rdev; |
638 | struct drm_file *filp; | |
639 | /* chunks */ | |
640 | unsigned nchunks; | |
641 | struct radeon_cs_chunk *chunks; | |
642 | uint64_t *chunks_array; | |
643 | /* IB */ | |
644 | unsigned idx; | |
645 | /* relocations */ | |
646 | unsigned nrelocs; | |
647 | struct radeon_cs_reloc *relocs; | |
648 | struct radeon_cs_reloc **relocs_ptr; | |
649 | struct list_head validated; | |
650 | /* indices of various chunks */ | |
651 | int chunk_ib_idx; | |
652 | int chunk_relocs_idx; | |
653 | struct radeon_ib *ib; | |
654 | void *track; | |
3ce0a23d | 655 | unsigned family; |
e70f224c MO |
656 | int parser_error; |
657 | bool keep_tiling_flags; | |
771fe6b9 JG |
658 | }; |
659 | ||
513bcb46 DA |
660 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
661 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); | |
ce580fab | 662 | extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); |
513bcb46 | 663 | |
771fe6b9 JG |
664 | struct radeon_cs_packet { |
665 | unsigned idx; | |
666 | unsigned type; | |
667 | unsigned reg; | |
668 | unsigned opcode; | |
669 | int count; | |
670 | unsigned one_reg_wr; | |
671 | }; | |
672 | ||
673 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, | |
674 | struct radeon_cs_packet *pkt, | |
675 | unsigned idx, unsigned reg); | |
676 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, | |
677 | struct radeon_cs_packet *pkt); | |
678 | ||
679 | ||
680 | /* | |
681 | * AGP | |
682 | */ | |
683 | int radeon_agp_init(struct radeon_device *rdev); | |
0ebf1717 | 684 | void radeon_agp_resume(struct radeon_device *rdev); |
10b06122 | 685 | void radeon_agp_suspend(struct radeon_device *rdev); |
771fe6b9 JG |
686 | void radeon_agp_fini(struct radeon_device *rdev); |
687 | ||
688 | ||
689 | /* | |
690 | * Writeback | |
691 | */ | |
692 | struct radeon_wb { | |
4c788679 | 693 | struct radeon_bo *wb_obj; |
771fe6b9 JG |
694 | volatile uint32_t *wb; |
695 | uint64_t gpu_addr; | |
724c80e1 | 696 | bool enabled; |
d0f8a854 | 697 | bool use_event; |
771fe6b9 JG |
698 | }; |
699 | ||
724c80e1 AD |
700 | #define RADEON_WB_SCRATCH_OFFSET 0 |
701 | #define RADEON_WB_CP_RPTR_OFFSET 1024 | |
0c88a02e AD |
702 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
703 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 | |
724c80e1 | 704 | #define R600_WB_IH_WPTR_OFFSET 2048 |
d0f8a854 | 705 | #define R600_WB_EVENT_OFFSET 3072 |
724c80e1 | 706 | |
c93bb85b JG |
707 | /** |
708 | * struct radeon_pm - power management datas | |
709 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) | |
710 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) | |
711 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) | |
712 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) | |
713 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) | |
714 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) | |
715 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) | |
716 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) | |
717 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) | |
25985edc | 718 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
c93bb85b JG |
719 | * @needed_bandwidth: current bandwidth needs |
720 | * | |
721 | * It keeps track of various data needed to take powermanagement decision. | |
25985edc | 722 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
c93bb85b JG |
723 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
724 | * (type of memory, bus size, efficiency, ...) | |
725 | */ | |
ce8f5370 AD |
726 | |
727 | enum radeon_pm_method { | |
728 | PM_METHOD_PROFILE, | |
729 | PM_METHOD_DYNPM, | |
730 | }; | |
731 | ||
732 | enum radeon_dynpm_state { | |
733 | DYNPM_STATE_DISABLED, | |
734 | DYNPM_STATE_MINIMUM, | |
735 | DYNPM_STATE_PAUSED, | |
3f53eb6f RW |
736 | DYNPM_STATE_ACTIVE, |
737 | DYNPM_STATE_SUSPENDED, | |
c913e23a | 738 | }; |
ce8f5370 AD |
739 | enum radeon_dynpm_action { |
740 | DYNPM_ACTION_NONE, | |
741 | DYNPM_ACTION_MINIMUM, | |
742 | DYNPM_ACTION_DOWNCLOCK, | |
743 | DYNPM_ACTION_UPCLOCK, | |
744 | DYNPM_ACTION_DEFAULT | |
c913e23a | 745 | }; |
56278a8e AD |
746 | |
747 | enum radeon_voltage_type { | |
748 | VOLTAGE_NONE = 0, | |
749 | VOLTAGE_GPIO, | |
750 | VOLTAGE_VDDC, | |
751 | VOLTAGE_SW | |
752 | }; | |
753 | ||
0ec0e74f AD |
754 | enum radeon_pm_state_type { |
755 | POWER_STATE_TYPE_DEFAULT, | |
756 | POWER_STATE_TYPE_POWERSAVE, | |
757 | POWER_STATE_TYPE_BATTERY, | |
758 | POWER_STATE_TYPE_BALANCED, | |
759 | POWER_STATE_TYPE_PERFORMANCE, | |
760 | }; | |
761 | ||
ce8f5370 AD |
762 | enum radeon_pm_profile_type { |
763 | PM_PROFILE_DEFAULT, | |
764 | PM_PROFILE_AUTO, | |
765 | PM_PROFILE_LOW, | |
c9e75b21 | 766 | PM_PROFILE_MID, |
ce8f5370 AD |
767 | PM_PROFILE_HIGH, |
768 | }; | |
769 | ||
770 | #define PM_PROFILE_DEFAULT_IDX 0 | |
771 | #define PM_PROFILE_LOW_SH_IDX 1 | |
c9e75b21 AD |
772 | #define PM_PROFILE_MID_SH_IDX 2 |
773 | #define PM_PROFILE_HIGH_SH_IDX 3 | |
774 | #define PM_PROFILE_LOW_MH_IDX 4 | |
775 | #define PM_PROFILE_MID_MH_IDX 5 | |
776 | #define PM_PROFILE_HIGH_MH_IDX 6 | |
777 | #define PM_PROFILE_MAX 7 | |
ce8f5370 AD |
778 | |
779 | struct radeon_pm_profile { | |
780 | int dpms_off_ps_idx; | |
781 | int dpms_on_ps_idx; | |
782 | int dpms_off_cm_idx; | |
783 | int dpms_on_cm_idx; | |
516d0e46 AD |
784 | }; |
785 | ||
21a8122a AD |
786 | enum radeon_int_thermal_type { |
787 | THERMAL_TYPE_NONE, | |
788 | THERMAL_TYPE_RV6XX, | |
789 | THERMAL_TYPE_RV770, | |
790 | THERMAL_TYPE_EVERGREEN, | |
e33df25f | 791 | THERMAL_TYPE_SUMO, |
4fddba1f | 792 | THERMAL_TYPE_NI, |
21a8122a AD |
793 | }; |
794 | ||
56278a8e AD |
795 | struct radeon_voltage { |
796 | enum radeon_voltage_type type; | |
797 | /* gpio voltage */ | |
798 | struct radeon_gpio_rec gpio; | |
799 | u32 delay; /* delay in usec from voltage drop to sclk change */ | |
800 | bool active_high; /* voltage drop is active when bit is high */ | |
801 | /* VDDC voltage */ | |
802 | u8 vddc_id; /* index into vddc voltage table */ | |
803 | u8 vddci_id; /* index into vddci voltage table */ | |
804 | bool vddci_enabled; | |
805 | /* r6xx+ sw */ | |
2feea49a AD |
806 | u16 voltage; |
807 | /* evergreen+ vddci */ | |
808 | u16 vddci; | |
56278a8e AD |
809 | }; |
810 | ||
d7311171 AD |
811 | /* clock mode flags */ |
812 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) | |
813 | ||
56278a8e AD |
814 | struct radeon_pm_clock_info { |
815 | /* memory clock */ | |
816 | u32 mclk; | |
817 | /* engine clock */ | |
818 | u32 sclk; | |
819 | /* voltage info */ | |
820 | struct radeon_voltage voltage; | |
d7311171 | 821 | /* standardized clock flags */ |
56278a8e AD |
822 | u32 flags; |
823 | }; | |
824 | ||
a48b9b4e | 825 | /* state flags */ |
d7311171 | 826 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
a48b9b4e | 827 | |
56278a8e | 828 | struct radeon_power_state { |
0ec0e74f | 829 | enum radeon_pm_state_type type; |
8f3f1c9a | 830 | struct radeon_pm_clock_info *clock_info; |
56278a8e AD |
831 | /* number of valid clock modes in this power state */ |
832 | int num_clock_modes; | |
56278a8e | 833 | struct radeon_pm_clock_info *default_clock_mode; |
a48b9b4e AD |
834 | /* standardized state flags */ |
835 | u32 flags; | |
79daedc9 AD |
836 | u32 misc; /* vbios specific flags */ |
837 | u32 misc2; /* vbios specific flags */ | |
838 | int pcie_lanes; /* pcie lanes */ | |
56278a8e AD |
839 | }; |
840 | ||
27459324 RM |
841 | /* |
842 | * Some modes are overclocked by very low value, accept them | |
843 | */ | |
844 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ | |
845 | ||
c93bb85b | 846 | struct radeon_pm { |
c913e23a | 847 | struct mutex mutex; |
a48b9b4e AD |
848 | u32 active_crtcs; |
849 | int active_crtc_count; | |
c913e23a | 850 | int req_vblank; |
839461d3 | 851 | bool vblank_sync; |
2031f77c | 852 | bool gui_idle; |
c93bb85b JG |
853 | fixed20_12 max_bandwidth; |
854 | fixed20_12 igp_sideport_mclk; | |
855 | fixed20_12 igp_system_mclk; | |
856 | fixed20_12 igp_ht_link_clk; | |
857 | fixed20_12 igp_ht_link_width; | |
858 | fixed20_12 k8_bandwidth; | |
859 | fixed20_12 sideport_bandwidth; | |
860 | fixed20_12 ht_bandwidth; | |
861 | fixed20_12 core_bandwidth; | |
862 | fixed20_12 sclk; | |
f47299c5 | 863 | fixed20_12 mclk; |
c93bb85b | 864 | fixed20_12 needed_bandwidth; |
0975b162 | 865 | struct radeon_power_state *power_state; |
56278a8e AD |
866 | /* number of valid power states */ |
867 | int num_power_states; | |
a48b9b4e AD |
868 | int current_power_state_index; |
869 | int current_clock_mode_index; | |
870 | int requested_power_state_index; | |
871 | int requested_clock_mode_index; | |
872 | int default_power_state_index; | |
873 | u32 current_sclk; | |
874 | u32 current_mclk; | |
2feea49a AD |
875 | u16 current_vddc; |
876 | u16 current_vddci; | |
9ace9f7b AD |
877 | u32 default_sclk; |
878 | u32 default_mclk; | |
2feea49a AD |
879 | u16 default_vddc; |
880 | u16 default_vddci; | |
29fb52ca | 881 | struct radeon_i2c_chan *i2c_bus; |
ce8f5370 AD |
882 | /* selected pm method */ |
883 | enum radeon_pm_method pm_method; | |
884 | /* dynpm power management */ | |
885 | struct delayed_work dynpm_idle_work; | |
886 | enum radeon_dynpm_state dynpm_state; | |
887 | enum radeon_dynpm_action dynpm_planned_action; | |
888 | unsigned long dynpm_action_timeout; | |
889 | bool dynpm_can_upclock; | |
890 | bool dynpm_can_downclock; | |
891 | /* profile-based power management */ | |
892 | enum radeon_pm_profile_type profile; | |
893 | int profile_index; | |
894 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; | |
21a8122a AD |
895 | /* internal thermal controller on rv6xx+ */ |
896 | enum radeon_int_thermal_type int_thermal_type; | |
897 | struct device *int_hwmon_dev; | |
c93bb85b JG |
898 | }; |
899 | ||
a4c9e2ee AD |
900 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
901 | enum radeon_pm_state_type ps_type, | |
902 | int instance); | |
771fe6b9 JG |
903 | |
904 | /* | |
905 | * Benchmarking | |
906 | */ | |
638dd7db | 907 | void radeon_benchmark(struct radeon_device *rdev, int test_number); |
771fe6b9 JG |
908 | |
909 | ||
ecc0b326 MD |
910 | /* |
911 | * Testing | |
912 | */ | |
913 | void radeon_test_moves(struct radeon_device *rdev); | |
914 | ||
915 | ||
771fe6b9 JG |
916 | /* |
917 | * Debugfs | |
918 | */ | |
4d8bf9ae CK |
919 | struct radeon_debugfs { |
920 | struct drm_info_list *files; | |
921 | unsigned num_files; | |
922 | }; | |
923 | ||
771fe6b9 JG |
924 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
925 | struct drm_info_list *files, | |
926 | unsigned nfiles); | |
927 | int radeon_debugfs_fence_init(struct radeon_device *rdev); | |
771fe6b9 JG |
928 | |
929 | ||
930 | /* | |
931 | * ASIC specific functions. | |
932 | */ | |
933 | struct radeon_asic { | |
068a117c | 934 | int (*init)(struct radeon_device *rdev); |
3ce0a23d JG |
935 | void (*fini)(struct radeon_device *rdev); |
936 | int (*resume)(struct radeon_device *rdev); | |
937 | int (*suspend)(struct radeon_device *rdev); | |
28d52043 | 938 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
7b1f2485 | 939 | bool (*gpu_is_lockup)(struct radeon_device *rdev, struct radeon_cp *cp); |
a2d07b74 | 940 | int (*asic_reset)(struct radeon_device *rdev); |
771fe6b9 JG |
941 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
942 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); | |
943 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); | |
944 | void (*cp_fini)(struct radeon_device *rdev); | |
945 | void (*cp_disable)(struct radeon_device *rdev); | |
946 | void (*ring_start)(struct radeon_device *rdev); | |
7b1f2485 | 947 | int (*ring_test)(struct radeon_device *rdev, struct radeon_cp *cp); |
3ce0a23d | 948 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
771fe6b9 JG |
949 | int (*irq_set)(struct radeon_device *rdev); |
950 | int (*irq_process)(struct radeon_device *rdev); | |
7ed220d7 | 951 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
771fe6b9 | 952 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
15d3332f | 953 | void (*semaphore_ring_emit)(struct radeon_device *rdev, |
7b1f2485 | 954 | struct radeon_cp *cp, |
15d3332f | 955 | struct radeon_semaphore *semaphore, |
7b1f2485 | 956 | bool emit_wait); |
771fe6b9 JG |
957 | int (*cs_parse)(struct radeon_cs_parser *p); |
958 | int (*copy_blit)(struct radeon_device *rdev, | |
959 | uint64_t src_offset, | |
960 | uint64_t dst_offset, | |
003cefe0 | 961 | unsigned num_gpu_pages, |
771fe6b9 JG |
962 | struct radeon_fence *fence); |
963 | int (*copy_dma)(struct radeon_device *rdev, | |
964 | uint64_t src_offset, | |
965 | uint64_t dst_offset, | |
003cefe0 | 966 | unsigned num_gpu_pages, |
771fe6b9 JG |
967 | struct radeon_fence *fence); |
968 | int (*copy)(struct radeon_device *rdev, | |
969 | uint64_t src_offset, | |
970 | uint64_t dst_offset, | |
003cefe0 | 971 | unsigned num_gpu_pages, |
771fe6b9 | 972 | struct radeon_fence *fence); |
7433874e | 973 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
771fe6b9 | 974 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
7433874e | 975 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
771fe6b9 | 976 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
c836a412 | 977 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
771fe6b9 JG |
978 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
979 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); | |
e024e110 DA |
980 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
981 | uint32_t tiling_flags, uint32_t pitch, | |
982 | uint32_t offset, uint32_t obj_size); | |
9479c54f | 983 | void (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
c93bb85b | 984 | void (*bandwidth_update)(struct radeon_device *rdev); |
429770b3 AD |
985 | void (*hpd_init)(struct radeon_device *rdev); |
986 | void (*hpd_fini)(struct radeon_device *rdev); | |
987 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
988 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
062b389c JG |
989 | /* ioctl hw specific callback. Some hw might want to perform special |
990 | * operation on specific ioctl. For instance on wait idle some hw | |
991 | * might want to perform and HDP flush through MMIO as it seems that | |
992 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed | |
993 | * through ring. | |
994 | */ | |
995 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); | |
def9ba9c | 996 | bool (*gui_idle)(struct radeon_device *rdev); |
ce8f5370 | 997 | /* power management */ |
49e02b73 AD |
998 | void (*pm_misc)(struct radeon_device *rdev); |
999 | void (*pm_prepare)(struct radeon_device *rdev); | |
1000 | void (*pm_finish)(struct radeon_device *rdev); | |
ce8f5370 AD |
1001 | void (*pm_init_profile)(struct radeon_device *rdev); |
1002 | void (*pm_get_dynpm_state)(struct radeon_device *rdev); | |
6f34be50 AD |
1003 | /* pageflipping */ |
1004 | void (*pre_page_flip)(struct radeon_device *rdev, int crtc); | |
1005 | u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
1006 | void (*post_page_flip)(struct radeon_device *rdev, int crtc); | |
771fe6b9 JG |
1007 | }; |
1008 | ||
21f9a437 JG |
1009 | /* |
1010 | * Asic structures | |
1011 | */ | |
225758d8 JG |
1012 | struct r100_gpu_lockup { |
1013 | unsigned long last_jiffies; | |
1014 | u32 last_cp_rptr; | |
1015 | }; | |
1016 | ||
551ebd83 | 1017 | struct r100_asic { |
225758d8 JG |
1018 | const unsigned *reg_safe_bm; |
1019 | unsigned reg_safe_bm_size; | |
1020 | u32 hdp_cntl; | |
1021 | struct r100_gpu_lockup lockup; | |
551ebd83 DA |
1022 | }; |
1023 | ||
21f9a437 | 1024 | struct r300_asic { |
225758d8 JG |
1025 | const unsigned *reg_safe_bm; |
1026 | unsigned reg_safe_bm_size; | |
1027 | u32 resync_scratch; | |
1028 | u32 hdp_cntl; | |
1029 | struct r100_gpu_lockup lockup; | |
21f9a437 JG |
1030 | }; |
1031 | ||
1032 | struct r600_asic { | |
225758d8 JG |
1033 | unsigned max_pipes; |
1034 | unsigned max_tile_pipes; | |
1035 | unsigned max_simds; | |
1036 | unsigned max_backends; | |
1037 | unsigned max_gprs; | |
1038 | unsigned max_threads; | |
1039 | unsigned max_stack_entries; | |
1040 | unsigned max_hw_contexts; | |
1041 | unsigned max_gs_threads; | |
1042 | unsigned sx_max_export_size; | |
1043 | unsigned sx_max_export_pos_size; | |
1044 | unsigned sx_max_export_smx_size; | |
1045 | unsigned sq_num_cf_insts; | |
1046 | unsigned tiling_nbanks; | |
1047 | unsigned tiling_npipes; | |
1048 | unsigned tiling_group_size; | |
e7aeeba6 | 1049 | unsigned tile_config; |
e55b9422 | 1050 | unsigned backend_map; |
225758d8 | 1051 | struct r100_gpu_lockup lockup; |
21f9a437 JG |
1052 | }; |
1053 | ||
1054 | struct rv770_asic { | |
225758d8 JG |
1055 | unsigned max_pipes; |
1056 | unsigned max_tile_pipes; | |
1057 | unsigned max_simds; | |
1058 | unsigned max_backends; | |
1059 | unsigned max_gprs; | |
1060 | unsigned max_threads; | |
1061 | unsigned max_stack_entries; | |
1062 | unsigned max_hw_contexts; | |
1063 | unsigned max_gs_threads; | |
1064 | unsigned sx_max_export_size; | |
1065 | unsigned sx_max_export_pos_size; | |
1066 | unsigned sx_max_export_smx_size; | |
1067 | unsigned sq_num_cf_insts; | |
1068 | unsigned sx_num_of_sets; | |
1069 | unsigned sc_prim_fifo_size; | |
1070 | unsigned sc_hiz_tile_fifo_size; | |
1071 | unsigned sc_earlyz_tile_fifo_fize; | |
1072 | unsigned tiling_nbanks; | |
1073 | unsigned tiling_npipes; | |
1074 | unsigned tiling_group_size; | |
e7aeeba6 | 1075 | unsigned tile_config; |
e55b9422 | 1076 | unsigned backend_map; |
225758d8 | 1077 | struct r100_gpu_lockup lockup; |
21f9a437 JG |
1078 | }; |
1079 | ||
32fcdbf4 AD |
1080 | struct evergreen_asic { |
1081 | unsigned num_ses; | |
1082 | unsigned max_pipes; | |
1083 | unsigned max_tile_pipes; | |
1084 | unsigned max_simds; | |
1085 | unsigned max_backends; | |
1086 | unsigned max_gprs; | |
1087 | unsigned max_threads; | |
1088 | unsigned max_stack_entries; | |
1089 | unsigned max_hw_contexts; | |
1090 | unsigned max_gs_threads; | |
1091 | unsigned sx_max_export_size; | |
1092 | unsigned sx_max_export_pos_size; | |
1093 | unsigned sx_max_export_smx_size; | |
1094 | unsigned sq_num_cf_insts; | |
1095 | unsigned sx_num_of_sets; | |
1096 | unsigned sc_prim_fifo_size; | |
1097 | unsigned sc_hiz_tile_fifo_size; | |
1098 | unsigned sc_earlyz_tile_fifo_size; | |
1099 | unsigned tiling_nbanks; | |
1100 | unsigned tiling_npipes; | |
1101 | unsigned tiling_group_size; | |
e7aeeba6 | 1102 | unsigned tile_config; |
e55b9422 | 1103 | unsigned backend_map; |
17db7042 | 1104 | struct r100_gpu_lockup lockup; |
32fcdbf4 AD |
1105 | }; |
1106 | ||
fecf1d07 AD |
1107 | struct cayman_asic { |
1108 | unsigned max_shader_engines; | |
1109 | unsigned max_pipes_per_simd; | |
1110 | unsigned max_tile_pipes; | |
1111 | unsigned max_simds_per_se; | |
1112 | unsigned max_backends_per_se; | |
1113 | unsigned max_texture_channel_caches; | |
1114 | unsigned max_gprs; | |
1115 | unsigned max_threads; | |
1116 | unsigned max_gs_threads; | |
1117 | unsigned max_stack_entries; | |
1118 | unsigned sx_num_of_sets; | |
1119 | unsigned sx_max_export_size; | |
1120 | unsigned sx_max_export_pos_size; | |
1121 | unsigned sx_max_export_smx_size; | |
1122 | unsigned max_hw_contexts; | |
1123 | unsigned sq_num_cf_insts; | |
1124 | unsigned sc_prim_fifo_size; | |
1125 | unsigned sc_hiz_tile_fifo_size; | |
1126 | unsigned sc_earlyz_tile_fifo_size; | |
1127 | ||
1128 | unsigned num_shader_engines; | |
1129 | unsigned num_shader_pipes_per_simd; | |
1130 | unsigned num_tile_pipes; | |
1131 | unsigned num_simds_per_se; | |
1132 | unsigned num_backends_per_se; | |
1133 | unsigned backend_disable_mask_per_asic; | |
1134 | unsigned backend_map; | |
1135 | unsigned num_texture_channel_caches; | |
1136 | unsigned mem_max_burst_length_bytes; | |
1137 | unsigned mem_row_size_in_kb; | |
1138 | unsigned shader_engine_tile_size; | |
1139 | unsigned num_gpus; | |
1140 | unsigned multi_gpu_tile_size; | |
1141 | ||
1142 | unsigned tile_config; | |
1143 | struct r100_gpu_lockup lockup; | |
1144 | }; | |
1145 | ||
068a117c JG |
1146 | union radeon_asic_config { |
1147 | struct r300_asic r300; | |
551ebd83 | 1148 | struct r100_asic r100; |
3ce0a23d JG |
1149 | struct r600_asic r600; |
1150 | struct rv770_asic rv770; | |
32fcdbf4 | 1151 | struct evergreen_asic evergreen; |
fecf1d07 | 1152 | struct cayman_asic cayman; |
068a117c JG |
1153 | }; |
1154 | ||
0a10c851 DV |
1155 | /* |
1156 | * asic initizalization from radeon_asic.c | |
1157 | */ | |
1158 | void radeon_agp_disable(struct radeon_device *rdev); | |
1159 | int radeon_asic_init(struct radeon_device *rdev); | |
1160 | ||
771fe6b9 JG |
1161 | |
1162 | /* | |
1163 | * IOCTL. | |
1164 | */ | |
1165 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |
1166 | struct drm_file *filp); | |
1167 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, | |
1168 | struct drm_file *filp); | |
1169 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, | |
1170 | struct drm_file *file_priv); | |
1171 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1172 | struct drm_file *file_priv); | |
1173 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1174 | struct drm_file *file_priv); | |
1175 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1176 | struct drm_file *file_priv); | |
1177 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1178 | struct drm_file *filp); | |
1179 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1180 | struct drm_file *filp); | |
1181 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1182 | struct drm_file *filp); | |
1183 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
1184 | struct drm_file *filp); | |
1185 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); | |
e024e110 DA |
1186 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
1187 | struct drm_file *filp); | |
1188 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
1189 | struct drm_file *filp); | |
771fe6b9 | 1190 | |
16cdf04d AD |
1191 | /* VRAM scratch page for HDP bug, default vram page */ |
1192 | struct r600_vram_scratch { | |
87cbf8f2 AD |
1193 | struct radeon_bo *robj; |
1194 | volatile uint32_t *ptr; | |
16cdf04d | 1195 | u64 gpu_addr; |
87cbf8f2 | 1196 | }; |
771fe6b9 | 1197 | |
7a1619b9 MD |
1198 | |
1199 | /* | |
1200 | * Mutex which allows recursive locking from the same process. | |
1201 | */ | |
1202 | struct radeon_mutex { | |
1203 | struct mutex mutex; | |
1204 | struct task_struct *owner; | |
1205 | int level; | |
1206 | }; | |
1207 | ||
1208 | static inline void radeon_mutex_init(struct radeon_mutex *mutex) | |
1209 | { | |
1210 | mutex_init(&mutex->mutex); | |
1211 | mutex->owner = NULL; | |
1212 | mutex->level = 0; | |
1213 | } | |
1214 | ||
1215 | static inline void radeon_mutex_lock(struct radeon_mutex *mutex) | |
1216 | { | |
1217 | if (mutex_trylock(&mutex->mutex)) { | |
1218 | /* The mutex was unlocked before, so it's ours now */ | |
1219 | mutex->owner = current; | |
1220 | } else if (mutex->owner != current) { | |
1221 | /* Another process locked the mutex, take it */ | |
1222 | mutex_lock(&mutex->mutex); | |
1223 | mutex->owner = current; | |
1224 | } | |
1225 | /* Otherwise the mutex was already locked by this process */ | |
1226 | ||
1227 | mutex->level++; | |
1228 | } | |
1229 | ||
1230 | static inline void radeon_mutex_unlock(struct radeon_mutex *mutex) | |
1231 | { | |
1232 | if (--mutex->level > 0) | |
1233 | return; | |
1234 | ||
1235 | mutex->owner = NULL; | |
1236 | mutex_unlock(&mutex->mutex); | |
1237 | } | |
1238 | ||
1239 | ||
771fe6b9 JG |
1240 | /* |
1241 | * Core structure, functions and helpers. | |
1242 | */ | |
1243 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); | |
1244 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); | |
1245 | ||
1246 | struct radeon_device { | |
9f022ddf | 1247 | struct device *dev; |
771fe6b9 JG |
1248 | struct drm_device *ddev; |
1249 | struct pci_dev *pdev; | |
1250 | /* ASIC */ | |
068a117c | 1251 | union radeon_asic_config config; |
771fe6b9 JG |
1252 | enum radeon_family family; |
1253 | unsigned long flags; | |
1254 | int usec_timeout; | |
1255 | enum radeon_pll_errata pll_errata; | |
1256 | int num_gb_pipes; | |
f779b3e5 | 1257 | int num_z_pipes; |
771fe6b9 JG |
1258 | int disp_priority; |
1259 | /* BIOS */ | |
1260 | uint8_t *bios; | |
1261 | bool is_atom_bios; | |
1262 | uint16_t bios_header_start; | |
4c788679 | 1263 | struct radeon_bo *stollen_vga_memory; |
771fe6b9 | 1264 | /* Register mmio */ |
4c9bc75c DA |
1265 | resource_size_t rmmio_base; |
1266 | resource_size_t rmmio_size; | |
a0533fbf | 1267 | void __iomem *rmmio; |
771fe6b9 JG |
1268 | radeon_rreg_t mc_rreg; |
1269 | radeon_wreg_t mc_wreg; | |
1270 | radeon_rreg_t pll_rreg; | |
1271 | radeon_wreg_t pll_wreg; | |
de1b2898 | 1272 | uint32_t pcie_reg_mask; |
771fe6b9 JG |
1273 | radeon_rreg_t pciep_rreg; |
1274 | radeon_wreg_t pciep_wreg; | |
351a52a2 AD |
1275 | /* io port */ |
1276 | void __iomem *rio_mem; | |
1277 | resource_size_t rio_mem_size; | |
771fe6b9 JG |
1278 | struct radeon_clock clock; |
1279 | struct radeon_mc mc; | |
1280 | struct radeon_gart gart; | |
1281 | struct radeon_mode_info mode_info; | |
1282 | struct radeon_scratch scratch; | |
1283 | struct radeon_mman mman; | |
7465280c AD |
1284 | rwlock_t fence_lock; |
1285 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; | |
15d3332f | 1286 | struct radeon_semaphore_driver semaphore_drv; |
771fe6b9 | 1287 | struct radeon_cp cp; |
0c88a02e AD |
1288 | struct radeon_cp cp1; |
1289 | struct radeon_cp cp2; | |
771fe6b9 JG |
1290 | struct radeon_ib_pool ib_pool; |
1291 | struct radeon_irq irq; | |
1292 | struct radeon_asic *asic; | |
1293 | struct radeon_gem gem; | |
c93bb85b | 1294 | struct radeon_pm pm; |
f657c2a7 | 1295 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
7a1619b9 | 1296 | struct radeon_mutex cs_mutex; |
771fe6b9 | 1297 | struct radeon_wb wb; |
3ce0a23d | 1298 | struct radeon_dummy_page dummy_page; |
771fe6b9 JG |
1299 | bool gpu_lockup; |
1300 | bool shutdown; | |
1301 | bool suspend; | |
ad49f501 | 1302 | bool need_dma32; |
733289c2 | 1303 | bool accel_working; |
e024e110 | 1304 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
3ce0a23d JG |
1305 | const struct firmware *me_fw; /* all family ME firmware */ |
1306 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ | |
d8f60cfc | 1307 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
0af62b01 | 1308 | const struct firmware *mc_fw; /* NI MC firmware */ |
3ce0a23d | 1309 | struct r600_blit r600_blit; |
16cdf04d | 1310 | struct r600_vram_scratch vram_scratch; |
3e5cb98d | 1311 | int msi_enabled; /* msi enabled */ |
d8f60cfc | 1312 | struct r600_ih ih; /* r6/700 interrupt ring */ |
d4877cf2 | 1313 | struct work_struct hotplug_work; |
18917b60 | 1314 | int num_crtc; /* number of crtcs */ |
40bacf16 | 1315 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
5876dd24 | 1316 | struct mutex vram_mutex; |
dafc3bd5 CK |
1317 | |
1318 | /* audio stuff */ | |
7eea7e9e | 1319 | bool audio_enabled; |
dafc3bd5 CK |
1320 | struct timer_list audio_timer; |
1321 | int audio_channels; | |
1322 | int audio_rate; | |
1323 | int audio_bits_per_sample; | |
1324 | uint8_t audio_status_bits; | |
1325 | uint8_t audio_category_code; | |
6a9ee8af | 1326 | |
ce8f5370 | 1327 | struct notifier_block acpi_nb; |
9eba4a93 | 1328 | /* only one userspace can use Hyperz features or CMASK at a time */ |
ab9e1f59 | 1329 | struct drm_file *hyperz_filp; |
9eba4a93 | 1330 | struct drm_file *cmask_filp; |
f376b94f AD |
1331 | /* i2c buses */ |
1332 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; | |
4d8bf9ae CK |
1333 | /* debugfs */ |
1334 | struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; | |
1335 | unsigned debugfs_count; | |
771fe6b9 JG |
1336 | }; |
1337 | ||
1338 | int radeon_device_init(struct radeon_device *rdev, | |
1339 | struct drm_device *ddev, | |
1340 | struct pci_dev *pdev, | |
1341 | uint32_t flags); | |
1342 | void radeon_device_fini(struct radeon_device *rdev); | |
1343 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); | |
1344 | ||
6fcbef7a AK |
1345 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); |
1346 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
1347 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); | |
1348 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
351a52a2 | 1349 | |
4c788679 JG |
1350 | /* |
1351 | * Cast helper | |
1352 | */ | |
1353 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) | |
771fe6b9 JG |
1354 | |
1355 | /* | |
1356 | * Registers read & write functions. | |
1357 | */ | |
a0533fbf BH |
1358 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
1359 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) | |
1360 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) | |
1361 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) | |
de1b2898 | 1362 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
3ce0a23d | 1363 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
de1b2898 | 1364 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
771fe6b9 JG |
1365 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1366 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
1367 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) | |
1368 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) | |
1369 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) | |
1370 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) | |
de1b2898 DA |
1371 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
1372 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) | |
aa5120d2 RM |
1373 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
1374 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) | |
771fe6b9 JG |
1375 | #define WREG32_P(reg, val, mask) \ |
1376 | do { \ | |
1377 | uint32_t tmp_ = RREG32(reg); \ | |
1378 | tmp_ &= (mask); \ | |
1379 | tmp_ |= ((val) & ~(mask)); \ | |
1380 | WREG32(reg, tmp_); \ | |
1381 | } while (0) | |
1382 | #define WREG32_PLL_P(reg, val, mask) \ | |
1383 | do { \ | |
1384 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
1385 | tmp_ &= (mask); \ | |
1386 | tmp_ |= ((val) & ~(mask)); \ | |
1387 | WREG32_PLL(reg, tmp_); \ | |
1388 | } while (0) | |
3ce0a23d | 1389 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) |
351a52a2 AD |
1390 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
1391 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) | |
771fe6b9 | 1392 | |
de1b2898 DA |
1393 | /* |
1394 | * Indirect registers accessor | |
1395 | */ | |
1396 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | |
1397 | { | |
1398 | uint32_t r; | |
1399 | ||
1400 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1401 | r = RREG32(RADEON_PCIE_DATA); | |
1402 | return r; | |
1403 | } | |
1404 | ||
1405 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
1406 | { | |
1407 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1408 | WREG32(RADEON_PCIE_DATA, (v)); | |
1409 | } | |
1410 | ||
771fe6b9 JG |
1411 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
1412 | ||
1413 | ||
1414 | /* | |
1415 | * ASICs helpers. | |
1416 | */ | |
b995e433 DA |
1417 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
1418 | (rdev->pdev->device == 0x5969)) | |
771fe6b9 JG |
1419 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1420 | (rdev->family == CHIP_RV200) || \ | |
1421 | (rdev->family == CHIP_RS100) || \ | |
1422 | (rdev->family == CHIP_RS200) || \ | |
1423 | (rdev->family == CHIP_RV250) || \ | |
1424 | (rdev->family == CHIP_RV280) || \ | |
1425 | (rdev->family == CHIP_RS300)) | |
1426 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ | |
1427 | (rdev->family == CHIP_RV350) || \ | |
1428 | (rdev->family == CHIP_R350) || \ | |
1429 | (rdev->family == CHIP_RV380) || \ | |
1430 | (rdev->family == CHIP_R420) || \ | |
1431 | (rdev->family == CHIP_R423) || \ | |
1432 | (rdev->family == CHIP_RV410) || \ | |
1433 | (rdev->family == CHIP_RS400) || \ | |
1434 | (rdev->family == CHIP_RS480)) | |
3313e3d4 AD |
1435 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
1436 | (rdev->ddev->pdev->device == 0x9443) || \ | |
1437 | (rdev->ddev->pdev->device == 0x944B) || \ | |
1438 | (rdev->ddev->pdev->device == 0x9506) || \ | |
1439 | (rdev->ddev->pdev->device == 0x9509) || \ | |
1440 | (rdev->ddev->pdev->device == 0x950F) || \ | |
1441 | (rdev->ddev->pdev->device == 0x689C) || \ | |
1442 | (rdev->ddev->pdev->device == 0x689D)) | |
771fe6b9 | 1443 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
99999aaa AD |
1444 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
1445 | (rdev->family == CHIP_RS690) || \ | |
1446 | (rdev->family == CHIP_RS740) || \ | |
1447 | (rdev->family >= CHIP_R600)) | |
771fe6b9 JG |
1448 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
1449 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) | |
bcc1c2a1 | 1450 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
633b9164 AD |
1451 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
1452 | (rdev->flags & RADEON_IS_IGP)) | |
1fe18305 | 1453 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
771fe6b9 JG |
1454 | |
1455 | /* | |
1456 | * BIOS helpers. | |
1457 | */ | |
1458 | #define RBIOS8(i) (rdev->bios[i]) | |
1459 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
1460 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
1461 | ||
1462 | int radeon_combios_init(struct radeon_device *rdev); | |
1463 | void radeon_combios_fini(struct radeon_device *rdev); | |
1464 | int radeon_atombios_init(struct radeon_device *rdev); | |
1465 | void radeon_atombios_fini(struct radeon_device *rdev); | |
1466 | ||
1467 | ||
1468 | /* | |
1469 | * RING helpers. | |
1470 | */ | |
ce580fab | 1471 | #if DRM_DEBUG_CODE == 0 |
7b1f2485 | 1472 | static inline void radeon_ring_write(struct radeon_cp *cp, uint32_t v) |
771fe6b9 | 1473 | { |
7b1f2485 CK |
1474 | cp->ring[cp->wptr++] = v; |
1475 | cp->wptr &= cp->ptr_mask; | |
1476 | cp->count_dw--; | |
1477 | cp->ring_free_dw--; | |
771fe6b9 | 1478 | } |
ce580fab AK |
1479 | #else |
1480 | /* With debugging this is just too big to inline */ | |
7b1f2485 | 1481 | void radeon_ring_write(struct radeon_cp *cp, uint32_t v); |
ce580fab | 1482 | #endif |
771fe6b9 JG |
1483 | |
1484 | /* | |
1485 | * ASICs macro. | |
1486 | */ | |
068a117c | 1487 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
3ce0a23d JG |
1488 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1489 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) | |
1490 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) | |
771fe6b9 | 1491 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
28d52043 | 1492 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
7b1f2485 | 1493 | #define radeon_gpu_is_lockup(rdev, cp) (rdev)->asic->gpu_is_lockup((rdev), (cp)) |
a2d07b74 | 1494 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
771fe6b9 JG |
1495 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
1496 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) | |
771fe6b9 | 1497 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
7b1f2485 | 1498 | #define radeon_ring_test(rdev, cp) (rdev)->asic->ring_test((rdev), (cp)) |
3ce0a23d | 1499 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) |
771fe6b9 JG |
1500 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
1501 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) | |
7ed220d7 | 1502 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
771fe6b9 | 1503 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
7b1f2485 | 1504 | #define radeon_semaphore_ring_emit(rdev, cp, semaphore, emit_wait) (rdev)->asic->semaphore_ring_emit((rdev), (cp), (semaphore), (emit_wait)) |
771fe6b9 JG |
1505 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
1506 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) | |
1507 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) | |
7433874e | 1508 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
771fe6b9 | 1509 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
7433874e | 1510 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
93e7de7b | 1511 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) |
c836a412 | 1512 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) |
771fe6b9 JG |
1513 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
1514 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) | |
e024e110 DA |
1515 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
1516 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) | |
c93bb85b | 1517 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
429770b3 AD |
1518 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) |
1519 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) | |
1520 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) | |
1521 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) | |
def9ba9c | 1522 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
a424816f AD |
1523 | #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev)) |
1524 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev)) | |
1525 | #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev)) | |
ce8f5370 AD |
1526 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev)) |
1527 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev)) | |
6f34be50 AD |
1528 | #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc)) |
1529 | #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base)) | |
1530 | #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc)) | |
771fe6b9 | 1531 | |
6cf8a3f5 | 1532 | /* Common functions */ |
700a0cc0 | 1533 | /* AGP */ |
90aca4d2 | 1534 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
700a0cc0 | 1535 | extern void radeon_agp_disable(struct radeon_device *rdev); |
21f9a437 JG |
1536 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1537 | extern void radeon_modeset_fini(struct radeon_device *rdev); | |
9f022ddf | 1538 | extern bool radeon_card_posted(struct radeon_device *rdev); |
f47299c5 | 1539 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
f46c0120 | 1540 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
72542d77 | 1541 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
21f9a437 | 1542 | extern void radeon_scratch_init(struct radeon_device *rdev); |
724c80e1 AD |
1543 | extern void radeon_wb_fini(struct radeon_device *rdev); |
1544 | extern int radeon_wb_init(struct radeon_device *rdev); | |
1545 | extern void radeon_wb_disable(struct radeon_device *rdev); | |
21f9a437 JG |
1546 | extern void radeon_surface_init(struct radeon_device *rdev); |
1547 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); | |
ca6ffc64 | 1548 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
d39c3b89 | 1549 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
312ea8da | 1550 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
d03d8589 | 1551 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
d594e46a JG |
1552 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
1553 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | |
6a9ee8af DA |
1554 | extern int radeon_resume_kms(struct drm_device *dev); |
1555 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); | |
53595338 | 1556 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
6cf8a3f5 | 1557 | |
16cdf04d AD |
1558 | /* |
1559 | * R600 vram scratch functions | |
1560 | */ | |
1561 | int r600_vram_scratch_init(struct radeon_device *rdev); | |
1562 | void r600_vram_scratch_fini(struct radeon_device *rdev); | |
1563 | ||
3574dda4 DV |
1564 | /* |
1565 | * r600 functions used by radeon_encoder.c | |
1566 | */ | |
2cd6218c RM |
1567 | extern void r600_hdmi_enable(struct drm_encoder *encoder); |
1568 | extern void r600_hdmi_disable(struct drm_encoder *encoder); | |
dafc3bd5 | 1569 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
fe251e2f | 1570 | |
0af62b01 | 1571 | extern int ni_init_microcode(struct radeon_device *rdev); |
755d819e | 1572 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
0af62b01 | 1573 | |
d7a2952f AM |
1574 | /* radeon_acpi.c */ |
1575 | #if defined(CONFIG_ACPI) | |
1576 | extern int radeon_acpi_init(struct radeon_device *rdev); | |
1577 | #else | |
1578 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } | |
1579 | #endif | |
1580 | ||
4c788679 JG |
1581 | #include "radeon_object.h" |
1582 | ||
771fe6b9 | 1583 | #endif |