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drm/radeon: allow selection of alignment in the sub-allocator
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
771fe6b9
JG		 100
101/*
102 * Copy from radeon_drv.h so we don't have to include both and have conflicting
103 * symbol;
104 */
bb635567
JG		 105#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
106#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 107/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 108#define RADEON_IB_POOL_SIZE 16
109#define RADEON_DEBUGFS_MAX_COMPONENTS 32
110#define RADEONFB_CONN_LIMIT 4
111#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 112
1b37078b 113/* max number of rings */
f2ba57b5 114#define RADEON_NUM_RINGS 6
bb635567
JG		 115
116/* fence seq are set to this number when signaled */
117#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 118
119/* internal ring indices */
120/* r1xx+ has gfx CP ring */
f2ba57b5 121#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 122
123/* cayman has 2 compute CP rings */
f2ba57b5
CK		 124#define CAYMAN_RING_TYPE_CP1_INDEX 1
125#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 126
4d75658b
AD		 127/* R600+ has an async dma ring */
128#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 129/* cayman add a second async dma ring */
130#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 131
f2ba57b5
CK		 132/* R600+ */
133#define R600_RING_TYPE_UVD_INDEX 5
134
721604a1 135/* hardcode those limit for now */
ca19f21e 136#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 137#define RADEON_VA_RESERVED_SIZE (8 << 20)
138#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 139
ec46c76d
AD		 140/* reset flags */
141#define RADEON_RESET_GFX (1 << 0)
142#define RADEON_RESET_COMPUTE (1 << 1)
143#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 144#define RADEON_RESET_CP (1 << 3)
145#define RADEON_RESET_GRBM (1 << 4)
146#define RADEON_RESET_DMA1 (1 << 5)
147#define RADEON_RESET_RLC (1 << 6)
148#define RADEON_RESET_SEM (1 << 7)
149#define RADEON_RESET_IH (1 << 8)
150#define RADEON_RESET_VMC (1 << 9)
151#define RADEON_RESET_MC (1 << 10)
152#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 153
9e05fa1d
AD		 154/* max cursor sizes (in pixels) */
155#define CURSOR_WIDTH 64
156#define CURSOR_HEIGHT 64
157
158#define CIK_CURSOR_WIDTH 128
159#define CIK_CURSOR_HEIGHT 128
160
771fe6b9
JG		 161/*
162 * Errata workarounds.
163 */
164enum radeon_pll_errata {
165 CHIP_ERRATA_R300_CG = 0x00000001,
166 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
167 CHIP_ERRATA_PLL_DELAY = 0x00000004
168};
169
170
171struct radeon_device;
172
173
174/*
175 * BIOS.
176 */
177bool radeon_get_bios(struct radeon_device *rdev);
178
179/*
3ce0a23d 180 * Dummy page
771fe6b9 181 */
3ce0a23d
JG		 182struct radeon_dummy_page {
183 struct page *page;
184 dma_addr_t addr;
185};
186int radeon_dummy_page_init(struct radeon_device *rdev);
187void radeon_dummy_page_fini(struct radeon_device *rdev);
188
771fe6b9 189
3ce0a23d
JG		 190/*
191 * Clocks
192 */
771fe6b9
JG		 193struct radeon_clock {
194 struct radeon_pll p1pll;
195 struct radeon_pll p2pll;
bcc1c2a1 196 struct radeon_pll dcpll;
771fe6b9
JG		 197 struct radeon_pll spll;
198 struct radeon_pll mpll;
199 /* 10 Khz units */
200 uint32_t default_mclk;
201 uint32_t default_sclk;
bcc1c2a1 202 uint32_t default_dispclk;
4489cd62 203 uint32_t current_dispclk;
bcc1c2a1 204 uint32_t dp_extclk;
b20f9bef 205 uint32_t max_pixel_clock;
771fe6b9
JG		 206};
207
7433874e
RM		 208/*
209 * Power management
210 */
211int radeon_pm_init(struct radeon_device *rdev);
29fb52ca 212void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 213void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 214void radeon_pm_suspend(struct radeon_device *rdev);
215void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 216void radeon_combios_get_power_modes(struct radeon_device *rdev);
217void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 218int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
219 u8 clock_type,
220 u32 clock,
221 bool strobe_mode,
222 struct atom_clock_dividers *dividers);
eaa778af
AD		 223int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
224 u32 clock,
225 bool strobe_mode,
226 struct atom_mpll_param *mpll_param);
8a83ec5e 227void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 228int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
229 u16 voltage_level, u8 voltage_type,
230 u32 *gpio_value, u32 *gpio_mask);
231void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
232 u32 eng_clock, u32 mem_clock);
233int radeon_atom_get_voltage_step(struct radeon_device *rdev,
234 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 235int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
236 u16 voltage_id, u16 *voltage);
beb79f40
AD		 237int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
238 u16 *voltage,
239 u16 leakage_idx);
ae5b0abb
AD		 240int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
241 u8 voltage_type,
242 u16 nominal_voltage,
243 u16 *true_voltage);
244int radeon_atom_get_min_voltage(struct radeon_device *rdev,
245 u8 voltage_type, u16 *min_voltage);
246int radeon_atom_get_max_voltage(struct radeon_device *rdev,
247 u8 voltage_type, u16 *max_voltage);
248int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 249 u8 voltage_type, u8 voltage_mode,
ae5b0abb 250 struct atom_voltage_table *voltage_table);
58653abd
AD		 251bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
252 u8 voltage_type, u8 voltage_mode);
ae5b0abb
AD		 253void radeon_atom_update_memory_dll(struct radeon_device *rdev,
254 u32 mem_clock);
255void radeon_atom_set_ac_timing(struct radeon_device *rdev,
256 u32 mem_clock);
257int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
258 u8 module_index,
259 struct atom_mc_reg_table *reg_table);
260int radeon_atom_get_memory_info(struct radeon_device *rdev,
261 u8 module_index, struct atom_memory_info *mem_info);
262int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
263 bool gddr5, u8 module_index,
264 struct atom_memory_clock_range_table *mclk_range_table);
265int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
266 u16 voltage_id, u16 *voltage);
f892034a 267void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 268extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
269 unsigned *bankh, unsigned *mtaspect,
270 unsigned *tile_split);
3ce0a23d 271
771fe6b9
JG		 272/*
273 * Fences.
274 */
275struct radeon_fence_driver {
276 uint32_t scratch_reg;
30eb77f4
JG		 277 uint64_t gpu_addr;
278 volatile uint32_t *cpu_addr;
68e250b7
CK		 279 /* sync_seq is protected by ring emission lock */
280 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 281 atomic64_t last_seq;
36abacae 282 unsigned long last_activity;
0a0c7596 283 bool initialized;
771fe6b9
JG		 284};
285
286struct radeon_fence {
287 struct radeon_device *rdev;
288 struct kref kref;
771fe6b9 289 /* protected by radeon_fence.lock */
bb635567 290 uint64_t seq;
7465280c 291 /* RB, DMA, etc. */
bb635567 292 unsigned ring;
771fe6b9
JG		 293};
294
30eb77f4
JG		 295int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
296int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 297void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 298void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 299int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 300void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 301bool radeon_fence_signaled(struct radeon_fence *fence);
302int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
8a47cc9e 303int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
5f8f635e 304int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
0085c950
JG		 305int radeon_fence_wait_any(struct radeon_device *rdev,
306 struct radeon_fence **fences,
307 bool intr);
771fe6b9
JG		 308struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
309void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 310unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 311bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
312void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
313static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
314 struct radeon_fence *b)
315{
316 if (!a) {
317 return b;
318 }
319
320 if (!b) {
321 return a;
322 }
323
324 BUG_ON(a->ring != b->ring);
325
326 if (a->seq > b->seq) {
327 return a;
328 } else {
329 return b;
330 }
331}
771fe6b9 332
ee60e29f
CK		 333static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
334 struct radeon_fence *b)
335{
336 if (!a) {
337 return false;
338 }
339
340 if (!b) {
341 return true;
342 }
343
344 BUG_ON(a->ring != b->ring);
345
346 return a->seq < b->seq;
347}
348
e024e110
DA		 349/*
350 * Tiling registers
351 */
352struct radeon_surface_reg {
4c788679 353 struct radeon_bo *bo;
e024e110
DA		 354};
355
356#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 357
358/*
4c788679 359 * TTM.
771fe6b9 360 */
4c788679
JG		 361struct radeon_mman {
362 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 363 struct drm_global_reference mem_global_ref;
4c788679 364 struct ttm_bo_device bdev;
0a0c7596
JG		 365 bool mem_global_referenced;
366 bool initialized;
4c788679
JG		 367};
368
721604a1
JG		 369/* bo virtual address in a specific vm */
370struct radeon_bo_va {
e971bd5e 371 /* protected by bo being reserved */
721604a1 372 struct list_head bo_list;
721604a1
JG		 373 uint64_t soffset;
374 uint64_t eoffset;
375 uint32_t flags;
376 bool valid;
e971bd5e
CK		 377 unsigned ref_count;
378
379 /* protected by vm mutex */
380 struct list_head vm_list;
381
382 /* constant after initialization */
383 struct radeon_vm *vm;
384 struct radeon_bo *bo;
721604a1
JG		 385};
386
4c788679
JG		 387struct radeon_bo {
388 /* Protected by gem.mutex */
389 struct list_head list;
390 /* Protected by tbo.reserved */
312ea8da
JG		 391 u32 placements[3];
392 struct ttm_placement placement;
4c788679
JG		 393 struct ttm_buffer_object tbo;
394 struct ttm_bo_kmap_obj kmap;
395 unsigned pin_count;
396 void *kptr;
397 u32 tiling_flags;
398 u32 pitch;
399 int surface_reg;
721604a1
JG		 400 /* list of all virtual address to which this bo
401 * is associated to
402 */
403 struct list_head va;
4c788679
JG		 404 /* Constant after initialization */
405 struct radeon_device *rdev;
441921d5 406 struct drm_gem_object gem_base;
63bc620b 407
409851f4
JG		 408 struct ttm_bo_kmap_obj dma_buf_vmap;
409 pid_t pid;
4c788679 410};
7e4d15d9 411#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 412
4c788679 413struct radeon_bo_list {
147666fb 414 struct ttm_validate_buffer tv;
4c788679 415 struct radeon_bo *bo;
771fe6b9 416 uint64_t gpu_offset;
4474f3a9
CK		 417 bool written;
418 unsigned domain;
419 unsigned alt_domain;
4c788679 420 u32 tiling_flags;
771fe6b9
JG		 421};
422
409851f4
JG		 423int radeon_gem_debugfs_init(struct radeon_device *rdev);
424
b15ba512
JG		 425/* sub-allocation manager, it has to be protected by another lock.
426 * By conception this is an helper for other part of the driver
427 * like the indirect buffer or semaphore, which both have their
428 * locking.
429 *
430 * Principe is simple, we keep a list of sub allocation in offset
431 * order (first entry has offset == 0, last entry has the highest
432 * offset).
433 *
434 * When allocating new object we first check if there is room at
435 * the end total_size - (last_object_offset + last_object_size) >=
436 * alloc_size. If so we allocate new object there.
437 *
438 * When there is not enough room at the end, we start waiting for
439 * each sub object until we reach object_offset+object_size >=
440 * alloc_size, this object then become the sub object we return.
441 *
442 * Alignment can't be bigger than page size.
443 *
444 * Hole are not considered for allocation to keep things simple.
445 * Assumption is that there won't be hole (all object on same
446 * alignment).
447 */
448struct radeon_sa_manager {
bfb38d35 449 wait_queue_head_t wq;
b15ba512 450 struct radeon_bo *bo;
c3b7fe8b
CK		 451 struct list_head *hole;
452 struct list_head flist[RADEON_NUM_RINGS];
453 struct list_head olist;
b15ba512
JG		 454 unsigned size;
455 uint64_t gpu_addr;
456 void *cpu_ptr;
457 uint32_t domain;
6c4f978b 458 uint32_t align;
b15ba512
JG		 459};
460
461struct radeon_sa_bo;
462
463/* sub-allocation buffer */
464struct radeon_sa_bo {
c3b7fe8b
CK		 465 struct list_head olist;
466 struct list_head flist;
b15ba512 467 struct radeon_sa_manager *manager;
e6661a96
CK		 468 unsigned soffset;
469 unsigned eoffset;
557017a0 470 struct radeon_fence *fence;
b15ba512
JG		 471};
472
771fe6b9
JG		 473/*
474 * GEM objects.
475 */
476struct radeon_gem {
4c788679 477 struct mutex mutex;
771fe6b9
JG		 478 struct list_head objects;
479};
480
481int radeon_gem_init(struct radeon_device *rdev);
482void radeon_gem_fini(struct radeon_device *rdev);
483int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 484 int alignment, int initial_domain,
485 bool discardable, bool kernel,
486 struct drm_gem_object **obj);
771fe6b9 487
ff72145b
DA		 488int radeon_mode_dumb_create(struct drm_file *file_priv,
489 struct drm_device *dev,
490 struct drm_mode_create_dumb *args);
491int radeon_mode_dumb_mmap(struct drm_file *filp,
492 struct drm_device *dev,
493 uint32_t handle, uint64_t *offset_p);
494int radeon_mode_dumb_destroy(struct drm_file *file_priv,
495 struct drm_device *dev,
496 uint32_t handle);
771fe6b9 497
c1341e52
JG		 498/*
499 * Semaphores.
500 */
c1341e52
JG		 501/* everything here is constant */
502struct radeon_semaphore {
a8c05940
JG		 503 struct radeon_sa_bo *sa_bo;
504 signed waiters;
c1341e52 505 uint64_t gpu_addr;
c1341e52
JG		 506};
507
c1341e52
JG		 508int radeon_semaphore_create(struct radeon_device *rdev,
509 struct radeon_semaphore **semaphore);
510void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
511 struct radeon_semaphore *semaphore);
512void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
513 struct radeon_semaphore *semaphore);
8f676c4c
CK		 514int radeon_semaphore_sync_rings(struct radeon_device *rdev,
515 struct radeon_semaphore *semaphore,
220907d9 516 int signaler, int waiter);
c1341e52 517void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 518 struct radeon_semaphore **semaphore,
a8c05940 519 struct radeon_fence *fence);
c1341e52 520
771fe6b9
JG		 521/*
522 * GART structures, functions & helpers
523 */
524struct radeon_mc;
525
a77f1718 526#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 527#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 528#define RADEON_GPU_PAGE_SHIFT 12
721604a1 529#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 530
771fe6b9
JG		 531struct radeon_gart {
532 dma_addr_t table_addr;
c9a1be96
JG		 533 struct radeon_bo *robj;
534 void *ptr;
771fe6b9
JG		 535 unsigned num_gpu_pages;
536 unsigned num_cpu_pages;
537 unsigned table_size;
771fe6b9
JG		 538 struct page **pages;
539 dma_addr_t *pages_addr;
540 bool ready;
541};
542
543int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
544void radeon_gart_table_ram_free(struct radeon_device *rdev);
545int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
546void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 547int radeon_gart_table_vram_pin(struct radeon_device *rdev);
548void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 549int radeon_gart_init(struct radeon_device *rdev);
550void radeon_gart_fini(struct radeon_device *rdev);
551void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
552 int pages);
553int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 554 int pages, struct page **pagelist,
555 dma_addr_t *dma_addr);
c9a1be96 556void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 557
558
559/*
560 * GPU MC structures, functions & helpers
561 */
562struct radeon_mc {
563 resource_size_t aper_size;
564 resource_size_t aper_base;
565 resource_size_t agp_base;
7a50f01a
DA		 566 /* for some chips with <= 32MB we need to lie
567 * about vram size near mc fb location */
3ce0a23d 568 u64 mc_vram_size;
d594e46a 569 u64 visible_vram_size;
3ce0a23d
JG		 570 u64 gtt_size;
571 u64 gtt_start;
572 u64 gtt_end;
3ce0a23d
JG		 573 u64 vram_start;
574 u64 vram_end;
771fe6b9 575 unsigned vram_width;
3ce0a23d 576 u64 real_vram_size;
771fe6b9
JG		 577 int vram_mtrr;
578 bool vram_is_ddr;
d594e46a 579 bool igp_sideport_enabled;
8d369bb1 580 u64 gtt_base_align;
9ed8b1f9 581 u64 mc_mask;
771fe6b9
JG		 582};
583
06b6476d
AD		 584bool radeon_combios_sideport_present(struct radeon_device *rdev);
585bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 586
587/*
588 * GPU scratch registers structures, functions & helpers
589 */
590struct radeon_scratch {
591 unsigned num_reg;
724c80e1 592 uint32_t reg_base;
771fe6b9
JG		 593 bool free[32];
594 uint32_t reg[32];
595};
596
597int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
598void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
599
75efdee1
AD		 600/*
601 * GPU doorbell structures, functions & helpers
602 */
603struct radeon_doorbell {
604 u32 num_pages;
605 bool free[1024];
606 /* doorbell mmio */
607 resource_size_t base;
608 resource_size_t size;
609 void __iomem *ptr;
610};
611
612int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
613void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 614
615/*
616 * IRQS.
617 */
6f34be50
AD		 618
619struct radeon_unpin_work {
620 struct work_struct work;
621 struct radeon_device *rdev;
622 int crtc_id;
623 struct radeon_fence *fence;
624 struct drm_pending_vblank_event *event;
625 struct radeon_bo *old_rbo;
626 u64 new_crtc_base;
627};
628
629struct r500_irq_stat_regs {
630 u32 disp_int;
f122c610 631 u32 hdmi0_status;
6f34be50
AD		 632};
633
634struct r600_irq_stat_regs {
635 u32 disp_int;
636 u32 disp_int_cont;
637 u32 disp_int_cont2;
638 u32 d1grph_int;
639 u32 d2grph_int;
f122c610
AD		 640 u32 hdmi0_status;
641 u32 hdmi1_status;
6f34be50
AD		 642};
643
644struct evergreen_irq_stat_regs {
645 u32 disp_int;
646 u32 disp_int_cont;
647 u32 disp_int_cont2;
648 u32 disp_int_cont3;
649 u32 disp_int_cont4;
650 u32 disp_int_cont5;
651 u32 d1grph_int;
652 u32 d2grph_int;
653 u32 d3grph_int;
654 u32 d4grph_int;
655 u32 d5grph_int;
656 u32 d6grph_int;
f122c610
AD		 657 u32 afmt_status1;
658 u32 afmt_status2;
659 u32 afmt_status3;
660 u32 afmt_status4;
661 u32 afmt_status5;
662 u32 afmt_status6;
6f34be50
AD		 663};
664
a59781bb
AD		 665struct cik_irq_stat_regs {
666 u32 disp_int;
667 u32 disp_int_cont;
668 u32 disp_int_cont2;
669 u32 disp_int_cont3;
670 u32 disp_int_cont4;
671 u32 disp_int_cont5;
672 u32 disp_int_cont6;
673};
674
6f34be50
AD		 675union radeon_irq_stat_regs {
676 struct r500_irq_stat_regs r500;
677 struct r600_irq_stat_regs r600;
678 struct evergreen_irq_stat_regs evergreen;
a59781bb 679 struct cik_irq_stat_regs cik;
6f34be50
AD		 680};
681
54bd5206
IH		 682#define RADEON_MAX_HPD_PINS 6
683#define RADEON_MAX_CRTCS 6
f122c610 684#define RADEON_MAX_AFMT_BLOCKS 6
54bd5206 685
771fe6b9 686struct radeon_irq {
fb98257a
CK		 687 bool installed;
688 spinlock_t lock;
736fc37f 689 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 690 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 691 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 692 wait_queue_head_t vblank_queue;
693 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 694 bool afmt[RADEON_MAX_AFMT_BLOCKS];
695 union radeon_irq_stat_regs stat_regs;
4a6369e9 696 bool dpm_thermal;
771fe6b9
JG		 697};
698
699int radeon_irq_kms_init(struct radeon_device *rdev);
700void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 701void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
702void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 703void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
704void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 705void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
706void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
707void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
708void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 709
710/*
e32eb50d 711 * CP & rings.
771fe6b9 712 */
7465280c 713
771fe6b9 714struct radeon_ib {
68470ae7
JG		 715 struct radeon_sa_bo *sa_bo;
716 uint32_t length_dw;
717 uint64_t gpu_addr;
718 uint32_t *ptr;
876dc9f3 719 int ring;
68470ae7 720 struct radeon_fence *fence;
4bf3dd92 721 struct radeon_vm *vm;
68470ae7 722 bool is_const_ib;
220907d9 723 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
68470ae7 724 struct radeon_semaphore *semaphore;
771fe6b9
JG		 725};
726
e32eb50d 727struct radeon_ring {
4c788679 728 struct radeon_bo *ring_obj;
771fe6b9
JG		 729 volatile uint32_t *ring;
730 unsigned rptr;
5596a9db
CK		 731 unsigned rptr_offs;
732 unsigned rptr_reg;
45df6803 733 unsigned rptr_save_reg;
89d35807
AD		 734 u64 next_rptr_gpu_addr;
735 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 736 unsigned wptr;
737 unsigned wptr_old;
5596a9db 738 unsigned wptr_reg;
771fe6b9
JG		 739 unsigned ring_size;
740 unsigned ring_free_dw;
741 int count_dw;
069211e5
CK		 742 unsigned long last_activity;
743 unsigned last_rptr;
771fe6b9
JG		 744 uint64_t gpu_addr;
745 uint32_t align_mask;
746 uint32_t ptr_mask;
771fe6b9 747 bool ready;
78c5560a
AD		 748 u32 ptr_reg_shift;
749 u32 ptr_reg_mask;
750 u32 nop;
8b25ed34 751 u32 idx;
5f0839c1
JG		 752 u64 last_semaphore_signal_addr;
753 u64 last_semaphore_wait_addr;
963e81f9
AD		 754 /* for CIK queues */
755 u32 me;
756 u32 pipe;
757 u32 queue;
758 struct radeon_bo *mqd_obj;
759 u32 doorbell_page_num;
760 u32 doorbell_offset;
761 unsigned wptr_offs;
762};
763
764struct radeon_mec {
765 struct radeon_bo *hpd_eop_obj;
766 u64 hpd_eop_gpu_addr;
767 u32 num_pipe;
768 u32 num_mec;
769 u32 num_queue;
771fe6b9
JG		 770};
771
721604a1
JG		 772/*
773 * VM
774 */
ee60e29f 775
fa87e62d 776/* maximum number of VMIDs */
ee60e29f
CK		 777#define RADEON_NUM_VM 16
778
fa87e62d
DC		 779/* defines number of bits in page table versus page directory,
780 * a page is 4KB so we have 12 bits offset, 9 bits in the page
781 * table and the remaining 19 bits are in the page directory */
782#define RADEON_VM_BLOCK_SIZE 9
783
784/* number of entries in page table */
785#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
786
721604a1
JG		 787struct radeon_vm {
788 struct list_head list;
789 struct list_head va;
ee60e29f 790 unsigned id;
90a51a32
CK		 791
792 /* contains the page directory */
793 struct radeon_sa_bo *page_directory;
794 uint64_t pd_gpu_addr;
795
796 /* array of page tables, one for each page directory entry */
797 struct radeon_sa_bo **page_tables;
798
721604a1
JG		 799 struct mutex mutex;
800 /* last fence for cs using this vm */
801 struct radeon_fence *fence;
9b40e5d8
CK		 802 /* last flush or NULL if we still need to flush */
803 struct radeon_fence *last_flush;
721604a1
JG		 804};
805
721604a1 806struct radeon_vm_manager {
36ff39c4 807 struct mutex lock;
721604a1 808 struct list_head lru_vm;
ee60e29f 809 struct radeon_fence *active[RADEON_NUM_VM];
721604a1
JG		 810 struct radeon_sa_manager sa_manager;
811 uint32_t max_pfn;
721604a1
JG		 812 /* number of VMIDs */
813 unsigned nvm;
814 /* vram base address for page table entry */
815 u64 vram_base_offset;
67e915e4
AD		 816 /* is vm enabled? */
817 bool enabled;
721604a1
JG		 818};
819
820/*
821 * file private structure
822 */
823struct radeon_fpriv {
824 struct radeon_vm vm;
825};
826
d8f60cfc
AD		 827/*
828 * R6xx+ IH ring
829 */
830struct r600_ih {
4c788679 831 struct radeon_bo *ring_obj;
d8f60cfc
AD		 832 volatile uint32_t *ring;
833 unsigned rptr;
d8f60cfc
AD		 834 unsigned ring_size;
835 uint64_t gpu_addr;
d8f60cfc 836 uint32_t ptr_mask;
c20dc369 837 atomic_t lock;
d8f60cfc
AD		 838 bool enabled;
839};
840
8eec9d6f
IH		 841struct r600_blit_cp_primitives {
842 void (*set_render_target)(struct radeon_device *rdev, int format,
843 int w, int h, u64 gpu_addr);
844 void (*cp_set_surface_sync)(struct radeon_device *rdev,
845 u32 sync_type, u32 size,
846 u64 mc_addr);
847 void (*set_shaders)(struct radeon_device *rdev);
848 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
849 void (*set_tex_resource)(struct radeon_device *rdev,
850 int format, int w, int h, int pitch,
9bb7703c 851 u64 gpu_addr, u32 size);
8eec9d6f
IH		 852 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
853 int x2, int y2);
854 void (*draw_auto)(struct radeon_device *rdev);
855 void (*set_default_state)(struct radeon_device *rdev);
856};
857
3ce0a23d 858struct r600_blit {
4c788679 859 struct radeon_bo *shader_obj;
8eec9d6f
IH		 860 struct r600_blit_cp_primitives primitives;
861 int max_dim;
862 int ring_size_common;
863 int ring_size_per_loop;
3ce0a23d
JG		 864 u64 shader_gpu_addr;
865 u32 vs_offset, ps_offset;
866 u32 state_offset;
867 u32 state_len;
3ce0a23d
JG		 868};
869
347e7592 870/*
2948f5e6 871 * RLC stuff
347e7592 872 */
2948f5e6
AD		 873#include "clearstate_defs.h"
874
875struct radeon_rlc {
347e7592
AD		 876 /* for power gating */
877 struct radeon_bo *save_restore_obj;
878 uint64_t save_restore_gpu_addr;
2948f5e6
AD		 879 volatile uint32_t *sr_ptr;
880 u32 *reg_list;
881 u32 reg_list_size;
347e7592
AD		 882 /* for clear state */
883 struct radeon_bo *clear_state_obj;
884 uint64_t clear_state_gpu_addr;
2948f5e6
AD		 885 volatile uint32_t *cs_ptr;
886 struct cs_section_def *cs_data;
347e7592
AD		 887};
888
69e130a6 889int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 890 struct radeon_ib *ib, struct radeon_vm *vm,
891 unsigned size);
f2e39221 892void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
43f1214a 893void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
4ef72566
CK		 894int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
895 struct radeon_ib *const_ib);
771fe6b9
JG		 896int radeon_ib_pool_init(struct radeon_device *rdev);
897void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 898int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 899/* Ring access between begin & end cannot sleep */
89d35807
AD		 900bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
901 struct radeon_ring *ring);
e32eb50d
CK		 902void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
903int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
904int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
905void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
906void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 907void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 908void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
909int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
7b9ef16b 910void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
069211e5
CK		 911void radeon_ring_lockup_update(struct radeon_ring *ring);
912bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 913unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
914 uint32_t **data);
915int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
916 unsigned size, uint32_t *data);
e32eb50d 917int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
78c5560a
AD		 918 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
919 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
e32eb50d 920void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 921
922
4d75658b
AD		 923/* r600 async dma */
924void r600_dma_stop(struct radeon_device *rdev);
925int r600_dma_resume(struct radeon_device *rdev);
926void r600_dma_fini(struct radeon_device *rdev);
927
8c5fd7ef
AD		 928void cayman_dma_stop(struct radeon_device *rdev);
929int cayman_dma_resume(struct radeon_device *rdev);
930void cayman_dma_fini(struct radeon_device *rdev);
931
771fe6b9
JG		 932/*
933 * CS.
934 */
935struct radeon_cs_reloc {
936 struct drm_gem_object *gobj;
4c788679
JG		 937 struct radeon_bo *robj;
938 struct radeon_bo_list lobj;
771fe6b9
JG		 939 uint32_t handle;
940 uint32_t flags;
941};
942
943struct radeon_cs_chunk {
944 uint32_t chunk_id;
945 uint32_t length_dw;
721604a1
JG		 946 int kpage_idx[2];
947 uint32_t *kpage[2];
771fe6b9 948 uint32_t *kdata;
721604a1
JG		 949 void __user *user_ptr;
950 int last_copied_page;
951 int last_page_index;
771fe6b9
JG		 952};
953
954struct radeon_cs_parser {
c8c15ff1 955 struct device *dev;
771fe6b9
JG		 956 struct radeon_device *rdev;
957 struct drm_file *filp;
958 /* chunks */
959 unsigned nchunks;
960 struct radeon_cs_chunk *chunks;
961 uint64_t *chunks_array;
962 /* IB */
963 unsigned idx;
964 /* relocations */
965 unsigned nrelocs;
966 struct radeon_cs_reloc *relocs;
967 struct radeon_cs_reloc **relocs_ptr;
968 struct list_head validated;
cf4ccd01 969 unsigned dma_reloc_idx;
771fe6b9
JG		 970 /* indices of various chunks */
971 int chunk_ib_idx;
972 int chunk_relocs_idx;
721604a1 973 int chunk_flags_idx;
dfcf5f36 974 int chunk_const_ib_idx;
f2e39221
JG		 975 struct radeon_ib ib;
976 struct radeon_ib const_ib;
771fe6b9 977 void *track;
3ce0a23d 978 unsigned family;
e70f224c 979 int parser_error;
721604a1
JG		 980 u32 cs_flags;
981 u32 ring;
982 s32 priority;
ecff665f 983 struct ww_acquire_ctx ticket;
771fe6b9
JG		 984};
985
513bcb46 986extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
ce580fab 987extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
513bcb46 988
771fe6b9
JG		 989struct radeon_cs_packet {
990 unsigned idx;
991 unsigned type;
992 unsigned reg;
993 unsigned opcode;
994 int count;
995 unsigned one_reg_wr;
996};
997
998typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
999 struct radeon_cs_packet *pkt,
1000 unsigned idx, unsigned reg);
1001typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1002 struct radeon_cs_packet *pkt);
1003
1004
1005/*
1006 * AGP
1007 */
1008int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1009void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1010void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1011void radeon_agp_fini(struct radeon_device *rdev);
1012
1013
1014/*
1015 * Writeback
1016 */
1017struct radeon_wb {
4c788679 1018 struct radeon_bo *wb_obj;
771fe6b9
JG		 1019 volatile uint32_t *wb;
1020 uint64_t gpu_addr;
724c80e1 1021 bool enabled;
d0f8a854 1022 bool use_event;
771fe6b9
JG		 1023};
1024
724c80e1 1025#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1026#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1027#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1028#define RADEON_WB_CP1_RPTR_OFFSET 1280
1029#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1030#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1031#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1032#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
f2ba57b5 1033#define R600_WB_UVD_RPTR_OFFSET 2560
d0f8a854 1034#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1035#define CIK_WB_CP1_WPTR_OFFSET 3328
1036#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1037
c93bb85b
JG		 1038/**
1039 * struct radeon_pm - power management datas
1040 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1041 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1042 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1043 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1044 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1045 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1046 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1047 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1048 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1049 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1050 * @needed_bandwidth: current bandwidth needs
1051 *
1052 * It keeps track of various data needed to take powermanagement decision.
25985edc 1053 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1054 * Equation between gpu/memory clock and available bandwidth is hw dependent
1055 * (type of memory, bus size, efficiency, ...)
1056 */
ce8f5370
AD		 1057
1058enum radeon_pm_method {
1059 PM_METHOD_PROFILE,
1060 PM_METHOD_DYNPM,
da321c8a 1061 PM_METHOD_DPM,
ce8f5370
AD		 1062};
1063
1064enum radeon_dynpm_state {
1065 DYNPM_STATE_DISABLED,
1066 DYNPM_STATE_MINIMUM,
1067 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1068 DYNPM_STATE_ACTIVE,
1069 DYNPM_STATE_SUSPENDED,
c913e23a 1070};
ce8f5370
AD		 1071enum radeon_dynpm_action {
1072 DYNPM_ACTION_NONE,
1073 DYNPM_ACTION_MINIMUM,
1074 DYNPM_ACTION_DOWNCLOCK,
1075 DYNPM_ACTION_UPCLOCK,
1076 DYNPM_ACTION_DEFAULT
c913e23a 1077};
56278a8e
AD		 1078
1079enum radeon_voltage_type {
1080 VOLTAGE_NONE = 0,
1081 VOLTAGE_GPIO,
1082 VOLTAGE_VDDC,
1083 VOLTAGE_SW
1084};
1085
0ec0e74f 1086enum radeon_pm_state_type {
da321c8a 1087 /* not used for dpm */
0ec0e74f
AD		 1088 POWER_STATE_TYPE_DEFAULT,
1089 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1090 /* user selectable states */
0ec0e74f
AD		 1091 POWER_STATE_TYPE_BATTERY,
1092 POWER_STATE_TYPE_BALANCED,
1093 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1094 /* internal states */
1095 POWER_STATE_TYPE_INTERNAL_UVD,
1096 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1097 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1098 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1099 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1100 POWER_STATE_TYPE_INTERNAL_BOOT,
1101 POWER_STATE_TYPE_INTERNAL_THERMAL,
1102 POWER_STATE_TYPE_INTERNAL_ACPI,
1103 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1104 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1105};
1106
ce8f5370
AD		 1107enum radeon_pm_profile_type {
1108 PM_PROFILE_DEFAULT,
1109 PM_PROFILE_AUTO,
1110 PM_PROFILE_LOW,
c9e75b21 1111 PM_PROFILE_MID,
ce8f5370
AD		 1112 PM_PROFILE_HIGH,
1113};
1114
1115#define PM_PROFILE_DEFAULT_IDX 0
1116#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1117#define PM_PROFILE_MID_SH_IDX 2
1118#define PM_PROFILE_HIGH_SH_IDX 3
1119#define PM_PROFILE_LOW_MH_IDX 4
1120#define PM_PROFILE_MID_MH_IDX 5
1121#define PM_PROFILE_HIGH_MH_IDX 6
1122#define PM_PROFILE_MAX 7
ce8f5370
AD		 1123
1124struct radeon_pm_profile {
1125 int dpms_off_ps_idx;
1126 int dpms_on_ps_idx;
1127 int dpms_off_cm_idx;
1128 int dpms_on_cm_idx;
516d0e46
AD		 1129};
1130
21a8122a
AD		 1131enum radeon_int_thermal_type {
1132 THERMAL_TYPE_NONE,
da321c8a
AD		 1133 THERMAL_TYPE_EXTERNAL,
1134 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1135 THERMAL_TYPE_RV6XX,
1136 THERMAL_TYPE_RV770,
da321c8a 1137 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1138 THERMAL_TYPE_EVERGREEN,
e33df25f 1139 THERMAL_TYPE_SUMO,
4fddba1f 1140 THERMAL_TYPE_NI,
14607d08 1141 THERMAL_TYPE_SI,
da321c8a 1142 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1143 THERMAL_TYPE_CI,
21a8122a
AD		 1144};
1145
56278a8e
AD		 1146struct radeon_voltage {
1147 enum radeon_voltage_type type;
1148 /* gpio voltage */
1149 struct radeon_gpio_rec gpio;
1150 u32 delay; /* delay in usec from voltage drop to sclk change */
1151 bool active_high; /* voltage drop is active when bit is high */
1152 /* VDDC voltage */
1153 u8 vddc_id; /* index into vddc voltage table */
1154 u8 vddci_id; /* index into vddci voltage table */
1155 bool vddci_enabled;
1156 /* r6xx+ sw */
2feea49a
AD		 1157 u16 voltage;
1158 /* evergreen+ vddci */
1159 u16 vddci;
56278a8e
AD		 1160};
1161
d7311171
AD		 1162/* clock mode flags */
1163#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1164
56278a8e
AD		 1165struct radeon_pm_clock_info {
1166 /* memory clock */
1167 u32 mclk;
1168 /* engine clock */
1169 u32 sclk;
1170 /* voltage info */
1171 struct radeon_voltage voltage;
d7311171 1172 /* standardized clock flags */
56278a8e
AD		 1173 u32 flags;
1174};
1175
a48b9b4e 1176/* state flags */
d7311171 1177#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1178
56278a8e 1179struct radeon_power_state {
0ec0e74f 1180 enum radeon_pm_state_type type;
8f3f1c9a 1181 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1182 /* number of valid clock modes in this power state */
1183 int num_clock_modes;
56278a8e 1184 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1185 /* standardized state flags */
1186 u32 flags;
79daedc9
AD		 1187 u32 misc; /* vbios specific flags */
1188 u32 misc2; /* vbios specific flags */
1189 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1190};
1191
27459324
RM		 1192/*
1193 * Some modes are overclocked by very low value, accept them
1194 */
1195#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1196
2e9d4c05
AD		 1197enum radeon_dpm_auto_throttle_src {
1198 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1199 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1200};
1201
1202enum radeon_dpm_event_src {
1203 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1204 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1205 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1206 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1207 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1208};
1209
da321c8a
AD		 1210struct radeon_ps {
1211 u32 caps; /* vbios flags */
1212 u32 class; /* vbios flags */
1213 u32 class2; /* vbios flags */
1214 /* UVD clocks */
1215 u32 vclk;
1216 u32 dclk;
1217 /* asic priv */
1218 void *ps_priv;
1219};
1220
1221struct radeon_dpm_thermal {
1222 /* thermal interrupt work */
1223 struct work_struct work;
1224 /* low temperature threshold */
1225 int min_temp;
1226 /* high temperature threshold */
1227 int max_temp;
1228 /* was interrupt low to high or high to low */
1229 bool high_to_low;
1230};
1231
d22b7e40
AD		 1232enum radeon_clk_action
1233{
1234 RADEON_SCLK_UP = 1,
1235 RADEON_SCLK_DOWN
1236};
1237
1238struct radeon_blacklist_clocks
1239{
1240 u32 sclk;
1241 u32 mclk;
1242 enum radeon_clk_action action;
1243};
1244
61b7d601
AD		 1245struct radeon_clock_and_voltage_limits {
1246 u32 sclk;
1247 u32 mclk;
1248 u32 vddc;
1249 u32 vddci;
1250};
1251
1252struct radeon_clock_array {
1253 u32 count;
1254 u32 *values;
1255};
1256
1257struct radeon_clock_voltage_dependency_entry {
1258 u32 clk;
1259 u16 v;
1260};
1261
1262struct radeon_clock_voltage_dependency_table {
1263 u32 count;
1264 struct radeon_clock_voltage_dependency_entry *entries;
1265};
1266
1267struct radeon_cac_leakage_entry {
1268 u16 vddc;
1269 u32 leakage;
1270};
1271
1272struct radeon_cac_leakage_table {
1273 u32 count;
1274 struct radeon_cac_leakage_entry *entries;
1275};
1276
929ee7a8
AD		 1277struct radeon_phase_shedding_limits_entry {
1278 u16 voltage;
1279 u32 sclk;
1280 u32 mclk;
1281};
1282
1283struct radeon_phase_shedding_limits_table {
1284 u32 count;
1285 struct radeon_phase_shedding_limits_entry *entries;
1286};
1287
a5cb318e
AD		 1288struct radeon_ppm_table {
1289 u8 ppm_design;
1290 u16 cpu_core_number;
1291 u32 platform_tdp;
1292 u32 small_ac_platform_tdp;
1293 u32 platform_tdc;
1294 u32 small_ac_platform_tdc;
1295 u32 apu_tdp;
1296 u32 dgpu_tdp;
1297 u32 dgpu_ulv_power;
1298 u32 tj_max;
1299};
1300
61b7d601
AD		 1301struct radeon_dpm_dynamic_state {
1302 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1303 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1304 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
4489cd62 1305 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
61b7d601
AD		 1306 struct radeon_clock_array valid_sclk_values;
1307 struct radeon_clock_array valid_mclk_values;
1308 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1309 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1310 u32 mclk_sclk_ratio;
1311 u32 sclk_mclk_delta;
1312 u16 vddc_vddci_delta;
1313 u16 min_vddc_for_pcie_gen2;
1314 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1315 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1316 struct radeon_ppm_table *ppm_table;
61b7d601
AD		 1317};
1318
1319struct radeon_dpm_fan {
1320 u16 t_min;
1321 u16 t_med;
1322 u16 t_high;
1323 u16 pwm_min;
1324 u16 pwm_med;
1325 u16 pwm_high;
1326 u8 t_hyst;
1327 u32 cycle_delay;
1328 u16 t_max;
1329 bool ucode_fan_control;
1330};
1331
32ce4652
AD		 1332enum radeon_pcie_gen {
1333 RADEON_PCIE_GEN1 = 0,
1334 RADEON_PCIE_GEN2 = 1,
1335 RADEON_PCIE_GEN3 = 2,
1336 RADEON_PCIE_GEN_INVALID = 0xffff
1337};
1338
70d01a5e
AD		 1339enum radeon_dpm_forced_level {
1340 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1341 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1342 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1343};
1344
da321c8a
AD		 1345struct radeon_dpm {
1346 struct radeon_ps *ps;
1347 /* number of valid power states */
1348 int num_ps;
1349 /* current power state that is active */
1350 struct radeon_ps *current_ps;
1351 /* requested power state */
1352 struct radeon_ps *requested_ps;
1353 /* boot up power state */
1354 struct radeon_ps *boot_ps;
1355 /* default uvd power state */
1356 struct radeon_ps *uvd_ps;
1357 enum radeon_pm_state_type state;
1358 enum radeon_pm_state_type user_state;
1359 u32 platform_caps;
1360 u32 voltage_response_time;
1361 u32 backbias_response_time;
1362 void *priv;
1363 u32 new_active_crtcs;
1364 int new_active_crtc_count;
1365 u32 current_active_crtcs;
1366 int current_active_crtc_count;
61b7d601
AD		 1367 struct radeon_dpm_dynamic_state dyn_state;
1368 struct radeon_dpm_fan fan;
1369 u32 tdp_limit;
1370 u32 near_tdp_limit;
a9e61410 1371 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1372 u32 sq_ramping_threshold;
1373 u32 cac_leakage;
1374 u16 tdp_od_limit;
1375 u32 tdp_adjustment;
1376 u16 load_line_slope;
1377 bool power_control;
5ca302f7 1378 bool ac_power;
da321c8a
AD		 1379 /* special states active */
1380 bool thermal_active;
8a227555 1381 bool uvd_active;
da321c8a
AD		 1382 /* thermal handling */
1383 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1384 /* forced levels */
1385 enum radeon_dpm_forced_level forced_level;
da321c8a
AD		 1386};
1387
1388void radeon_dpm_enable_power_state(struct radeon_device *rdev,
1389 enum radeon_pm_state_type dpm_state);
1390
1391
c93bb85b 1392struct radeon_pm {
c913e23a 1393 struct mutex mutex;
db7fce39
CK		 1394 /* write locked while reprogramming mclk */
1395 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1396 u32 active_crtcs;
1397 int active_crtc_count;
c913e23a 1398 int req_vblank;
839461d3 1399 bool vblank_sync;
c93bb85b
JG		 1400 fixed20_12 max_bandwidth;
1401 fixed20_12 igp_sideport_mclk;
1402 fixed20_12 igp_system_mclk;
1403 fixed20_12 igp_ht_link_clk;
1404 fixed20_12 igp_ht_link_width;
1405 fixed20_12 k8_bandwidth;
1406 fixed20_12 sideport_bandwidth;
1407 fixed20_12 ht_bandwidth;
1408 fixed20_12 core_bandwidth;
1409 fixed20_12 sclk;
f47299c5 1410 fixed20_12 mclk;
c93bb85b 1411 fixed20_12 needed_bandwidth;
0975b162 1412 struct radeon_power_state *power_state;
56278a8e
AD		 1413 /* number of valid power states */
1414 int num_power_states;
a48b9b4e
AD		 1415 int current_power_state_index;
1416 int current_clock_mode_index;
1417 int requested_power_state_index;
1418 int requested_clock_mode_index;
1419 int default_power_state_index;
1420 u32 current_sclk;
1421 u32 current_mclk;
2feea49a
AD		 1422 u16 current_vddc;
1423 u16 current_vddci;
9ace9f7b
AD		 1424 u32 default_sclk;
1425 u32 default_mclk;
2feea49a
AD		 1426 u16 default_vddc;
1427 u16 default_vddci;
29fb52ca 1428 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1429 /* selected pm method */
1430 enum radeon_pm_method pm_method;
1431 /* dynpm power management */
1432 struct delayed_work dynpm_idle_work;
1433 enum radeon_dynpm_state dynpm_state;
1434 enum radeon_dynpm_action dynpm_planned_action;
1435 unsigned long dynpm_action_timeout;
1436 bool dynpm_can_upclock;
1437 bool dynpm_can_downclock;
1438 /* profile-based power management */
1439 enum radeon_pm_profile_type profile;
1440 int profile_index;
1441 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1442 /* internal thermal controller on rv6xx+ */
1443 enum radeon_int_thermal_type int_thermal_type;
1444 struct device *int_hwmon_dev;
da321c8a
AD		 1445 /* dpm */
1446 bool dpm_enabled;
1447 struct radeon_dpm dpm;
c93bb85b
JG		 1448};
1449
a4c9e2ee
AD		 1450int radeon_pm_get_type_index(struct radeon_device *rdev,
1451 enum radeon_pm_state_type ps_type,
1452 int instance);
f2ba57b5
CK		 1453/*
1454 * UVD
1455 */
1456#define RADEON_MAX_UVD_HANDLES 10
1457#define RADEON_UVD_STACK_SIZE (1024*1024)
1458#define RADEON_UVD_HEAP_SIZE (1024*1024)
1459
1460struct radeon_uvd {
1461 struct radeon_bo *vcpu_bo;
1462 void *cpu_addr;
1463 uint64_t gpu_addr;
9cc2e0e9
CK		 1464 void *saved_bo;
1465 unsigned fw_size;
f2ba57b5
CK		 1466 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1467 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
55b51c88 1468 struct delayed_work idle_work;
f2ba57b5
CK		 1469};
1470
1471int radeon_uvd_init(struct radeon_device *rdev);
1472void radeon_uvd_fini(struct radeon_device *rdev);
1473int radeon_uvd_suspend(struct radeon_device *rdev);
1474int radeon_uvd_resume(struct radeon_device *rdev);
1475int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1476 uint32_t handle, struct radeon_fence **fence);
1477int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1478 uint32_t handle, struct radeon_fence **fence);
1479void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1480void radeon_uvd_free_handles(struct radeon_device *rdev,
1481 struct drm_file *filp);
1482int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1483void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1484int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1485 unsigned vclk, unsigned dclk,
1486 unsigned vco_min, unsigned vco_max,
1487 unsigned fb_factor, unsigned fb_mask,
1488 unsigned pd_min, unsigned pd_max,
1489 unsigned pd_even,
1490 unsigned *optimal_fb_div,
1491 unsigned *optimal_vclk_div,
1492 unsigned *optimal_dclk_div);
1493int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1494 unsigned cg_upll_func_cntl);
771fe6b9 1495
a92553ab 1496struct r600_audio {
a92553ab
RM		 1497 int channels;
1498 int rate;
1499 int bits_per_sample;
1500 u8 status_bits;
1501 u8 category_code;
1502};
1503
771fe6b9
JG		 1504/*
1505 * Benchmarking
1506 */
638dd7db 1507void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1508
1509
ecc0b326
MD		 1510/*
1511 * Testing
1512 */
1513void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1514void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1515 struct radeon_ring *cpA,
1516 struct radeon_ring *cpB);
60a7e396 1517void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1518
1519
771fe6b9
JG		 1520/*
1521 * Debugfs
1522 */
4d8bf9ae
CK		 1523struct radeon_debugfs {
1524 struct drm_info_list *files;
1525 unsigned num_files;
1526};
1527
771fe6b9
JG		 1528int radeon_debugfs_add_files(struct radeon_device *rdev,
1529 struct drm_info_list *files,
1530 unsigned nfiles);
1531int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9
JG		 1532
1533
1534/*
1535 * ASIC specific functions.
1536 */
1537struct radeon_asic {
068a117c 1538 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1539 void (*fini)(struct radeon_device *rdev);
1540 int (*resume)(struct radeon_device *rdev);
1541 int (*suspend)(struct radeon_device *rdev);
28d52043 1542 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1543 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1544 /* ioctl hw specific callback. Some hw might want to perform special
1545 * operation on specific ioctl. For instance on wait idle some hw
1546 * might want to perform and HDP flush through MMIO as it seems that
1547 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1548 * through ring.
1549 */
1550 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1551 /* check if 3D engine is idle */
1552 bool (*gui_idle)(struct radeon_device *rdev);
1553 /* wait for mc_idle */
1554 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1555 /* get the reference clock */
1556 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1557 /* get the gpu clock counter */
1558 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1559 /* gart */
c5b3b850
AD		 1560 struct {
1561 void (*tlb_flush)(struct radeon_device *rdev);
1562 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1563 } gart;
05b07147
CK		 1564 struct {
1565 int (*init)(struct radeon_device *rdev);
1566 void (*fini)(struct radeon_device *rdev);
2a6f1abb
CK		 1567
1568 u32 pt_ring_index;
43f1214a
AD		 1569 void (*set_page)(struct radeon_device *rdev,
1570 struct radeon_ib *ib,
1571 uint64_t pe,
dce34bfd
CK		 1572 uint64_t addr, unsigned count,
1573 uint32_t incr, uint32_t flags);
05b07147 1574 } vm;
54e88e06 1575 /* ring specific callbacks */
4c87bc26
CK		 1576 struct {
1577 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
721604a1 1578 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
4c87bc26 1579 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
e32eb50d 1580 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
4c87bc26 1581 struct radeon_semaphore *semaphore, bool emit_wait);
eb0c19c5 1582 int (*cs_parse)(struct radeon_cs_parser *p);
f712812e
AD		 1583 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1584 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1585 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
312c4a8c 1586 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
498522b4 1587 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
f93bdefe
AD		 1588
1589 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1590 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1591 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
4c87bc26 1592 } ring[RADEON_NUM_RINGS];
54e88e06 1593 /* irqs */
b35ea4ab
AD		 1594 struct {
1595 int (*set)(struct radeon_device *rdev);
1596 int (*process)(struct radeon_device *rdev);
1597 } irq;
54e88e06 1598 /* displays */
c79a49ca
AD		 1599 struct {
1600 /* display watermarks */
1601 void (*bandwidth_update)(struct radeon_device *rdev);
1602 /* get frame count */
1603 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1604 /* wait for vblank */
1605 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1606 /* set backlight level */
1607 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1608 /* get backlight level */
1609 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1610 /* audio callbacks */
1611 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1612 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1613 } display;
54e88e06 1614 /* copy functions for bo handling */
27cd7769
AD		 1615 struct {
1616 int (*blit)(struct radeon_device *rdev,
1617 uint64_t src_offset,
1618 uint64_t dst_offset,
1619 unsigned num_gpu_pages,
876dc9f3 1620 struct radeon_fence **fence);
27cd7769
AD		 1621 u32 blit_ring_index;
1622 int (*dma)(struct radeon_device *rdev,
1623 uint64_t src_offset,
1624 uint64_t dst_offset,
1625 unsigned num_gpu_pages,
876dc9f3 1626 struct radeon_fence **fence);
27cd7769
AD		 1627 u32 dma_ring_index;
1628 /* method used for bo copy */
1629 int (*copy)(struct radeon_device *rdev,
1630 uint64_t src_offset,
1631 uint64_t dst_offset,
1632 unsigned num_gpu_pages,
876dc9f3 1633 struct radeon_fence **fence);
27cd7769
AD		 1634 /* ring used for bo copies */
1635 u32 copy_ring_index;
1636 } copy;
54e88e06 1637 /* surfaces */
9e6f3d02
AD		 1638 struct {
1639 int (*set_reg)(struct radeon_device *rdev, int reg,
1640 uint32_t tiling_flags, uint32_t pitch,
1641 uint32_t offset, uint32_t obj_size);
1642 void (*clear_reg)(struct radeon_device *rdev, int reg);
1643 } surface;
54e88e06 1644 /* hotplug detect */
901ea57d
AD		 1645 struct {
1646 void (*init)(struct radeon_device *rdev);
1647 void (*fini)(struct radeon_device *rdev);
1648 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1649 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1650 } hpd;
da321c8a 1651 /* static power management */
a02fa397
AD		 1652 struct {
1653 void (*misc)(struct radeon_device *rdev);
1654 void (*prepare)(struct radeon_device *rdev);
1655 void (*finish)(struct radeon_device *rdev);
1656 void (*init_profile)(struct radeon_device *rdev);
1657 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1658 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1659 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1660 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1661 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1662 int (*get_pcie_lanes)(struct radeon_device *rdev);
1663 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1664 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1665 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
6bd1c385 1666 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1667 } pm;
da321c8a
AD		 1668 /* dynamic power management */
1669 struct {
1670 int (*init)(struct radeon_device *rdev);
1671 void (*setup_asic)(struct radeon_device *rdev);
1672 int (*enable)(struct radeon_device *rdev);
1673 void (*disable)(struct radeon_device *rdev);
84dd1928 1674 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1675 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1676 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1677 void (*display_configuration_changed)(struct radeon_device *rdev);
1678 void (*fini)(struct radeon_device *rdev);
1679 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1680 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1681 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1682 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1683 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1684 bool (*vblank_too_short)(struct radeon_device *rdev);
da321c8a 1685 } dpm;
6f34be50 1686 /* pageflipping */
0f9e006c
AD		 1687 struct {
1688 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1689 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1690 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1691 } pflip;
771fe6b9
JG		 1692};
1693
21f9a437
JG		 1694/*
1695 * Asic structures
1696 */
551ebd83 1697struct r100_asic {
225758d8
JG		 1698 const unsigned *reg_safe_bm;
1699 unsigned reg_safe_bm_size;
1700 u32 hdp_cntl;
551ebd83
DA		 1701};
1702
21f9a437 1703struct r300_asic {
225758d8
JG		 1704 const unsigned *reg_safe_bm;
1705 unsigned reg_safe_bm_size;
1706 u32 resync_scratch;
1707 u32 hdp_cntl;
21f9a437
JG		 1708};
1709
1710struct r600_asic {
225758d8
JG		 1711 unsigned max_pipes;
1712 unsigned max_tile_pipes;
1713 unsigned max_simds;
1714 unsigned max_backends;
1715 unsigned max_gprs;
1716 unsigned max_threads;
1717 unsigned max_stack_entries;
1718 unsigned max_hw_contexts;
1719 unsigned max_gs_threads;
1720 unsigned sx_max_export_size;
1721 unsigned sx_max_export_pos_size;
1722 unsigned sx_max_export_smx_size;
1723 unsigned sq_num_cf_insts;
1724 unsigned tiling_nbanks;
1725 unsigned tiling_npipes;
1726 unsigned tiling_group_size;
e7aeeba6 1727 unsigned tile_config;
e55b9422 1728 unsigned backend_map;
21f9a437
JG		 1729};
1730
1731struct rv770_asic {
225758d8
JG		 1732 unsigned max_pipes;
1733 unsigned max_tile_pipes;
1734 unsigned max_simds;
1735 unsigned max_backends;
1736 unsigned max_gprs;
1737 unsigned max_threads;
1738 unsigned max_stack_entries;
1739 unsigned max_hw_contexts;
1740 unsigned max_gs_threads;
1741 unsigned sx_max_export_size;
1742 unsigned sx_max_export_pos_size;
1743 unsigned sx_max_export_smx_size;
1744 unsigned sq_num_cf_insts;
1745 unsigned sx_num_of_sets;
1746 unsigned sc_prim_fifo_size;
1747 unsigned sc_hiz_tile_fifo_size;
1748 unsigned sc_earlyz_tile_fifo_fize;
1749 unsigned tiling_nbanks;
1750 unsigned tiling_npipes;
1751 unsigned tiling_group_size;
e7aeeba6 1752 unsigned tile_config;
e55b9422 1753 unsigned backend_map;
21f9a437
JG		 1754};
1755
32fcdbf4
AD		 1756struct evergreen_asic {
1757 unsigned num_ses;
1758 unsigned max_pipes;
1759 unsigned max_tile_pipes;
1760 unsigned max_simds;
1761 unsigned max_backends;
1762 unsigned max_gprs;
1763 unsigned max_threads;
1764 unsigned max_stack_entries;
1765 unsigned max_hw_contexts;
1766 unsigned max_gs_threads;
1767 unsigned sx_max_export_size;
1768 unsigned sx_max_export_pos_size;
1769 unsigned sx_max_export_smx_size;
1770 unsigned sq_num_cf_insts;
1771 unsigned sx_num_of_sets;
1772 unsigned sc_prim_fifo_size;
1773 unsigned sc_hiz_tile_fifo_size;
1774 unsigned sc_earlyz_tile_fifo_size;
1775 unsigned tiling_nbanks;
1776 unsigned tiling_npipes;
1777 unsigned tiling_group_size;
e7aeeba6 1778 unsigned tile_config;
e55b9422 1779 unsigned backend_map;
32fcdbf4
AD		 1780};
1781
fecf1d07
AD		 1782struct cayman_asic {
1783 unsigned max_shader_engines;
1784 unsigned max_pipes_per_simd;
1785 unsigned max_tile_pipes;
1786 unsigned max_simds_per_se;
1787 unsigned max_backends_per_se;
1788 unsigned max_texture_channel_caches;
1789 unsigned max_gprs;
1790 unsigned max_threads;
1791 unsigned max_gs_threads;
1792 unsigned max_stack_entries;
1793 unsigned sx_num_of_sets;
1794 unsigned sx_max_export_size;
1795 unsigned sx_max_export_pos_size;
1796 unsigned sx_max_export_smx_size;
1797 unsigned max_hw_contexts;
1798 unsigned sq_num_cf_insts;
1799 unsigned sc_prim_fifo_size;
1800 unsigned sc_hiz_tile_fifo_size;
1801 unsigned sc_earlyz_tile_fifo_size;
1802
1803 unsigned num_shader_engines;
1804 unsigned num_shader_pipes_per_simd;
1805 unsigned num_tile_pipes;
1806 unsigned num_simds_per_se;
1807 unsigned num_backends_per_se;
1808 unsigned backend_disable_mask_per_asic;
1809 unsigned backend_map;
1810 unsigned num_texture_channel_caches;
1811 unsigned mem_max_burst_length_bytes;
1812 unsigned mem_row_size_in_kb;
1813 unsigned shader_engine_tile_size;
1814 unsigned num_gpus;
1815 unsigned multi_gpu_tile_size;
1816
1817 unsigned tile_config;
fecf1d07
AD		 1818};
1819
0a96d72b
AD		 1820struct si_asic {
1821 unsigned max_shader_engines;
0a96d72b 1822 unsigned max_tile_pipes;
1a8ca750
AD		 1823 unsigned max_cu_per_sh;
1824 unsigned max_sh_per_se;
0a96d72b
AD		 1825 unsigned max_backends_per_se;
1826 unsigned max_texture_channel_caches;
1827 unsigned max_gprs;
1828 unsigned max_gs_threads;
1829 unsigned max_hw_contexts;
1830 unsigned sc_prim_fifo_size_frontend;
1831 unsigned sc_prim_fifo_size_backend;
1832 unsigned sc_hiz_tile_fifo_size;
1833 unsigned sc_earlyz_tile_fifo_size;
1834
0a96d72b
AD		 1835 unsigned num_tile_pipes;
1836 unsigned num_backends_per_se;
1837 unsigned backend_disable_mask_per_asic;
1838 unsigned backend_map;
1839 unsigned num_texture_channel_caches;
1840 unsigned mem_max_burst_length_bytes;
1841 unsigned mem_row_size_in_kb;
1842 unsigned shader_engine_tile_size;
1843 unsigned num_gpus;
1844 unsigned multi_gpu_tile_size;
1845
1846 unsigned tile_config;
64d7b8be 1847 uint32_t tile_mode_array[32];
0a96d72b
AD		 1848};
1849
8cc1a532
AD		 1850struct cik_asic {
1851 unsigned max_shader_engines;
1852 unsigned max_tile_pipes;
1853 unsigned max_cu_per_sh;
1854 unsigned max_sh_per_se;
1855 unsigned max_backends_per_se;
1856 unsigned max_texture_channel_caches;
1857 unsigned max_gprs;
1858 unsigned max_gs_threads;
1859 unsigned max_hw_contexts;
1860 unsigned sc_prim_fifo_size_frontend;
1861 unsigned sc_prim_fifo_size_backend;
1862 unsigned sc_hiz_tile_fifo_size;
1863 unsigned sc_earlyz_tile_fifo_size;
1864
1865 unsigned num_tile_pipes;
1866 unsigned num_backends_per_se;
1867 unsigned backend_disable_mask_per_asic;
1868 unsigned backend_map;
1869 unsigned num_texture_channel_caches;
1870 unsigned mem_max_burst_length_bytes;
1871 unsigned mem_row_size_in_kb;
1872 unsigned shader_engine_tile_size;
1873 unsigned num_gpus;
1874 unsigned multi_gpu_tile_size;
1875
1876 unsigned tile_config;
39aee490 1877 uint32_t tile_mode_array[32];
8cc1a532
AD		 1878};
1879
068a117c
JG		 1880union radeon_asic_config {
1881 struct r300_asic r300;
551ebd83 1882 struct r100_asic r100;
3ce0a23d
JG		 1883 struct r600_asic r600;
1884 struct rv770_asic rv770;
32fcdbf4 1885 struct evergreen_asic evergreen;
fecf1d07 1886 struct cayman_asic cayman;
0a96d72b 1887 struct si_asic si;
8cc1a532 1888 struct cik_asic cik;
068a117c
JG		 1889};
1890
0a10c851
DV		 1891/*
1892 * asic initizalization from radeon_asic.c
1893 */
1894void radeon_agp_disable(struct radeon_device *rdev);
1895int radeon_asic_init(struct radeon_device *rdev);
1896
771fe6b9
JG		 1897
1898/*
1899 * IOCTL.
1900 */
1901int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1902 struct drm_file *filp);
1903int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1904 struct drm_file *filp);
1905int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1906 struct drm_file *file_priv);
1907int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1908 struct drm_file *file_priv);
1909int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1910 struct drm_file *file_priv);
1911int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1912 struct drm_file *file_priv);
1913int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1914 struct drm_file *filp);
1915int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1916 struct drm_file *filp);
1917int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1918 struct drm_file *filp);
1919int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1920 struct drm_file *filp);
721604a1
JG		 1921int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1922 struct drm_file *filp);
771fe6b9 1923int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 1924int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1925 struct drm_file *filp);
1926int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1927 struct drm_file *filp);
771fe6b9 1928
16cdf04d
AD		 1929/* VRAM scratch page for HDP bug, default vram page */
1930struct r600_vram_scratch {
87cbf8f2
AD		 1931 struct radeon_bo *robj;
1932 volatile uint32_t *ptr;
16cdf04d 1933 u64 gpu_addr;
87cbf8f2 1934};
771fe6b9 1935
fd64ca8a
LT		 1936/*
1937 * ACPI
1938 */
1939struct radeon_atif_notification_cfg {
1940 bool enabled;
1941 int command_code;
1942};
1943
1944struct radeon_atif_notifications {
1945 bool display_switch;
1946 bool expansion_mode_change;
1947 bool thermal_state;
1948 bool forced_power_state;
1949 bool system_power_state;
1950 bool display_conf_change;
1951 bool px_gfx_switch;
1952 bool brightness_change;
1953 bool dgpu_display_event;
1954};
1955
1956struct radeon_atif_functions {
1957 bool system_params;
1958 bool sbios_requests;
1959 bool select_active_disp;
1960 bool lid_state;
1961 bool get_tv_standard;
1962 bool set_tv_standard;
1963 bool get_panel_expansion_mode;
1964 bool set_panel_expansion_mode;
1965 bool temperature_change;
1966 bool graphics_device_types;
1967};
1968
1969struct radeon_atif {
1970 struct radeon_atif_notifications notifications;
1971 struct radeon_atif_functions functions;
1972 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 1973 struct radeon_encoder *encoder_for_bl;
fd64ca8a 1974};
7a1619b9 1975
e3a15920
AD		 1976struct radeon_atcs_functions {
1977 bool get_ext_state;
1978 bool pcie_perf_req;
1979 bool pcie_dev_rdy;
1980 bool pcie_bus_width;
1981};
1982
1983struct radeon_atcs {
1984 struct radeon_atcs_functions functions;
1985};
1986
771fe6b9
JG		 1987/*
1988 * Core structure, functions and helpers.
1989 */
1990typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1991typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1992
1993struct radeon_device {
9f022ddf 1994 struct device *dev;
771fe6b9
JG		 1995 struct drm_device *ddev;
1996 struct pci_dev *pdev;
dee53e7f 1997 struct rw_semaphore exclusive_lock;
771fe6b9 1998 /* ASIC */
068a117c 1999 union radeon_asic_config config;
771fe6b9
JG		 2000 enum radeon_family family;
2001 unsigned long flags;
2002 int usec_timeout;
2003 enum radeon_pll_errata pll_errata;
2004 int num_gb_pipes;
f779b3e5 2005 int num_z_pipes;
771fe6b9
JG		 2006 int disp_priority;
2007 /* BIOS */
2008 uint8_t *bios;
2009 bool is_atom_bios;
2010 uint16_t bios_header_start;
4c788679 2011 struct radeon_bo *stollen_vga_memory;
771fe6b9 2012 /* Register mmio */
4c9bc75c
DA		 2013 resource_size_t rmmio_base;
2014 resource_size_t rmmio_size;
2c385151
DV		 2015 /* protects concurrent MM_INDEX/DATA based register access */
2016 spinlock_t mmio_idx_lock;
a0533fbf 2017 void __iomem *rmmio;
771fe6b9
JG		 2018 radeon_rreg_t mc_rreg;
2019 radeon_wreg_t mc_wreg;
2020 radeon_rreg_t pll_rreg;
2021 radeon_wreg_t pll_wreg;
de1b2898 2022 uint32_t pcie_reg_mask;
771fe6b9
JG		 2023 radeon_rreg_t pciep_rreg;
2024 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2025 /* io port */
2026 void __iomem *rio_mem;
2027 resource_size_t rio_mem_size;
771fe6b9
JG		 2028 struct radeon_clock clock;
2029 struct radeon_mc mc;
2030 struct radeon_gart gart;
2031 struct radeon_mode_info mode_info;
2032 struct radeon_scratch scratch;
75efdee1 2033 struct radeon_doorbell doorbell;
771fe6b9 2034 struct radeon_mman mman;
7465280c 2035 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2036 wait_queue_head_t fence_queue;
d6999bc7 2037 struct mutex ring_lock;
e32eb50d 2038 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2039 bool ib_pool_ready;
2040 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2041 struct radeon_irq irq;
2042 struct radeon_asic *asic;
2043 struct radeon_gem gem;
c93bb85b 2044 struct radeon_pm pm;
f2ba57b5 2045 struct radeon_uvd uvd;
f657c2a7 2046 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2047 struct radeon_wb wb;
3ce0a23d 2048 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2049 bool shutdown;
2050 bool suspend;
ad49f501 2051 bool need_dma32;
733289c2 2052 bool accel_working;
a0a53aa8 2053 bool fastfb_working; /* IGP feature*/
e024e110 2054 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2055 const struct firmware *me_fw; /* all family ME firmware */
2056 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2057 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2058 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2059 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2060 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 2061 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2062 const struct firmware *smc_fw; /* SMC firmware */
3ce0a23d 2063 struct r600_blit r600_blit;
16cdf04d 2064 struct r600_vram_scratch vram_scratch;
3e5cb98d 2065 int msi_enabled; /* msi enabled */
d8f60cfc 2066 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2067 struct radeon_rlc rlc;
963e81f9 2068 struct radeon_mec mec;
d4877cf2 2069 struct work_struct hotplug_work;
f122c610 2070 struct work_struct audio_work;
8f61b34c 2071 struct work_struct reset_work;
18917b60 2072 int num_crtc; /* number of crtcs */
40bacf16 2073 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
3299de95 2074 bool audio_enabled;
948bee3f 2075 bool has_uvd;
3299de95 2076 struct r600_audio audio_status; /* audio stuff */
ce8f5370 2077 struct notifier_block acpi_nb;
9eba4a93 2078 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2079 struct drm_file *hyperz_filp;
9eba4a93 2080 struct drm_file *cmask_filp;
f376b94f
AD		 2081 /* i2c buses */
2082 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2083 /* debugfs */
2084 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2085 unsigned debugfs_count;
721604a1
JG		 2086 /* virtual memory */
2087 struct radeon_vm_manager vm_manager;
6759a0a7 2088 struct mutex gpu_clock_mutex;
fd64ca8a
LT		 2089 /* ACPI interface */
2090 struct radeon_atif atif;
e3a15920 2091 struct radeon_atcs atcs;
771fe6b9
JG		 2092};
2093
2094int radeon_device_init(struct radeon_device *rdev,
2095 struct drm_device *ddev,
2096 struct pci_dev *pdev,
2097 uint32_t flags);
2098void radeon_device_fini(struct radeon_device *rdev);
2099int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2100
2ef9bdfe
DV		 2101uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2102 bool always_indirect);
2103void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2104 bool always_indirect);
6fcbef7a
AK		 2105u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2106void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2107
75efdee1
AD		 2108u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
2109void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
2110
4c788679
JG		 2111/*
2112 * Cast helper
2113 */
2114#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2115
2116/*
2117 * Registers read & write functions.
2118 */
a0533fbf
BH		 2119#define RREG8(reg) readb((rdev->rmmio) + (reg))
2120#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2121#define RREG16(reg) readw((rdev->rmmio) + (reg))
2122#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2123#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2124#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2125#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2126#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2127#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2128#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2129#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2130#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2131#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2132#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2133#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2134#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2135#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2136#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2137#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2138#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2139#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2140#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2141#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2142#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2143#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2144#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2145#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2146#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2147#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2148#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2149#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
771fe6b9
JG		 2150#define WREG32_P(reg, val, mask) \
2151 do { \
2152 uint32_t tmp_ = RREG32(reg); \
2153 tmp_ &= (mask); \
2154 tmp_ |= ((val) & ~(mask)); \
2155 WREG32(reg, tmp_); \
2156 } while (0)
d5169fc4
RM		 2157#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2158#define WREG32_OR(reg, or) WREG32_P(reg, or, ~or)
771fe6b9
JG		 2159#define WREG32_PLL_P(reg, val, mask) \
2160 do { \
2161 uint32_t tmp_ = RREG32_PLL(reg); \
2162 tmp_ &= (mask); \
2163 tmp_ |= ((val) & ~(mask)); \
2164 WREG32_PLL(reg, tmp_); \
2165 } while (0)
2ef9bdfe 2166#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2167#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2168#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2169
75efdee1
AD		 2170#define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
2171#define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
2172
de1b2898
DA		 2173/*
2174 * Indirect registers accessor
2175 */
2176static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2177{
2178 uint32_t r;
2179
2180 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2181 r = RREG32(RADEON_PCIE_DATA);
2182 return r;
2183}
2184
2185static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2186{
2187 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2188 WREG32(RADEON_PCIE_DATA, (v));
2189}
2190
1d5d0c34
AD		 2191static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2192{
2193 u32 r;
2194
2195 WREG32(TN_SMC_IND_INDEX_0, (reg));
2196 r = RREG32(TN_SMC_IND_DATA_0);
2197 return r;
2198}
2199
2200static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2201{
2202 WREG32(TN_SMC_IND_INDEX_0, (reg));
2203 WREG32(TN_SMC_IND_DATA_0, (v));
2204}
2205
ff82bbc4
AD		 2206static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2207{
2208 u32 r;
2209
2210 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2211 r = RREG32(R600_RCU_DATA);
2212 return r;
2213}
2214
2215static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2216{
2217 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2218 WREG32(R600_RCU_DATA, (v));
2219}
2220
46f9564a
AD		 2221static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2222{
2223 u32 r;
2224
2225 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2226 r = RREG32(EVERGREEN_CG_IND_DATA);
2227 return r;
2228}
2229
2230static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2231{
2232 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2233 WREG32(EVERGREEN_CG_IND_DATA, (v));
2234}
2235
792edd69
AD		 2236static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2237{
2238 u32 r;
2239
2240 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2241 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2242 return r;
2243}
2244
2245static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2246{
2247 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2248 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2249}
2250
2251static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2252{
2253 u32 r;
2254
2255 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2256 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2257 return r;
2258}
2259
2260static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2261{
2262 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2263 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2264}
2265
93656cdd
AD		 2266static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2267{
2268 u32 r;
2269
2270 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2271 r = RREG32(R600_UVD_CTX_DATA);
2272 return r;
2273}
2274
2275static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2276{
2277 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2278 WREG32(R600_UVD_CTX_DATA, (v));
2279}
2280
771fe6b9
JG		 2281void r100_pll_errata_after_index(struct radeon_device *rdev);
2282
2283
2284/*
2285 * ASICs helpers.
2286 */
b995e433
DA		 2287#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2288 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2289#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2290 (rdev->family == CHIP_RV200) || \
2291 (rdev->family == CHIP_RS100) || \
2292 (rdev->family == CHIP_RS200) || \
2293 (rdev->family == CHIP_RV250) || \
2294 (rdev->family == CHIP_RV280) || \
2295 (rdev->family == CHIP_RS300))
2296#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2297 (rdev->family == CHIP_RV350) || \
2298 (rdev->family == CHIP_R350) || \
2299 (rdev->family == CHIP_RV380) || \
2300 (rdev->family == CHIP_R420) || \
2301 (rdev->family == CHIP_R423) || \
2302 (rdev->family == CHIP_RV410) || \
2303 (rdev->family == CHIP_RS400) || \
2304 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2305#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2306 (rdev->ddev->pdev->device == 0x9443) || \
2307 (rdev->ddev->pdev->device == 0x944B) || \
2308 (rdev->ddev->pdev->device == 0x9506) || \
2309 (rdev->ddev->pdev->device == 0x9509) || \
2310 (rdev->ddev->pdev->device == 0x950F) || \
2311 (rdev->ddev->pdev->device == 0x689C) || \
2312 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2313#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2314#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2315 (rdev->family == CHIP_RS690) || \
2316 (rdev->family == CHIP_RS740) || \
2317 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2318#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2319#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2320#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2321#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2322 (rdev->flags & RADEON_IS_IGP))
1fe18305 2323#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2324#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2325#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2326 (rdev->flags & RADEON_IS_IGP))
624d3524 2327#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2328#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2329#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
771fe6b9 2330
dc50ba7f
AD		 2331#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2332 (rdev->ddev->pdev->device == 0x6850) || \
2333 (rdev->ddev->pdev->device == 0x6858) || \
2334 (rdev->ddev->pdev->device == 0x6859) || \
2335 (rdev->ddev->pdev->device == 0x6840) || \
2336 (rdev->ddev->pdev->device == 0x6841) || \
2337 (rdev->ddev->pdev->device == 0x6842) || \
2338 (rdev->ddev->pdev->device == 0x6843))
2339
771fe6b9
JG		 2340/*
2341 * BIOS helpers.
2342 */
2343#define RBIOS8(i) (rdev->bios[i])
2344#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2345#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2346
2347int radeon_combios_init(struct radeon_device *rdev);
2348void radeon_combios_fini(struct radeon_device *rdev);
2349int radeon_atombios_init(struct radeon_device *rdev);
2350void radeon_atombios_fini(struct radeon_device *rdev);
2351
2352
2353/*
2354 * RING helpers.
2355 */
ce580fab 2356#if DRM_DEBUG_CODE == 0
e32eb50d 2357static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2358{
e32eb50d
CK		 2359 ring->ring[ring->wptr++] = v;
2360 ring->wptr &= ring->ptr_mask;
2361 ring->count_dw--;
2362 ring->ring_free_dw--;
771fe6b9 2363}
ce580fab
AK		 2364#else
2365/* With debugging this is just too big to inline */
e32eb50d 2366void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2367#endif
771fe6b9
JG		 2368
2369/*
2370 * ASICs macro.
2371 */
068a117c 2372#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2373#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2374#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2375#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
eb0c19c5 2376#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
28d52043 2377#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2378#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2379#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2380#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2381#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2382#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2383#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
f712812e
AD		 2384#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
2385#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
2386#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
4c87bc26 2387#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
721604a1 2388#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
312c4a8c 2389#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
498522b4 2390#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
f93bdefe
AD		 2391#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r))
2392#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r))
2393#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r))
b35ea4ab
AD		 2394#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2395#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2396#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2397#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2398#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2399#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2400#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
4c87bc26
CK		 2401#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
2402#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2403#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2404#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2405#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2406#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2407#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2408#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2409#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2410#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2411#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2412#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2413#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2414#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2415#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2416#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
6bd1c385 2417#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2418#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2419#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2420#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2421#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2422#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2423#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2424#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2425#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2426#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2427#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2428#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2429#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2430#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8
AD		 2431#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2432#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2433#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2434#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2435#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2436#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2437#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2438#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2439#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2440#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2441#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2442#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2443#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2444#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2445#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2446#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2447#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2448#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2449#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2450#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2451#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2452#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
771fe6b9 2453
6cf8a3f5 2454/* Common functions */
700a0cc0 2455/* AGP */
90aca4d2 2456extern int radeon_gpu_reset(struct radeon_device *rdev);
410a3418 2457extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2458extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2459extern int radeon_modeset_init(struct radeon_device *rdev);
2460extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2461extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2462extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2463extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2464extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2465extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2466extern void radeon_wb_fini(struct radeon_device *rdev);
2467extern int radeon_wb_init(struct radeon_device *rdev);
2468extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2469extern void radeon_surface_init(struct radeon_device *rdev);
2470extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2471extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2472extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2473extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2474extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2475extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2476extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
6a9ee8af
DA		 2477extern int radeon_resume_kms(struct drm_device *dev);
2478extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
53595338 2479extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2480extern void radeon_program_register_sequence(struct radeon_device *rdev,
2481 const u32 *registers,
2482 const u32 array_size);
6cf8a3f5 2483
721604a1
JG		 2484/*
2485 * vm
2486 */
2487int radeon_vm_manager_init(struct radeon_device *rdev);
2488void radeon_vm_manager_fini(struct radeon_device *rdev);
d72d43cf 2489void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2490void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
ddf03f5c 2491int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
13e55c38 2492void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
ee60e29f
CK		 2493struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2494 struct radeon_vm *vm, int ring);
2495void radeon_vm_fence(struct radeon_device *rdev,
2496 struct radeon_vm *vm,
2497 struct radeon_fence *fence);
dce34bfd 2498uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
721604a1
JG		 2499int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2500 struct radeon_vm *vm,
2501 struct radeon_bo *bo,
2502 struct ttm_mem_reg *mem);
2503void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2504 struct radeon_bo *bo);
421ca7ab
CK		 2505struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2506 struct radeon_bo *bo);
e971bd5e
CK		 2507struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2508 struct radeon_vm *vm,
2509 struct radeon_bo *bo);
2510int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2511 struct radeon_bo_va *bo_va,
2512 uint64_t offset,
2513 uint32_t flags);
721604a1 2514int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2515 struct radeon_bo_va *bo_va);
721604a1 2516
f122c610
AD		 2517/* audio */
2518void r600_audio_update_hdmi(struct work_struct *work);
721604a1 2519
16cdf04d
AD		 2520/*
2521 * R600 vram scratch functions
2522 */
2523int r600_vram_scratch_init(struct radeon_device *rdev);
2524void r600_vram_scratch_fini(struct radeon_device *rdev);
2525
285484e2
JG		 2526/*
2527 * r600 cs checking helper
2528 */
2529unsigned r600_mip_minify(unsigned size, unsigned level);
2530bool r600_fmt_is_valid_color(u32 format);
2531bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2532int r600_fmt_get_blocksize(u32 format);
2533int r600_fmt_get_nblocksx(u32 format, u32 w);
2534int r600_fmt_get_nblocksy(u32 format, u32 h);
2535
3574dda4
DV		 2536/*
2537 * r600 functions used by radeon_encoder.c
2538 */
1b688d08
RM		 2539struct radeon_hdmi_acr {
2540 u32 clock;
2541
2542 int n_32khz;
2543 int cts_32khz;
2544
2545 int n_44_1khz;
2546 int cts_44_1khz;
2547
2548 int n_48khz;
2549 int cts_48khz;
2550
2551};
2552
e55d3e6c
RM		 2553extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2554
416a2bd2
AD		 2555extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2556 u32 tiling_pipe_num,
2557 u32 max_rb_num,
2558 u32 total_max_rb_num,
2559 u32 enabled_rb_mask);
fe251e2f 2560
e55d3e6c
RM		 2561/*
2562 * evergreen functions used by radeon_encoder.c
2563 */
2564
0af62b01 2565extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2566extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2567
c4917074
AD		 2568/* radeon_acpi.c */
2569#if defined(CONFIG_ACPI)
2570extern int radeon_acpi_init(struct radeon_device *rdev);
2571extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2572extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2573extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2574 u8 perf_req, bool advertise);
dc50ba7f 2575extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2576#else
2577static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2578static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2579#endif
d7a2952f 2580
c38f34b5
IH		 2581int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2582 struct radeon_cs_packet *pkt,
2583 unsigned idx);
9ffb7a6d 2584bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2585void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2586 struct radeon_cs_packet *pkt);
e9716993
IH		 2587int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2588 struct radeon_cs_reloc **cs_reloc,
2589 int nomm);
40592a17
IH		 2590int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2591 uint32_t *vline_start_end,
2592 uint32_t *vline_status);
c38f34b5 2593
4c788679
JG		 2594#include "radeon_object.h"
2595
771fe6b9 2596#endif
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