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drm/radeon: allow to force hard GPU reset.
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
0aea5e4a 67#include <linux/interval_tree.h>
341cb9e4 68#include <linux/hashtable.h>
954605ca 69#include <linux/fence.h>
771fe6b9 70
4c788679
JG		 71#include <ttm/ttm_bo_api.h>
72#include <ttm/ttm_bo_driver.h>
73#include <ttm/ttm_placement.h>
74#include <ttm/ttm_module.h>
147666fb 75#include <ttm/ttm_execbuf_util.h>
4c788679 76
d9fc9413
DV		 77#include <drm/drm_gem.h>
78
c2142715 79#include "radeon_family.h"
771fe6b9
JG		 80#include "radeon_mode.h"
81#include "radeon_reg.h"
771fe6b9
JG		 82
83/*
84 * Modules parameters.
85 */
86extern int radeon_no_wb;
87extern int radeon_modeset;
88extern int radeon_dynclks;
89extern int radeon_r4xx_atom;
90extern int radeon_agpmode;
91extern int radeon_vram_limit;
92extern int radeon_gart_size;
93extern int radeon_benchmarking;
ecc0b326 94extern int radeon_testing;
771fe6b9 95extern int radeon_connector_table;
4ce001ab 96extern int radeon_tv;
dafc3bd5 97extern int radeon_audio;
f46c0120 98extern int radeon_disp_priority;
e2b0a8e1 99extern int radeon_hw_i2c;
d42dd579 100extern int radeon_pcie_gen2;
a18cee15 101extern int radeon_msi;
3368ff0c 102extern int radeon_lockup_timeout;
a0a53aa8 103extern int radeon_fastfb;
da321c8a 104extern int radeon_dpm;
1294d4a3 105extern int radeon_aspm;
10ebc0bc 106extern int radeon_runtime_pm;
363eb0b4 107extern int radeon_hard_reset;
c1c44132 108extern int radeon_vm_size;
4510fb98 109extern int radeon_vm_block_size;
a624f429 110extern int radeon_deep_color;
39dc5454 111extern int radeon_use_pflipirq;
6e909f74 112extern int radeon_bapm;
bc13018b 113extern int radeon_backlight;
875711f0 114extern int radeon_auxch;
9843ead0 115extern int radeon_mst;
f1a0a67a 116extern int radeon_uvd;
fabb5935 117extern int radeon_vce;
771fe6b9
JG		 118
119/*
120 * Copy from radeon_drv.h so we don't have to include both and have conflicting
121 * symbol;
122 */
bb635567
JG		 123#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
124#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
04db4caf 125#define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */
e821767b 126/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 127#define RADEON_IB_POOL_SIZE 16
128#define RADEON_DEBUGFS_MAX_COMPONENTS 32
129#define RADEONFB_CONN_LIMIT 4
130#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 131
1b37078b
AD		 132/* internal ring indices */
133/* r1xx+ has gfx CP ring */
d93f7937 134#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 135
136/* cayman has 2 compute CP rings */
d93f7937
CK		 137#define CAYMAN_RING_TYPE_CP1_INDEX 1
138#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 139
4d75658b
AD		 140/* R600+ has an async dma ring */
141#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 142/* cayman add a second async dma ring */
143#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 144
f2ba57b5 145/* R600+ */
d93f7937
CK		 146#define R600_RING_TYPE_UVD_INDEX 5
147
148/* TN+ */
149#define TN_RING_TYPE_VCE1_INDEX 6
150#define TN_RING_TYPE_VCE2_INDEX 7
151
152/* max number of rings */
153#define RADEON_NUM_RINGS 8
f2ba57b5 154
1c61eae4
CK		 155/* number of hw syncs before falling back on blocking */
156#define RADEON_NUM_SYNCS 4
f2ba57b5 157
721604a1 158/* hardcode those limit for now */
ca19f21e 159#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 160#define RADEON_VA_RESERVED_SIZE (8 << 20)
161#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 162
1a0041b8
AD		 163/* hard reset data */
164#define RADEON_ASIC_RESET_DATA 0x39d5e86b
165
ec46c76d
AD		 166/* reset flags */
167#define RADEON_RESET_GFX (1 << 0)
168#define RADEON_RESET_COMPUTE (1 << 1)
169#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 170#define RADEON_RESET_CP (1 << 3)
171#define RADEON_RESET_GRBM (1 << 4)
172#define RADEON_RESET_DMA1 (1 << 5)
173#define RADEON_RESET_RLC (1 << 6)
174#define RADEON_RESET_SEM (1 << 7)
175#define RADEON_RESET_IH (1 << 8)
176#define RADEON_RESET_VMC (1 << 9)
177#define RADEON_RESET_MC (1 << 10)
178#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 179
22c775ce
AD		 180/* CG block flags */
181#define RADEON_CG_BLOCK_GFX (1 << 0)
182#define RADEON_CG_BLOCK_MC (1 << 1)
183#define RADEON_CG_BLOCK_SDMA (1 << 2)
184#define RADEON_CG_BLOCK_UVD (1 << 3)
185#define RADEON_CG_BLOCK_VCE (1 << 4)
186#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 187#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 188
64d8a728
AD		 189/* CG flags */
190#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
191#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
192#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
193#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
194#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
195#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
196#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
197#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
198#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
199#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
200#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
201#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
202#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
203#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
204#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
205#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
206#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
207
208/* PG flags */
2b19d17f 209#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 210#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
211#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
212#define RADEON_PG_SUPPORT_UVD (1 << 3)
213#define RADEON_PG_SUPPORT_VCE (1 << 4)
214#define RADEON_PG_SUPPORT_CP (1 << 5)
215#define RADEON_PG_SUPPORT_GDS (1 << 6)
216#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
217#define RADEON_PG_SUPPORT_SDMA (1 << 8)
218#define RADEON_PG_SUPPORT_ACP (1 << 9)
219#define RADEON_PG_SUPPORT_SAMU (1 << 10)
220
9e05fa1d
AD		 221/* max cursor sizes (in pixels) */
222#define CURSOR_WIDTH 64
223#define CURSOR_HEIGHT 64
224
225#define CIK_CURSOR_WIDTH 128
226#define CIK_CURSOR_HEIGHT 128
227
771fe6b9
JG		 228/*
229 * Errata workarounds.
230 */
231enum radeon_pll_errata {
232 CHIP_ERRATA_R300_CG = 0x00000001,
233 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
234 CHIP_ERRATA_PLL_DELAY = 0x00000004
235};
236
237
238struct radeon_device;
239
240
241/*
242 * BIOS.
243 */
244bool radeon_get_bios(struct radeon_device *rdev);
245
246/*
3ce0a23d 247 * Dummy page
771fe6b9 248 */
3ce0a23d 249struct radeon_dummy_page {
cb658906 250 uint64_t entry;
3ce0a23d
JG		 251 struct page *page;
252 dma_addr_t addr;
253};
254int radeon_dummy_page_init(struct radeon_device *rdev);
255void radeon_dummy_page_fini(struct radeon_device *rdev);
256
771fe6b9 257
3ce0a23d
JG		 258/*
259 * Clocks
260 */
771fe6b9
JG		 261struct radeon_clock {
262 struct radeon_pll p1pll;
263 struct radeon_pll p2pll;
bcc1c2a1 264 struct radeon_pll dcpll;
771fe6b9
JG		 265 struct radeon_pll spll;
266 struct radeon_pll mpll;
267 /* 10 Khz units */
268 uint32_t default_mclk;
269 uint32_t default_sclk;
bcc1c2a1 270 uint32_t default_dispclk;
4489cd62 271 uint32_t current_dispclk;
bcc1c2a1 272 uint32_t dp_extclk;
b20f9bef 273 uint32_t max_pixel_clock;
c9a392ea 274 uint32_t vco_freq;
771fe6b9
JG		 275};
276
7433874e
RM		 277/*
278 * Power management
279 */
280int radeon_pm_init(struct radeon_device *rdev);
914a8987 281int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 282void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 283void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 284void radeon_pm_suspend(struct radeon_device *rdev);
285void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 286void radeon_combios_get_power_modes(struct radeon_device *rdev);
287void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 288int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
289 u8 clock_type,
290 u32 clock,
291 bool strobe_mode,
292 struct atom_clock_dividers *dividers);
eaa778af
AD		 293int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
294 u32 clock,
295 bool strobe_mode,
296 struct atom_mpll_param *mpll_param);
8a83ec5e 297void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 298int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
299 u16 voltage_level, u8 voltage_type,
300 u32 *gpio_value, u32 *gpio_mask);
301void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
302 u32 eng_clock, u32 mem_clock);
303int radeon_atom_get_voltage_step(struct radeon_device *rdev,
304 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 305int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
306 u16 voltage_id, u16 *voltage);
beb79f40
AD		 307int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
308 u16 *voltage,
309 u16 leakage_idx);
cc8dbbb4
AD		 310int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
311 u16 *leakage_id);
312int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
313 u16 *vddc, u16 *vddci,
314 u16 virtual_voltage_id,
315 u16 vbios_voltage_id);
e9f274b2
AD		 316int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
317 u16 virtual_voltage_id,
318 u16 *voltage);
ae5b0abb
AD		 319int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
320 u8 voltage_type,
321 u16 nominal_voltage,
322 u16 *true_voltage);
323int radeon_atom_get_min_voltage(struct radeon_device *rdev,
324 u8 voltage_type, u16 *min_voltage);
325int radeon_atom_get_max_voltage(struct radeon_device *rdev,
326 u8 voltage_type, u16 *max_voltage);
327int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 328 u8 voltage_type, u8 voltage_mode,
ae5b0abb 329 struct atom_voltage_table *voltage_table);
58653abd
AD		 330bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
331 u8 voltage_type, u8 voltage_mode);
636e2582
AD		 332int radeon_atom_get_svi2_info(struct radeon_device *rdev,
333 u8 voltage_type,
334 u8 *svd_gpio_id, u8 *svc_gpio_id);
ae5b0abb
AD		 335void radeon_atom_update_memory_dll(struct radeon_device *rdev,
336 u32 mem_clock);
337void radeon_atom_set_ac_timing(struct radeon_device *rdev,
338 u32 mem_clock);
339int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
340 u8 module_index,
341 struct atom_mc_reg_table *reg_table);
342int radeon_atom_get_memory_info(struct radeon_device *rdev,
343 u8 module_index, struct atom_memory_info *mem_info);
344int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
345 bool gddr5, u8 module_index,
346 struct atom_memory_clock_range_table *mclk_range_table);
347int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
348 u16 voltage_id, u16 *voltage);
f892034a 349void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 350extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
351 unsigned *bankh, unsigned *mtaspect,
352 unsigned *tile_split);
3ce0a23d 353
771fe6b9
JG		 354/*
355 * Fences.
356 */
357struct radeon_fence_driver {
0bfa4b41 358 struct radeon_device *rdev;
771fe6b9 359 uint32_t scratch_reg;
30eb77f4
JG		 360 uint64_t gpu_addr;
361 volatile uint32_t *cpu_addr;
68e250b7
CK		 362 /* sync_seq is protected by ring emission lock */
363 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 364 atomic64_t last_seq;
954605ca 365 bool initialized, delayed_irq;
0bfa4b41 366 struct delayed_work lockup_work;
771fe6b9
JG		 367};
368
369struct radeon_fence {
ad1a58a4 370 struct fence base;
954605ca 371
ad1a58a4
CK		 372 struct radeon_device *rdev;
373 uint64_t seq;
7465280c 374 /* RB, DMA, etc. */
ad1a58a4
CK		 375 unsigned ring;
376 bool is_vm_update;
954605ca 377
ad1a58a4 378 wait_queue_t fence_wake;
771fe6b9
JG		 379};
380
30eb77f4
JG		 381int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
382int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 383void radeon_fence_driver_fini(struct radeon_device *rdev);
eb98c709 384void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
876dc9f3 385int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 386void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9 387bool radeon_fence_signaled(struct radeon_fence *fence);
04db4caf 388long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
771fe6b9 389int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
37615527
CK		 390int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
391int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
0085c950
JG		 392int radeon_fence_wait_any(struct radeon_device *rdev,
393 struct radeon_fence **fences,
394 bool intr);
771fe6b9
JG		 395struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
396void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 397unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 398bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
399void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
400static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
401 struct radeon_fence *b)
402{
403 if (!a) {
404 return b;
405 }
406
407 if (!b) {
408 return a;
409 }
410
411 BUG_ON(a->ring != b->ring);
412
413 if (a->seq > b->seq) {
414 return a;
415 } else {
416 return b;
417 }
418}
771fe6b9 419
ee60e29f
CK		 420static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
421 struct radeon_fence *b)
422{
423 if (!a) {
424 return false;
425 }
426
427 if (!b) {
428 return true;
429 }
430
431 BUG_ON(a->ring != b->ring);
432
433 return a->seq < b->seq;
434}
435
e024e110
DA		 436/*
437 * Tiling registers
438 */
439struct radeon_surface_reg {
4c788679 440 struct radeon_bo *bo;
e024e110
DA		 441};
442
443#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 444
445/*
4c788679 446 * TTM.
771fe6b9 447 */
4c788679
JG		 448struct radeon_mman {
449 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 450 struct drm_global_reference mem_global_ref;
4c788679 451 struct ttm_bo_device bdev;
0a0c7596
JG		 452 bool mem_global_referenced;
453 bool initialized;
2014b569
CK		 454
455#if defined(CONFIG_DEBUG_FS)
456 struct dentry *vram;
dd66d20e 457 struct dentry *gtt;
2014b569 458#endif
4c788679
JG		 459};
460
1d0c0942
CK		 461struct radeon_bo_list {
462 struct radeon_bo *robj;
463 struct ttm_validate_buffer tv;
464 uint64_t gpu_offset;
465 unsigned prefered_domains;
466 unsigned allowed_domains;
467 uint32_t tiling_flags;
468};
469
721604a1
JG		 470/* bo virtual address in a specific vm */
471struct radeon_bo_va {
e971bd5e 472 /* protected by bo being reserved */
721604a1 473 struct list_head bo_list;
721604a1 474 uint32_t flags;
94214635 475 struct radeon_fence *last_pt_update;
e971bd5e
CK		 476 unsigned ref_count;
477
478 /* protected by vm mutex */
0aea5e4a 479 struct interval_tree_node it;
036bf46a 480 struct list_head vm_status;
e971bd5e
CK		 481
482 /* constant after initialization */
483 struct radeon_vm *vm;
484 struct radeon_bo *bo;
721604a1
JG		 485};
486
4c788679
JG		 487struct radeon_bo {
488 /* Protected by gem.mutex */
489 struct list_head list;
490 /* Protected by tbo.reserved */
bda72d58 491 u32 initial_domain;
c9da4a4b 492 struct ttm_place placements[4];
312ea8da 493 struct ttm_placement placement;
4c788679
JG		 494 struct ttm_buffer_object tbo;
495 struct ttm_bo_kmap_obj kmap;
02376d82 496 u32 flags;
4c788679
JG		 497 unsigned pin_count;
498 void *kptr;
499 u32 tiling_flags;
500 u32 pitch;
501 int surface_reg;
721604a1
JG		 502 /* list of all virtual address to which this bo
503 * is associated to
504 */
505 struct list_head va;
4c788679
JG		 506 /* Constant after initialization */
507 struct radeon_device *rdev;
441921d5 508 struct drm_gem_object gem_base;
63bc620b 509
409851f4
JG		 510 struct ttm_bo_kmap_obj dma_buf_vmap;
511 pid_t pid;
341cb9e4
CK		 512
513 struct radeon_mn *mn;
49ecb10e 514 struct list_head mn_list;
4c788679 515};
7e4d15d9 516#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 517
409851f4
JG		 518int radeon_gem_debugfs_init(struct radeon_device *rdev);
519
b15ba512
JG		 520/* sub-allocation manager, it has to be protected by another lock.
521 * By conception this is an helper for other part of the driver
522 * like the indirect buffer or semaphore, which both have their
523 * locking.
524 *
525 * Principe is simple, we keep a list of sub allocation in offset
526 * order (first entry has offset == 0, last entry has the highest
527 * offset).
528 *
529 * When allocating new object we first check if there is room at
530 * the end total_size - (last_object_offset + last_object_size) >=
531 * alloc_size. If so we allocate new object there.
532 *
533 * When there is not enough room at the end, we start waiting for
534 * each sub object until we reach object_offset+object_size >=
535 * alloc_size, this object then become the sub object we return.
536 *
537 * Alignment can't be bigger than page size.
538 *
539 * Hole are not considered for allocation to keep things simple.
540 * Assumption is that there won't be hole (all object on same
541 * alignment).
542 */
543struct radeon_sa_manager {
bfb38d35 544 wait_queue_head_t wq;
b15ba512 545 struct radeon_bo *bo;
c3b7fe8b
CK		 546 struct list_head *hole;
547 struct list_head flist[RADEON_NUM_RINGS];
548 struct list_head olist;
b15ba512
JG		 549 unsigned size;
550 uint64_t gpu_addr;
551 void *cpu_ptr;
552 uint32_t domain;
6c4f978b 553 uint32_t align;
b15ba512
JG		 554};
555
556struct radeon_sa_bo;
557
558/* sub-allocation buffer */
559struct radeon_sa_bo {
c3b7fe8b
CK		 560 struct list_head olist;
561 struct list_head flist;
b15ba512 562 struct radeon_sa_manager *manager;
e6661a96
CK		 563 unsigned soffset;
564 unsigned eoffset;
557017a0 565 struct radeon_fence *fence;
b15ba512
JG		 566};
567
771fe6b9
JG		 568/*
569 * GEM objects.
570 */
571struct radeon_gem {
4c788679 572 struct mutex mutex;
771fe6b9
JG		 573 struct list_head objects;
574};
575
576int radeon_gem_init(struct radeon_device *rdev);
577void radeon_gem_fini(struct radeon_device *rdev);
391bfec3 578int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
4c788679 579 int alignment, int initial_domain,
ed5cb43f 580 u32 flags, bool kernel,
4c788679 581 struct drm_gem_object **obj);
771fe6b9 582
ff72145b
DA		 583int radeon_mode_dumb_create(struct drm_file *file_priv,
584 struct drm_device *dev,
585 struct drm_mode_create_dumb *args);
586int radeon_mode_dumb_mmap(struct drm_file *filp,
587 struct drm_device *dev,
588 uint32_t handle, uint64_t *offset_p);
771fe6b9 589
c1341e52
JG		 590/*
591 * Semaphores.
592 */
c1341e52 593struct radeon_semaphore {
975700d2
CK		 594 struct radeon_sa_bo *sa_bo;
595 signed waiters;
596 uint64_t gpu_addr;
c1341e52
JG		 597};
598
c1341e52
JG		 599int radeon_semaphore_create(struct radeon_device *rdev,
600 struct radeon_semaphore **semaphore);
1654b817 601bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 602 struct radeon_semaphore *semaphore);
1654b817 603bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52
JG		 604 struct radeon_semaphore *semaphore);
605void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 606 struct radeon_semaphore **semaphore,
a8c05940 607 struct radeon_fence *fence);
c1341e52 608
975700d2
CK		 609/*
610 * Synchronization
611 */
612struct radeon_sync {
613 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
614 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
ad1a58a4 615 struct radeon_fence *last_vm_update;
975700d2
CK		 616};
617
618void radeon_sync_create(struct radeon_sync *sync);
619void radeon_sync_fence(struct radeon_sync *sync,
620 struct radeon_fence *fence);
621int radeon_sync_resv(struct radeon_device *rdev,
622 struct radeon_sync *sync,
623 struct reservation_object *resv,
624 bool shared);
625int radeon_sync_rings(struct radeon_device *rdev,
626 struct radeon_sync *sync,
627 int waiting_ring);
628void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
629 struct radeon_fence *fence);
630
771fe6b9
JG		 631/*
632 * GART structures, functions & helpers
633 */
634struct radeon_mc;
635
a77f1718 636#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 637#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 638#define RADEON_GPU_PAGE_SHIFT 12
721604a1 639#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 640
77497f27
MD		 641#define RADEON_GART_PAGE_DUMMY 0
642#define RADEON_GART_PAGE_VALID (1 << 0)
643#define RADEON_GART_PAGE_READ (1 << 1)
644#define RADEON_GART_PAGE_WRITE (1 << 2)
645#define RADEON_GART_PAGE_SNOOP (1 << 3)
646
771fe6b9
JG		 647struct radeon_gart {
648 dma_addr_t table_addr;
c9a1be96
JG		 649 struct radeon_bo *robj;
650 void *ptr;
771fe6b9
JG		 651 unsigned num_gpu_pages;
652 unsigned num_cpu_pages;
653 unsigned table_size;
771fe6b9 654 struct page **pages;
cb658906 655 uint64_t *pages_entry;
771fe6b9
JG		 656 bool ready;
657};
658
659int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
660void radeon_gart_table_ram_free(struct radeon_device *rdev);
661int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
662void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 663int radeon_gart_table_vram_pin(struct radeon_device *rdev);
664void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 665int radeon_gart_init(struct radeon_device *rdev);
666void radeon_gart_fini(struct radeon_device *rdev);
667void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
668 int pages);
669int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516 670 int pages, struct page **pagelist,
77497f27 671 dma_addr_t *dma_addr, uint32_t flags);
771fe6b9
JG		 672
673
674/*
675 * GPU MC structures, functions & helpers
676 */
677struct radeon_mc {
678 resource_size_t aper_size;
679 resource_size_t aper_base;
680 resource_size_t agp_base;
7a50f01a
DA		 681 /* for some chips with <= 32MB we need to lie
682 * about vram size near mc fb location */
3ce0a23d 683 u64 mc_vram_size;
d594e46a 684 u64 visible_vram_size;
3ce0a23d
JG		 685 u64 gtt_size;
686 u64 gtt_start;
687 u64 gtt_end;
3ce0a23d
JG		 688 u64 vram_start;
689 u64 vram_end;
771fe6b9 690 unsigned vram_width;
3ce0a23d 691 u64 real_vram_size;
771fe6b9
JG		 692 int vram_mtrr;
693 bool vram_is_ddr;
d594e46a 694 bool igp_sideport_enabled;
8d369bb1 695 u64 gtt_base_align;
9ed8b1f9 696 u64 mc_mask;
771fe6b9
JG		 697};
698
06b6476d
AD		 699bool radeon_combios_sideport_present(struct radeon_device *rdev);
700bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 701
702/*
703 * GPU scratch registers structures, functions & helpers
704 */
705struct radeon_scratch {
706 unsigned num_reg;
724c80e1 707 uint32_t reg_base;
771fe6b9
JG		 708 bool free[32];
709 uint32_t reg[32];
710};
711
712int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
713void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
714
75efdee1
AD		 715/*
716 * GPU doorbell structures, functions & helpers
717 */
d5754ab8
AL		 718#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
719
75efdee1 720struct radeon_doorbell {
75efdee1 721 /* doorbell mmio */
d5754ab8
AL		 722 resource_size_t base;
723 resource_size_t size;
724 u32 __iomem *ptr;
725 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
a10e04f4 726 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
75efdee1
AD		 727};
728
729int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
730void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
ebff8453
OG		 731void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
732 phys_addr_t *aperture_base,
733 size_t *aperture_size,
734 size_t *start_offset);
771fe6b9
JG		 735
736/*
737 * IRQS.
738 */
6f34be50 739
fa7f517c
CK		 740struct radeon_flip_work {
741 struct work_struct flip_work;
742 struct work_struct unpin_work;
743 struct radeon_device *rdev;
744 int crtc_id;
c60381bd 745 uint64_t base;
6f34be50 746 struct drm_pending_vblank_event *event;
fa7f517c 747 struct radeon_bo *old_rbo;
a0e84764 748 struct fence *fence;
6f34be50
AD		 749};
750
751struct r500_irq_stat_regs {
752 u32 disp_int;
f122c610 753 u32 hdmi0_status;
6f34be50
AD		 754};
755
756struct r600_irq_stat_regs {
757 u32 disp_int;
758 u32 disp_int_cont;
759 u32 disp_int_cont2;
760 u32 d1grph_int;
761 u32 d2grph_int;
f122c610
AD		 762 u32 hdmi0_status;
763 u32 hdmi1_status;
6f34be50
AD		 764};
765
766struct evergreen_irq_stat_regs {
767 u32 disp_int;
768 u32 disp_int_cont;
769 u32 disp_int_cont2;
770 u32 disp_int_cont3;
771 u32 disp_int_cont4;
772 u32 disp_int_cont5;
773 u32 d1grph_int;
774 u32 d2grph_int;
775 u32 d3grph_int;
776 u32 d4grph_int;
777 u32 d5grph_int;
778 u32 d6grph_int;
f122c610
AD		 779 u32 afmt_status1;
780 u32 afmt_status2;
781 u32 afmt_status3;
782 u32 afmt_status4;
783 u32 afmt_status5;
784 u32 afmt_status6;
6f34be50
AD		 785};
786
a59781bb
AD		 787struct cik_irq_stat_regs {
788 u32 disp_int;
789 u32 disp_int_cont;
790 u32 disp_int_cont2;
791 u32 disp_int_cont3;
792 u32 disp_int_cont4;
793 u32 disp_int_cont5;
794 u32 disp_int_cont6;
f5d636d2
CK		 795 u32 d1grph_int;
796 u32 d2grph_int;
797 u32 d3grph_int;
798 u32 d4grph_int;
799 u32 d5grph_int;
800 u32 d6grph_int;
a59781bb
AD		 801};
802
6f34be50
AD		 803union radeon_irq_stat_regs {
804 struct r500_irq_stat_regs r500;
805 struct r600_irq_stat_regs r600;
806 struct evergreen_irq_stat_regs evergreen;
a59781bb 807 struct cik_irq_stat_regs cik;
6f34be50
AD		 808};
809
771fe6b9 810struct radeon_irq {
fb98257a
CK		 811 bool installed;
812 spinlock_t lock;
736fc37f 813 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 814 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 815 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 816 wait_queue_head_t vblank_queue;
817 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 818 bool afmt[RADEON_MAX_AFMT_BLOCKS];
819 union radeon_irq_stat_regs stat_regs;
4a6369e9 820 bool dpm_thermal;
771fe6b9
JG		 821};
822
823int radeon_irq_kms_init(struct radeon_device *rdev);
824void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b 825void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
954605ca 826bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
1b37078b 827void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 828void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
829void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 830void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
831void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
832void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
833void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 834
835/*
e32eb50d 836 * CP & rings.
771fe6b9 837 */
7465280c 838
771fe6b9 839struct radeon_ib {
68470ae7
JG		 840 struct radeon_sa_bo *sa_bo;
841 uint32_t length_dw;
842 uint64_t gpu_addr;
843 uint32_t *ptr;
876dc9f3 844 int ring;
68470ae7 845 struct radeon_fence *fence;
4bf3dd92 846 struct radeon_vm *vm;
68470ae7 847 bool is_const_ib;
975700d2 848 struct radeon_sync sync;
771fe6b9
JG		 849};
850
e32eb50d 851struct radeon_ring {
4c788679 852 struct radeon_bo *ring_obj;
771fe6b9 853 volatile uint32_t *ring;
5596a9db 854 unsigned rptr_offs;
45df6803 855 unsigned rptr_save_reg;
89d35807
AD		 856 u64 next_rptr_gpu_addr;
857 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 858 unsigned wptr;
859 unsigned wptr_old;
860 unsigned ring_size;
861 unsigned ring_free_dw;
862 int count_dw;
aee4aa73
CK		 863 atomic_t last_rptr;
864 atomic64_t last_activity;
771fe6b9
JG		 865 uint64_t gpu_addr;
866 uint32_t align_mask;
867 uint32_t ptr_mask;
771fe6b9 868 bool ready;
78c5560a 869 u32 nop;
8b25ed34 870 u32 idx;
5f0839c1
JG		 871 u64 last_semaphore_signal_addr;
872 u64 last_semaphore_wait_addr;
963e81f9
AD		 873 /* for CIK queues */
874 u32 me;
875 u32 pipe;
876 u32 queue;
877 struct radeon_bo *mqd_obj;
d5754ab8 878 u32 doorbell_index;
963e81f9
AD		 879 unsigned wptr_offs;
880};
881
882struct radeon_mec {
883 struct radeon_bo *hpd_eop_obj;
884 u64 hpd_eop_gpu_addr;
885 u32 num_pipe;
886 u32 num_mec;
887 u32 num_queue;
771fe6b9
JG		 888};
889
721604a1
JG		 890/*
891 * VM
892 */
ee60e29f 893
fa87e62d 894/* maximum number of VMIDs */
ee60e29f
CK		 895#define RADEON_NUM_VM 16
896
fa87e62d 897/* number of entries in page table */
4510fb98 898#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
fa87e62d 899
1c01103c
AD		 900/* PTBs (Page Table Blocks) need to be aligned to 32K */
901#define RADEON_VM_PTB_ALIGN_SIZE 32768
902#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
903#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
904
24c16439
CK		 905#define R600_PTE_VALID (1 << 0)
906#define R600_PTE_SYSTEM (1 << 1)
907#define R600_PTE_SNOOPED (1 << 2)
908#define R600_PTE_READABLE (1 << 5)
909#define R600_PTE_WRITEABLE (1 << 6)
910
ec3dbbcb
CK		 911/* PTE (Page Table Entry) fragment field for different page sizes */
912#define R600_PTE_FRAG_4KB (0 << 7)
913#define R600_PTE_FRAG_64KB (4 << 7)
914#define R600_PTE_FRAG_256KB (6 << 7)
915
33fa9fe3
CK		 916/* flags needed to be set so we can copy directly from the GART table */
917#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
918 R600_PTE_SYSTEM | R600_PTE_VALID )
0e97703c 919
6d2f2944
CK		 920struct radeon_vm_pt {
921 struct radeon_bo *bo;
922 uint64_t addr;
923};
924
7c42bc1a
CK		 925struct radeon_vm_id {
926 unsigned id;
927 uint64_t pd_gpu_addr;
928 /* last flushed PD/PT update */
929 struct radeon_fence *flushed_updates;
930 /* last use of vmid */
931 struct radeon_fence *last_id_use;
932};
933
721604a1 934struct radeon_vm {
94214635
CK		 935 struct mutex mutex;
936
7c42bc1a 937 struct rb_root va;
90a51a32 938
f7a3db75
CK		 939 /* protecting invalidated and freed */
940 spinlock_t status_lock;
941
e31ad969 942 /* BOs moved, but not yet updated in the PT */
7c42bc1a 943 struct list_head invalidated;
e31ad969 944
036bf46a 945 /* BOs freed, but not yet updated in the PT */
7c42bc1a 946 struct list_head freed;
036bf46a 947
161ab658
CK		 948 /* BOs cleared in the PT */
949 struct list_head cleared;
950
90a51a32 951 /* contains the page directory */
7c42bc1a
CK		 952 struct radeon_bo *page_directory;
953 unsigned max_pde_used;
90a51a32
CK		 954
955 /* array of page tables, one for each page directory entry */
7c42bc1a 956 struct radeon_vm_pt *page_tables;
90a51a32 957
7c42bc1a 958 struct radeon_bo_va *ib_bo_va;
cc9e67e3 959
7c42bc1a
CK		 960 /* for id and flush management per ring */
961 struct radeon_vm_id ids[RADEON_NUM_RINGS];
721604a1
JG		 962};
963
721604a1 964struct radeon_vm_manager {
ee60e29f 965 struct radeon_fence *active[RADEON_NUM_VM];
721604a1 966 uint32_t max_pfn;
721604a1
JG		 967 /* number of VMIDs */
968 unsigned nvm;
969 /* vram base address for page table entry */
970 u64 vram_base_offset;
67e915e4
AD		 971 /* is vm enabled? */
972 bool enabled;
054e01d6
CK		 973 /* for hw to save the PD addr on suspend/resume */
974 uint32_t saved_table_addr[RADEON_NUM_VM];
721604a1
JG		 975};
976
977/*
978 * file private structure
979 */
980struct radeon_fpriv {
981 struct radeon_vm vm;
982};
983
d8f60cfc
AD		 984/*
985 * R6xx+ IH ring
986 */
987struct r600_ih {
4c788679 988 struct radeon_bo *ring_obj;
d8f60cfc
AD		 989 volatile uint32_t *ring;
990 unsigned rptr;
d8f60cfc
AD		 991 unsigned ring_size;
992 uint64_t gpu_addr;
d8f60cfc 993 uint32_t ptr_mask;
c20dc369 994 atomic_t lock;
d8f60cfc
AD		 995 bool enabled;
996};
997
347e7592 998/*
2948f5e6 999 * RLC stuff
347e7592 1000 */
2948f5e6
AD		 1001#include "clearstate_defs.h"
1002
1003struct radeon_rlc {
347e7592
AD		 1004 /* for power gating */
1005 struct radeon_bo *save_restore_obj;
1006 uint64_t save_restore_gpu_addr;
2948f5e6 1007 volatile uint32_t *sr_ptr;
1fd11777 1008 const u32 *reg_list;
2948f5e6 1009 u32 reg_list_size;
347e7592
AD		 1010 /* for clear state */
1011 struct radeon_bo *clear_state_obj;
1012 uint64_t clear_state_gpu_addr;
2948f5e6 1013 volatile uint32_t *cs_ptr;
1fd11777 1014 const struct cs_section_def *cs_data;
22c775ce
AD		 1015 u32 clear_state_size;
1016 /* for cp tables */
1017 struct radeon_bo *cp_table_obj;
1018 uint64_t cp_table_gpu_addr;
1019 volatile uint32_t *cp_table_ptr;
1020 u32 cp_table_size;
347e7592
AD		 1021};
1022
69e130a6 1023int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 1024 struct radeon_ib *ib, struct radeon_vm *vm,
1025 unsigned size);
f2e39221 1026void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566 1027int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1538a9e0 1028 struct radeon_ib *const_ib, bool hdp_flush);
771fe6b9
JG		 1029int radeon_ib_pool_init(struct radeon_device *rdev);
1030void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 1031int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 1032/* Ring access between begin & end cannot sleep */
89d35807
AD		 1033bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1034 struct radeon_ring *ring);
e32eb50d
CK		 1035void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1036int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1037int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1538a9e0
MD		 1038void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1039 bool hdp_flush);
1040void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1041 bool hdp_flush);
d6999bc7 1042void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 1043void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1044int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
ff212f25
CK		 1045void radeon_ring_lockup_update(struct radeon_device *rdev,
1046 struct radeon_ring *ring);
069211e5 1047bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 1048unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1049 uint32_t **data);
1050int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1051 unsigned size, uint32_t *data);
e32eb50d 1052int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 1053 unsigned rptr_offs, u32 nop);
e32eb50d 1054void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 1055
1056
4d75658b
AD		 1057/* r600 async dma */
1058void r600_dma_stop(struct radeon_device *rdev);
1059int r600_dma_resume(struct radeon_device *rdev);
1060void r600_dma_fini(struct radeon_device *rdev);
1061
8c5fd7ef
AD		 1062void cayman_dma_stop(struct radeon_device *rdev);
1063int cayman_dma_resume(struct radeon_device *rdev);
1064void cayman_dma_fini(struct radeon_device *rdev);
1065
771fe6b9
JG		 1066/*
1067 * CS.
1068 */
771fe6b9 1069struct radeon_cs_chunk {
771fe6b9
JG		 1070 uint32_t length_dw;
1071 uint32_t *kdata;
721604a1 1072 void __user *user_ptr;
771fe6b9
JG		 1073};
1074
1075struct radeon_cs_parser {
c8c15ff1 1076 struct device *dev;
771fe6b9
JG		 1077 struct radeon_device *rdev;
1078 struct drm_file *filp;
1079 /* chunks */
1080 unsigned nchunks;
1081 struct radeon_cs_chunk *chunks;
1082 uint64_t *chunks_array;
1083 /* IB */
1084 unsigned idx;
1085 /* relocations */
1086 unsigned nrelocs;
1d0c0942 1087 struct radeon_bo_list *relocs;
1d0c0942 1088 struct radeon_bo_list *vm_bos;
771fe6b9 1089 struct list_head validated;
cf4ccd01 1090 unsigned dma_reloc_idx;
771fe6b9 1091 /* indices of various chunks */
6d2d13dd
CK		 1092 struct radeon_cs_chunk *chunk_ib;
1093 struct radeon_cs_chunk *chunk_relocs;
1094 struct radeon_cs_chunk *chunk_flags;
1095 struct radeon_cs_chunk *chunk_const_ib;
f2e39221
JG		 1096 struct radeon_ib ib;
1097 struct radeon_ib const_ib;
771fe6b9 1098 void *track;
3ce0a23d 1099 unsigned family;
e70f224c 1100 int parser_error;
721604a1
JG		 1101 u32 cs_flags;
1102 u32 ring;
1103 s32 priority;
ecff665f 1104 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1105};
1106
28a326c5
ML		 1107static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1108{
6d2d13dd 1109 struct radeon_cs_chunk *ibc = p->chunk_ib;
28a326c5
ML		 1110
1111 if (ibc->kdata)
1112 return ibc->kdata[idx];
1113 return p->ib.ptr[idx];
1114}
1115
513bcb46 1116
771fe6b9
JG		 1117struct radeon_cs_packet {
1118 unsigned idx;
1119 unsigned type;
1120 unsigned reg;
1121 unsigned opcode;
1122 int count;
1123 unsigned one_reg_wr;
1124};
1125
1126typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1127 struct radeon_cs_packet *pkt,
1128 unsigned idx, unsigned reg);
1129typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1130 struct radeon_cs_packet *pkt);
1131
1132
1133/*
1134 * AGP
1135 */
1136int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1137void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1138void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1139void radeon_agp_fini(struct radeon_device *rdev);
1140
1141
1142/*
1143 * Writeback
1144 */
1145struct radeon_wb {
4c788679 1146 struct radeon_bo *wb_obj;
771fe6b9
JG		 1147 volatile uint32_t *wb;
1148 uint64_t gpu_addr;
724c80e1 1149 bool enabled;
d0f8a854 1150 bool use_event;
771fe6b9
JG		 1151};
1152
724c80e1 1153#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1154#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1155#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1156#define RADEON_WB_CP1_RPTR_OFFSET 1280
1157#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1158#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1159#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1160#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1161#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1162#define CIK_WB_CP1_WPTR_OFFSET 3328
1163#define CIK_WB_CP2_WPTR_OFFSET 3584
adfed2b0
AD		 1164#define R600_WB_DMA_RING_TEST_OFFSET 3588
1165#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
724c80e1 1166
c93bb85b
JG		 1167/**
1168 * struct radeon_pm - power management datas
1169 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1170 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1171 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1172 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1173 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1174 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1175 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1176 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1177 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1178 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1179 * @needed_bandwidth: current bandwidth needs
1180 *
1181 * It keeps track of various data needed to take powermanagement decision.
25985edc 1182 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1183 * Equation between gpu/memory clock and available bandwidth is hw dependent
1184 * (type of memory, bus size, efficiency, ...)
1185 */
ce8f5370
AD		 1186
1187enum radeon_pm_method {
1188 PM_METHOD_PROFILE,
1189 PM_METHOD_DYNPM,
da321c8a 1190 PM_METHOD_DPM,
ce8f5370
AD		 1191};
1192
1193enum radeon_dynpm_state {
1194 DYNPM_STATE_DISABLED,
1195 DYNPM_STATE_MINIMUM,
1196 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1197 DYNPM_STATE_ACTIVE,
1198 DYNPM_STATE_SUSPENDED,
c913e23a 1199};
ce8f5370
AD		 1200enum radeon_dynpm_action {
1201 DYNPM_ACTION_NONE,
1202 DYNPM_ACTION_MINIMUM,
1203 DYNPM_ACTION_DOWNCLOCK,
1204 DYNPM_ACTION_UPCLOCK,
1205 DYNPM_ACTION_DEFAULT
c913e23a 1206};
56278a8e
AD		 1207
1208enum radeon_voltage_type {
1209 VOLTAGE_NONE = 0,
1210 VOLTAGE_GPIO,
1211 VOLTAGE_VDDC,
1212 VOLTAGE_SW
1213};
1214
0ec0e74f 1215enum radeon_pm_state_type {
da321c8a 1216 /* not used for dpm */
0ec0e74f
AD		 1217 POWER_STATE_TYPE_DEFAULT,
1218 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1219 /* user selectable states */
0ec0e74f
AD		 1220 POWER_STATE_TYPE_BATTERY,
1221 POWER_STATE_TYPE_BALANCED,
1222 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1223 /* internal states */
1224 POWER_STATE_TYPE_INTERNAL_UVD,
1225 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1226 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1227 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1228 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1229 POWER_STATE_TYPE_INTERNAL_BOOT,
1230 POWER_STATE_TYPE_INTERNAL_THERMAL,
1231 POWER_STATE_TYPE_INTERNAL_ACPI,
1232 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1233 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1234};
1235
ce8f5370
AD		 1236enum radeon_pm_profile_type {
1237 PM_PROFILE_DEFAULT,
1238 PM_PROFILE_AUTO,
1239 PM_PROFILE_LOW,
c9e75b21 1240 PM_PROFILE_MID,
ce8f5370
AD		 1241 PM_PROFILE_HIGH,
1242};
1243
1244#define PM_PROFILE_DEFAULT_IDX 0
1245#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1246#define PM_PROFILE_MID_SH_IDX 2
1247#define PM_PROFILE_HIGH_SH_IDX 3
1248#define PM_PROFILE_LOW_MH_IDX 4
1249#define PM_PROFILE_MID_MH_IDX 5
1250#define PM_PROFILE_HIGH_MH_IDX 6
1251#define PM_PROFILE_MAX 7
ce8f5370
AD		 1252
1253struct radeon_pm_profile {
1254 int dpms_off_ps_idx;
1255 int dpms_on_ps_idx;
1256 int dpms_off_cm_idx;
1257 int dpms_on_cm_idx;
516d0e46
AD		 1258};
1259
21a8122a
AD		 1260enum radeon_int_thermal_type {
1261 THERMAL_TYPE_NONE,
da321c8a
AD		 1262 THERMAL_TYPE_EXTERNAL,
1263 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1264 THERMAL_TYPE_RV6XX,
1265 THERMAL_TYPE_RV770,
da321c8a 1266 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1267 THERMAL_TYPE_EVERGREEN,
e33df25f 1268 THERMAL_TYPE_SUMO,
4fddba1f 1269 THERMAL_TYPE_NI,
14607d08 1270 THERMAL_TYPE_SI,
da321c8a 1271 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1272 THERMAL_TYPE_CI,
16fbe00d 1273 THERMAL_TYPE_KV,
21a8122a
AD		 1274};
1275
56278a8e
AD		 1276struct radeon_voltage {
1277 enum radeon_voltage_type type;
1278 /* gpio voltage */
1279 struct radeon_gpio_rec gpio;
1280 u32 delay; /* delay in usec from voltage drop to sclk change */
1281 bool active_high; /* voltage drop is active when bit is high */
1282 /* VDDC voltage */
1283 u8 vddc_id; /* index into vddc voltage table */
1284 u8 vddci_id; /* index into vddci voltage table */
1285 bool vddci_enabled;
1286 /* r6xx+ sw */
2feea49a
AD		 1287 u16 voltage;
1288 /* evergreen+ vddci */
1289 u16 vddci;
56278a8e
AD		 1290};
1291
d7311171
AD		 1292/* clock mode flags */
1293#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1294
56278a8e
AD		 1295struct radeon_pm_clock_info {
1296 /* memory clock */
1297 u32 mclk;
1298 /* engine clock */
1299 u32 sclk;
1300 /* voltage info */
1301 struct radeon_voltage voltage;
d7311171 1302 /* standardized clock flags */
56278a8e
AD		 1303 u32 flags;
1304};
1305
a48b9b4e 1306/* state flags */
d7311171 1307#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1308
56278a8e 1309struct radeon_power_state {
0ec0e74f 1310 enum radeon_pm_state_type type;
8f3f1c9a 1311 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1312 /* number of valid clock modes in this power state */
1313 int num_clock_modes;
56278a8e 1314 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1315 /* standardized state flags */
1316 u32 flags;
79daedc9
AD		 1317 u32 misc; /* vbios specific flags */
1318 u32 misc2; /* vbios specific flags */
1319 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1320};
1321
27459324
RM		 1322/*
1323 * Some modes are overclocked by very low value, accept them
1324 */
1325#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1326
2e9d4c05
AD		 1327enum radeon_dpm_auto_throttle_src {
1328 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1329 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1330};
1331
1332enum radeon_dpm_event_src {
1333 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1334 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1335 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1336 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1337 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1338};
1339
58bd2a88
AD		 1340#define RADEON_MAX_VCE_LEVELS 6
1341
b62d628b
AD		 1342enum radeon_vce_level {
1343 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1344 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1345 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1346 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1347 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1348 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1349};
1350
da321c8a
AD		 1351struct radeon_ps {
1352 u32 caps; /* vbios flags */
1353 u32 class; /* vbios flags */
1354 u32 class2; /* vbios flags */
1355 /* UVD clocks */
1356 u32 vclk;
1357 u32 dclk;
c4453e66
AD		 1358 /* VCE clocks */
1359 u32 evclk;
1360 u32 ecclk;
b62d628b
AD		 1361 bool vce_active;
1362 enum radeon_vce_level vce_level;
da321c8a
AD		 1363 /* asic priv */
1364 void *ps_priv;
1365};
1366
1367struct radeon_dpm_thermal {
1368 /* thermal interrupt work */
1369 struct work_struct work;
1370 /* low temperature threshold */
1371 int min_temp;
1372 /* high temperature threshold */
1373 int max_temp;
1374 /* was interrupt low to high or high to low */
1375 bool high_to_low;
1376};
1377
d22b7e40
AD		 1378enum radeon_clk_action
1379{
1380 RADEON_SCLK_UP = 1,
1381 RADEON_SCLK_DOWN
1382};
1383
1384struct radeon_blacklist_clocks
1385{
1386 u32 sclk;
1387 u32 mclk;
1388 enum radeon_clk_action action;
1389};
1390
61b7d601
AD		 1391struct radeon_clock_and_voltage_limits {
1392 u32 sclk;
1393 u32 mclk;
cdf6e805
AD		 1394 u16 vddc;
1395 u16 vddci;
61b7d601
AD		 1396};
1397
1398struct radeon_clock_array {
1399 u32 count;
1400 u32 *values;
1401};
1402
1403struct radeon_clock_voltage_dependency_entry {
1404 u32 clk;
1405 u16 v;
1406};
1407
1408struct radeon_clock_voltage_dependency_table {
1409 u32 count;
1410 struct radeon_clock_voltage_dependency_entry *entries;
1411};
1412
ef976ec4
AD		 1413union radeon_cac_leakage_entry {
1414 struct {
1415 u16 vddc;
1416 u32 leakage;
1417 };
1418 struct {
1419 u16 vddc1;
1420 u16 vddc2;
1421 u16 vddc3;
1422 };
61b7d601
AD		 1423};
1424
1425struct radeon_cac_leakage_table {
1426 u32 count;
ef976ec4 1427 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1428};
1429
929ee7a8
AD		 1430struct radeon_phase_shedding_limits_entry {
1431 u16 voltage;
1432 u32 sclk;
1433 u32 mclk;
1434};
1435
1436struct radeon_phase_shedding_limits_table {
1437 u32 count;
1438 struct radeon_phase_shedding_limits_entry *entries;
1439};
1440
84a9d9ee
AD		 1441struct radeon_uvd_clock_voltage_dependency_entry {
1442 u32 vclk;
1443 u32 dclk;
1444 u16 v;
1445};
1446
1447struct radeon_uvd_clock_voltage_dependency_table {
1448 u8 count;
1449 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1450};
1451
d29f013b
AD		 1452struct radeon_vce_clock_voltage_dependency_entry {
1453 u32 ecclk;
1454 u32 evclk;
1455 u16 v;
1456};
1457
1458struct radeon_vce_clock_voltage_dependency_table {
1459 u8 count;
1460 struct radeon_vce_clock_voltage_dependency_entry *entries;
1461};
1462
a5cb318e
AD		 1463struct radeon_ppm_table {
1464 u8 ppm_design;
1465 u16 cpu_core_number;
1466 u32 platform_tdp;
1467 u32 small_ac_platform_tdp;
1468 u32 platform_tdc;
1469 u32 small_ac_platform_tdc;
1470 u32 apu_tdp;
1471 u32 dgpu_tdp;
1472 u32 dgpu_ulv_power;
1473 u32 tj_max;
1474};
1475
58cb7632
AD		 1476struct radeon_cac_tdp_table {
1477 u16 tdp;
1478 u16 configurable_tdp;
1479 u16 tdc;
1480 u16 battery_power_limit;
1481 u16 small_power_limit;
1482 u16 low_cac_leakage;
1483 u16 high_cac_leakage;
1484 u16 maximum_power_delivery_limit;
1485};
1486
61b7d601
AD		 1487struct radeon_dpm_dynamic_state {
1488 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1489 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1490 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1491 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1492 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1493 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1494 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1495 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1496 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1497 struct radeon_clock_array valid_sclk_values;
1498 struct radeon_clock_array valid_mclk_values;
1499 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1500 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1501 u32 mclk_sclk_ratio;
1502 u32 sclk_mclk_delta;
1503 u16 vddc_vddci_delta;
1504 u16 min_vddc_for_pcie_gen2;
1505 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1506 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1507 struct radeon_ppm_table *ppm_table;
58cb7632 1508 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1509};
1510
1511struct radeon_dpm_fan {
1512 u16 t_min;
1513 u16 t_med;
1514 u16 t_high;
1515 u16 pwm_min;
1516 u16 pwm_med;
1517 u16 pwm_high;
1518 u8 t_hyst;
1519 u32 cycle_delay;
1520 u16 t_max;
e03cea36
AD		 1521 u8 control_mode;
1522 u16 default_max_fan_pwm;
1523 u16 default_fan_output_sensitivity;
1524 u16 fan_output_sensitivity;
61b7d601
AD		 1525 bool ucode_fan_control;
1526};
1527
32ce4652
AD		 1528enum radeon_pcie_gen {
1529 RADEON_PCIE_GEN1 = 0,
1530 RADEON_PCIE_GEN2 = 1,
1531 RADEON_PCIE_GEN3 = 2,
1532 RADEON_PCIE_GEN_INVALID = 0xffff
1533};
1534
70d01a5e
AD		 1535enum radeon_dpm_forced_level {
1536 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1537 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1538 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1539};
1540
58bd2a88
AD		 1541struct radeon_vce_state {
1542 /* vce clocks */
1543 u32 evclk;
1544 u32 ecclk;
1545 /* gpu clocks */
1546 u32 sclk;
1547 u32 mclk;
1548 u8 clk_idx;
1549 u8 pstate;
1550};
1551
da321c8a
AD		 1552struct radeon_dpm {
1553 struct radeon_ps *ps;
1554 /* number of valid power states */
1555 int num_ps;
1556 /* current power state that is active */
1557 struct radeon_ps *current_ps;
1558 /* requested power state */
1559 struct radeon_ps *requested_ps;
1560 /* boot up power state */
1561 struct radeon_ps *boot_ps;
1562 /* default uvd power state */
1563 struct radeon_ps *uvd_ps;
58bd2a88
AD		 1564 /* vce requirements */
1565 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1566 enum radeon_vce_level vce_level;
da321c8a
AD		 1567 enum radeon_pm_state_type state;
1568 enum radeon_pm_state_type user_state;
1569 u32 platform_caps;
1570 u32 voltage_response_time;
1571 u32 backbias_response_time;
1572 void *priv;
1573 u32 new_active_crtcs;
1574 int new_active_crtc_count;
1575 u32 current_active_crtcs;
1576 int current_active_crtc_count;
3899ca84 1577 bool single_display;
61b7d601
AD		 1578 struct radeon_dpm_dynamic_state dyn_state;
1579 struct radeon_dpm_fan fan;
1580 u32 tdp_limit;
1581 u32 near_tdp_limit;
a9e61410 1582 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1583 u32 sq_ramping_threshold;
1584 u32 cac_leakage;
1585 u16 tdp_od_limit;
1586 u32 tdp_adjustment;
1587 u16 load_line_slope;
1588 bool power_control;
5ca302f7 1589 bool ac_power;
da321c8a
AD		 1590 /* special states active */
1591 bool thermal_active;
8a227555 1592 bool uvd_active;
b62d628b 1593 bool vce_active;
da321c8a
AD		 1594 /* thermal handling */
1595 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1596 /* forced levels */
1597 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1598 /* track UVD streams */
1599 unsigned sd;
1600 unsigned hd;
da321c8a
AD		 1601};
1602
ce3537d5 1603void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
03afe6f6 1604void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
da321c8a 1605
c93bb85b 1606struct radeon_pm {
c913e23a 1607 struct mutex mutex;
db7fce39
CK		 1608 /* write locked while reprogramming mclk */
1609 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1610 u32 active_crtcs;
1611 int active_crtc_count;
c913e23a 1612 int req_vblank;
839461d3 1613 bool vblank_sync;
c93bb85b
JG		 1614 fixed20_12 max_bandwidth;
1615 fixed20_12 igp_sideport_mclk;
1616 fixed20_12 igp_system_mclk;
1617 fixed20_12 igp_ht_link_clk;
1618 fixed20_12 igp_ht_link_width;
1619 fixed20_12 k8_bandwidth;
1620 fixed20_12 sideport_bandwidth;
1621 fixed20_12 ht_bandwidth;
1622 fixed20_12 core_bandwidth;
1623 fixed20_12 sclk;
f47299c5 1624 fixed20_12 mclk;
c93bb85b 1625 fixed20_12 needed_bandwidth;
0975b162 1626 struct radeon_power_state *power_state;
56278a8e
AD		 1627 /* number of valid power states */
1628 int num_power_states;
a48b9b4e
AD		 1629 int current_power_state_index;
1630 int current_clock_mode_index;
1631 int requested_power_state_index;
1632 int requested_clock_mode_index;
1633 int default_power_state_index;
1634 u32 current_sclk;
1635 u32 current_mclk;
2feea49a
AD		 1636 u16 current_vddc;
1637 u16 current_vddci;
9ace9f7b
AD		 1638 u32 default_sclk;
1639 u32 default_mclk;
2feea49a
AD		 1640 u16 default_vddc;
1641 u16 default_vddci;
29fb52ca 1642 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1643 /* selected pm method */
1644 enum radeon_pm_method pm_method;
1645 /* dynpm power management */
1646 struct delayed_work dynpm_idle_work;
1647 enum radeon_dynpm_state dynpm_state;
1648 enum radeon_dynpm_action dynpm_planned_action;
1649 unsigned long dynpm_action_timeout;
1650 bool dynpm_can_upclock;
1651 bool dynpm_can_downclock;
1652 /* profile-based power management */
1653 enum radeon_pm_profile_type profile;
1654 int profile_index;
1655 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1656 /* internal thermal controller on rv6xx+ */
1657 enum radeon_int_thermal_type int_thermal_type;
1658 struct device *int_hwmon_dev;
9b92d1ec
AD		 1659 /* fan control parameters */
1660 bool no_fan;
1661 u8 fan_pulses_per_revolution;
1662 u8 fan_min_rpm;
1663 u8 fan_max_rpm;
da321c8a
AD		 1664 /* dpm */
1665 bool dpm_enabled;
49abb266 1666 bool sysfs_initialized;
da321c8a 1667 struct radeon_dpm dpm;
c93bb85b
JG		 1668};
1669
a4c9e2ee
AD		 1670int radeon_pm_get_type_index(struct radeon_device *rdev,
1671 enum radeon_pm_state_type ps_type,
1672 int instance);
f2ba57b5
CK		 1673/*
1674 * UVD
1675 */
1676#define RADEON_MAX_UVD_HANDLES 10
1677#define RADEON_UVD_STACK_SIZE (1024*1024)
1678#define RADEON_UVD_HEAP_SIZE (1024*1024)
1679
1680struct radeon_uvd {
1681 struct radeon_bo *vcpu_bo;
1682 void *cpu_addr;
1683 uint64_t gpu_addr;
1684 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1685 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1686 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1687 struct delayed_work idle_work;
f2ba57b5
CK		 1688};
1689
1690int radeon_uvd_init(struct radeon_device *rdev);
1691void radeon_uvd_fini(struct radeon_device *rdev);
1692int radeon_uvd_suspend(struct radeon_device *rdev);
1693int radeon_uvd_resume(struct radeon_device *rdev);
1694int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1695 uint32_t handle, struct radeon_fence **fence);
1696int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1697 uint32_t handle, struct radeon_fence **fence);
3852752c
CK		 1698void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1699 uint32_t allowed_domains);
f2ba57b5
CK		 1700void radeon_uvd_free_handles(struct radeon_device *rdev,
1701 struct drm_file *filp);
1702int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1703void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1704int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1705 unsigned vclk, unsigned dclk,
1706 unsigned vco_min, unsigned vco_max,
1707 unsigned fb_factor, unsigned fb_mask,
1708 unsigned pd_min, unsigned pd_max,
1709 unsigned pd_even,
1710 unsigned *optimal_fb_div,
1711 unsigned *optimal_vclk_div,
1712 unsigned *optimal_dclk_div);
1713int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1714 unsigned cg_upll_func_cntl);
771fe6b9 1715
d93f7937
CK		 1716/*
1717 * VCE
1718 */
1719#define RADEON_MAX_VCE_HANDLES 16
d93f7937
CK		 1720
1721struct radeon_vce {
1722 struct radeon_bo *vcpu_bo;
d93f7937 1723 uint64_t gpu_addr;
98ccc291
CK		 1724 unsigned fw_version;
1725 unsigned fb_version;
d93f7937
CK		 1726 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1727 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
2fc5703a 1728 unsigned img_size[RADEON_MAX_VCE_HANDLES];
03afe6f6 1729 struct delayed_work idle_work;
a918efab 1730 uint32_t keyselect;
d93f7937
CK		 1731};
1732
1733int radeon_vce_init(struct radeon_device *rdev);
1734void radeon_vce_fini(struct radeon_device *rdev);
1735int radeon_vce_suspend(struct radeon_device *rdev);
1736int radeon_vce_resume(struct radeon_device *rdev);
1737int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1738 uint32_t handle, struct radeon_fence **fence);
1739int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1740 uint32_t handle, struct radeon_fence **fence);
1741void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
03afe6f6 1742void radeon_vce_note_usage(struct radeon_device *rdev);
2fc5703a 1743int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
d93f7937
CK		 1744int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1745bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1746 struct radeon_ring *ring,
1747 struct radeon_semaphore *semaphore,
1748 bool emit_wait);
1749void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1750void radeon_vce_fence_emit(struct radeon_device *rdev,
1751 struct radeon_fence *fence);
1752int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1753int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1754
b530602f 1755struct r600_audio_pin {
a92553ab
RM		 1756 int channels;
1757 int rate;
1758 int bits_per_sample;
1759 u8 status_bits;
1760 u8 category_code;
b530602f
AD		 1761 u32 offset;
1762 bool connected;
1763 u32 id;
1764};
1765
1766struct r600_audio {
1767 bool enabled;
1768 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1769 int num_pins;
1a626b68
SG		 1770 struct radeon_audio_funcs *hdmi_funcs;
1771 struct radeon_audio_funcs *dp_funcs;
1772 struct radeon_audio_basic_funcs *funcs;
a92553ab
RM		 1773};
1774
771fe6b9
JG		 1775/*
1776 * Benchmarking
1777 */
638dd7db 1778void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1779
1780
ecc0b326
MD		 1781/*
1782 * Testing
1783 */
1784void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1785void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1786 struct radeon_ring *cpA,
1787 struct radeon_ring *cpB);
60a7e396 1788void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326 1789
341cb9e4
CK		 1790/*
1791 * MMU Notifier
1792 */
5a1aa4b4 1793#if defined(CONFIG_MMU_NOTIFIER)
341cb9e4
CK		 1794int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1795void radeon_mn_unregister(struct radeon_bo *bo);
5a1aa4b4
RC		 1796#else
1797static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1798{
1799 return -ENODEV;
1800}
1801static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1802#endif
ecc0b326 1803
771fe6b9
JG		 1804/*
1805 * Debugfs
1806 */
4d8bf9ae
CK		 1807struct radeon_debugfs {
1808 struct drm_info_list *files;
1809 unsigned num_files;
1810};
1811
771fe6b9
JG		 1812int radeon_debugfs_add_files(struct radeon_device *rdev,
1813 struct drm_info_list *files,
1814 unsigned nfiles);
1815int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1816
76a0df85
CK		 1817/*
1818 * ASIC ring specific functions.
1819 */
1820struct radeon_asic_ring {
1821 /* ring read/write ptr handling */
1822 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1823 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1824 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1825
1826 /* validating and patching of IBs */
1827 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1828 int (*cs_parse)(struct radeon_cs_parser *p);
1829
1830 /* command emmit functions */
1831 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1832 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
72a9987e 1833 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1654b817 1834 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85 1835 struct radeon_semaphore *semaphore, bool emit_wait);
faffaf62
CK		 1836 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1837 unsigned vm_id, uint64_t pd_addr);
76a0df85
CK		 1838
1839 /* testing functions */
1840 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1841 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1842 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1843
1844 /* deprecated */
1845 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1846};
771fe6b9
JG		 1847
1848/*
1849 * ASIC specific functions.
1850 */
1851struct radeon_asic {
068a117c 1852 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1853 void (*fini)(struct radeon_device *rdev);
1854 int (*resume)(struct radeon_device *rdev);
1855 int (*suspend)(struct radeon_device *rdev);
28d52043 1856 void (*vga_set_state)(struct radeon_device *rdev, bool state);
71fe2899 1857 int (*asic_reset)(struct radeon_device *rdev, bool hard);
124764f1
MD		 1858 /* Flush the HDP cache via MMIO */
1859 void (*mmio_hdp_flush)(struct radeon_device *rdev);
54e88e06
AD		 1860 /* check if 3D engine is idle */
1861 bool (*gui_idle)(struct radeon_device *rdev);
1862 /* wait for mc_idle */
1863 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1864 /* get the reference clock */
1865 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1866 /* get the gpu clock counter */
1867 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
4ce4728b
AD		 1868 /* get register for info ioctl */
1869 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
54e88e06 1870 /* gart */
c5b3b850
AD		 1871 struct {
1872 void (*tlb_flush)(struct radeon_device *rdev);
cb658906 1873 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
7f90fc96 1874 void (*set_page)(struct radeon_device *rdev, unsigned i,
cb658906 1875 uint64_t entry);
c5b3b850 1876 } gart;
05b07147
CK		 1877 struct {
1878 int (*init)(struct radeon_device *rdev);
1879 void (*fini)(struct radeon_device *rdev);
03f62abd
CK		 1880 void (*copy_pages)(struct radeon_device *rdev,
1881 struct radeon_ib *ib,
1882 uint64_t pe, uint64_t src,
1883 unsigned count);
1884 void (*write_pages)(struct radeon_device *rdev,
1885 struct radeon_ib *ib,
1886 uint64_t pe,
1887 uint64_t addr, unsigned count,
1888 uint32_t incr, uint32_t flags);
1889 void (*set_pages)(struct radeon_device *rdev,
1890 struct radeon_ib *ib,
1891 uint64_t pe,
1892 uint64_t addr, unsigned count,
1893 uint32_t incr, uint32_t flags);
1894 void (*pad_ib)(struct radeon_ib *ib);
05b07147 1895 } vm;
54e88e06 1896 /* ring specific callbacks */
d26678da 1897 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1898 /* irqs */
b35ea4ab
AD		 1899 struct {
1900 int (*set)(struct radeon_device *rdev);
1901 int (*process)(struct radeon_device *rdev);
1902 } irq;
54e88e06 1903 /* displays */
c79a49ca
AD		 1904 struct {
1905 /* display watermarks */
1906 void (*bandwidth_update)(struct radeon_device *rdev);
1907 /* get frame count */
1908 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1909 /* wait for vblank */
1910 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1911 /* set backlight level */
1912 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1913 /* get backlight level */
1914 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1915 /* audio callbacks */
1916 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1917 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1918 } display;
54e88e06 1919 /* copy functions for bo handling */
27cd7769 1920 struct {
57d20a43
CK		 1921 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1922 uint64_t src_offset,
1923 uint64_t dst_offset,
1924 unsigned num_gpu_pages,
1925 struct reservation_object *resv);
27cd7769 1926 u32 blit_ring_index;
57d20a43
CK		 1927 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1928 uint64_t src_offset,
1929 uint64_t dst_offset,
1930 unsigned num_gpu_pages,
1931 struct reservation_object *resv);
27cd7769
AD		 1932 u32 dma_ring_index;
1933 /* method used for bo copy */
57d20a43
CK		 1934 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1935 uint64_t src_offset,
1936 uint64_t dst_offset,
1937 unsigned num_gpu_pages,
1938 struct reservation_object *resv);
27cd7769
AD		 1939 /* ring used for bo copies */
1940 u32 copy_ring_index;
1941 } copy;
54e88e06 1942 /* surfaces */
9e6f3d02
AD		 1943 struct {
1944 int (*set_reg)(struct radeon_device *rdev, int reg,
1945 uint32_t tiling_flags, uint32_t pitch,
1946 uint32_t offset, uint32_t obj_size);
1947 void (*clear_reg)(struct radeon_device *rdev, int reg);
1948 } surface;
54e88e06 1949 /* hotplug detect */
901ea57d
AD		 1950 struct {
1951 void (*init)(struct radeon_device *rdev);
1952 void (*fini)(struct radeon_device *rdev);
1953 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1954 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1955 } hpd;
da321c8a 1956 /* static power management */
a02fa397
AD		 1957 struct {
1958 void (*misc)(struct radeon_device *rdev);
1959 void (*prepare)(struct radeon_device *rdev);
1960 void (*finish)(struct radeon_device *rdev);
1961 void (*init_profile)(struct radeon_device *rdev);
1962 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1963 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1964 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1965 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1966 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1967 int (*get_pcie_lanes)(struct radeon_device *rdev);
1968 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1969 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1970 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
b59b7333 1971 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
6bd1c385 1972 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1973 } pm;
da321c8a
AD		 1974 /* dynamic power management */
1975 struct {
1976 int (*init)(struct radeon_device *rdev);
1977 void (*setup_asic)(struct radeon_device *rdev);
1978 int (*enable)(struct radeon_device *rdev);
914a8987 1979 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1980 void (*disable)(struct radeon_device *rdev);
84dd1928 1981 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1982 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1983 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1984 void (*display_configuration_changed)(struct radeon_device *rdev);
1985 void (*fini)(struct radeon_device *rdev);
1986 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1987 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1988 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1989 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1990 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1991 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1992 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1993 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
a35a4b2b
OC		 1994 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1995 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1996 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1997 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
d7dbce09
AD		 1998 u32 (*get_current_sclk)(struct radeon_device *rdev);
1999 u32 (*get_current_mclk)(struct radeon_device *rdev);
da321c8a 2000 } dpm;
6f34be50 2001 /* pageflipping */
0f9e006c 2002 struct {
157fa14d
CK		 2003 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
2004 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
0f9e006c 2005 } pflip;
771fe6b9
JG		 2006};
2007
21f9a437
JG		 2008/*
2009 * Asic structures
2010 */
551ebd83 2011struct r100_asic {
225758d8
JG		 2012 const unsigned *reg_safe_bm;
2013 unsigned reg_safe_bm_size;
2014 u32 hdp_cntl;
551ebd83
DA		 2015};
2016
21f9a437 2017struct r300_asic {
225758d8
JG		 2018 const unsigned *reg_safe_bm;
2019 unsigned reg_safe_bm_size;
2020 u32 resync_scratch;
2021 u32 hdp_cntl;
21f9a437
JG		 2022};
2023
2024struct r600_asic {
225758d8
JG		 2025 unsigned max_pipes;
2026 unsigned max_tile_pipes;
2027 unsigned max_simds;
2028 unsigned max_backends;
2029 unsigned max_gprs;
2030 unsigned max_threads;
2031 unsigned max_stack_entries;
2032 unsigned max_hw_contexts;
2033 unsigned max_gs_threads;
2034 unsigned sx_max_export_size;
2035 unsigned sx_max_export_pos_size;
2036 unsigned sx_max_export_smx_size;
2037 unsigned sq_num_cf_insts;
2038 unsigned tiling_nbanks;
2039 unsigned tiling_npipes;
2040 unsigned tiling_group_size;
e7aeeba6 2041 unsigned tile_config;
e55b9422 2042 unsigned backend_map;
65fcf668 2043 unsigned active_simds;
21f9a437
JG		 2044};
2045
2046struct rv770_asic {
225758d8
JG		 2047 unsigned max_pipes;
2048 unsigned max_tile_pipes;
2049 unsigned max_simds;
2050 unsigned max_backends;
2051 unsigned max_gprs;
2052 unsigned max_threads;
2053 unsigned max_stack_entries;
2054 unsigned max_hw_contexts;
2055 unsigned max_gs_threads;
2056 unsigned sx_max_export_size;
2057 unsigned sx_max_export_pos_size;
2058 unsigned sx_max_export_smx_size;
2059 unsigned sq_num_cf_insts;
2060 unsigned sx_num_of_sets;
2061 unsigned sc_prim_fifo_size;
2062 unsigned sc_hiz_tile_fifo_size;
2063 unsigned sc_earlyz_tile_fifo_fize;
2064 unsigned tiling_nbanks;
2065 unsigned tiling_npipes;
2066 unsigned tiling_group_size;
e7aeeba6 2067 unsigned tile_config;
e55b9422 2068 unsigned backend_map;
65fcf668 2069 unsigned active_simds;
21f9a437
JG		 2070};
2071
32fcdbf4
AD		 2072struct evergreen_asic {
2073 unsigned num_ses;
2074 unsigned max_pipes;
2075 unsigned max_tile_pipes;
2076 unsigned max_simds;
2077 unsigned max_backends;
2078 unsigned max_gprs;
2079 unsigned max_threads;
2080 unsigned max_stack_entries;
2081 unsigned max_hw_contexts;
2082 unsigned max_gs_threads;
2083 unsigned sx_max_export_size;
2084 unsigned sx_max_export_pos_size;
2085 unsigned sx_max_export_smx_size;
2086 unsigned sq_num_cf_insts;
2087 unsigned sx_num_of_sets;
2088 unsigned sc_prim_fifo_size;
2089 unsigned sc_hiz_tile_fifo_size;
2090 unsigned sc_earlyz_tile_fifo_size;
2091 unsigned tiling_nbanks;
2092 unsigned tiling_npipes;
2093 unsigned tiling_group_size;
e7aeeba6 2094 unsigned tile_config;
e55b9422 2095 unsigned backend_map;
65fcf668 2096 unsigned active_simds;
32fcdbf4
AD		 2097};
2098
fecf1d07
AD		 2099struct cayman_asic {
2100 unsigned max_shader_engines;
2101 unsigned max_pipes_per_simd;
2102 unsigned max_tile_pipes;
2103 unsigned max_simds_per_se;
2104 unsigned max_backends_per_se;
2105 unsigned max_texture_channel_caches;
2106 unsigned max_gprs;
2107 unsigned max_threads;
2108 unsigned max_gs_threads;
2109 unsigned max_stack_entries;
2110 unsigned sx_num_of_sets;
2111 unsigned sx_max_export_size;
2112 unsigned sx_max_export_pos_size;
2113 unsigned sx_max_export_smx_size;
2114 unsigned max_hw_contexts;
2115 unsigned sq_num_cf_insts;
2116 unsigned sc_prim_fifo_size;
2117 unsigned sc_hiz_tile_fifo_size;
2118 unsigned sc_earlyz_tile_fifo_size;
2119
2120 unsigned num_shader_engines;
2121 unsigned num_shader_pipes_per_simd;
2122 unsigned num_tile_pipes;
2123 unsigned num_simds_per_se;
2124 unsigned num_backends_per_se;
2125 unsigned backend_disable_mask_per_asic;
2126 unsigned backend_map;
2127 unsigned num_texture_channel_caches;
2128 unsigned mem_max_burst_length_bytes;
2129 unsigned mem_row_size_in_kb;
2130 unsigned shader_engine_tile_size;
2131 unsigned num_gpus;
2132 unsigned multi_gpu_tile_size;
2133
2134 unsigned tile_config;
65fcf668 2135 unsigned active_simds;
fecf1d07
AD		 2136};
2137
0a96d72b
AD		 2138struct si_asic {
2139 unsigned max_shader_engines;
0a96d72b 2140 unsigned max_tile_pipes;
1a8ca750
AD		 2141 unsigned max_cu_per_sh;
2142 unsigned max_sh_per_se;
0a96d72b
AD		 2143 unsigned max_backends_per_se;
2144 unsigned max_texture_channel_caches;
2145 unsigned max_gprs;
2146 unsigned max_gs_threads;
2147 unsigned max_hw_contexts;
2148 unsigned sc_prim_fifo_size_frontend;
2149 unsigned sc_prim_fifo_size_backend;
2150 unsigned sc_hiz_tile_fifo_size;
2151 unsigned sc_earlyz_tile_fifo_size;
2152
0a96d72b 2153 unsigned num_tile_pipes;
439a1cff 2154 unsigned backend_enable_mask;
0a96d72b
AD		 2155 unsigned backend_disable_mask_per_asic;
2156 unsigned backend_map;
2157 unsigned num_texture_channel_caches;
2158 unsigned mem_max_burst_length_bytes;
2159 unsigned mem_row_size_in_kb;
2160 unsigned shader_engine_tile_size;
2161 unsigned num_gpus;
2162 unsigned multi_gpu_tile_size;
2163
2164 unsigned tile_config;
64d7b8be 2165 uint32_t tile_mode_array[32];
65fcf668 2166 uint32_t active_cus;
0a96d72b
AD		 2167};
2168
8cc1a532
AD		 2169struct cik_asic {
2170 unsigned max_shader_engines;
2171 unsigned max_tile_pipes;
2172 unsigned max_cu_per_sh;
2173 unsigned max_sh_per_se;
2174 unsigned max_backends_per_se;
2175 unsigned max_texture_channel_caches;
2176 unsigned max_gprs;
2177 unsigned max_gs_threads;
2178 unsigned max_hw_contexts;
2179 unsigned sc_prim_fifo_size_frontend;
2180 unsigned sc_prim_fifo_size_backend;
2181 unsigned sc_hiz_tile_fifo_size;
2182 unsigned sc_earlyz_tile_fifo_size;
2183
2184 unsigned num_tile_pipes;
439a1cff 2185 unsigned backend_enable_mask;
8cc1a532
AD		 2186 unsigned backend_disable_mask_per_asic;
2187 unsigned backend_map;
2188 unsigned num_texture_channel_caches;
2189 unsigned mem_max_burst_length_bytes;
2190 unsigned mem_row_size_in_kb;
2191 unsigned shader_engine_tile_size;
2192 unsigned num_gpus;
2193 unsigned multi_gpu_tile_size;
2194
2195 unsigned tile_config;
39aee490 2196 uint32_t tile_mode_array[32];
32f79a8a 2197 uint32_t macrotile_mode_array[16];
65fcf668 2198 uint32_t active_cus;
8cc1a532
AD		 2199};
2200
068a117c
JG		 2201union radeon_asic_config {
2202 struct r300_asic r300;
551ebd83 2203 struct r100_asic r100;
3ce0a23d
JG		 2204 struct r600_asic r600;
2205 struct rv770_asic rv770;
32fcdbf4 2206 struct evergreen_asic evergreen;
fecf1d07 2207 struct cayman_asic cayman;
0a96d72b 2208 struct si_asic si;
8cc1a532 2209 struct cik_asic cik;
068a117c
JG		 2210};
2211
0a10c851
DV		 2212/*
2213 * asic initizalization from radeon_asic.c
2214 */
2215void radeon_agp_disable(struct radeon_device *rdev);
2216int radeon_asic_init(struct radeon_device *rdev);
2217
771fe6b9
JG		 2218
2219/*
2220 * IOCTL.
2221 */
2222int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2223 struct drm_file *filp);
2224int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2225 struct drm_file *filp);
f72a113a
CK		 2226int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2227 struct drm_file *filp);
771fe6b9
JG		 2228int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2229 struct drm_file *file_priv);
2230int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2231 struct drm_file *file_priv);
2232int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2233 struct drm_file *file_priv);
2234int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2235 struct drm_file *file_priv);
2236int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2237 struct drm_file *filp);
2238int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2239 struct drm_file *filp);
2240int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2241 struct drm_file *filp);
2242int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2243 struct drm_file *filp);
721604a1
JG		 2244int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2245 struct drm_file *filp);
bda72d58
MO		 2246int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2247 struct drm_file *filp);
771fe6b9 2248int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2249int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2250 struct drm_file *filp);
2251int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2252 struct drm_file *filp);
771fe6b9 2253
16cdf04d
AD		 2254/* VRAM scratch page for HDP bug, default vram page */
2255struct r600_vram_scratch {
87cbf8f2
AD		 2256 struct radeon_bo *robj;
2257 volatile uint32_t *ptr;
16cdf04d 2258 u64 gpu_addr;
87cbf8f2 2259};
771fe6b9 2260
fd64ca8a
LT		 2261/*
2262 * ACPI
2263 */
2264struct radeon_atif_notification_cfg {
2265 bool enabled;
2266 int command_code;
2267};
2268
2269struct radeon_atif_notifications {
2270 bool display_switch;
2271 bool expansion_mode_change;
2272 bool thermal_state;
2273 bool forced_power_state;
2274 bool system_power_state;
2275 bool display_conf_change;
2276 bool px_gfx_switch;
2277 bool brightness_change;
2278 bool dgpu_display_event;
2279};
2280
2281struct radeon_atif_functions {
2282 bool system_params;
2283 bool sbios_requests;
2284 bool select_active_disp;
2285 bool lid_state;
2286 bool get_tv_standard;
2287 bool set_tv_standard;
2288 bool get_panel_expansion_mode;
2289 bool set_panel_expansion_mode;
2290 bool temperature_change;
2291 bool graphics_device_types;
2292};
2293
2294struct radeon_atif {
2295 struct radeon_atif_notifications notifications;
2296 struct radeon_atif_functions functions;
2297 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2298 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2299};
7a1619b9 2300
e3a15920
AD		 2301struct radeon_atcs_functions {
2302 bool get_ext_state;
2303 bool pcie_perf_req;
2304 bool pcie_dev_rdy;
2305 bool pcie_bus_width;
2306};
2307
2308struct radeon_atcs {
2309 struct radeon_atcs_functions functions;
2310};
2311
771fe6b9
JG		 2312/*
2313 * Core structure, functions and helpers.
2314 */
2315typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2316typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2317
2318struct radeon_device {
9f022ddf 2319 struct device *dev;
771fe6b9
JG		 2320 struct drm_device *ddev;
2321 struct pci_dev *pdev;
dee53e7f 2322 struct rw_semaphore exclusive_lock;
771fe6b9 2323 /* ASIC */
068a117c 2324 union radeon_asic_config config;
771fe6b9
JG		 2325 enum radeon_family family;
2326 unsigned long flags;
2327 int usec_timeout;
2328 enum radeon_pll_errata pll_errata;
2329 int num_gb_pipes;
f779b3e5 2330 int num_z_pipes;
771fe6b9
JG		 2331 int disp_priority;
2332 /* BIOS */
2333 uint8_t *bios;
2334 bool is_atom_bios;
2335 uint16_t bios_header_start;
4c788679 2336 struct radeon_bo *stollen_vga_memory;
771fe6b9 2337 /* Register mmio */
4c9bc75c
DA		 2338 resource_size_t rmmio_base;
2339 resource_size_t rmmio_size;
2c385151
DV		 2340 /* protects concurrent MM_INDEX/DATA based register access */
2341 spinlock_t mmio_idx_lock;
fe78118c
AD		 2342 /* protects concurrent SMC based register access */
2343 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2344 /* protects concurrent PLL register access */
2345 spinlock_t pll_idx_lock;
2346 /* protects concurrent MC register access */
2347 spinlock_t mc_idx_lock;
2348 /* protects concurrent PCIE register access */
2349 spinlock_t pcie_idx_lock;
2350 /* protects concurrent PCIE_PORT register access */
2351 spinlock_t pciep_idx_lock;
2352 /* protects concurrent PIF register access */
2353 spinlock_t pif_idx_lock;
2354 /* protects concurrent CG register access */
2355 spinlock_t cg_idx_lock;
2356 /* protects concurrent UVD register access */
2357 spinlock_t uvd_idx_lock;
2358 /* protects concurrent RCU register access */
2359 spinlock_t rcu_idx_lock;
2360 /* protects concurrent DIDT register access */
2361 spinlock_t didt_idx_lock;
2362 /* protects concurrent ENDPOINT (audio) register access */
2363 spinlock_t end_idx_lock;
a0533fbf 2364 void __iomem *rmmio;
771fe6b9
JG		 2365 radeon_rreg_t mc_rreg;
2366 radeon_wreg_t mc_wreg;
2367 radeon_rreg_t pll_rreg;
2368 radeon_wreg_t pll_wreg;
de1b2898 2369 uint32_t pcie_reg_mask;
771fe6b9
JG		 2370 radeon_rreg_t pciep_rreg;
2371 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2372 /* io port */
2373 void __iomem *rio_mem;
2374 resource_size_t rio_mem_size;
771fe6b9
JG		 2375 struct radeon_clock clock;
2376 struct radeon_mc mc;
2377 struct radeon_gart gart;
2378 struct radeon_mode_info mode_info;
2379 struct radeon_scratch scratch;
75efdee1 2380 struct radeon_doorbell doorbell;
771fe6b9 2381 struct radeon_mman mman;
7465280c 2382 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2383 wait_queue_head_t fence_queue;
954605ca 2384 unsigned fence_context;
d6999bc7 2385 struct mutex ring_lock;
e32eb50d 2386 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2387 bool ib_pool_ready;
2388 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2389 struct radeon_irq irq;
2390 struct radeon_asic *asic;
2391 struct radeon_gem gem;
c93bb85b 2392 struct radeon_pm pm;
f2ba57b5 2393 struct radeon_uvd uvd;
d93f7937 2394 struct radeon_vce vce;
f657c2a7 2395 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2396 struct radeon_wb wb;
3ce0a23d 2397 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2398 bool shutdown;
2399 bool suspend;
ad49f501 2400 bool need_dma32;
733289c2 2401 bool accel_working;
a0a53aa8 2402 bool fastfb_working; /* IGP feature*/
9bb39ff4 2403 bool needs_reset, in_reset;
e024e110 2404 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2405 const struct firmware *me_fw; /* all family ME firmware */
2406 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2407 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2408 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2409 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2410 const struct firmware *mec_fw; /* CIK MEC firmware */
f2c6b0f4 2411 const struct firmware *mec2_fw; /* KV MEC2 firmware */
21a93e13 2412 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2413 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2414 const struct firmware *uvd_fw; /* UVD firmware */
d93f7937 2415 const struct firmware *vce_fw; /* VCE firmware */
629bd33c 2416 bool new_fw;
16cdf04d 2417 struct r600_vram_scratch vram_scratch;
3e5cb98d 2418 int msi_enabled; /* msi enabled */
d8f60cfc 2419 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2420 struct radeon_rlc rlc;
963e81f9 2421 struct radeon_mec mec;
cb5d4166 2422 struct delayed_work hotplug_work;
de6284aa 2423 struct work_struct dp_work;
f122c610 2424 struct work_struct audio_work;
18917b60 2425 int num_crtc; /* number of crtcs */
40bacf16 2426 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2427 bool has_uvd;
e3ebfcfa 2428 bool has_vce;
b530602f 2429 struct r600_audio audio; /* audio stuff */
ce8f5370 2430 struct notifier_block acpi_nb;
9eba4a93 2431 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2432 struct drm_file *hyperz_filp;
9eba4a93 2433 struct drm_file *cmask_filp;
f376b94f
AD		 2434 /* i2c buses */
2435 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2436 /* debugfs */
2437 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2438 unsigned debugfs_count;
721604a1
JG		 2439 /* virtual memory */
2440 struct radeon_vm_manager vm_manager;
6759a0a7 2441 struct mutex gpu_clock_mutex;
67e8e3f9
MO		 2442 /* memory stats */
2443 atomic64_t vram_usage;
2444 atomic64_t gtt_usage;
2445 atomic64_t num_bytes_moved;
72b9076b 2446 atomic_t gpu_reset_counter;
fd64ca8a
LT		 2447 /* ACPI interface */
2448 struct radeon_atif atif;
e3a15920 2449 struct radeon_atcs atcs;
f61d5b46
AD		 2450 /* srbm instance registers */
2451 struct mutex srbm_mutex;
1c0a4625
OG		 2452 /* GRBM index mutex. Protects concurrents access to GRBM index */
2453 struct mutex grbm_idx_mutex;
64d8a728
AD		 2454 /* clock, powergating flags */
2455 u32 cg_flags;
2456 u32 pg_flags;
10ebc0bc
DA		 2457
2458 struct dev_pm_domain vga_pm_domain;
2459 bool have_disp_power_ref;
4807c5a8 2460 u32 px_quirk_flags;
71ecc97e
AD		 2461
2462 /* tracking pinned memory */
2463 u64 vram_pin_size;
2464 u64 gart_pin_size;
341cb9e4 2465
e28740ec
OG		 2466 /* amdkfd interface */
2467 struct kfd_dev *kfd;
e28740ec 2468
341cb9e4
CK		 2469 struct mutex mn_lock;
2470 DECLARE_HASHTABLE(mn_hash, 7);
771fe6b9
JG		 2471};
2472
90c4cde9 2473bool radeon_is_px(struct drm_device *dev);
771fe6b9
JG		 2474int radeon_device_init(struct radeon_device *rdev,
2475 struct drm_device *ddev,
2476 struct pci_dev *pdev,
2477 uint32_t flags);
2478void radeon_device_fini(struct radeon_device *rdev);
2479int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2480
59bc1d89
LK		 2481#define RADEON_MIN_MMIO_SIZE 0x10000
2482
9e5acbc2
DV		 2483uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2484void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
59bc1d89
LK		 2485static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2486 bool always_indirect)
2487{
2488 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2489 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2490 return readl(((void __iomem *)rdev->rmmio) + reg);
9e5acbc2
DV		 2491 else
2492 return r100_mm_rreg_slow(rdev, reg);
59bc1d89 2493}
59bc1d89
LK		 2494static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2495 bool always_indirect)
2496{
2497 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2498 writel(v, ((void __iomem *)rdev->rmmio) + reg);
9e5acbc2
DV		 2499 else
2500 r100_mm_wreg_slow(rdev, reg, v);
59bc1d89
LK		 2501}
2502
6fcbef7a
AK		 2503u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2504void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2505
d5754ab8
AL		 2506u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2507void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2508
4c788679
JG		 2509/*
2510 * Cast helper
2511 */
954605ca
ML		 2512extern const struct fence_ops radeon_fence_ops;
2513
2514static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2515{
2516 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2517
2518 if (__f->base.ops == &radeon_fence_ops)
2519 return __f;
2520
2521 return NULL;
2522}
771fe6b9
JG		 2523
2524/*
2525 * Registers read & write functions.
2526 */
a0533fbf
BH		 2527#define RREG8(reg) readb((rdev->rmmio) + (reg))
2528#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2529#define RREG16(reg) readw((rdev->rmmio) + (reg))
2530#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2531#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2532#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2533#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2534#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2535#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2536#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2537#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2538#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2539#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2540#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2541#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2542#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2543#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2544#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2545#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2546#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2547#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2548#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2549#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2550#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2551#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2552#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2553#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2554#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2555#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2556#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2557#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2558#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2559#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2560#define WREG32_P(reg, val, mask) \
2561 do { \
2562 uint32_t tmp_ = RREG32(reg); \
2563 tmp_ &= (mask); \
2564 tmp_ |= ((val) & ~(mask)); \
2565 WREG32(reg, tmp_); \
2566 } while (0)
d5169fc4 2567#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2568#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2569#define WREG32_PLL_P(reg, val, mask) \
2570 do { \
2571 uint32_t tmp_ = RREG32_PLL(reg); \
2572 tmp_ &= (mask); \
2573 tmp_ |= ((val) & ~(mask)); \
2574 WREG32_PLL(reg, tmp_); \
2575 } while (0)
b7af630c
CK		 2576#define WREG32_SMC_P(reg, val, mask) \
2577 do { \
2578 uint32_t tmp_ = RREG32_SMC(reg); \
2579 tmp_ &= (mask); \
2580 tmp_ |= ((val) & ~(mask)); \
2581 WREG32_SMC(reg, tmp_); \
2582 } while (0)
2ef9bdfe 2583#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2584#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2585#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2586
d5754ab8
AL		 2587#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2588#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2589
de1b2898 2590/*
9e5acbc2
DV		 2591 * Indirect registers accessors.
2592 * They used to be inlined, but this increases code size by ~65 kbytes.
2593 * Since each performs a pair of MMIO ops
2594 * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2595 * the cost of call+ret is almost negligible. MMIO and locking
2596 * costs several dozens of cycles each at best, call+ret is ~5 cycles.
de1b2898 2597 */
9e5acbc2
DV		 2598uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2599void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2600u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2601void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2602u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2603void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2604u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2605void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2606u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2607void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2608u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2609void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2610u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2611void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2612u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2613void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1d58234d 2614
771fe6b9
JG		 2615void r100_pll_errata_after_index(struct radeon_device *rdev);
2616
2617
2618/*
2619 * ASICs helpers.
2620 */
b995e433
DA		 2621#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2622 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2623#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2624 (rdev->family == CHIP_RV200) || \
2625 (rdev->family == CHIP_RS100) || \
2626 (rdev->family == CHIP_RS200) || \
2627 (rdev->family == CHIP_RV250) || \
2628 (rdev->family == CHIP_RV280) || \
2629 (rdev->family == CHIP_RS300))
2630#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2631 (rdev->family == CHIP_RV350) || \
2632 (rdev->family == CHIP_R350) || \
2633 (rdev->family == CHIP_RV380) || \
2634 (rdev->family == CHIP_R420) || \
2635 (rdev->family == CHIP_R423) || \
2636 (rdev->family == CHIP_RV410) || \
2637 (rdev->family == CHIP_RS400) || \
2638 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2639#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2640 (rdev->ddev->pdev->device == 0x9443) || \
2641 (rdev->ddev->pdev->device == 0x944B) || \
2642 (rdev->ddev->pdev->device == 0x9506) || \
2643 (rdev->ddev->pdev->device == 0x9509) || \
2644 (rdev->ddev->pdev->device == 0x950F) || \
2645 (rdev->ddev->pdev->device == 0x689C) || \
2646 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2647#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2648#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2649 (rdev->family == CHIP_RS690) || \
2650 (rdev->family == CHIP_RS740) || \
2651 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2652#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2653#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2654#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2655#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2656 (rdev->flags & RADEON_IS_IGP))
1fe18305 2657#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2658#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2659#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2660 (rdev->flags & RADEON_IS_IGP))
624d3524 2661#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2662#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2663#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
be0949f5
AD		 2664#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2665#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
89d2618d
AD		 2666#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2667 (rdev->family == CHIP_MULLINS))
771fe6b9 2668
dc50ba7f
AD		 2669#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2670 (rdev->ddev->pdev->device == 0x6850) || \
2671 (rdev->ddev->pdev->device == 0x6858) || \
2672 (rdev->ddev->pdev->device == 0x6859) || \
2673 (rdev->ddev->pdev->device == 0x6840) || \
2674 (rdev->ddev->pdev->device == 0x6841) || \
2675 (rdev->ddev->pdev->device == 0x6842) || \
2676 (rdev->ddev->pdev->device == 0x6843))
2677
771fe6b9
JG		 2678/*
2679 * BIOS helpers.
2680 */
2681#define RBIOS8(i) (rdev->bios[i])
2682#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2683#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2684
2685int radeon_combios_init(struct radeon_device *rdev);
2686void radeon_combios_fini(struct radeon_device *rdev);
2687int radeon_atombios_init(struct radeon_device *rdev);
2688void radeon_atombios_fini(struct radeon_device *rdev);
2689
2690
2691/*
2692 * RING helpers.
2693 */
edf0ac7c
DH		 2694
2695/**
2696 * radeon_ring_write - write a value to the ring
2697 *
2698 * @ring: radeon_ring structure holding ring information
2699 * @v: dword (dw) value to write
2700 *
2701 * Write a value to the requested ring buffer (all asics).
2702 */
e32eb50d 2703static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2704{
edf0ac7c
DH		 2705 if (ring->count_dw <= 0)
2706 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2707
e32eb50d
CK		 2708 ring->ring[ring->wptr++] = v;
2709 ring->wptr &= ring->ptr_mask;
2710 ring->count_dw--;
2711 ring->ring_free_dw--;
771fe6b9 2712}
771fe6b9
JG		 2713
2714/*
2715 * ASICs macro.
2716 */
068a117c 2717#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2718#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2719#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2720#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2721#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2722#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
71fe2899 2723#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
c5b3b850 2724#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
cb658906
MD		 2725#define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2726#define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
05b07147
CK		 2727#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2728#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
03f62abd
CK		 2729#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2730#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2731#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2732#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
76a0df85
CK		 2733#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2734#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2735#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2736#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2737#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2738#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
faffaf62 2739#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
76a0df85
CK		 2740#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2741#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2742#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2743#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2744#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2745#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2746#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2747#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2748#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2749#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2750#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2751#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
57d20a43
CK		 2752#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2753#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2754#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
27cd7769
AD		 2755#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2756#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2757#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2758#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2759#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2760#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2761#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2762#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2763#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2764#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2765#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
b59b7333 2766#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
6bd1c385 2767#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2768#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2769#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2770#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2771#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2772#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2773#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2774#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2775#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2776#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2777#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2778#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2779#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2780#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8 2781#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
157fa14d 2782#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
69b62ad8
AD		 2783#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2784#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2785#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2786#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
4ce4728b 2787#define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
da321c8a
AD		 2788#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2789#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2790#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2791#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2792#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2793#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2794#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2795#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2796#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2797#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2798#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2799#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2800#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2801#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2802#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2803#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2804#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2805#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
d7dbce09
AD		 2806#define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2807#define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
771fe6b9 2808
6cf8a3f5 2809/* Common functions */
700a0cc0 2810/* AGP */
90aca4d2 2811extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2812extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2813extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2814extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2815extern int radeon_modeset_init(struct radeon_device *rdev);
2816extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2817extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2818extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2819extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2820extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2821extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2822extern void radeon_wb_fini(struct radeon_device *rdev);
2823extern int radeon_wb_init(struct radeon_device *rdev);
2824extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2825extern void radeon_surface_init(struct radeon_device *rdev);
2826extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2827extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2828extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2829extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2830extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
f72a113a
CK		 2831extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2832 uint32_t flags);
2833extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2834extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
d594e46a
JG		 2835extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2836extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2837extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2838extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2839extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2840extern void radeon_program_register_sequence(struct radeon_device *rdev,
2841 const u32 *registers,
2842 const u32 array_size);
6cf8a3f5 2843
721604a1
JG		 2844/*
2845 * vm
2846 */
2847int radeon_vm_manager_init(struct radeon_device *rdev);
2848void radeon_vm_manager_fini(struct radeon_device *rdev);
6d2f2944 2849int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2850void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1d0c0942 2851struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
df0af440
CK		 2852 struct radeon_vm *vm,
2853 struct list_head *head);
ee60e29f
CK		 2854struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2855 struct radeon_vm *vm, int ring);
fa688343
CK		 2856void radeon_vm_flush(struct radeon_device *rdev,
2857 struct radeon_vm *vm,
ad1a58a4 2858 int ring, struct radeon_fence *fence);
ee60e29f
CK		 2859void radeon_vm_fence(struct radeon_device *rdev,
2860 struct radeon_vm *vm,
2861 struct radeon_fence *fence);
dce34bfd 2862uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
6d2f2944
CK		 2863int radeon_vm_update_page_directory(struct radeon_device *rdev,
2864 struct radeon_vm *vm);
036bf46a
CK		 2865int radeon_vm_clear_freed(struct radeon_device *rdev,
2866 struct radeon_vm *vm);
e31ad969
CK		 2867int radeon_vm_clear_invalids(struct radeon_device *rdev,
2868 struct radeon_vm *vm);
9c57a6bd 2869int radeon_vm_bo_update(struct radeon_device *rdev,
036bf46a 2870 struct radeon_bo_va *bo_va,
9c57a6bd 2871 struct ttm_mem_reg *mem);
721604a1
JG		 2872void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2873 struct radeon_bo *bo);
421ca7ab
CK		 2874struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2875 struct radeon_bo *bo);
e971bd5e
CK		 2876struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2877 struct radeon_vm *vm,
2878 struct radeon_bo *bo);
2879int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2880 struct radeon_bo_va *bo_va,
2881 uint64_t offset,
2882 uint32_t flags);
036bf46a
CK		 2883void radeon_vm_bo_rmv(struct radeon_device *rdev,
2884 struct radeon_bo_va *bo_va);
721604a1 2885
f122c610
AD		 2886/* audio */
2887void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2888struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2889struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
832eafaf
AD		 2890void r600_audio_enable(struct radeon_device *rdev,
2891 struct r600_audio_pin *pin,
d3d8c141 2892 u8 enable_mask);
832eafaf
AD		 2893void dce6_audio_enable(struct radeon_device *rdev,
2894 struct r600_audio_pin *pin,
d3d8c141 2895 u8 enable_mask);
721604a1 2896
16cdf04d
AD		 2897/*
2898 * R600 vram scratch functions
2899 */
2900int r600_vram_scratch_init(struct radeon_device *rdev);
2901void r600_vram_scratch_fini(struct radeon_device *rdev);
2902
285484e2
JG		 2903/*
2904 * r600 cs checking helper
2905 */
2906unsigned r600_mip_minify(unsigned size, unsigned level);
2907bool r600_fmt_is_valid_color(u32 format);
2908bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2909int r600_fmt_get_blocksize(u32 format);
2910int r600_fmt_get_nblocksx(u32 format, u32 w);
2911int r600_fmt_get_nblocksy(u32 format, u32 h);
2912
3574dda4
DV		 2913/*
2914 * r600 functions used by radeon_encoder.c
2915 */
1b688d08
RM		 2916struct radeon_hdmi_acr {
2917 u32 clock;
2918
2919 int n_32khz;
2920 int cts_32khz;
2921
2922 int n_44_1khz;
2923 int cts_44_1khz;
2924
2925 int n_48khz;
2926 int cts_48khz;
2927
2928};
2929
e55d3e6c
RM		 2930extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2931
416a2bd2
AD		 2932extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2933 u32 tiling_pipe_num,
2934 u32 max_rb_num,
2935 u32 total_max_rb_num,
2936 u32 enabled_rb_mask);
fe251e2f 2937
e55d3e6c
RM		 2938/*
2939 * evergreen functions used by radeon_encoder.c
2940 */
2941
0af62b01 2942extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2943extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2944
c4917074
AD		 2945/* radeon_acpi.c */
2946#if defined(CONFIG_ACPI)
2947extern int radeon_acpi_init(struct radeon_device *rdev);
2948extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2949extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2950extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2951 u8 perf_req, bool advertise);
dc50ba7f 2952extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2953#else
2954static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2955static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2956#endif
d7a2952f 2957
c38f34b5
IH		 2958int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2959 struct radeon_cs_packet *pkt,
2960 unsigned idx);
9ffb7a6d 2961bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2962void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2963 struct radeon_cs_packet *pkt);
e9716993 2964int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
1d0c0942 2965 struct radeon_bo_list **cs_reloc,
e9716993 2966 int nomm);
40592a17
IH		 2967int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2968 uint32_t *vline_start_end,
2969 uint32_t *vline_status);
c38f34b5 2970
4c788679
JG		 2971#include "radeon_object.h"
2972
771fe6b9 2973#endif
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