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drm/radeon: add driver option to disable uvd block.
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
0aea5e4a 67#include <linux/interval_tree.h>
341cb9e4 68#include <linux/hashtable.h>
954605ca 69#include <linux/fence.h>
771fe6b9 70
4c788679
JG		 71#include <ttm/ttm_bo_api.h>
72#include <ttm/ttm_bo_driver.h>
73#include <ttm/ttm_placement.h>
74#include <ttm/ttm_module.h>
147666fb 75#include <ttm/ttm_execbuf_util.h>
4c788679 76
d9fc9413
DV		 77#include <drm/drm_gem.h>
78
c2142715 79#include "radeon_family.h"
771fe6b9
JG		 80#include "radeon_mode.h"
81#include "radeon_reg.h"
771fe6b9
JG		 82
83/*
84 * Modules parameters.
85 */
86extern int radeon_no_wb;
87extern int radeon_modeset;
88extern int radeon_dynclks;
89extern int radeon_r4xx_atom;
90extern int radeon_agpmode;
91extern int radeon_vram_limit;
92extern int radeon_gart_size;
93extern int radeon_benchmarking;
ecc0b326 94extern int radeon_testing;
771fe6b9 95extern int radeon_connector_table;
4ce001ab 96extern int radeon_tv;
dafc3bd5 97extern int radeon_audio;
f46c0120 98extern int radeon_disp_priority;
e2b0a8e1 99extern int radeon_hw_i2c;
d42dd579 100extern int radeon_pcie_gen2;
a18cee15 101extern int radeon_msi;
3368ff0c 102extern int radeon_lockup_timeout;
a0a53aa8 103extern int radeon_fastfb;
da321c8a 104extern int radeon_dpm;
1294d4a3 105extern int radeon_aspm;
10ebc0bc 106extern int radeon_runtime_pm;
363eb0b4 107extern int radeon_hard_reset;
c1c44132 108extern int radeon_vm_size;
4510fb98 109extern int radeon_vm_block_size;
a624f429 110extern int radeon_deep_color;
39dc5454 111extern int radeon_use_pflipirq;
6e909f74 112extern int radeon_bapm;
bc13018b 113extern int radeon_backlight;
875711f0 114extern int radeon_auxch;
9843ead0 115extern int radeon_mst;
f1a0a67a 116extern int radeon_uvd;
771fe6b9
JG		 117
118/*
119 * Copy from radeon_drv.h so we don't have to include both and have conflicting
120 * symbol;
121 */
bb635567
JG		 122#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
123#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
04db4caf 124#define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */
e821767b 125/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 126#define RADEON_IB_POOL_SIZE 16
127#define RADEON_DEBUGFS_MAX_COMPONENTS 32
128#define RADEONFB_CONN_LIMIT 4
129#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 130
1b37078b
AD		 131/* internal ring indices */
132/* r1xx+ has gfx CP ring */
d93f7937 133#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 134
135/* cayman has 2 compute CP rings */
d93f7937
CK		 136#define CAYMAN_RING_TYPE_CP1_INDEX 1
137#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 138
4d75658b
AD		 139/* R600+ has an async dma ring */
140#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 141/* cayman add a second async dma ring */
142#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 143
f2ba57b5 144/* R600+ */
d93f7937
CK		 145#define R600_RING_TYPE_UVD_INDEX 5
146
147/* TN+ */
148#define TN_RING_TYPE_VCE1_INDEX 6
149#define TN_RING_TYPE_VCE2_INDEX 7
150
151/* max number of rings */
152#define RADEON_NUM_RINGS 8
f2ba57b5 153
1c61eae4
CK		 154/* number of hw syncs before falling back on blocking */
155#define RADEON_NUM_SYNCS 4
f2ba57b5 156
721604a1 157/* hardcode those limit for now */
ca19f21e 158#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 159#define RADEON_VA_RESERVED_SIZE (8 << 20)
160#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 161
1a0041b8
AD		 162/* hard reset data */
163#define RADEON_ASIC_RESET_DATA 0x39d5e86b
164
ec46c76d
AD		 165/* reset flags */
166#define RADEON_RESET_GFX (1 << 0)
167#define RADEON_RESET_COMPUTE (1 << 1)
168#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 169#define RADEON_RESET_CP (1 << 3)
170#define RADEON_RESET_GRBM (1 << 4)
171#define RADEON_RESET_DMA1 (1 << 5)
172#define RADEON_RESET_RLC (1 << 6)
173#define RADEON_RESET_SEM (1 << 7)
174#define RADEON_RESET_IH (1 << 8)
175#define RADEON_RESET_VMC (1 << 9)
176#define RADEON_RESET_MC (1 << 10)
177#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 178
22c775ce
AD		 179/* CG block flags */
180#define RADEON_CG_BLOCK_GFX (1 << 0)
181#define RADEON_CG_BLOCK_MC (1 << 1)
182#define RADEON_CG_BLOCK_SDMA (1 << 2)
183#define RADEON_CG_BLOCK_UVD (1 << 3)
184#define RADEON_CG_BLOCK_VCE (1 << 4)
185#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 186#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 187
64d8a728
AD		 188/* CG flags */
189#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
190#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
191#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
192#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
193#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
194#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
195#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
196#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
197#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
198#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
199#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
200#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
201#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
202#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
203#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
204#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
205#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
206
207/* PG flags */
2b19d17f 208#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 209#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
210#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
211#define RADEON_PG_SUPPORT_UVD (1 << 3)
212#define RADEON_PG_SUPPORT_VCE (1 << 4)
213#define RADEON_PG_SUPPORT_CP (1 << 5)
214#define RADEON_PG_SUPPORT_GDS (1 << 6)
215#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
216#define RADEON_PG_SUPPORT_SDMA (1 << 8)
217#define RADEON_PG_SUPPORT_ACP (1 << 9)
218#define RADEON_PG_SUPPORT_SAMU (1 << 10)
219
9e05fa1d
AD		 220/* max cursor sizes (in pixels) */
221#define CURSOR_WIDTH 64
222#define CURSOR_HEIGHT 64
223
224#define CIK_CURSOR_WIDTH 128
225#define CIK_CURSOR_HEIGHT 128
226
771fe6b9
JG		 227/*
228 * Errata workarounds.
229 */
230enum radeon_pll_errata {
231 CHIP_ERRATA_R300_CG = 0x00000001,
232 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
233 CHIP_ERRATA_PLL_DELAY = 0x00000004
234};
235
236
237struct radeon_device;
238
239
240/*
241 * BIOS.
242 */
243bool radeon_get_bios(struct radeon_device *rdev);
244
245/*
3ce0a23d 246 * Dummy page
771fe6b9 247 */
3ce0a23d 248struct radeon_dummy_page {
cb658906 249 uint64_t entry;
3ce0a23d
JG		 250 struct page *page;
251 dma_addr_t addr;
252};
253int radeon_dummy_page_init(struct radeon_device *rdev);
254void radeon_dummy_page_fini(struct radeon_device *rdev);
255
771fe6b9 256
3ce0a23d
JG		 257/*
258 * Clocks
259 */
771fe6b9
JG		 260struct radeon_clock {
261 struct radeon_pll p1pll;
262 struct radeon_pll p2pll;
bcc1c2a1 263 struct radeon_pll dcpll;
771fe6b9
JG		 264 struct radeon_pll spll;
265 struct radeon_pll mpll;
266 /* 10 Khz units */
267 uint32_t default_mclk;
268 uint32_t default_sclk;
bcc1c2a1 269 uint32_t default_dispclk;
4489cd62 270 uint32_t current_dispclk;
bcc1c2a1 271 uint32_t dp_extclk;
b20f9bef 272 uint32_t max_pixel_clock;
c9a392ea 273 uint32_t vco_freq;
771fe6b9
JG		 274};
275
7433874e
RM		 276/*
277 * Power management
278 */
279int radeon_pm_init(struct radeon_device *rdev);
914a8987 280int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 281void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 282void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 283void radeon_pm_suspend(struct radeon_device *rdev);
284void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 285void radeon_combios_get_power_modes(struct radeon_device *rdev);
286void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 287int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
288 u8 clock_type,
289 u32 clock,
290 bool strobe_mode,
291 struct atom_clock_dividers *dividers);
eaa778af
AD		 292int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
293 u32 clock,
294 bool strobe_mode,
295 struct atom_mpll_param *mpll_param);
8a83ec5e 296void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 297int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
298 u16 voltage_level, u8 voltage_type,
299 u32 *gpio_value, u32 *gpio_mask);
300void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
301 u32 eng_clock, u32 mem_clock);
302int radeon_atom_get_voltage_step(struct radeon_device *rdev,
303 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 304int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
305 u16 voltage_id, u16 *voltage);
beb79f40
AD		 306int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
307 u16 *voltage,
308 u16 leakage_idx);
cc8dbbb4
AD		 309int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
310 u16 *leakage_id);
311int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
312 u16 *vddc, u16 *vddci,
313 u16 virtual_voltage_id,
314 u16 vbios_voltage_id);
e9f274b2
AD		 315int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
316 u16 virtual_voltage_id,
317 u16 *voltage);
ae5b0abb
AD		 318int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
319 u8 voltage_type,
320 u16 nominal_voltage,
321 u16 *true_voltage);
322int radeon_atom_get_min_voltage(struct radeon_device *rdev,
323 u8 voltage_type, u16 *min_voltage);
324int radeon_atom_get_max_voltage(struct radeon_device *rdev,
325 u8 voltage_type, u16 *max_voltage);
326int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 327 u8 voltage_type, u8 voltage_mode,
ae5b0abb 328 struct atom_voltage_table *voltage_table);
58653abd
AD		 329bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
330 u8 voltage_type, u8 voltage_mode);
636e2582
AD		 331int radeon_atom_get_svi2_info(struct radeon_device *rdev,
332 u8 voltage_type,
333 u8 *svd_gpio_id, u8 *svc_gpio_id);
ae5b0abb
AD		 334void radeon_atom_update_memory_dll(struct radeon_device *rdev,
335 u32 mem_clock);
336void radeon_atom_set_ac_timing(struct radeon_device *rdev,
337 u32 mem_clock);
338int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
339 u8 module_index,
340 struct atom_mc_reg_table *reg_table);
341int radeon_atom_get_memory_info(struct radeon_device *rdev,
342 u8 module_index, struct atom_memory_info *mem_info);
343int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
344 bool gddr5, u8 module_index,
345 struct atom_memory_clock_range_table *mclk_range_table);
346int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
347 u16 voltage_id, u16 *voltage);
f892034a 348void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 349extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
350 unsigned *bankh, unsigned *mtaspect,
351 unsigned *tile_split);
3ce0a23d 352
771fe6b9
JG		 353/*
354 * Fences.
355 */
356struct radeon_fence_driver {
0bfa4b41 357 struct radeon_device *rdev;
771fe6b9 358 uint32_t scratch_reg;
30eb77f4
JG		 359 uint64_t gpu_addr;
360 volatile uint32_t *cpu_addr;
68e250b7
CK		 361 /* sync_seq is protected by ring emission lock */
362 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 363 atomic64_t last_seq;
954605ca 364 bool initialized, delayed_irq;
0bfa4b41 365 struct delayed_work lockup_work;
771fe6b9
JG		 366};
367
368struct radeon_fence {
ad1a58a4 369 struct fence base;
954605ca 370
ad1a58a4
CK		 371 struct radeon_device *rdev;
372 uint64_t seq;
7465280c 373 /* RB, DMA, etc. */
ad1a58a4
CK		 374 unsigned ring;
375 bool is_vm_update;
954605ca 376
ad1a58a4 377 wait_queue_t fence_wake;
771fe6b9
JG		 378};
379
30eb77f4
JG		 380int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
381int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 382void radeon_fence_driver_fini(struct radeon_device *rdev);
eb98c709 383void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
876dc9f3 384int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 385void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9 386bool radeon_fence_signaled(struct radeon_fence *fence);
04db4caf 387long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
771fe6b9 388int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
37615527
CK		 389int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
390int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
0085c950
JG		 391int radeon_fence_wait_any(struct radeon_device *rdev,
392 struct radeon_fence **fences,
393 bool intr);
771fe6b9
JG		 394struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
395void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 396unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 397bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
398void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
399static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
400 struct radeon_fence *b)
401{
402 if (!a) {
403 return b;
404 }
405
406 if (!b) {
407 return a;
408 }
409
410 BUG_ON(a->ring != b->ring);
411
412 if (a->seq > b->seq) {
413 return a;
414 } else {
415 return b;
416 }
417}
771fe6b9 418
ee60e29f
CK		 419static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
420 struct radeon_fence *b)
421{
422 if (!a) {
423 return false;
424 }
425
426 if (!b) {
427 return true;
428 }
429
430 BUG_ON(a->ring != b->ring);
431
432 return a->seq < b->seq;
433}
434
e024e110
DA		 435/*
436 * Tiling registers
437 */
438struct radeon_surface_reg {
4c788679 439 struct radeon_bo *bo;
e024e110
DA		 440};
441
442#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 443
444/*
4c788679 445 * TTM.
771fe6b9 446 */
4c788679
JG		 447struct radeon_mman {
448 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 449 struct drm_global_reference mem_global_ref;
4c788679 450 struct ttm_bo_device bdev;
0a0c7596
JG		 451 bool mem_global_referenced;
452 bool initialized;
2014b569
CK		 453
454#if defined(CONFIG_DEBUG_FS)
455 struct dentry *vram;
dd66d20e 456 struct dentry *gtt;
2014b569 457#endif
4c788679
JG		 458};
459
1d0c0942
CK		 460struct radeon_bo_list {
461 struct radeon_bo *robj;
462 struct ttm_validate_buffer tv;
463 uint64_t gpu_offset;
464 unsigned prefered_domains;
465 unsigned allowed_domains;
466 uint32_t tiling_flags;
467};
468
721604a1
JG		 469/* bo virtual address in a specific vm */
470struct radeon_bo_va {
e971bd5e 471 /* protected by bo being reserved */
721604a1 472 struct list_head bo_list;
721604a1 473 uint32_t flags;
94214635 474 struct radeon_fence *last_pt_update;
e971bd5e
CK		 475 unsigned ref_count;
476
477 /* protected by vm mutex */
0aea5e4a 478 struct interval_tree_node it;
036bf46a 479 struct list_head vm_status;
e971bd5e
CK		 480
481 /* constant after initialization */
482 struct radeon_vm *vm;
483 struct radeon_bo *bo;
721604a1
JG		 484};
485
4c788679
JG		 486struct radeon_bo {
487 /* Protected by gem.mutex */
488 struct list_head list;
489 /* Protected by tbo.reserved */
bda72d58 490 u32 initial_domain;
c9da4a4b 491 struct ttm_place placements[4];
312ea8da 492 struct ttm_placement placement;
4c788679
JG		 493 struct ttm_buffer_object tbo;
494 struct ttm_bo_kmap_obj kmap;
02376d82 495 u32 flags;
4c788679
JG		 496 unsigned pin_count;
497 void *kptr;
498 u32 tiling_flags;
499 u32 pitch;
500 int surface_reg;
721604a1
JG		 501 /* list of all virtual address to which this bo
502 * is associated to
503 */
504 struct list_head va;
4c788679
JG		 505 /* Constant after initialization */
506 struct radeon_device *rdev;
441921d5 507 struct drm_gem_object gem_base;
63bc620b 508
409851f4
JG		 509 struct ttm_bo_kmap_obj dma_buf_vmap;
510 pid_t pid;
341cb9e4
CK		 511
512 struct radeon_mn *mn;
49ecb10e 513 struct list_head mn_list;
4c788679 514};
7e4d15d9 515#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 516
409851f4
JG		 517int radeon_gem_debugfs_init(struct radeon_device *rdev);
518
b15ba512
JG		 519/* sub-allocation manager, it has to be protected by another lock.
520 * By conception this is an helper for other part of the driver
521 * like the indirect buffer or semaphore, which both have their
522 * locking.
523 *
524 * Principe is simple, we keep a list of sub allocation in offset
525 * order (first entry has offset == 0, last entry has the highest
526 * offset).
527 *
528 * When allocating new object we first check if there is room at
529 * the end total_size - (last_object_offset + last_object_size) >=
530 * alloc_size. If so we allocate new object there.
531 *
532 * When there is not enough room at the end, we start waiting for
533 * each sub object until we reach object_offset+object_size >=
534 * alloc_size, this object then become the sub object we return.
535 *
536 * Alignment can't be bigger than page size.
537 *
538 * Hole are not considered for allocation to keep things simple.
539 * Assumption is that there won't be hole (all object on same
540 * alignment).
541 */
542struct radeon_sa_manager {
bfb38d35 543 wait_queue_head_t wq;
b15ba512 544 struct radeon_bo *bo;
c3b7fe8b
CK		 545 struct list_head *hole;
546 struct list_head flist[RADEON_NUM_RINGS];
547 struct list_head olist;
b15ba512
JG		 548 unsigned size;
549 uint64_t gpu_addr;
550 void *cpu_ptr;
551 uint32_t domain;
6c4f978b 552 uint32_t align;
b15ba512
JG		 553};
554
555struct radeon_sa_bo;
556
557/* sub-allocation buffer */
558struct radeon_sa_bo {
c3b7fe8b
CK		 559 struct list_head olist;
560 struct list_head flist;
b15ba512 561 struct radeon_sa_manager *manager;
e6661a96
CK		 562 unsigned soffset;
563 unsigned eoffset;
557017a0 564 struct radeon_fence *fence;
b15ba512
JG		 565};
566
771fe6b9
JG		 567/*
568 * GEM objects.
569 */
570struct radeon_gem {
4c788679 571 struct mutex mutex;
771fe6b9
JG		 572 struct list_head objects;
573};
574
575int radeon_gem_init(struct radeon_device *rdev);
576void radeon_gem_fini(struct radeon_device *rdev);
391bfec3 577int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
4c788679 578 int alignment, int initial_domain,
ed5cb43f 579 u32 flags, bool kernel,
4c788679 580 struct drm_gem_object **obj);
771fe6b9 581
ff72145b
DA		 582int radeon_mode_dumb_create(struct drm_file *file_priv,
583 struct drm_device *dev,
584 struct drm_mode_create_dumb *args);
585int radeon_mode_dumb_mmap(struct drm_file *filp,
586 struct drm_device *dev,
587 uint32_t handle, uint64_t *offset_p);
771fe6b9 588
c1341e52
JG		 589/*
590 * Semaphores.
591 */
c1341e52 592struct radeon_semaphore {
975700d2
CK		 593 struct radeon_sa_bo *sa_bo;
594 signed waiters;
595 uint64_t gpu_addr;
c1341e52
JG		 596};
597
c1341e52
JG		 598int radeon_semaphore_create(struct radeon_device *rdev,
599 struct radeon_semaphore **semaphore);
1654b817 600bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 601 struct radeon_semaphore *semaphore);
1654b817 602bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52
JG		 603 struct radeon_semaphore *semaphore);
604void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 605 struct radeon_semaphore **semaphore,
a8c05940 606 struct radeon_fence *fence);
c1341e52 607
975700d2
CK		 608/*
609 * Synchronization
610 */
611struct radeon_sync {
612 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
613 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
ad1a58a4 614 struct radeon_fence *last_vm_update;
975700d2
CK		 615};
616
617void radeon_sync_create(struct radeon_sync *sync);
618void radeon_sync_fence(struct radeon_sync *sync,
619 struct radeon_fence *fence);
620int radeon_sync_resv(struct radeon_device *rdev,
621 struct radeon_sync *sync,
622 struct reservation_object *resv,
623 bool shared);
624int radeon_sync_rings(struct radeon_device *rdev,
625 struct radeon_sync *sync,
626 int waiting_ring);
627void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
628 struct radeon_fence *fence);
629
771fe6b9
JG		 630/*
631 * GART structures, functions & helpers
632 */
633struct radeon_mc;
634
a77f1718 635#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 636#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 637#define RADEON_GPU_PAGE_SHIFT 12
721604a1 638#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 639
77497f27
MD		 640#define RADEON_GART_PAGE_DUMMY 0
641#define RADEON_GART_PAGE_VALID (1 << 0)
642#define RADEON_GART_PAGE_READ (1 << 1)
643#define RADEON_GART_PAGE_WRITE (1 << 2)
644#define RADEON_GART_PAGE_SNOOP (1 << 3)
645
771fe6b9
JG		 646struct radeon_gart {
647 dma_addr_t table_addr;
c9a1be96
JG		 648 struct radeon_bo *robj;
649 void *ptr;
771fe6b9
JG		 650 unsigned num_gpu_pages;
651 unsigned num_cpu_pages;
652 unsigned table_size;
771fe6b9 653 struct page **pages;
cb658906 654 uint64_t *pages_entry;
771fe6b9
JG		 655 bool ready;
656};
657
658int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
659void radeon_gart_table_ram_free(struct radeon_device *rdev);
660int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
661void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 662int radeon_gart_table_vram_pin(struct radeon_device *rdev);
663void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 664int radeon_gart_init(struct radeon_device *rdev);
665void radeon_gart_fini(struct radeon_device *rdev);
666void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
667 int pages);
668int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516 669 int pages, struct page **pagelist,
77497f27 670 dma_addr_t *dma_addr, uint32_t flags);
771fe6b9
JG		 671
672
673/*
674 * GPU MC structures, functions & helpers
675 */
676struct radeon_mc {
677 resource_size_t aper_size;
678 resource_size_t aper_base;
679 resource_size_t agp_base;
7a50f01a
DA		 680 /* for some chips with <= 32MB we need to lie
681 * about vram size near mc fb location */
3ce0a23d 682 u64 mc_vram_size;
d594e46a 683 u64 visible_vram_size;
3ce0a23d
JG		 684 u64 gtt_size;
685 u64 gtt_start;
686 u64 gtt_end;
3ce0a23d
JG		 687 u64 vram_start;
688 u64 vram_end;
771fe6b9 689 unsigned vram_width;
3ce0a23d 690 u64 real_vram_size;
771fe6b9
JG		 691 int vram_mtrr;
692 bool vram_is_ddr;
d594e46a 693 bool igp_sideport_enabled;
8d369bb1 694 u64 gtt_base_align;
9ed8b1f9 695 u64 mc_mask;
771fe6b9
JG		 696};
697
06b6476d
AD		 698bool radeon_combios_sideport_present(struct radeon_device *rdev);
699bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 700
701/*
702 * GPU scratch registers structures, functions & helpers
703 */
704struct radeon_scratch {
705 unsigned num_reg;
724c80e1 706 uint32_t reg_base;
771fe6b9
JG		 707 bool free[32];
708 uint32_t reg[32];
709};
710
711int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
712void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
713
75efdee1
AD		 714/*
715 * GPU doorbell structures, functions & helpers
716 */
d5754ab8
AL		 717#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
718
75efdee1 719struct radeon_doorbell {
75efdee1 720 /* doorbell mmio */
d5754ab8
AL		 721 resource_size_t base;
722 resource_size_t size;
723 u32 __iomem *ptr;
724 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
a10e04f4 725 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
75efdee1
AD		 726};
727
728int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
729void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
ebff8453
OG		 730void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
731 phys_addr_t *aperture_base,
732 size_t *aperture_size,
733 size_t *start_offset);
771fe6b9
JG		 734
735/*
736 * IRQS.
737 */
6f34be50 738
fa7f517c
CK		 739struct radeon_flip_work {
740 struct work_struct flip_work;
741 struct work_struct unpin_work;
742 struct radeon_device *rdev;
743 int crtc_id;
c60381bd 744 uint64_t base;
6f34be50 745 struct drm_pending_vblank_event *event;
fa7f517c 746 struct radeon_bo *old_rbo;
a0e84764 747 struct fence *fence;
6f34be50
AD		 748};
749
750struct r500_irq_stat_regs {
751 u32 disp_int;
f122c610 752 u32 hdmi0_status;
6f34be50
AD		 753};
754
755struct r600_irq_stat_regs {
756 u32 disp_int;
757 u32 disp_int_cont;
758 u32 disp_int_cont2;
759 u32 d1grph_int;
760 u32 d2grph_int;
f122c610
AD		 761 u32 hdmi0_status;
762 u32 hdmi1_status;
6f34be50
AD		 763};
764
765struct evergreen_irq_stat_regs {
766 u32 disp_int;
767 u32 disp_int_cont;
768 u32 disp_int_cont2;
769 u32 disp_int_cont3;
770 u32 disp_int_cont4;
771 u32 disp_int_cont5;
772 u32 d1grph_int;
773 u32 d2grph_int;
774 u32 d3grph_int;
775 u32 d4grph_int;
776 u32 d5grph_int;
777 u32 d6grph_int;
f122c610
AD		 778 u32 afmt_status1;
779 u32 afmt_status2;
780 u32 afmt_status3;
781 u32 afmt_status4;
782 u32 afmt_status5;
783 u32 afmt_status6;
6f34be50
AD		 784};
785
a59781bb
AD		 786struct cik_irq_stat_regs {
787 u32 disp_int;
788 u32 disp_int_cont;
789 u32 disp_int_cont2;
790 u32 disp_int_cont3;
791 u32 disp_int_cont4;
792 u32 disp_int_cont5;
793 u32 disp_int_cont6;
f5d636d2
CK		 794 u32 d1grph_int;
795 u32 d2grph_int;
796 u32 d3grph_int;
797 u32 d4grph_int;
798 u32 d5grph_int;
799 u32 d6grph_int;
a59781bb
AD		 800};
801
6f34be50
AD		 802union radeon_irq_stat_regs {
803 struct r500_irq_stat_regs r500;
804 struct r600_irq_stat_regs r600;
805 struct evergreen_irq_stat_regs evergreen;
a59781bb 806 struct cik_irq_stat_regs cik;
6f34be50
AD		 807};
808
771fe6b9 809struct radeon_irq {
fb98257a
CK		 810 bool installed;
811 spinlock_t lock;
736fc37f 812 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 813 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 814 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 815 wait_queue_head_t vblank_queue;
816 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 817 bool afmt[RADEON_MAX_AFMT_BLOCKS];
818 union radeon_irq_stat_regs stat_regs;
4a6369e9 819 bool dpm_thermal;
771fe6b9
JG		 820};
821
822int radeon_irq_kms_init(struct radeon_device *rdev);
823void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b 824void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
954605ca 825bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
1b37078b 826void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 827void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
828void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 829void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
830void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
831void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
832void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 833
834/*
e32eb50d 835 * CP & rings.
771fe6b9 836 */
7465280c 837
771fe6b9 838struct radeon_ib {
68470ae7
JG		 839 struct radeon_sa_bo *sa_bo;
840 uint32_t length_dw;
841 uint64_t gpu_addr;
842 uint32_t *ptr;
876dc9f3 843 int ring;
68470ae7 844 struct radeon_fence *fence;
4bf3dd92 845 struct radeon_vm *vm;
68470ae7 846 bool is_const_ib;
975700d2 847 struct radeon_sync sync;
771fe6b9
JG		 848};
849
e32eb50d 850struct radeon_ring {
4c788679 851 struct radeon_bo *ring_obj;
771fe6b9 852 volatile uint32_t *ring;
5596a9db 853 unsigned rptr_offs;
45df6803 854 unsigned rptr_save_reg;
89d35807
AD		 855 u64 next_rptr_gpu_addr;
856 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 857 unsigned wptr;
858 unsigned wptr_old;
859 unsigned ring_size;
860 unsigned ring_free_dw;
861 int count_dw;
aee4aa73
CK		 862 atomic_t last_rptr;
863 atomic64_t last_activity;
771fe6b9
JG		 864 uint64_t gpu_addr;
865 uint32_t align_mask;
866 uint32_t ptr_mask;
771fe6b9 867 bool ready;
78c5560a 868 u32 nop;
8b25ed34 869 u32 idx;
5f0839c1
JG		 870 u64 last_semaphore_signal_addr;
871 u64 last_semaphore_wait_addr;
963e81f9
AD		 872 /* for CIK queues */
873 u32 me;
874 u32 pipe;
875 u32 queue;
876 struct radeon_bo *mqd_obj;
d5754ab8 877 u32 doorbell_index;
963e81f9
AD		 878 unsigned wptr_offs;
879};
880
881struct radeon_mec {
882 struct radeon_bo *hpd_eop_obj;
883 u64 hpd_eop_gpu_addr;
884 u32 num_pipe;
885 u32 num_mec;
886 u32 num_queue;
771fe6b9
JG		 887};
888
721604a1
JG		 889/*
890 * VM
891 */
ee60e29f 892
fa87e62d 893/* maximum number of VMIDs */
ee60e29f
CK		 894#define RADEON_NUM_VM 16
895
fa87e62d 896/* number of entries in page table */
4510fb98 897#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
fa87e62d 898
1c01103c
AD		 899/* PTBs (Page Table Blocks) need to be aligned to 32K */
900#define RADEON_VM_PTB_ALIGN_SIZE 32768
901#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
902#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
903
24c16439
CK		 904#define R600_PTE_VALID (1 << 0)
905#define R600_PTE_SYSTEM (1 << 1)
906#define R600_PTE_SNOOPED (1 << 2)
907#define R600_PTE_READABLE (1 << 5)
908#define R600_PTE_WRITEABLE (1 << 6)
909
ec3dbbcb
CK		 910/* PTE (Page Table Entry) fragment field for different page sizes */
911#define R600_PTE_FRAG_4KB (0 << 7)
912#define R600_PTE_FRAG_64KB (4 << 7)
913#define R600_PTE_FRAG_256KB (6 << 7)
914
33fa9fe3
CK		 915/* flags needed to be set so we can copy directly from the GART table */
916#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
917 R600_PTE_SYSTEM | R600_PTE_VALID )
0e97703c 918
6d2f2944
CK		 919struct radeon_vm_pt {
920 struct radeon_bo *bo;
921 uint64_t addr;
922};
923
7c42bc1a
CK		 924struct radeon_vm_id {
925 unsigned id;
926 uint64_t pd_gpu_addr;
927 /* last flushed PD/PT update */
928 struct radeon_fence *flushed_updates;
929 /* last use of vmid */
930 struct radeon_fence *last_id_use;
931};
932
721604a1 933struct radeon_vm {
94214635
CK		 934 struct mutex mutex;
935
7c42bc1a 936 struct rb_root va;
90a51a32 937
f7a3db75
CK		 938 /* protecting invalidated and freed */
939 spinlock_t status_lock;
940
e31ad969 941 /* BOs moved, but not yet updated in the PT */
7c42bc1a 942 struct list_head invalidated;
e31ad969 943
036bf46a 944 /* BOs freed, but not yet updated in the PT */
7c42bc1a 945 struct list_head freed;
036bf46a 946
161ab658
CK		 947 /* BOs cleared in the PT */
948 struct list_head cleared;
949
90a51a32 950 /* contains the page directory */
7c42bc1a
CK		 951 struct radeon_bo *page_directory;
952 unsigned max_pde_used;
90a51a32
CK		 953
954 /* array of page tables, one for each page directory entry */
7c42bc1a 955 struct radeon_vm_pt *page_tables;
90a51a32 956
7c42bc1a 957 struct radeon_bo_va *ib_bo_va;
cc9e67e3 958
7c42bc1a
CK		 959 /* for id and flush management per ring */
960 struct radeon_vm_id ids[RADEON_NUM_RINGS];
721604a1
JG		 961};
962
721604a1 963struct radeon_vm_manager {
ee60e29f 964 struct radeon_fence *active[RADEON_NUM_VM];
721604a1 965 uint32_t max_pfn;
721604a1
JG		 966 /* number of VMIDs */
967 unsigned nvm;
968 /* vram base address for page table entry */
969 u64 vram_base_offset;
67e915e4
AD		 970 /* is vm enabled? */
971 bool enabled;
054e01d6
CK		 972 /* for hw to save the PD addr on suspend/resume */
973 uint32_t saved_table_addr[RADEON_NUM_VM];
721604a1
JG		 974};
975
976/*
977 * file private structure
978 */
979struct radeon_fpriv {
980 struct radeon_vm vm;
981};
982
d8f60cfc
AD		 983/*
984 * R6xx+ IH ring
985 */
986struct r600_ih {
4c788679 987 struct radeon_bo *ring_obj;
d8f60cfc
AD		 988 volatile uint32_t *ring;
989 unsigned rptr;
d8f60cfc
AD		 990 unsigned ring_size;
991 uint64_t gpu_addr;
d8f60cfc 992 uint32_t ptr_mask;
c20dc369 993 atomic_t lock;
d8f60cfc
AD		 994 bool enabled;
995};
996
347e7592 997/*
2948f5e6 998 * RLC stuff
347e7592 999 */
2948f5e6
AD		 1000#include "clearstate_defs.h"
1001
1002struct radeon_rlc {
347e7592
AD		 1003 /* for power gating */
1004 struct radeon_bo *save_restore_obj;
1005 uint64_t save_restore_gpu_addr;
2948f5e6 1006 volatile uint32_t *sr_ptr;
1fd11777 1007 const u32 *reg_list;
2948f5e6 1008 u32 reg_list_size;
347e7592
AD		 1009 /* for clear state */
1010 struct radeon_bo *clear_state_obj;
1011 uint64_t clear_state_gpu_addr;
2948f5e6 1012 volatile uint32_t *cs_ptr;
1fd11777 1013 const struct cs_section_def *cs_data;
22c775ce
AD		 1014 u32 clear_state_size;
1015 /* for cp tables */
1016 struct radeon_bo *cp_table_obj;
1017 uint64_t cp_table_gpu_addr;
1018 volatile uint32_t *cp_table_ptr;
1019 u32 cp_table_size;
347e7592
AD		 1020};
1021
69e130a6 1022int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 1023 struct radeon_ib *ib, struct radeon_vm *vm,
1024 unsigned size);
f2e39221 1025void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566 1026int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1538a9e0 1027 struct radeon_ib *const_ib, bool hdp_flush);
771fe6b9
JG		 1028int radeon_ib_pool_init(struct radeon_device *rdev);
1029void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 1030int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 1031/* Ring access between begin & end cannot sleep */
89d35807
AD		 1032bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1033 struct radeon_ring *ring);
e32eb50d
CK		 1034void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1035int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1036int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1538a9e0
MD		 1037void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1038 bool hdp_flush);
1039void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1040 bool hdp_flush);
d6999bc7 1041void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 1042void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1043int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
ff212f25
CK		 1044void radeon_ring_lockup_update(struct radeon_device *rdev,
1045 struct radeon_ring *ring);
069211e5 1046bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 1047unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1048 uint32_t **data);
1049int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1050 unsigned size, uint32_t *data);
e32eb50d 1051int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 1052 unsigned rptr_offs, u32 nop);
e32eb50d 1053void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 1054
1055
4d75658b
AD		 1056/* r600 async dma */
1057void r600_dma_stop(struct radeon_device *rdev);
1058int r600_dma_resume(struct radeon_device *rdev);
1059void r600_dma_fini(struct radeon_device *rdev);
1060
8c5fd7ef
AD		 1061void cayman_dma_stop(struct radeon_device *rdev);
1062int cayman_dma_resume(struct radeon_device *rdev);
1063void cayman_dma_fini(struct radeon_device *rdev);
1064
771fe6b9
JG		 1065/*
1066 * CS.
1067 */
771fe6b9 1068struct radeon_cs_chunk {
771fe6b9
JG		 1069 uint32_t length_dw;
1070 uint32_t *kdata;
721604a1 1071 void __user *user_ptr;
771fe6b9
JG		 1072};
1073
1074struct radeon_cs_parser {
c8c15ff1 1075 struct device *dev;
771fe6b9
JG		 1076 struct radeon_device *rdev;
1077 struct drm_file *filp;
1078 /* chunks */
1079 unsigned nchunks;
1080 struct radeon_cs_chunk *chunks;
1081 uint64_t *chunks_array;
1082 /* IB */
1083 unsigned idx;
1084 /* relocations */
1085 unsigned nrelocs;
1d0c0942 1086 struct radeon_bo_list *relocs;
1d0c0942 1087 struct radeon_bo_list *vm_bos;
771fe6b9 1088 struct list_head validated;
cf4ccd01 1089 unsigned dma_reloc_idx;
771fe6b9 1090 /* indices of various chunks */
6d2d13dd
CK		 1091 struct radeon_cs_chunk *chunk_ib;
1092 struct radeon_cs_chunk *chunk_relocs;
1093 struct radeon_cs_chunk *chunk_flags;
1094 struct radeon_cs_chunk *chunk_const_ib;
f2e39221
JG		 1095 struct radeon_ib ib;
1096 struct radeon_ib const_ib;
771fe6b9 1097 void *track;
3ce0a23d 1098 unsigned family;
e70f224c 1099 int parser_error;
721604a1
JG		 1100 u32 cs_flags;
1101 u32 ring;
1102 s32 priority;
ecff665f 1103 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1104};
1105
28a326c5
ML		 1106static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1107{
6d2d13dd 1108 struct radeon_cs_chunk *ibc = p->chunk_ib;
28a326c5
ML		 1109
1110 if (ibc->kdata)
1111 return ibc->kdata[idx];
1112 return p->ib.ptr[idx];
1113}
1114
513bcb46 1115
771fe6b9
JG		 1116struct radeon_cs_packet {
1117 unsigned idx;
1118 unsigned type;
1119 unsigned reg;
1120 unsigned opcode;
1121 int count;
1122 unsigned one_reg_wr;
1123};
1124
1125typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1126 struct radeon_cs_packet *pkt,
1127 unsigned idx, unsigned reg);
1128typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1129 struct radeon_cs_packet *pkt);
1130
1131
1132/*
1133 * AGP
1134 */
1135int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1136void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1137void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1138void radeon_agp_fini(struct radeon_device *rdev);
1139
1140
1141/*
1142 * Writeback
1143 */
1144struct radeon_wb {
4c788679 1145 struct radeon_bo *wb_obj;
771fe6b9
JG		 1146 volatile uint32_t *wb;
1147 uint64_t gpu_addr;
724c80e1 1148 bool enabled;
d0f8a854 1149 bool use_event;
771fe6b9
JG		 1150};
1151
724c80e1 1152#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1153#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1154#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1155#define RADEON_WB_CP1_RPTR_OFFSET 1280
1156#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1157#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1158#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1159#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1160#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1161#define CIK_WB_CP1_WPTR_OFFSET 3328
1162#define CIK_WB_CP2_WPTR_OFFSET 3584
adfed2b0
AD		 1163#define R600_WB_DMA_RING_TEST_OFFSET 3588
1164#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
724c80e1 1165
c93bb85b
JG		 1166/**
1167 * struct radeon_pm - power management datas
1168 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1169 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1170 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1171 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1172 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1173 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1174 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1175 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1176 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1177 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1178 * @needed_bandwidth: current bandwidth needs
1179 *
1180 * It keeps track of various data needed to take powermanagement decision.
25985edc 1181 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1182 * Equation between gpu/memory clock and available bandwidth is hw dependent
1183 * (type of memory, bus size, efficiency, ...)
1184 */
ce8f5370
AD		 1185
1186enum radeon_pm_method {
1187 PM_METHOD_PROFILE,
1188 PM_METHOD_DYNPM,
da321c8a 1189 PM_METHOD_DPM,
ce8f5370
AD		 1190};
1191
1192enum radeon_dynpm_state {
1193 DYNPM_STATE_DISABLED,
1194 DYNPM_STATE_MINIMUM,
1195 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1196 DYNPM_STATE_ACTIVE,
1197 DYNPM_STATE_SUSPENDED,
c913e23a 1198};
ce8f5370
AD		 1199enum radeon_dynpm_action {
1200 DYNPM_ACTION_NONE,
1201 DYNPM_ACTION_MINIMUM,
1202 DYNPM_ACTION_DOWNCLOCK,
1203 DYNPM_ACTION_UPCLOCK,
1204 DYNPM_ACTION_DEFAULT
c913e23a 1205};
56278a8e
AD		 1206
1207enum radeon_voltage_type {
1208 VOLTAGE_NONE = 0,
1209 VOLTAGE_GPIO,
1210 VOLTAGE_VDDC,
1211 VOLTAGE_SW
1212};
1213
0ec0e74f 1214enum radeon_pm_state_type {
da321c8a 1215 /* not used for dpm */
0ec0e74f
AD		 1216 POWER_STATE_TYPE_DEFAULT,
1217 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1218 /* user selectable states */
0ec0e74f
AD		 1219 POWER_STATE_TYPE_BATTERY,
1220 POWER_STATE_TYPE_BALANCED,
1221 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1222 /* internal states */
1223 POWER_STATE_TYPE_INTERNAL_UVD,
1224 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1225 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1226 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1227 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1228 POWER_STATE_TYPE_INTERNAL_BOOT,
1229 POWER_STATE_TYPE_INTERNAL_THERMAL,
1230 POWER_STATE_TYPE_INTERNAL_ACPI,
1231 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1232 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1233};
1234
ce8f5370
AD		 1235enum radeon_pm_profile_type {
1236 PM_PROFILE_DEFAULT,
1237 PM_PROFILE_AUTO,
1238 PM_PROFILE_LOW,
c9e75b21 1239 PM_PROFILE_MID,
ce8f5370
AD		 1240 PM_PROFILE_HIGH,
1241};
1242
1243#define PM_PROFILE_DEFAULT_IDX 0
1244#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1245#define PM_PROFILE_MID_SH_IDX 2
1246#define PM_PROFILE_HIGH_SH_IDX 3
1247#define PM_PROFILE_LOW_MH_IDX 4
1248#define PM_PROFILE_MID_MH_IDX 5
1249#define PM_PROFILE_HIGH_MH_IDX 6
1250#define PM_PROFILE_MAX 7
ce8f5370
AD		 1251
1252struct radeon_pm_profile {
1253 int dpms_off_ps_idx;
1254 int dpms_on_ps_idx;
1255 int dpms_off_cm_idx;
1256 int dpms_on_cm_idx;
516d0e46
AD		 1257};
1258
21a8122a
AD		 1259enum radeon_int_thermal_type {
1260 THERMAL_TYPE_NONE,
da321c8a
AD		 1261 THERMAL_TYPE_EXTERNAL,
1262 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1263 THERMAL_TYPE_RV6XX,
1264 THERMAL_TYPE_RV770,
da321c8a 1265 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1266 THERMAL_TYPE_EVERGREEN,
e33df25f 1267 THERMAL_TYPE_SUMO,
4fddba1f 1268 THERMAL_TYPE_NI,
14607d08 1269 THERMAL_TYPE_SI,
da321c8a 1270 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1271 THERMAL_TYPE_CI,
16fbe00d 1272 THERMAL_TYPE_KV,
21a8122a
AD		 1273};
1274
56278a8e
AD		 1275struct radeon_voltage {
1276 enum radeon_voltage_type type;
1277 /* gpio voltage */
1278 struct radeon_gpio_rec gpio;
1279 u32 delay; /* delay in usec from voltage drop to sclk change */
1280 bool active_high; /* voltage drop is active when bit is high */
1281 /* VDDC voltage */
1282 u8 vddc_id; /* index into vddc voltage table */
1283 u8 vddci_id; /* index into vddci voltage table */
1284 bool vddci_enabled;
1285 /* r6xx+ sw */
2feea49a
AD		 1286 u16 voltage;
1287 /* evergreen+ vddci */
1288 u16 vddci;
56278a8e
AD		 1289};
1290
d7311171
AD		 1291/* clock mode flags */
1292#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1293
56278a8e
AD		 1294struct radeon_pm_clock_info {
1295 /* memory clock */
1296 u32 mclk;
1297 /* engine clock */
1298 u32 sclk;
1299 /* voltage info */
1300 struct radeon_voltage voltage;
d7311171 1301 /* standardized clock flags */
56278a8e
AD		 1302 u32 flags;
1303};
1304
a48b9b4e 1305/* state flags */
d7311171 1306#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1307
56278a8e 1308struct radeon_power_state {
0ec0e74f 1309 enum radeon_pm_state_type type;
8f3f1c9a 1310 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1311 /* number of valid clock modes in this power state */
1312 int num_clock_modes;
56278a8e 1313 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1314 /* standardized state flags */
1315 u32 flags;
79daedc9
AD		 1316 u32 misc; /* vbios specific flags */
1317 u32 misc2; /* vbios specific flags */
1318 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1319};
1320
27459324
RM		 1321/*
1322 * Some modes are overclocked by very low value, accept them
1323 */
1324#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1325
2e9d4c05
AD		 1326enum radeon_dpm_auto_throttle_src {
1327 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1328 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1329};
1330
1331enum radeon_dpm_event_src {
1332 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1333 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1334 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1335 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1336 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1337};
1338
58bd2a88
AD		 1339#define RADEON_MAX_VCE_LEVELS 6
1340
b62d628b
AD		 1341enum radeon_vce_level {
1342 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1343 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1344 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1345 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1346 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1347 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1348};
1349
da321c8a
AD		 1350struct radeon_ps {
1351 u32 caps; /* vbios flags */
1352 u32 class; /* vbios flags */
1353 u32 class2; /* vbios flags */
1354 /* UVD clocks */
1355 u32 vclk;
1356 u32 dclk;
c4453e66
AD		 1357 /* VCE clocks */
1358 u32 evclk;
1359 u32 ecclk;
b62d628b
AD		 1360 bool vce_active;
1361 enum radeon_vce_level vce_level;
da321c8a
AD		 1362 /* asic priv */
1363 void *ps_priv;
1364};
1365
1366struct radeon_dpm_thermal {
1367 /* thermal interrupt work */
1368 struct work_struct work;
1369 /* low temperature threshold */
1370 int min_temp;
1371 /* high temperature threshold */
1372 int max_temp;
1373 /* was interrupt low to high or high to low */
1374 bool high_to_low;
1375};
1376
d22b7e40
AD		 1377enum radeon_clk_action
1378{
1379 RADEON_SCLK_UP = 1,
1380 RADEON_SCLK_DOWN
1381};
1382
1383struct radeon_blacklist_clocks
1384{
1385 u32 sclk;
1386 u32 mclk;
1387 enum radeon_clk_action action;
1388};
1389
61b7d601
AD		 1390struct radeon_clock_and_voltage_limits {
1391 u32 sclk;
1392 u32 mclk;
cdf6e805
AD		 1393 u16 vddc;
1394 u16 vddci;
61b7d601
AD		 1395};
1396
1397struct radeon_clock_array {
1398 u32 count;
1399 u32 *values;
1400};
1401
1402struct radeon_clock_voltage_dependency_entry {
1403 u32 clk;
1404 u16 v;
1405};
1406
1407struct radeon_clock_voltage_dependency_table {
1408 u32 count;
1409 struct radeon_clock_voltage_dependency_entry *entries;
1410};
1411
ef976ec4
AD		 1412union radeon_cac_leakage_entry {
1413 struct {
1414 u16 vddc;
1415 u32 leakage;
1416 };
1417 struct {
1418 u16 vddc1;
1419 u16 vddc2;
1420 u16 vddc3;
1421 };
61b7d601
AD		 1422};
1423
1424struct radeon_cac_leakage_table {
1425 u32 count;
ef976ec4 1426 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1427};
1428
929ee7a8
AD		 1429struct radeon_phase_shedding_limits_entry {
1430 u16 voltage;
1431 u32 sclk;
1432 u32 mclk;
1433};
1434
1435struct radeon_phase_shedding_limits_table {
1436 u32 count;
1437 struct radeon_phase_shedding_limits_entry *entries;
1438};
1439
84a9d9ee
AD		 1440struct radeon_uvd_clock_voltage_dependency_entry {
1441 u32 vclk;
1442 u32 dclk;
1443 u16 v;
1444};
1445
1446struct radeon_uvd_clock_voltage_dependency_table {
1447 u8 count;
1448 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1449};
1450
d29f013b
AD		 1451struct radeon_vce_clock_voltage_dependency_entry {
1452 u32 ecclk;
1453 u32 evclk;
1454 u16 v;
1455};
1456
1457struct radeon_vce_clock_voltage_dependency_table {
1458 u8 count;
1459 struct radeon_vce_clock_voltage_dependency_entry *entries;
1460};
1461
a5cb318e
AD		 1462struct radeon_ppm_table {
1463 u8 ppm_design;
1464 u16 cpu_core_number;
1465 u32 platform_tdp;
1466 u32 small_ac_platform_tdp;
1467 u32 platform_tdc;
1468 u32 small_ac_platform_tdc;
1469 u32 apu_tdp;
1470 u32 dgpu_tdp;
1471 u32 dgpu_ulv_power;
1472 u32 tj_max;
1473};
1474
58cb7632
AD		 1475struct radeon_cac_tdp_table {
1476 u16 tdp;
1477 u16 configurable_tdp;
1478 u16 tdc;
1479 u16 battery_power_limit;
1480 u16 small_power_limit;
1481 u16 low_cac_leakage;
1482 u16 high_cac_leakage;
1483 u16 maximum_power_delivery_limit;
1484};
1485
61b7d601
AD		 1486struct radeon_dpm_dynamic_state {
1487 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1488 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1489 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1490 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1491 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1492 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1493 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1494 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1495 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1496 struct radeon_clock_array valid_sclk_values;
1497 struct radeon_clock_array valid_mclk_values;
1498 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1499 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1500 u32 mclk_sclk_ratio;
1501 u32 sclk_mclk_delta;
1502 u16 vddc_vddci_delta;
1503 u16 min_vddc_for_pcie_gen2;
1504 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1505 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1506 struct radeon_ppm_table *ppm_table;
58cb7632 1507 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1508};
1509
1510struct radeon_dpm_fan {
1511 u16 t_min;
1512 u16 t_med;
1513 u16 t_high;
1514 u16 pwm_min;
1515 u16 pwm_med;
1516 u16 pwm_high;
1517 u8 t_hyst;
1518 u32 cycle_delay;
1519 u16 t_max;
e03cea36
AD		 1520 u8 control_mode;
1521 u16 default_max_fan_pwm;
1522 u16 default_fan_output_sensitivity;
1523 u16 fan_output_sensitivity;
61b7d601
AD		 1524 bool ucode_fan_control;
1525};
1526
32ce4652
AD		 1527enum radeon_pcie_gen {
1528 RADEON_PCIE_GEN1 = 0,
1529 RADEON_PCIE_GEN2 = 1,
1530 RADEON_PCIE_GEN3 = 2,
1531 RADEON_PCIE_GEN_INVALID = 0xffff
1532};
1533
70d01a5e
AD		 1534enum radeon_dpm_forced_level {
1535 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1536 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1537 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1538};
1539
58bd2a88
AD		 1540struct radeon_vce_state {
1541 /* vce clocks */
1542 u32 evclk;
1543 u32 ecclk;
1544 /* gpu clocks */
1545 u32 sclk;
1546 u32 mclk;
1547 u8 clk_idx;
1548 u8 pstate;
1549};
1550
da321c8a
AD		 1551struct radeon_dpm {
1552 struct radeon_ps *ps;
1553 /* number of valid power states */
1554 int num_ps;
1555 /* current power state that is active */
1556 struct radeon_ps *current_ps;
1557 /* requested power state */
1558 struct radeon_ps *requested_ps;
1559 /* boot up power state */
1560 struct radeon_ps *boot_ps;
1561 /* default uvd power state */
1562 struct radeon_ps *uvd_ps;
58bd2a88
AD		 1563 /* vce requirements */
1564 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1565 enum radeon_vce_level vce_level;
da321c8a
AD		 1566 enum radeon_pm_state_type state;
1567 enum radeon_pm_state_type user_state;
1568 u32 platform_caps;
1569 u32 voltage_response_time;
1570 u32 backbias_response_time;
1571 void *priv;
1572 u32 new_active_crtcs;
1573 int new_active_crtc_count;
1574 u32 current_active_crtcs;
1575 int current_active_crtc_count;
3899ca84 1576 bool single_display;
61b7d601
AD		 1577 struct radeon_dpm_dynamic_state dyn_state;
1578 struct radeon_dpm_fan fan;
1579 u32 tdp_limit;
1580 u32 near_tdp_limit;
a9e61410 1581 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1582 u32 sq_ramping_threshold;
1583 u32 cac_leakage;
1584 u16 tdp_od_limit;
1585 u32 tdp_adjustment;
1586 u16 load_line_slope;
1587 bool power_control;
5ca302f7 1588 bool ac_power;
da321c8a
AD		 1589 /* special states active */
1590 bool thermal_active;
8a227555 1591 bool uvd_active;
b62d628b 1592 bool vce_active;
da321c8a
AD		 1593 /* thermal handling */
1594 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1595 /* forced levels */
1596 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1597 /* track UVD streams */
1598 unsigned sd;
1599 unsigned hd;
da321c8a
AD		 1600};
1601
ce3537d5 1602void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
03afe6f6 1603void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
da321c8a 1604
c93bb85b 1605struct radeon_pm {
c913e23a 1606 struct mutex mutex;
db7fce39
CK		 1607 /* write locked while reprogramming mclk */
1608 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1609 u32 active_crtcs;
1610 int active_crtc_count;
c913e23a 1611 int req_vblank;
839461d3 1612 bool vblank_sync;
c93bb85b
JG		 1613 fixed20_12 max_bandwidth;
1614 fixed20_12 igp_sideport_mclk;
1615 fixed20_12 igp_system_mclk;
1616 fixed20_12 igp_ht_link_clk;
1617 fixed20_12 igp_ht_link_width;
1618 fixed20_12 k8_bandwidth;
1619 fixed20_12 sideport_bandwidth;
1620 fixed20_12 ht_bandwidth;
1621 fixed20_12 core_bandwidth;
1622 fixed20_12 sclk;
f47299c5 1623 fixed20_12 mclk;
c93bb85b 1624 fixed20_12 needed_bandwidth;
0975b162 1625 struct radeon_power_state *power_state;
56278a8e
AD		 1626 /* number of valid power states */
1627 int num_power_states;
a48b9b4e
AD		 1628 int current_power_state_index;
1629 int current_clock_mode_index;
1630 int requested_power_state_index;
1631 int requested_clock_mode_index;
1632 int default_power_state_index;
1633 u32 current_sclk;
1634 u32 current_mclk;
2feea49a
AD		 1635 u16 current_vddc;
1636 u16 current_vddci;
9ace9f7b
AD		 1637 u32 default_sclk;
1638 u32 default_mclk;
2feea49a
AD		 1639 u16 default_vddc;
1640 u16 default_vddci;
29fb52ca 1641 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1642 /* selected pm method */
1643 enum radeon_pm_method pm_method;
1644 /* dynpm power management */
1645 struct delayed_work dynpm_idle_work;
1646 enum radeon_dynpm_state dynpm_state;
1647 enum radeon_dynpm_action dynpm_planned_action;
1648 unsigned long dynpm_action_timeout;
1649 bool dynpm_can_upclock;
1650 bool dynpm_can_downclock;
1651 /* profile-based power management */
1652 enum radeon_pm_profile_type profile;
1653 int profile_index;
1654 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1655 /* internal thermal controller on rv6xx+ */
1656 enum radeon_int_thermal_type int_thermal_type;
1657 struct device *int_hwmon_dev;
9b92d1ec
AD		 1658 /* fan control parameters */
1659 bool no_fan;
1660 u8 fan_pulses_per_revolution;
1661 u8 fan_min_rpm;
1662 u8 fan_max_rpm;
da321c8a
AD		 1663 /* dpm */
1664 bool dpm_enabled;
49abb266 1665 bool sysfs_initialized;
da321c8a 1666 struct radeon_dpm dpm;
c93bb85b
JG		 1667};
1668
a4c9e2ee
AD		 1669int radeon_pm_get_type_index(struct radeon_device *rdev,
1670 enum radeon_pm_state_type ps_type,
1671 int instance);
f2ba57b5
CK		 1672/*
1673 * UVD
1674 */
1675#define RADEON_MAX_UVD_HANDLES 10
1676#define RADEON_UVD_STACK_SIZE (1024*1024)
1677#define RADEON_UVD_HEAP_SIZE (1024*1024)
1678
1679struct radeon_uvd {
1680 struct radeon_bo *vcpu_bo;
1681 void *cpu_addr;
1682 uint64_t gpu_addr;
1683 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1684 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1685 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1686 struct delayed_work idle_work;
f2ba57b5
CK		 1687};
1688
1689int radeon_uvd_init(struct radeon_device *rdev);
1690void radeon_uvd_fini(struct radeon_device *rdev);
1691int radeon_uvd_suspend(struct radeon_device *rdev);
1692int radeon_uvd_resume(struct radeon_device *rdev);
1693int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1694 uint32_t handle, struct radeon_fence **fence);
1695int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1696 uint32_t handle, struct radeon_fence **fence);
3852752c
CK		 1697void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1698 uint32_t allowed_domains);
f2ba57b5
CK		 1699void radeon_uvd_free_handles(struct radeon_device *rdev,
1700 struct drm_file *filp);
1701int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1702void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1703int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1704 unsigned vclk, unsigned dclk,
1705 unsigned vco_min, unsigned vco_max,
1706 unsigned fb_factor, unsigned fb_mask,
1707 unsigned pd_min, unsigned pd_max,
1708 unsigned pd_even,
1709 unsigned *optimal_fb_div,
1710 unsigned *optimal_vclk_div,
1711 unsigned *optimal_dclk_div);
1712int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1713 unsigned cg_upll_func_cntl);
771fe6b9 1714
d93f7937
CK		 1715/*
1716 * VCE
1717 */
1718#define RADEON_MAX_VCE_HANDLES 16
d93f7937
CK		 1719
1720struct radeon_vce {
1721 struct radeon_bo *vcpu_bo;
d93f7937 1722 uint64_t gpu_addr;
98ccc291
CK		 1723 unsigned fw_version;
1724 unsigned fb_version;
d93f7937
CK		 1725 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1726 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
2fc5703a 1727 unsigned img_size[RADEON_MAX_VCE_HANDLES];
03afe6f6 1728 struct delayed_work idle_work;
a918efab 1729 uint32_t keyselect;
d93f7937
CK		 1730};
1731
1732int radeon_vce_init(struct radeon_device *rdev);
1733void radeon_vce_fini(struct radeon_device *rdev);
1734int radeon_vce_suspend(struct radeon_device *rdev);
1735int radeon_vce_resume(struct radeon_device *rdev);
1736int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1737 uint32_t handle, struct radeon_fence **fence);
1738int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1739 uint32_t handle, struct radeon_fence **fence);
1740void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
03afe6f6 1741void radeon_vce_note_usage(struct radeon_device *rdev);
2fc5703a 1742int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
d93f7937
CK		 1743int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1744bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1745 struct radeon_ring *ring,
1746 struct radeon_semaphore *semaphore,
1747 bool emit_wait);
1748void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1749void radeon_vce_fence_emit(struct radeon_device *rdev,
1750 struct radeon_fence *fence);
1751int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1752int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1753
b530602f 1754struct r600_audio_pin {
a92553ab
RM		 1755 int channels;
1756 int rate;
1757 int bits_per_sample;
1758 u8 status_bits;
1759 u8 category_code;
b530602f
AD		 1760 u32 offset;
1761 bool connected;
1762 u32 id;
1763};
1764
1765struct r600_audio {
1766 bool enabled;
1767 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1768 int num_pins;
1a626b68
SG		 1769 struct radeon_audio_funcs *hdmi_funcs;
1770 struct radeon_audio_funcs *dp_funcs;
1771 struct radeon_audio_basic_funcs *funcs;
a92553ab
RM		 1772};
1773
771fe6b9
JG		 1774/*
1775 * Benchmarking
1776 */
638dd7db 1777void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1778
1779
ecc0b326
MD		 1780/*
1781 * Testing
1782 */
1783void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1784void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1785 struct radeon_ring *cpA,
1786 struct radeon_ring *cpB);
60a7e396 1787void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326 1788
341cb9e4
CK		 1789/*
1790 * MMU Notifier
1791 */
5a1aa4b4 1792#if defined(CONFIG_MMU_NOTIFIER)
341cb9e4
CK		 1793int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1794void radeon_mn_unregister(struct radeon_bo *bo);
5a1aa4b4
RC		 1795#else
1796static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1797{
1798 return -ENODEV;
1799}
1800static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1801#endif
ecc0b326 1802
771fe6b9
JG		 1803/*
1804 * Debugfs
1805 */
4d8bf9ae
CK		 1806struct radeon_debugfs {
1807 struct drm_info_list *files;
1808 unsigned num_files;
1809};
1810
771fe6b9
JG		 1811int radeon_debugfs_add_files(struct radeon_device *rdev,
1812 struct drm_info_list *files,
1813 unsigned nfiles);
1814int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1815
76a0df85
CK		 1816/*
1817 * ASIC ring specific functions.
1818 */
1819struct radeon_asic_ring {
1820 /* ring read/write ptr handling */
1821 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1822 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1823 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1824
1825 /* validating and patching of IBs */
1826 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1827 int (*cs_parse)(struct radeon_cs_parser *p);
1828
1829 /* command emmit functions */
1830 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1831 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
72a9987e 1832 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1654b817 1833 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85 1834 struct radeon_semaphore *semaphore, bool emit_wait);
faffaf62
CK		 1835 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1836 unsigned vm_id, uint64_t pd_addr);
76a0df85
CK		 1837
1838 /* testing functions */
1839 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1840 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1841 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1842
1843 /* deprecated */
1844 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1845};
771fe6b9
JG		 1846
1847/*
1848 * ASIC specific functions.
1849 */
1850struct radeon_asic {
068a117c 1851 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1852 void (*fini)(struct radeon_device *rdev);
1853 int (*resume)(struct radeon_device *rdev);
1854 int (*suspend)(struct radeon_device *rdev);
28d52043 1855 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1856 int (*asic_reset)(struct radeon_device *rdev);
124764f1
MD		 1857 /* Flush the HDP cache via MMIO */
1858 void (*mmio_hdp_flush)(struct radeon_device *rdev);
54e88e06
AD		 1859 /* check if 3D engine is idle */
1860 bool (*gui_idle)(struct radeon_device *rdev);
1861 /* wait for mc_idle */
1862 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1863 /* get the reference clock */
1864 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1865 /* get the gpu clock counter */
1866 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
4ce4728b
AD		 1867 /* get register for info ioctl */
1868 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
54e88e06 1869 /* gart */
c5b3b850
AD		 1870 struct {
1871 void (*tlb_flush)(struct radeon_device *rdev);
cb658906 1872 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
7f90fc96 1873 void (*set_page)(struct radeon_device *rdev, unsigned i,
cb658906 1874 uint64_t entry);
c5b3b850 1875 } gart;
05b07147
CK		 1876 struct {
1877 int (*init)(struct radeon_device *rdev);
1878 void (*fini)(struct radeon_device *rdev);
03f62abd
CK		 1879 void (*copy_pages)(struct radeon_device *rdev,
1880 struct radeon_ib *ib,
1881 uint64_t pe, uint64_t src,
1882 unsigned count);
1883 void (*write_pages)(struct radeon_device *rdev,
1884 struct radeon_ib *ib,
1885 uint64_t pe,
1886 uint64_t addr, unsigned count,
1887 uint32_t incr, uint32_t flags);
1888 void (*set_pages)(struct radeon_device *rdev,
1889 struct radeon_ib *ib,
1890 uint64_t pe,
1891 uint64_t addr, unsigned count,
1892 uint32_t incr, uint32_t flags);
1893 void (*pad_ib)(struct radeon_ib *ib);
05b07147 1894 } vm;
54e88e06 1895 /* ring specific callbacks */
d26678da 1896 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1897 /* irqs */
b35ea4ab
AD		 1898 struct {
1899 int (*set)(struct radeon_device *rdev);
1900 int (*process)(struct radeon_device *rdev);
1901 } irq;
54e88e06 1902 /* displays */
c79a49ca
AD		 1903 struct {
1904 /* display watermarks */
1905 void (*bandwidth_update)(struct radeon_device *rdev);
1906 /* get frame count */
1907 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1908 /* wait for vblank */
1909 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1910 /* set backlight level */
1911 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1912 /* get backlight level */
1913 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1914 /* audio callbacks */
1915 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1916 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1917 } display;
54e88e06 1918 /* copy functions for bo handling */
27cd7769 1919 struct {
57d20a43
CK		 1920 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1921 uint64_t src_offset,
1922 uint64_t dst_offset,
1923 unsigned num_gpu_pages,
1924 struct reservation_object *resv);
27cd7769 1925 u32 blit_ring_index;
57d20a43
CK		 1926 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1927 uint64_t src_offset,
1928 uint64_t dst_offset,
1929 unsigned num_gpu_pages,
1930 struct reservation_object *resv);
27cd7769
AD		 1931 u32 dma_ring_index;
1932 /* method used for bo copy */
57d20a43
CK		 1933 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1934 uint64_t src_offset,
1935 uint64_t dst_offset,
1936 unsigned num_gpu_pages,
1937 struct reservation_object *resv);
27cd7769
AD		 1938 /* ring used for bo copies */
1939 u32 copy_ring_index;
1940 } copy;
54e88e06 1941 /* surfaces */
9e6f3d02
AD		 1942 struct {
1943 int (*set_reg)(struct radeon_device *rdev, int reg,
1944 uint32_t tiling_flags, uint32_t pitch,
1945 uint32_t offset, uint32_t obj_size);
1946 void (*clear_reg)(struct radeon_device *rdev, int reg);
1947 } surface;
54e88e06 1948 /* hotplug detect */
901ea57d
AD		 1949 struct {
1950 void (*init)(struct radeon_device *rdev);
1951 void (*fini)(struct radeon_device *rdev);
1952 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1953 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1954 } hpd;
da321c8a 1955 /* static power management */
a02fa397
AD		 1956 struct {
1957 void (*misc)(struct radeon_device *rdev);
1958 void (*prepare)(struct radeon_device *rdev);
1959 void (*finish)(struct radeon_device *rdev);
1960 void (*init_profile)(struct radeon_device *rdev);
1961 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1962 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1963 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1964 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1965 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1966 int (*get_pcie_lanes)(struct radeon_device *rdev);
1967 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1968 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1969 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
b59b7333 1970 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
6bd1c385 1971 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1972 } pm;
da321c8a
AD		 1973 /* dynamic power management */
1974 struct {
1975 int (*init)(struct radeon_device *rdev);
1976 void (*setup_asic)(struct radeon_device *rdev);
1977 int (*enable)(struct radeon_device *rdev);
914a8987 1978 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1979 void (*disable)(struct radeon_device *rdev);
84dd1928 1980 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1981 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1982 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1983 void (*display_configuration_changed)(struct radeon_device *rdev);
1984 void (*fini)(struct radeon_device *rdev);
1985 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1986 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1987 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1988 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1989 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1990 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1991 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1992 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
a35a4b2b
OC		 1993 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1994 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1995 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1996 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
d7dbce09
AD		 1997 u32 (*get_current_sclk)(struct radeon_device *rdev);
1998 u32 (*get_current_mclk)(struct radeon_device *rdev);
da321c8a 1999 } dpm;
6f34be50 2000 /* pageflipping */
0f9e006c 2001 struct {
157fa14d
CK		 2002 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
2003 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
0f9e006c 2004 } pflip;
771fe6b9
JG		 2005};
2006
21f9a437
JG		 2007/*
2008 * Asic structures
2009 */
551ebd83 2010struct r100_asic {
225758d8
JG		 2011 const unsigned *reg_safe_bm;
2012 unsigned reg_safe_bm_size;
2013 u32 hdp_cntl;
551ebd83
DA		 2014};
2015
21f9a437 2016struct r300_asic {
225758d8
JG		 2017 const unsigned *reg_safe_bm;
2018 unsigned reg_safe_bm_size;
2019 u32 resync_scratch;
2020 u32 hdp_cntl;
21f9a437
JG		 2021};
2022
2023struct r600_asic {
225758d8
JG		 2024 unsigned max_pipes;
2025 unsigned max_tile_pipes;
2026 unsigned max_simds;
2027 unsigned max_backends;
2028 unsigned max_gprs;
2029 unsigned max_threads;
2030 unsigned max_stack_entries;
2031 unsigned max_hw_contexts;
2032 unsigned max_gs_threads;
2033 unsigned sx_max_export_size;
2034 unsigned sx_max_export_pos_size;
2035 unsigned sx_max_export_smx_size;
2036 unsigned sq_num_cf_insts;
2037 unsigned tiling_nbanks;
2038 unsigned tiling_npipes;
2039 unsigned tiling_group_size;
e7aeeba6 2040 unsigned tile_config;
e55b9422 2041 unsigned backend_map;
65fcf668 2042 unsigned active_simds;
21f9a437
JG		 2043};
2044
2045struct rv770_asic {
225758d8
JG		 2046 unsigned max_pipes;
2047 unsigned max_tile_pipes;
2048 unsigned max_simds;
2049 unsigned max_backends;
2050 unsigned max_gprs;
2051 unsigned max_threads;
2052 unsigned max_stack_entries;
2053 unsigned max_hw_contexts;
2054 unsigned max_gs_threads;
2055 unsigned sx_max_export_size;
2056 unsigned sx_max_export_pos_size;
2057 unsigned sx_max_export_smx_size;
2058 unsigned sq_num_cf_insts;
2059 unsigned sx_num_of_sets;
2060 unsigned sc_prim_fifo_size;
2061 unsigned sc_hiz_tile_fifo_size;
2062 unsigned sc_earlyz_tile_fifo_fize;
2063 unsigned tiling_nbanks;
2064 unsigned tiling_npipes;
2065 unsigned tiling_group_size;
e7aeeba6 2066 unsigned tile_config;
e55b9422 2067 unsigned backend_map;
65fcf668 2068 unsigned active_simds;
21f9a437
JG		 2069};
2070
32fcdbf4
AD		 2071struct evergreen_asic {
2072 unsigned num_ses;
2073 unsigned max_pipes;
2074 unsigned max_tile_pipes;
2075 unsigned max_simds;
2076 unsigned max_backends;
2077 unsigned max_gprs;
2078 unsigned max_threads;
2079 unsigned max_stack_entries;
2080 unsigned max_hw_contexts;
2081 unsigned max_gs_threads;
2082 unsigned sx_max_export_size;
2083 unsigned sx_max_export_pos_size;
2084 unsigned sx_max_export_smx_size;
2085 unsigned sq_num_cf_insts;
2086 unsigned sx_num_of_sets;
2087 unsigned sc_prim_fifo_size;
2088 unsigned sc_hiz_tile_fifo_size;
2089 unsigned sc_earlyz_tile_fifo_size;
2090 unsigned tiling_nbanks;
2091 unsigned tiling_npipes;
2092 unsigned tiling_group_size;
e7aeeba6 2093 unsigned tile_config;
e55b9422 2094 unsigned backend_map;
65fcf668 2095 unsigned active_simds;
32fcdbf4
AD		 2096};
2097
fecf1d07
AD		 2098struct cayman_asic {
2099 unsigned max_shader_engines;
2100 unsigned max_pipes_per_simd;
2101 unsigned max_tile_pipes;
2102 unsigned max_simds_per_se;
2103 unsigned max_backends_per_se;
2104 unsigned max_texture_channel_caches;
2105 unsigned max_gprs;
2106 unsigned max_threads;
2107 unsigned max_gs_threads;
2108 unsigned max_stack_entries;
2109 unsigned sx_num_of_sets;
2110 unsigned sx_max_export_size;
2111 unsigned sx_max_export_pos_size;
2112 unsigned sx_max_export_smx_size;
2113 unsigned max_hw_contexts;
2114 unsigned sq_num_cf_insts;
2115 unsigned sc_prim_fifo_size;
2116 unsigned sc_hiz_tile_fifo_size;
2117 unsigned sc_earlyz_tile_fifo_size;
2118
2119 unsigned num_shader_engines;
2120 unsigned num_shader_pipes_per_simd;
2121 unsigned num_tile_pipes;
2122 unsigned num_simds_per_se;
2123 unsigned num_backends_per_se;
2124 unsigned backend_disable_mask_per_asic;
2125 unsigned backend_map;
2126 unsigned num_texture_channel_caches;
2127 unsigned mem_max_burst_length_bytes;
2128 unsigned mem_row_size_in_kb;
2129 unsigned shader_engine_tile_size;
2130 unsigned num_gpus;
2131 unsigned multi_gpu_tile_size;
2132
2133 unsigned tile_config;
65fcf668 2134 unsigned active_simds;
fecf1d07
AD		 2135};
2136
0a96d72b
AD		 2137struct si_asic {
2138 unsigned max_shader_engines;
0a96d72b 2139 unsigned max_tile_pipes;
1a8ca750
AD		 2140 unsigned max_cu_per_sh;
2141 unsigned max_sh_per_se;
0a96d72b
AD		 2142 unsigned max_backends_per_se;
2143 unsigned max_texture_channel_caches;
2144 unsigned max_gprs;
2145 unsigned max_gs_threads;
2146 unsigned max_hw_contexts;
2147 unsigned sc_prim_fifo_size_frontend;
2148 unsigned sc_prim_fifo_size_backend;
2149 unsigned sc_hiz_tile_fifo_size;
2150 unsigned sc_earlyz_tile_fifo_size;
2151
0a96d72b 2152 unsigned num_tile_pipes;
439a1cff 2153 unsigned backend_enable_mask;
0a96d72b
AD		 2154 unsigned backend_disable_mask_per_asic;
2155 unsigned backend_map;
2156 unsigned num_texture_channel_caches;
2157 unsigned mem_max_burst_length_bytes;
2158 unsigned mem_row_size_in_kb;
2159 unsigned shader_engine_tile_size;
2160 unsigned num_gpus;
2161 unsigned multi_gpu_tile_size;
2162
2163 unsigned tile_config;
64d7b8be 2164 uint32_t tile_mode_array[32];
65fcf668 2165 uint32_t active_cus;
0a96d72b
AD		 2166};
2167
8cc1a532
AD		 2168struct cik_asic {
2169 unsigned max_shader_engines;
2170 unsigned max_tile_pipes;
2171 unsigned max_cu_per_sh;
2172 unsigned max_sh_per_se;
2173 unsigned max_backends_per_se;
2174 unsigned max_texture_channel_caches;
2175 unsigned max_gprs;
2176 unsigned max_gs_threads;
2177 unsigned max_hw_contexts;
2178 unsigned sc_prim_fifo_size_frontend;
2179 unsigned sc_prim_fifo_size_backend;
2180 unsigned sc_hiz_tile_fifo_size;
2181 unsigned sc_earlyz_tile_fifo_size;
2182
2183 unsigned num_tile_pipes;
439a1cff 2184 unsigned backend_enable_mask;
8cc1a532
AD		 2185 unsigned backend_disable_mask_per_asic;
2186 unsigned backend_map;
2187 unsigned num_texture_channel_caches;
2188 unsigned mem_max_burst_length_bytes;
2189 unsigned mem_row_size_in_kb;
2190 unsigned shader_engine_tile_size;
2191 unsigned num_gpus;
2192 unsigned multi_gpu_tile_size;
2193
2194 unsigned tile_config;
39aee490 2195 uint32_t tile_mode_array[32];
32f79a8a 2196 uint32_t macrotile_mode_array[16];
65fcf668 2197 uint32_t active_cus;
8cc1a532
AD		 2198};
2199
068a117c
JG		 2200union radeon_asic_config {
2201 struct r300_asic r300;
551ebd83 2202 struct r100_asic r100;
3ce0a23d
JG		 2203 struct r600_asic r600;
2204 struct rv770_asic rv770;
32fcdbf4 2205 struct evergreen_asic evergreen;
fecf1d07 2206 struct cayman_asic cayman;
0a96d72b 2207 struct si_asic si;
8cc1a532 2208 struct cik_asic cik;
068a117c
JG		 2209};
2210
0a10c851
DV		 2211/*
2212 * asic initizalization from radeon_asic.c
2213 */
2214void radeon_agp_disable(struct radeon_device *rdev);
2215int radeon_asic_init(struct radeon_device *rdev);
2216
771fe6b9
JG		 2217
2218/*
2219 * IOCTL.
2220 */
2221int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2222 struct drm_file *filp);
2223int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2224 struct drm_file *filp);
f72a113a
CK		 2225int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2226 struct drm_file *filp);
771fe6b9
JG		 2227int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2228 struct drm_file *file_priv);
2229int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2230 struct drm_file *file_priv);
2231int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2232 struct drm_file *file_priv);
2233int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2234 struct drm_file *file_priv);
2235int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2236 struct drm_file *filp);
2237int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2238 struct drm_file *filp);
2239int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2240 struct drm_file *filp);
2241int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2242 struct drm_file *filp);
721604a1
JG		 2243int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2244 struct drm_file *filp);
bda72d58
MO		 2245int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2246 struct drm_file *filp);
771fe6b9 2247int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2248int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2249 struct drm_file *filp);
2250int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2251 struct drm_file *filp);
771fe6b9 2252
16cdf04d
AD		 2253/* VRAM scratch page for HDP bug, default vram page */
2254struct r600_vram_scratch {
87cbf8f2
AD		 2255 struct radeon_bo *robj;
2256 volatile uint32_t *ptr;
16cdf04d 2257 u64 gpu_addr;
87cbf8f2 2258};
771fe6b9 2259
fd64ca8a
LT		 2260/*
2261 * ACPI
2262 */
2263struct radeon_atif_notification_cfg {
2264 bool enabled;
2265 int command_code;
2266};
2267
2268struct radeon_atif_notifications {
2269 bool display_switch;
2270 bool expansion_mode_change;
2271 bool thermal_state;
2272 bool forced_power_state;
2273 bool system_power_state;
2274 bool display_conf_change;
2275 bool px_gfx_switch;
2276 bool brightness_change;
2277 bool dgpu_display_event;
2278};
2279
2280struct radeon_atif_functions {
2281 bool system_params;
2282 bool sbios_requests;
2283 bool select_active_disp;
2284 bool lid_state;
2285 bool get_tv_standard;
2286 bool set_tv_standard;
2287 bool get_panel_expansion_mode;
2288 bool set_panel_expansion_mode;
2289 bool temperature_change;
2290 bool graphics_device_types;
2291};
2292
2293struct radeon_atif {
2294 struct radeon_atif_notifications notifications;
2295 struct radeon_atif_functions functions;
2296 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2297 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2298};
7a1619b9 2299
e3a15920
AD		 2300struct radeon_atcs_functions {
2301 bool get_ext_state;
2302 bool pcie_perf_req;
2303 bool pcie_dev_rdy;
2304 bool pcie_bus_width;
2305};
2306
2307struct radeon_atcs {
2308 struct radeon_atcs_functions functions;
2309};
2310
771fe6b9
JG		 2311/*
2312 * Core structure, functions and helpers.
2313 */
2314typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2315typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2316
2317struct radeon_device {
9f022ddf 2318 struct device *dev;
771fe6b9
JG		 2319 struct drm_device *ddev;
2320 struct pci_dev *pdev;
dee53e7f 2321 struct rw_semaphore exclusive_lock;
771fe6b9 2322 /* ASIC */
068a117c 2323 union radeon_asic_config config;
771fe6b9
JG		 2324 enum radeon_family family;
2325 unsigned long flags;
2326 int usec_timeout;
2327 enum radeon_pll_errata pll_errata;
2328 int num_gb_pipes;
f779b3e5 2329 int num_z_pipes;
771fe6b9
JG		 2330 int disp_priority;
2331 /* BIOS */
2332 uint8_t *bios;
2333 bool is_atom_bios;
2334 uint16_t bios_header_start;
4c788679 2335 struct radeon_bo *stollen_vga_memory;
771fe6b9 2336 /* Register mmio */
4c9bc75c
DA		 2337 resource_size_t rmmio_base;
2338 resource_size_t rmmio_size;
2c385151
DV		 2339 /* protects concurrent MM_INDEX/DATA based register access */
2340 spinlock_t mmio_idx_lock;
fe78118c
AD		 2341 /* protects concurrent SMC based register access */
2342 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2343 /* protects concurrent PLL register access */
2344 spinlock_t pll_idx_lock;
2345 /* protects concurrent MC register access */
2346 spinlock_t mc_idx_lock;
2347 /* protects concurrent PCIE register access */
2348 spinlock_t pcie_idx_lock;
2349 /* protects concurrent PCIE_PORT register access */
2350 spinlock_t pciep_idx_lock;
2351 /* protects concurrent PIF register access */
2352 spinlock_t pif_idx_lock;
2353 /* protects concurrent CG register access */
2354 spinlock_t cg_idx_lock;
2355 /* protects concurrent UVD register access */
2356 spinlock_t uvd_idx_lock;
2357 /* protects concurrent RCU register access */
2358 spinlock_t rcu_idx_lock;
2359 /* protects concurrent DIDT register access */
2360 spinlock_t didt_idx_lock;
2361 /* protects concurrent ENDPOINT (audio) register access */
2362 spinlock_t end_idx_lock;
a0533fbf 2363 void __iomem *rmmio;
771fe6b9
JG		 2364 radeon_rreg_t mc_rreg;
2365 radeon_wreg_t mc_wreg;
2366 radeon_rreg_t pll_rreg;
2367 radeon_wreg_t pll_wreg;
de1b2898 2368 uint32_t pcie_reg_mask;
771fe6b9
JG		 2369 radeon_rreg_t pciep_rreg;
2370 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2371 /* io port */
2372 void __iomem *rio_mem;
2373 resource_size_t rio_mem_size;
771fe6b9
JG		 2374 struct radeon_clock clock;
2375 struct radeon_mc mc;
2376 struct radeon_gart gart;
2377 struct radeon_mode_info mode_info;
2378 struct radeon_scratch scratch;
75efdee1 2379 struct radeon_doorbell doorbell;
771fe6b9 2380 struct radeon_mman mman;
7465280c 2381 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2382 wait_queue_head_t fence_queue;
954605ca 2383 unsigned fence_context;
d6999bc7 2384 struct mutex ring_lock;
e32eb50d 2385 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2386 bool ib_pool_ready;
2387 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2388 struct radeon_irq irq;
2389 struct radeon_asic *asic;
2390 struct radeon_gem gem;
c93bb85b 2391 struct radeon_pm pm;
f2ba57b5 2392 struct radeon_uvd uvd;
d93f7937 2393 struct radeon_vce vce;
f657c2a7 2394 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2395 struct radeon_wb wb;
3ce0a23d 2396 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2397 bool shutdown;
2398 bool suspend;
ad49f501 2399 bool need_dma32;
733289c2 2400 bool accel_working;
a0a53aa8 2401 bool fastfb_working; /* IGP feature*/
9bb39ff4 2402 bool needs_reset, in_reset;
e024e110 2403 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2404 const struct firmware *me_fw; /* all family ME firmware */
2405 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2406 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2407 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2408 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2409 const struct firmware *mec_fw; /* CIK MEC firmware */
f2c6b0f4 2410 const struct firmware *mec2_fw; /* KV MEC2 firmware */
21a93e13 2411 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2412 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2413 const struct firmware *uvd_fw; /* UVD firmware */
d93f7937 2414 const struct firmware *vce_fw; /* VCE firmware */
629bd33c 2415 bool new_fw;
16cdf04d 2416 struct r600_vram_scratch vram_scratch;
3e5cb98d 2417 int msi_enabled; /* msi enabled */
d8f60cfc 2418 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2419 struct radeon_rlc rlc;
963e81f9 2420 struct radeon_mec mec;
cb5d4166 2421 struct delayed_work hotplug_work;
de6284aa 2422 struct work_struct dp_work;
f122c610 2423 struct work_struct audio_work;
18917b60 2424 int num_crtc; /* number of crtcs */
40bacf16 2425 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2426 bool has_uvd;
e3ebfcfa 2427 bool has_vce;
b530602f 2428 struct r600_audio audio; /* audio stuff */
ce8f5370 2429 struct notifier_block acpi_nb;
9eba4a93 2430 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2431 struct drm_file *hyperz_filp;
9eba4a93 2432 struct drm_file *cmask_filp;
f376b94f
AD		 2433 /* i2c buses */
2434 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2435 /* debugfs */
2436 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2437 unsigned debugfs_count;
721604a1
JG		 2438 /* virtual memory */
2439 struct radeon_vm_manager vm_manager;
6759a0a7 2440 struct mutex gpu_clock_mutex;
67e8e3f9
MO		 2441 /* memory stats */
2442 atomic64_t vram_usage;
2443 atomic64_t gtt_usage;
2444 atomic64_t num_bytes_moved;
72b9076b 2445 atomic_t gpu_reset_counter;
fd64ca8a
LT		 2446 /* ACPI interface */
2447 struct radeon_atif atif;
e3a15920 2448 struct radeon_atcs atcs;
f61d5b46
AD		 2449 /* srbm instance registers */
2450 struct mutex srbm_mutex;
1c0a4625
OG		 2451 /* GRBM index mutex. Protects concurrents access to GRBM index */
2452 struct mutex grbm_idx_mutex;
64d8a728
AD		 2453 /* clock, powergating flags */
2454 u32 cg_flags;
2455 u32 pg_flags;
10ebc0bc
DA		 2456
2457 struct dev_pm_domain vga_pm_domain;
2458 bool have_disp_power_ref;
4807c5a8 2459 u32 px_quirk_flags;
71ecc97e
AD		 2460
2461 /* tracking pinned memory */
2462 u64 vram_pin_size;
2463 u64 gart_pin_size;
341cb9e4 2464
e28740ec
OG		 2465 /* amdkfd interface */
2466 struct kfd_dev *kfd;
e28740ec 2467
341cb9e4
CK		 2468 struct mutex mn_lock;
2469 DECLARE_HASHTABLE(mn_hash, 7);
771fe6b9
JG		 2470};
2471
90c4cde9 2472bool radeon_is_px(struct drm_device *dev);
771fe6b9
JG		 2473int radeon_device_init(struct radeon_device *rdev,
2474 struct drm_device *ddev,
2475 struct pci_dev *pdev,
2476 uint32_t flags);
2477void radeon_device_fini(struct radeon_device *rdev);
2478int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2479
59bc1d89
LK		 2480#define RADEON_MIN_MMIO_SIZE 0x10000
2481
9e5acbc2
DV		 2482uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2483void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
59bc1d89
LK		 2484static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2485 bool always_indirect)
2486{
2487 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2488 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2489 return readl(((void __iomem *)rdev->rmmio) + reg);
9e5acbc2
DV		 2490 else
2491 return r100_mm_rreg_slow(rdev, reg);
59bc1d89 2492}
59bc1d89
LK		 2493static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2494 bool always_indirect)
2495{
2496 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2497 writel(v, ((void __iomem *)rdev->rmmio) + reg);
9e5acbc2
DV		 2498 else
2499 r100_mm_wreg_slow(rdev, reg, v);
59bc1d89
LK		 2500}
2501
6fcbef7a
AK		 2502u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2503void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2504
d5754ab8
AL		 2505u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2506void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2507
4c788679
JG		 2508/*
2509 * Cast helper
2510 */
954605ca
ML		 2511extern const struct fence_ops radeon_fence_ops;
2512
2513static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2514{
2515 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2516
2517 if (__f->base.ops == &radeon_fence_ops)
2518 return __f;
2519
2520 return NULL;
2521}
771fe6b9
JG		 2522
2523/*
2524 * Registers read & write functions.
2525 */
a0533fbf
BH		 2526#define RREG8(reg) readb((rdev->rmmio) + (reg))
2527#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2528#define RREG16(reg) readw((rdev->rmmio) + (reg))
2529#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2530#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2531#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2532#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2533#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2534#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2535#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2536#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2537#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2538#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2539#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2540#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2541#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2542#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2543#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2544#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2545#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2546#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2547#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2548#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2549#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2550#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2551#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2552#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2553#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2554#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2555#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2556#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2557#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2558#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2559#define WREG32_P(reg, val, mask) \
2560 do { \
2561 uint32_t tmp_ = RREG32(reg); \
2562 tmp_ &= (mask); \
2563 tmp_ |= ((val) & ~(mask)); \
2564 WREG32(reg, tmp_); \
2565 } while (0)
d5169fc4 2566#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2567#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2568#define WREG32_PLL_P(reg, val, mask) \
2569 do { \
2570 uint32_t tmp_ = RREG32_PLL(reg); \
2571 tmp_ &= (mask); \
2572 tmp_ |= ((val) & ~(mask)); \
2573 WREG32_PLL(reg, tmp_); \
2574 } while (0)
b7af630c
CK		 2575#define WREG32_SMC_P(reg, val, mask) \
2576 do { \
2577 uint32_t tmp_ = RREG32_SMC(reg); \
2578 tmp_ &= (mask); \
2579 tmp_ |= ((val) & ~(mask)); \
2580 WREG32_SMC(reg, tmp_); \
2581 } while (0)
2ef9bdfe 2582#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2583#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2584#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2585
d5754ab8
AL		 2586#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2587#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2588
de1b2898 2589/*
9e5acbc2
DV		 2590 * Indirect registers accessors.
2591 * They used to be inlined, but this increases code size by ~65 kbytes.
2592 * Since each performs a pair of MMIO ops
2593 * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2594 * the cost of call+ret is almost negligible. MMIO and locking
2595 * costs several dozens of cycles each at best, call+ret is ~5 cycles.
de1b2898 2596 */
9e5acbc2
DV		 2597uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2598void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2599u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2600void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2601u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2602void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2603u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2604void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2605u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2606void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2607u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2608void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2609u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2610void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2611u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2612void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1d58234d 2613
771fe6b9
JG		 2614void r100_pll_errata_after_index(struct radeon_device *rdev);
2615
2616
2617/*
2618 * ASICs helpers.
2619 */
b995e433
DA		 2620#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2621 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2622#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2623 (rdev->family == CHIP_RV200) || \
2624 (rdev->family == CHIP_RS100) || \
2625 (rdev->family == CHIP_RS200) || \
2626 (rdev->family == CHIP_RV250) || \
2627 (rdev->family == CHIP_RV280) || \
2628 (rdev->family == CHIP_RS300))
2629#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2630 (rdev->family == CHIP_RV350) || \
2631 (rdev->family == CHIP_R350) || \
2632 (rdev->family == CHIP_RV380) || \
2633 (rdev->family == CHIP_R420) || \
2634 (rdev->family == CHIP_R423) || \
2635 (rdev->family == CHIP_RV410) || \
2636 (rdev->family == CHIP_RS400) || \
2637 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2638#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2639 (rdev->ddev->pdev->device == 0x9443) || \
2640 (rdev->ddev->pdev->device == 0x944B) || \
2641 (rdev->ddev->pdev->device == 0x9506) || \
2642 (rdev->ddev->pdev->device == 0x9509) || \
2643 (rdev->ddev->pdev->device == 0x950F) || \
2644 (rdev->ddev->pdev->device == 0x689C) || \
2645 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2646#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2647#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2648 (rdev->family == CHIP_RS690) || \
2649 (rdev->family == CHIP_RS740) || \
2650 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2651#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2652#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2653#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2654#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2655 (rdev->flags & RADEON_IS_IGP))
1fe18305 2656#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2657#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2658#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2659 (rdev->flags & RADEON_IS_IGP))
624d3524 2660#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2661#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2662#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
be0949f5
AD		 2663#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2664#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
89d2618d
AD		 2665#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2666 (rdev->family == CHIP_MULLINS))
771fe6b9 2667
dc50ba7f
AD		 2668#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2669 (rdev->ddev->pdev->device == 0x6850) || \
2670 (rdev->ddev->pdev->device == 0x6858) || \
2671 (rdev->ddev->pdev->device == 0x6859) || \
2672 (rdev->ddev->pdev->device == 0x6840) || \
2673 (rdev->ddev->pdev->device == 0x6841) || \
2674 (rdev->ddev->pdev->device == 0x6842) || \
2675 (rdev->ddev->pdev->device == 0x6843))
2676
771fe6b9
JG		 2677/*
2678 * BIOS helpers.
2679 */
2680#define RBIOS8(i) (rdev->bios[i])
2681#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2682#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2683
2684int radeon_combios_init(struct radeon_device *rdev);
2685void radeon_combios_fini(struct radeon_device *rdev);
2686int radeon_atombios_init(struct radeon_device *rdev);
2687void radeon_atombios_fini(struct radeon_device *rdev);
2688
2689
2690/*
2691 * RING helpers.
2692 */
edf0ac7c
DH		 2693
2694/**
2695 * radeon_ring_write - write a value to the ring
2696 *
2697 * @ring: radeon_ring structure holding ring information
2698 * @v: dword (dw) value to write
2699 *
2700 * Write a value to the requested ring buffer (all asics).
2701 */
e32eb50d 2702static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2703{
edf0ac7c
DH		 2704 if (ring->count_dw <= 0)
2705 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2706
e32eb50d
CK		 2707 ring->ring[ring->wptr++] = v;
2708 ring->wptr &= ring->ptr_mask;
2709 ring->count_dw--;
2710 ring->ring_free_dw--;
771fe6b9 2711}
771fe6b9
JG		 2712
2713/*
2714 * ASICs macro.
2715 */
068a117c 2716#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2717#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2718#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2719#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2720#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2721#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2722#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850 2723#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
cb658906
MD		 2724#define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2725#define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
05b07147
CK		 2726#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2727#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
03f62abd
CK		 2728#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2729#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2730#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2731#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
76a0df85
CK		 2732#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2733#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2734#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2735#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2736#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2737#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
faffaf62 2738#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
76a0df85
CK		 2739#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2740#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2741#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2742#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2743#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2744#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2745#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2746#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2747#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2748#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2749#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2750#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
57d20a43
CK		 2751#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2752#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2753#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
27cd7769
AD		 2754#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2755#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2756#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2757#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2758#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2759#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2760#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2761#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2762#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2763#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2764#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
b59b7333 2765#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
6bd1c385 2766#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2767#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2768#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2769#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2770#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2771#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2772#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2773#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2774#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2775#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2776#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2777#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2778#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2779#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8 2780#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
157fa14d 2781#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
69b62ad8
AD		 2782#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2783#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2784#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2785#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
4ce4728b 2786#define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
da321c8a
AD		 2787#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2788#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2789#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2790#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2791#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2792#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2793#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2794#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2795#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2796#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2797#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2798#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2799#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2800#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2801#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2802#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2803#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2804#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
d7dbce09
AD		 2805#define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2806#define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
771fe6b9 2807
6cf8a3f5 2808/* Common functions */
700a0cc0 2809/* AGP */
90aca4d2 2810extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2811extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2812extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2813extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2814extern int radeon_modeset_init(struct radeon_device *rdev);
2815extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2816extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2817extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2818extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2819extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2820extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2821extern void radeon_wb_fini(struct radeon_device *rdev);
2822extern int radeon_wb_init(struct radeon_device *rdev);
2823extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2824extern void radeon_surface_init(struct radeon_device *rdev);
2825extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2826extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2827extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2828extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2829extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
f72a113a
CK		 2830extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2831 uint32_t flags);
2832extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2833extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
d594e46a
JG		 2834extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2835extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2836extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2837extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2838extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2839extern void radeon_program_register_sequence(struct radeon_device *rdev,
2840 const u32 *registers,
2841 const u32 array_size);
6cf8a3f5 2842
721604a1
JG		 2843/*
2844 * vm
2845 */
2846int radeon_vm_manager_init(struct radeon_device *rdev);
2847void radeon_vm_manager_fini(struct radeon_device *rdev);
6d2f2944 2848int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2849void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1d0c0942 2850struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
df0af440
CK		 2851 struct radeon_vm *vm,
2852 struct list_head *head);
ee60e29f
CK		 2853struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2854 struct radeon_vm *vm, int ring);
fa688343
CK		 2855void radeon_vm_flush(struct radeon_device *rdev,
2856 struct radeon_vm *vm,
ad1a58a4 2857 int ring, struct radeon_fence *fence);
ee60e29f
CK		 2858void radeon_vm_fence(struct radeon_device *rdev,
2859 struct radeon_vm *vm,
2860 struct radeon_fence *fence);
dce34bfd 2861uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
6d2f2944
CK		 2862int radeon_vm_update_page_directory(struct radeon_device *rdev,
2863 struct radeon_vm *vm);
036bf46a
CK		 2864int radeon_vm_clear_freed(struct radeon_device *rdev,
2865 struct radeon_vm *vm);
e31ad969
CK		 2866int radeon_vm_clear_invalids(struct radeon_device *rdev,
2867 struct radeon_vm *vm);
9c57a6bd 2868int radeon_vm_bo_update(struct radeon_device *rdev,
036bf46a 2869 struct radeon_bo_va *bo_va,
9c57a6bd 2870 struct ttm_mem_reg *mem);
721604a1
JG		 2871void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2872 struct radeon_bo *bo);
421ca7ab
CK		 2873struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2874 struct radeon_bo *bo);
e971bd5e
CK		 2875struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2876 struct radeon_vm *vm,
2877 struct radeon_bo *bo);
2878int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2879 struct radeon_bo_va *bo_va,
2880 uint64_t offset,
2881 uint32_t flags);
036bf46a
CK		 2882void radeon_vm_bo_rmv(struct radeon_device *rdev,
2883 struct radeon_bo_va *bo_va);
721604a1 2884
f122c610
AD		 2885/* audio */
2886void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2887struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2888struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
832eafaf
AD		 2889void r600_audio_enable(struct radeon_device *rdev,
2890 struct r600_audio_pin *pin,
d3d8c141 2891 u8 enable_mask);
832eafaf
AD		 2892void dce6_audio_enable(struct radeon_device *rdev,
2893 struct r600_audio_pin *pin,
d3d8c141 2894 u8 enable_mask);
721604a1 2895
16cdf04d
AD		 2896/*
2897 * R600 vram scratch functions
2898 */
2899int r600_vram_scratch_init(struct radeon_device *rdev);
2900void r600_vram_scratch_fini(struct radeon_device *rdev);
2901
285484e2
JG		 2902/*
2903 * r600 cs checking helper
2904 */
2905unsigned r600_mip_minify(unsigned size, unsigned level);
2906bool r600_fmt_is_valid_color(u32 format);
2907bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2908int r600_fmt_get_blocksize(u32 format);
2909int r600_fmt_get_nblocksx(u32 format, u32 w);
2910int r600_fmt_get_nblocksy(u32 format, u32 h);
2911
3574dda4
DV		 2912/*
2913 * r600 functions used by radeon_encoder.c
2914 */
1b688d08
RM		 2915struct radeon_hdmi_acr {
2916 u32 clock;
2917
2918 int n_32khz;
2919 int cts_32khz;
2920
2921 int n_44_1khz;
2922 int cts_44_1khz;
2923
2924 int n_48khz;
2925 int cts_48khz;
2926
2927};
2928
e55d3e6c
RM		 2929extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2930
416a2bd2
AD		 2931extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2932 u32 tiling_pipe_num,
2933 u32 max_rb_num,
2934 u32 total_max_rb_num,
2935 u32 enabled_rb_mask);
fe251e2f 2936
e55d3e6c
RM		 2937/*
2938 * evergreen functions used by radeon_encoder.c
2939 */
2940
0af62b01 2941extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2942extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2943
c4917074
AD		 2944/* radeon_acpi.c */
2945#if defined(CONFIG_ACPI)
2946extern int radeon_acpi_init(struct radeon_device *rdev);
2947extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2948extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2949extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2950 u8 perf_req, bool advertise);
dc50ba7f 2951extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2952#else
2953static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2954static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2955#endif
d7a2952f 2956
c38f34b5
IH		 2957int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2958 struct radeon_cs_packet *pkt,
2959 unsigned idx);
9ffb7a6d 2960bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2961void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2962 struct radeon_cs_packet *pkt);
e9716993 2963int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
1d0c0942 2964 struct radeon_bo_list **cs_reloc,
e9716993 2965 int nomm);
40592a17
IH		 2966int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2967 uint32_t *vline_start_end,
2968 uint32_t *vline_status);
c38f34b5 2969
4c788679
JG		 2970#include "radeon_object.h"
2971
771fe6b9 2972#endif
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