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0a10c851 DV |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | ||
29 | #include <linux/console.h> | |
30 | #include <drm/drmP.h> | |
31 | #include <drm/drm_crtc_helper.h> | |
32 | #include <drm/radeon_drm.h> | |
33 | #include <linux/vgaarb.h> | |
34 | #include <linux/vga_switcheroo.h> | |
35 | #include "radeon_reg.h" | |
36 | #include "radeon.h" | |
37 | #include "radeon_asic.h" | |
38 | #include "atom.h" | |
39 | ||
40 | /* | |
41 | * Registers accessors functions. | |
42 | */ | |
43 | static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) | |
44 | { | |
45 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
46 | BUG_ON(1); | |
47 | return 0; | |
48 | } | |
49 | ||
50 | static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
51 | { | |
52 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
53 | reg, v); | |
54 | BUG_ON(1); | |
55 | } | |
56 | ||
57 | static void radeon_register_accessor_init(struct radeon_device *rdev) | |
58 | { | |
59 | rdev->mc_rreg = &radeon_invalid_rreg; | |
60 | rdev->mc_wreg = &radeon_invalid_wreg; | |
61 | rdev->pll_rreg = &radeon_invalid_rreg; | |
62 | rdev->pll_wreg = &radeon_invalid_wreg; | |
63 | rdev->pciep_rreg = &radeon_invalid_rreg; | |
64 | rdev->pciep_wreg = &radeon_invalid_wreg; | |
65 | ||
66 | /* Don't change order as we are overridding accessor. */ | |
67 | if (rdev->family < CHIP_RV515) { | |
68 | rdev->pcie_reg_mask = 0xff; | |
69 | } else { | |
70 | rdev->pcie_reg_mask = 0x7ff; | |
71 | } | |
72 | /* FIXME: not sure here */ | |
73 | if (rdev->family <= CHIP_R580) { | |
74 | rdev->pll_rreg = &r100_pll_rreg; | |
75 | rdev->pll_wreg = &r100_pll_wreg; | |
76 | } | |
77 | if (rdev->family >= CHIP_R420) { | |
78 | rdev->mc_rreg = &r420_mc_rreg; | |
79 | rdev->mc_wreg = &r420_mc_wreg; | |
80 | } | |
81 | if (rdev->family >= CHIP_RV515) { | |
82 | rdev->mc_rreg = &rv515_mc_rreg; | |
83 | rdev->mc_wreg = &rv515_mc_wreg; | |
84 | } | |
85 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { | |
86 | rdev->mc_rreg = &rs400_mc_rreg; | |
87 | rdev->mc_wreg = &rs400_mc_wreg; | |
88 | } | |
89 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { | |
90 | rdev->mc_rreg = &rs690_mc_rreg; | |
91 | rdev->mc_wreg = &rs690_mc_wreg; | |
92 | } | |
93 | if (rdev->family == CHIP_RS600) { | |
94 | rdev->mc_rreg = &rs600_mc_rreg; | |
95 | rdev->mc_wreg = &rs600_mc_wreg; | |
96 | } | |
b4df8be1 | 97 | if (rdev->family >= CHIP_R600) { |
0a10c851 DV |
98 | rdev->pciep_rreg = &r600_pciep_rreg; |
99 | rdev->pciep_wreg = &r600_pciep_wreg; | |
100 | } | |
101 | } | |
102 | ||
103 | ||
104 | /* helper to disable agp */ | |
105 | void radeon_agp_disable(struct radeon_device *rdev) | |
106 | { | |
107 | rdev->flags &= ~RADEON_IS_AGP; | |
108 | if (rdev->family >= CHIP_R600) { | |
109 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
110 | rdev->flags |= RADEON_IS_PCIE; | |
111 | } else if (rdev->family >= CHIP_RV515 || | |
112 | rdev->family == CHIP_RV380 || | |
113 | rdev->family == CHIP_RV410 || | |
114 | rdev->family == CHIP_R423) { | |
115 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
116 | rdev->flags |= RADEON_IS_PCIE; | |
117 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; | |
118 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; | |
119 | } else { | |
120 | DRM_INFO("Forcing AGP to PCI mode\n"); | |
121 | rdev->flags |= RADEON_IS_PCI; | |
122 | rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; | |
123 | rdev->asic->gart_set_page = &r100_pci_gart_set_page; | |
124 | } | |
125 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
126 | } | |
127 | ||
128 | /* | |
129 | * ASIC | |
130 | */ | |
48e7a5f1 DV |
131 | static struct radeon_asic r100_asic = { |
132 | .init = &r100_init, | |
133 | .fini = &r100_fini, | |
134 | .suspend = &r100_suspend, | |
135 | .resume = &r100_resume, | |
136 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 137 | .gpu_is_lockup = &r100_gpu_is_lockup, |
a2d07b74 | 138 | .asic_reset = &r100_asic_reset, |
48e7a5f1 DV |
139 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
140 | .gart_set_page = &r100_pci_gart_set_page, | |
48e7a5f1 DV |
141 | .ring_start = &r100_ring_start, |
142 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
143 | .ring = { |
144 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
145 | .ib_execute = &r100_ring_ib_execute, | |
146 | .emit_fence = &r100_fence_ring_emit, | |
147 | .emit_semaphore = &r100_semaphore_ring_emit, | |
148 | } | |
149 | }, | |
48e7a5f1 DV |
150 | .irq_set = &r100_irq_set, |
151 | .irq_process = &r100_irq_process, | |
152 | .get_vblank_counter = &r100_get_vblank_counter, | |
48e7a5f1 DV |
153 | .cs_parse = &r100_cs_parse, |
154 | .copy_blit = &r100_copy_blit, | |
155 | .copy_dma = NULL, | |
156 | .copy = &r100_copy_blit, | |
157 | .get_engine_clock = &radeon_legacy_get_engine_clock, | |
158 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
159 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
160 | .set_memory_clock = NULL, | |
161 | .get_pcie_lanes = NULL, | |
162 | .set_pcie_lanes = NULL, | |
163 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
164 | .set_surface_reg = r100_set_surface_reg, | |
165 | .clear_surface_reg = r100_clear_surface_reg, | |
166 | .bandwidth_update = &r100_bandwidth_update, | |
167 | .hpd_init = &r100_hpd_init, | |
168 | .hpd_fini = &r100_hpd_fini, | |
169 | .hpd_sense = &r100_hpd_sense, | |
170 | .hpd_set_polarity = &r100_hpd_set_polarity, | |
171 | .ioctl_wait_idle = NULL, | |
def9ba9c | 172 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
173 | .pm_misc = &r100_pm_misc, |
174 | .pm_prepare = &r100_pm_prepare, | |
175 | .pm_finish = &r100_pm_finish, | |
ce8f5370 AD |
176 | .pm_init_profile = &r100_pm_init_profile, |
177 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
178 | .pre_page_flip = &r100_pre_page_flip, |
179 | .page_flip = &r100_page_flip, | |
180 | .post_page_flip = &r100_post_page_flip, | |
3ae19b75 | 181 | .wait_for_vblank = &r100_wait_for_vblank, |
48e7a5f1 DV |
182 | }; |
183 | ||
184 | static struct radeon_asic r200_asic = { | |
185 | .init = &r100_init, | |
186 | .fini = &r100_fini, | |
187 | .suspend = &r100_suspend, | |
188 | .resume = &r100_resume, | |
189 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 190 | .gpu_is_lockup = &r100_gpu_is_lockup, |
a2d07b74 | 191 | .asic_reset = &r100_asic_reset, |
48e7a5f1 DV |
192 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
193 | .gart_set_page = &r100_pci_gart_set_page, | |
48e7a5f1 DV |
194 | .ring_start = &r100_ring_start, |
195 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
196 | .ring = { |
197 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
198 | .ib_execute = &r100_ring_ib_execute, | |
199 | .emit_fence = &r100_fence_ring_emit, | |
200 | .emit_semaphore = &r100_semaphore_ring_emit, | |
201 | } | |
202 | }, | |
48e7a5f1 DV |
203 | .irq_set = &r100_irq_set, |
204 | .irq_process = &r100_irq_process, | |
205 | .get_vblank_counter = &r100_get_vblank_counter, | |
48e7a5f1 DV |
206 | .cs_parse = &r100_cs_parse, |
207 | .copy_blit = &r100_copy_blit, | |
208 | .copy_dma = &r200_copy_dma, | |
209 | .copy = &r100_copy_blit, | |
210 | .get_engine_clock = &radeon_legacy_get_engine_clock, | |
211 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
212 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
213 | .set_memory_clock = NULL, | |
214 | .set_pcie_lanes = NULL, | |
215 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
216 | .set_surface_reg = r100_set_surface_reg, | |
217 | .clear_surface_reg = r100_clear_surface_reg, | |
218 | .bandwidth_update = &r100_bandwidth_update, | |
219 | .hpd_init = &r100_hpd_init, | |
220 | .hpd_fini = &r100_hpd_fini, | |
221 | .hpd_sense = &r100_hpd_sense, | |
222 | .hpd_set_polarity = &r100_hpd_set_polarity, | |
223 | .ioctl_wait_idle = NULL, | |
def9ba9c | 224 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
225 | .pm_misc = &r100_pm_misc, |
226 | .pm_prepare = &r100_pm_prepare, | |
227 | .pm_finish = &r100_pm_finish, | |
ce8f5370 AD |
228 | .pm_init_profile = &r100_pm_init_profile, |
229 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
230 | .pre_page_flip = &r100_pre_page_flip, |
231 | .page_flip = &r100_page_flip, | |
232 | .post_page_flip = &r100_post_page_flip, | |
3ae19b75 | 233 | .wait_for_vblank = &r100_wait_for_vblank, |
48e7a5f1 DV |
234 | }; |
235 | ||
236 | static struct radeon_asic r300_asic = { | |
237 | .init = &r300_init, | |
238 | .fini = &r300_fini, | |
239 | .suspend = &r300_suspend, | |
240 | .resume = &r300_resume, | |
241 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 242 | .gpu_is_lockup = &r300_gpu_is_lockup, |
a2d07b74 | 243 | .asic_reset = &r300_asic_reset, |
48e7a5f1 DV |
244 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
245 | .gart_set_page = &r100_pci_gart_set_page, | |
48e7a5f1 DV |
246 | .ring_start = &r300_ring_start, |
247 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
248 | .ring = { |
249 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
250 | .ib_execute = &r100_ring_ib_execute, | |
251 | .emit_fence = &r300_fence_ring_emit, | |
252 | .emit_semaphore = &r100_semaphore_ring_emit, | |
253 | } | |
254 | }, | |
48e7a5f1 DV |
255 | .irq_set = &r100_irq_set, |
256 | .irq_process = &r100_irq_process, | |
257 | .get_vblank_counter = &r100_get_vblank_counter, | |
48e7a5f1 DV |
258 | .cs_parse = &r300_cs_parse, |
259 | .copy_blit = &r100_copy_blit, | |
260 | .copy_dma = &r200_copy_dma, | |
261 | .copy = &r100_copy_blit, | |
262 | .get_engine_clock = &radeon_legacy_get_engine_clock, | |
263 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
264 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
265 | .set_memory_clock = NULL, | |
266 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
267 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
268 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
269 | .set_surface_reg = r100_set_surface_reg, | |
270 | .clear_surface_reg = r100_clear_surface_reg, | |
271 | .bandwidth_update = &r100_bandwidth_update, | |
272 | .hpd_init = &r100_hpd_init, | |
273 | .hpd_fini = &r100_hpd_fini, | |
274 | .hpd_sense = &r100_hpd_sense, | |
275 | .hpd_set_polarity = &r100_hpd_set_polarity, | |
276 | .ioctl_wait_idle = NULL, | |
def9ba9c | 277 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
278 | .pm_misc = &r100_pm_misc, |
279 | .pm_prepare = &r100_pm_prepare, | |
280 | .pm_finish = &r100_pm_finish, | |
ce8f5370 AD |
281 | .pm_init_profile = &r100_pm_init_profile, |
282 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
283 | .pre_page_flip = &r100_pre_page_flip, |
284 | .page_flip = &r100_page_flip, | |
285 | .post_page_flip = &r100_post_page_flip, | |
3ae19b75 | 286 | .wait_for_vblank = &r100_wait_for_vblank, |
48e7a5f1 DV |
287 | }; |
288 | ||
289 | static struct radeon_asic r300_asic_pcie = { | |
290 | .init = &r300_init, | |
291 | .fini = &r300_fini, | |
292 | .suspend = &r300_suspend, | |
293 | .resume = &r300_resume, | |
294 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 295 | .gpu_is_lockup = &r300_gpu_is_lockup, |
a2d07b74 | 296 | .asic_reset = &r300_asic_reset, |
48e7a5f1 DV |
297 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
298 | .gart_set_page = &rv370_pcie_gart_set_page, | |
48e7a5f1 DV |
299 | .ring_start = &r300_ring_start, |
300 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
301 | .ring = { |
302 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
303 | .ib_execute = &r100_ring_ib_execute, | |
304 | .emit_fence = &r300_fence_ring_emit, | |
305 | .emit_semaphore = &r100_semaphore_ring_emit, | |
306 | } | |
307 | }, | |
48e7a5f1 DV |
308 | .irq_set = &r100_irq_set, |
309 | .irq_process = &r100_irq_process, | |
310 | .get_vblank_counter = &r100_get_vblank_counter, | |
48e7a5f1 DV |
311 | .cs_parse = &r300_cs_parse, |
312 | .copy_blit = &r100_copy_blit, | |
313 | .copy_dma = &r200_copy_dma, | |
314 | .copy = &r100_copy_blit, | |
315 | .get_engine_clock = &radeon_legacy_get_engine_clock, | |
316 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
317 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
318 | .set_memory_clock = NULL, | |
319 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
320 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
321 | .set_surface_reg = r100_set_surface_reg, | |
322 | .clear_surface_reg = r100_clear_surface_reg, | |
323 | .bandwidth_update = &r100_bandwidth_update, | |
324 | .hpd_init = &r100_hpd_init, | |
325 | .hpd_fini = &r100_hpd_fini, | |
326 | .hpd_sense = &r100_hpd_sense, | |
327 | .hpd_set_polarity = &r100_hpd_set_polarity, | |
328 | .ioctl_wait_idle = NULL, | |
def9ba9c | 329 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
330 | .pm_misc = &r100_pm_misc, |
331 | .pm_prepare = &r100_pm_prepare, | |
332 | .pm_finish = &r100_pm_finish, | |
ce8f5370 AD |
333 | .pm_init_profile = &r100_pm_init_profile, |
334 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
335 | .pre_page_flip = &r100_pre_page_flip, |
336 | .page_flip = &r100_page_flip, | |
337 | .post_page_flip = &r100_post_page_flip, | |
3ae19b75 | 338 | .wait_for_vblank = &r100_wait_for_vblank, |
48e7a5f1 DV |
339 | }; |
340 | ||
341 | static struct radeon_asic r420_asic = { | |
342 | .init = &r420_init, | |
343 | .fini = &r420_fini, | |
344 | .suspend = &r420_suspend, | |
345 | .resume = &r420_resume, | |
346 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 347 | .gpu_is_lockup = &r300_gpu_is_lockup, |
a2d07b74 | 348 | .asic_reset = &r300_asic_reset, |
48e7a5f1 DV |
349 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
350 | .gart_set_page = &rv370_pcie_gart_set_page, | |
48e7a5f1 DV |
351 | .ring_start = &r300_ring_start, |
352 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
353 | .ring = { |
354 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
355 | .ib_execute = &r100_ring_ib_execute, | |
356 | .emit_fence = &r300_fence_ring_emit, | |
357 | .emit_semaphore = &r100_semaphore_ring_emit, | |
358 | } | |
359 | }, | |
48e7a5f1 DV |
360 | .irq_set = &r100_irq_set, |
361 | .irq_process = &r100_irq_process, | |
362 | .get_vblank_counter = &r100_get_vblank_counter, | |
48e7a5f1 DV |
363 | .cs_parse = &r300_cs_parse, |
364 | .copy_blit = &r100_copy_blit, | |
365 | .copy_dma = &r200_copy_dma, | |
366 | .copy = &r100_copy_blit, | |
367 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
368 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
369 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
370 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
371 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
372 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
373 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
374 | .set_surface_reg = r100_set_surface_reg, | |
375 | .clear_surface_reg = r100_clear_surface_reg, | |
376 | .bandwidth_update = &r100_bandwidth_update, | |
377 | .hpd_init = &r100_hpd_init, | |
378 | .hpd_fini = &r100_hpd_fini, | |
379 | .hpd_sense = &r100_hpd_sense, | |
380 | .hpd_set_polarity = &r100_hpd_set_polarity, | |
381 | .ioctl_wait_idle = NULL, | |
def9ba9c | 382 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
383 | .pm_misc = &r100_pm_misc, |
384 | .pm_prepare = &r100_pm_prepare, | |
385 | .pm_finish = &r100_pm_finish, | |
ce8f5370 AD |
386 | .pm_init_profile = &r420_pm_init_profile, |
387 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
388 | .pre_page_flip = &r100_pre_page_flip, |
389 | .page_flip = &r100_page_flip, | |
390 | .post_page_flip = &r100_post_page_flip, | |
3ae19b75 | 391 | .wait_for_vblank = &r100_wait_for_vblank, |
48e7a5f1 DV |
392 | }; |
393 | ||
394 | static struct radeon_asic rs400_asic = { | |
395 | .init = &rs400_init, | |
396 | .fini = &rs400_fini, | |
397 | .suspend = &rs400_suspend, | |
398 | .resume = &rs400_resume, | |
399 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 400 | .gpu_is_lockup = &r300_gpu_is_lockup, |
a2d07b74 | 401 | .asic_reset = &r300_asic_reset, |
48e7a5f1 DV |
402 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
403 | .gart_set_page = &rs400_gart_set_page, | |
48e7a5f1 DV |
404 | .ring_start = &r300_ring_start, |
405 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
406 | .ring = { |
407 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
408 | .ib_execute = &r100_ring_ib_execute, | |
409 | .emit_fence = &r300_fence_ring_emit, | |
410 | .emit_semaphore = &r100_semaphore_ring_emit, | |
411 | } | |
412 | }, | |
48e7a5f1 DV |
413 | .irq_set = &r100_irq_set, |
414 | .irq_process = &r100_irq_process, | |
415 | .get_vblank_counter = &r100_get_vblank_counter, | |
48e7a5f1 DV |
416 | .cs_parse = &r300_cs_parse, |
417 | .copy_blit = &r100_copy_blit, | |
418 | .copy_dma = &r200_copy_dma, | |
419 | .copy = &r100_copy_blit, | |
420 | .get_engine_clock = &radeon_legacy_get_engine_clock, | |
421 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
422 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
423 | .set_memory_clock = NULL, | |
424 | .get_pcie_lanes = NULL, | |
425 | .set_pcie_lanes = NULL, | |
426 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
427 | .set_surface_reg = r100_set_surface_reg, | |
428 | .clear_surface_reg = r100_clear_surface_reg, | |
429 | .bandwidth_update = &r100_bandwidth_update, | |
430 | .hpd_init = &r100_hpd_init, | |
431 | .hpd_fini = &r100_hpd_fini, | |
432 | .hpd_sense = &r100_hpd_sense, | |
433 | .hpd_set_polarity = &r100_hpd_set_polarity, | |
434 | .ioctl_wait_idle = NULL, | |
def9ba9c | 435 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
436 | .pm_misc = &r100_pm_misc, |
437 | .pm_prepare = &r100_pm_prepare, | |
438 | .pm_finish = &r100_pm_finish, | |
ce8f5370 AD |
439 | .pm_init_profile = &r100_pm_init_profile, |
440 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
441 | .pre_page_flip = &r100_pre_page_flip, |
442 | .page_flip = &r100_page_flip, | |
443 | .post_page_flip = &r100_post_page_flip, | |
3ae19b75 | 444 | .wait_for_vblank = &r100_wait_for_vblank, |
48e7a5f1 DV |
445 | }; |
446 | ||
447 | static struct radeon_asic rs600_asic = { | |
448 | .init = &rs600_init, | |
449 | .fini = &rs600_fini, | |
450 | .suspend = &rs600_suspend, | |
451 | .resume = &rs600_resume, | |
452 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 453 | .gpu_is_lockup = &r300_gpu_is_lockup, |
90aca4d2 | 454 | .asic_reset = &rs600_asic_reset, |
48e7a5f1 DV |
455 | .gart_tlb_flush = &rs600_gart_tlb_flush, |
456 | .gart_set_page = &rs600_gart_set_page, | |
48e7a5f1 DV |
457 | .ring_start = &r300_ring_start, |
458 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
459 | .ring = { |
460 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
461 | .ib_execute = &r100_ring_ib_execute, | |
462 | .emit_fence = &r300_fence_ring_emit, | |
463 | .emit_semaphore = &r100_semaphore_ring_emit, | |
464 | } | |
465 | }, | |
48e7a5f1 DV |
466 | .irq_set = &rs600_irq_set, |
467 | .irq_process = &rs600_irq_process, | |
468 | .get_vblank_counter = &rs600_get_vblank_counter, | |
48e7a5f1 DV |
469 | .cs_parse = &r300_cs_parse, |
470 | .copy_blit = &r100_copy_blit, | |
471 | .copy_dma = &r200_copy_dma, | |
472 | .copy = &r100_copy_blit, | |
473 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
474 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
475 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
476 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
477 | .get_pcie_lanes = NULL, | |
478 | .set_pcie_lanes = NULL, | |
479 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
480 | .set_surface_reg = r100_set_surface_reg, | |
481 | .clear_surface_reg = r100_clear_surface_reg, | |
482 | .bandwidth_update = &rs600_bandwidth_update, | |
483 | .hpd_init = &rs600_hpd_init, | |
484 | .hpd_fini = &rs600_hpd_fini, | |
485 | .hpd_sense = &rs600_hpd_sense, | |
486 | .hpd_set_polarity = &rs600_hpd_set_polarity, | |
487 | .ioctl_wait_idle = NULL, | |
def9ba9c | 488 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
489 | .pm_misc = &rs600_pm_misc, |
490 | .pm_prepare = &rs600_pm_prepare, | |
491 | .pm_finish = &rs600_pm_finish, | |
ce8f5370 AD |
492 | .pm_init_profile = &r420_pm_init_profile, |
493 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
494 | .pre_page_flip = &rs600_pre_page_flip, |
495 | .page_flip = &rs600_page_flip, | |
496 | .post_page_flip = &rs600_post_page_flip, | |
3ae19b75 | 497 | .wait_for_vblank = &avivo_wait_for_vblank, |
48e7a5f1 DV |
498 | }; |
499 | ||
500 | static struct radeon_asic rs690_asic = { | |
501 | .init = &rs690_init, | |
502 | .fini = &rs690_fini, | |
503 | .suspend = &rs690_suspend, | |
504 | .resume = &rs690_resume, | |
505 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 506 | .gpu_is_lockup = &r300_gpu_is_lockup, |
90aca4d2 | 507 | .asic_reset = &rs600_asic_reset, |
48e7a5f1 DV |
508 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
509 | .gart_set_page = &rs400_gart_set_page, | |
48e7a5f1 DV |
510 | .ring_start = &r300_ring_start, |
511 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
512 | .ring = { |
513 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
514 | .ib_execute = &r100_ring_ib_execute, | |
515 | .emit_fence = &r300_fence_ring_emit, | |
516 | .emit_semaphore = &r100_semaphore_ring_emit, | |
517 | } | |
518 | }, | |
48e7a5f1 DV |
519 | .irq_set = &rs600_irq_set, |
520 | .irq_process = &rs600_irq_process, | |
521 | .get_vblank_counter = &rs600_get_vblank_counter, | |
48e7a5f1 DV |
522 | .cs_parse = &r300_cs_parse, |
523 | .copy_blit = &r100_copy_blit, | |
524 | .copy_dma = &r200_copy_dma, | |
525 | .copy = &r200_copy_dma, | |
526 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
527 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
528 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
529 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
530 | .get_pcie_lanes = NULL, | |
531 | .set_pcie_lanes = NULL, | |
532 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
533 | .set_surface_reg = r100_set_surface_reg, | |
534 | .clear_surface_reg = r100_clear_surface_reg, | |
535 | .bandwidth_update = &rs690_bandwidth_update, | |
536 | .hpd_init = &rs600_hpd_init, | |
537 | .hpd_fini = &rs600_hpd_fini, | |
538 | .hpd_sense = &rs600_hpd_sense, | |
539 | .hpd_set_polarity = &rs600_hpd_set_polarity, | |
540 | .ioctl_wait_idle = NULL, | |
def9ba9c | 541 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
542 | .pm_misc = &rs600_pm_misc, |
543 | .pm_prepare = &rs600_pm_prepare, | |
544 | .pm_finish = &rs600_pm_finish, | |
ce8f5370 AD |
545 | .pm_init_profile = &r420_pm_init_profile, |
546 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
547 | .pre_page_flip = &rs600_pre_page_flip, |
548 | .page_flip = &rs600_page_flip, | |
549 | .post_page_flip = &rs600_post_page_flip, | |
3ae19b75 | 550 | .wait_for_vblank = &avivo_wait_for_vblank, |
48e7a5f1 DV |
551 | }; |
552 | ||
553 | static struct radeon_asic rv515_asic = { | |
554 | .init = &rv515_init, | |
555 | .fini = &rv515_fini, | |
556 | .suspend = &rv515_suspend, | |
557 | .resume = &rv515_resume, | |
558 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 559 | .gpu_is_lockup = &r300_gpu_is_lockup, |
90aca4d2 | 560 | .asic_reset = &rs600_asic_reset, |
48e7a5f1 DV |
561 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
562 | .gart_set_page = &rv370_pcie_gart_set_page, | |
48e7a5f1 DV |
563 | .ring_start = &rv515_ring_start, |
564 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
565 | .ring = { |
566 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
567 | .ib_execute = &r100_ring_ib_execute, | |
568 | .emit_fence = &r300_fence_ring_emit, | |
569 | .emit_semaphore = &r100_semaphore_ring_emit, | |
570 | } | |
571 | }, | |
48e7a5f1 DV |
572 | .irq_set = &rs600_irq_set, |
573 | .irq_process = &rs600_irq_process, | |
574 | .get_vblank_counter = &rs600_get_vblank_counter, | |
48e7a5f1 DV |
575 | .cs_parse = &r300_cs_parse, |
576 | .copy_blit = &r100_copy_blit, | |
577 | .copy_dma = &r200_copy_dma, | |
578 | .copy = &r100_copy_blit, | |
579 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
580 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
581 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
582 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
583 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
584 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
585 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
586 | .set_surface_reg = r100_set_surface_reg, | |
587 | .clear_surface_reg = r100_clear_surface_reg, | |
588 | .bandwidth_update = &rv515_bandwidth_update, | |
589 | .hpd_init = &rs600_hpd_init, | |
590 | .hpd_fini = &rs600_hpd_fini, | |
591 | .hpd_sense = &rs600_hpd_sense, | |
592 | .hpd_set_polarity = &rs600_hpd_set_polarity, | |
593 | .ioctl_wait_idle = NULL, | |
def9ba9c | 594 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
595 | .pm_misc = &rs600_pm_misc, |
596 | .pm_prepare = &rs600_pm_prepare, | |
597 | .pm_finish = &rs600_pm_finish, | |
ce8f5370 AD |
598 | .pm_init_profile = &r420_pm_init_profile, |
599 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
600 | .pre_page_flip = &rs600_pre_page_flip, |
601 | .page_flip = &rs600_page_flip, | |
602 | .post_page_flip = &rs600_post_page_flip, | |
3ae19b75 | 603 | .wait_for_vblank = &avivo_wait_for_vblank, |
48e7a5f1 DV |
604 | }; |
605 | ||
606 | static struct radeon_asic r520_asic = { | |
607 | .init = &r520_init, | |
608 | .fini = &rv515_fini, | |
609 | .suspend = &rv515_suspend, | |
610 | .resume = &r520_resume, | |
611 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 612 | .gpu_is_lockup = &r300_gpu_is_lockup, |
90aca4d2 | 613 | .asic_reset = &rs600_asic_reset, |
48e7a5f1 DV |
614 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
615 | .gart_set_page = &rv370_pcie_gart_set_page, | |
48e7a5f1 DV |
616 | .ring_start = &rv515_ring_start, |
617 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
618 | .ring = { |
619 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
620 | .ib_execute = &r100_ring_ib_execute, | |
621 | .emit_fence = &r300_fence_ring_emit, | |
622 | .emit_semaphore = &r100_semaphore_ring_emit, | |
623 | } | |
624 | }, | |
48e7a5f1 DV |
625 | .irq_set = &rs600_irq_set, |
626 | .irq_process = &rs600_irq_process, | |
627 | .get_vblank_counter = &rs600_get_vblank_counter, | |
48e7a5f1 DV |
628 | .cs_parse = &r300_cs_parse, |
629 | .copy_blit = &r100_copy_blit, | |
630 | .copy_dma = &r200_copy_dma, | |
631 | .copy = &r100_copy_blit, | |
632 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
633 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
634 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
635 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
636 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
637 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
638 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
639 | .set_surface_reg = r100_set_surface_reg, | |
640 | .clear_surface_reg = r100_clear_surface_reg, | |
641 | .bandwidth_update = &rv515_bandwidth_update, | |
642 | .hpd_init = &rs600_hpd_init, | |
643 | .hpd_fini = &rs600_hpd_fini, | |
644 | .hpd_sense = &rs600_hpd_sense, | |
645 | .hpd_set_polarity = &rs600_hpd_set_polarity, | |
646 | .ioctl_wait_idle = NULL, | |
def9ba9c | 647 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
648 | .pm_misc = &rs600_pm_misc, |
649 | .pm_prepare = &rs600_pm_prepare, | |
650 | .pm_finish = &rs600_pm_finish, | |
ce8f5370 AD |
651 | .pm_init_profile = &r420_pm_init_profile, |
652 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
653 | .pre_page_flip = &rs600_pre_page_flip, |
654 | .page_flip = &rs600_page_flip, | |
655 | .post_page_flip = &rs600_post_page_flip, | |
3ae19b75 | 656 | .wait_for_vblank = &avivo_wait_for_vblank, |
48e7a5f1 DV |
657 | }; |
658 | ||
659 | static struct radeon_asic r600_asic = { | |
660 | .init = &r600_init, | |
661 | .fini = &r600_fini, | |
662 | .suspend = &r600_suspend, | |
663 | .resume = &r600_resume, | |
48e7a5f1 | 664 | .vga_set_state = &r600_vga_set_state, |
225758d8 | 665 | .gpu_is_lockup = &r600_gpu_is_lockup, |
a2d07b74 | 666 | .asic_reset = &r600_asic_reset, |
48e7a5f1 DV |
667 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
668 | .gart_set_page = &rs600_gart_set_page, | |
669 | .ring_test = &r600_ring_test, | |
4c87bc26 CK |
670 | .ring = { |
671 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
672 | .ib_execute = &r600_ring_ib_execute, | |
673 | .emit_fence = &r600_fence_ring_emit, | |
674 | .emit_semaphore = &r600_semaphore_ring_emit, | |
675 | } | |
676 | }, | |
48e7a5f1 DV |
677 | .irq_set = &r600_irq_set, |
678 | .irq_process = &r600_irq_process, | |
679 | .get_vblank_counter = &rs600_get_vblank_counter, | |
48e7a5f1 DV |
680 | .cs_parse = &r600_cs_parse, |
681 | .copy_blit = &r600_copy_blit, | |
20633442 | 682 | .copy_dma = NULL, |
48e7a5f1 DV |
683 | .copy = &r600_copy_blit, |
684 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
685 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
686 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
687 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
3313e3d4 AD |
688 | .get_pcie_lanes = &r600_get_pcie_lanes, |
689 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
48e7a5f1 DV |
690 | .set_clock_gating = NULL, |
691 | .set_surface_reg = r600_set_surface_reg, | |
692 | .clear_surface_reg = r600_clear_surface_reg, | |
693 | .bandwidth_update = &rv515_bandwidth_update, | |
694 | .hpd_init = &r600_hpd_init, | |
695 | .hpd_fini = &r600_hpd_fini, | |
696 | .hpd_sense = &r600_hpd_sense, | |
697 | .hpd_set_polarity = &r600_hpd_set_polarity, | |
698 | .ioctl_wait_idle = r600_ioctl_wait_idle, | |
def9ba9c | 699 | .gui_idle = &r600_gui_idle, |
49e02b73 AD |
700 | .pm_misc = &r600_pm_misc, |
701 | .pm_prepare = &rs600_pm_prepare, | |
702 | .pm_finish = &rs600_pm_finish, | |
ce8f5370 AD |
703 | .pm_init_profile = &r600_pm_init_profile, |
704 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | |
6f34be50 AD |
705 | .pre_page_flip = &rs600_pre_page_flip, |
706 | .page_flip = &rs600_page_flip, | |
707 | .post_page_flip = &rs600_post_page_flip, | |
3ae19b75 | 708 | .wait_for_vblank = &avivo_wait_for_vblank, |
48e7a5f1 DV |
709 | }; |
710 | ||
f47299c5 AD |
711 | static struct radeon_asic rs780_asic = { |
712 | .init = &r600_init, | |
713 | .fini = &r600_fini, | |
714 | .suspend = &r600_suspend, | |
715 | .resume = &r600_resume, | |
90aca4d2 | 716 | .gpu_is_lockup = &r600_gpu_is_lockup, |
f47299c5 | 717 | .vga_set_state = &r600_vga_set_state, |
a2d07b74 | 718 | .asic_reset = &r600_asic_reset, |
f47299c5 AD |
719 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
720 | .gart_set_page = &rs600_gart_set_page, | |
721 | .ring_test = &r600_ring_test, | |
4c87bc26 CK |
722 | .ring = { |
723 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
724 | .ib_execute = &r600_ring_ib_execute, | |
725 | .emit_fence = &r600_fence_ring_emit, | |
726 | .emit_semaphore = &r600_semaphore_ring_emit, | |
727 | } | |
728 | }, | |
f47299c5 AD |
729 | .irq_set = &r600_irq_set, |
730 | .irq_process = &r600_irq_process, | |
731 | .get_vblank_counter = &rs600_get_vblank_counter, | |
f47299c5 AD |
732 | .cs_parse = &r600_cs_parse, |
733 | .copy_blit = &r600_copy_blit, | |
20633442 | 734 | .copy_dma = NULL, |
f47299c5 AD |
735 | .copy = &r600_copy_blit, |
736 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
737 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
738 | .get_memory_clock = NULL, | |
739 | .set_memory_clock = NULL, | |
740 | .get_pcie_lanes = NULL, | |
741 | .set_pcie_lanes = NULL, | |
742 | .set_clock_gating = NULL, | |
743 | .set_surface_reg = r600_set_surface_reg, | |
744 | .clear_surface_reg = r600_clear_surface_reg, | |
745 | .bandwidth_update = &rs690_bandwidth_update, | |
746 | .hpd_init = &r600_hpd_init, | |
747 | .hpd_fini = &r600_hpd_fini, | |
748 | .hpd_sense = &r600_hpd_sense, | |
749 | .hpd_set_polarity = &r600_hpd_set_polarity, | |
750 | .ioctl_wait_idle = r600_ioctl_wait_idle, | |
def9ba9c | 751 | .gui_idle = &r600_gui_idle, |
49e02b73 AD |
752 | .pm_misc = &r600_pm_misc, |
753 | .pm_prepare = &rs600_pm_prepare, | |
754 | .pm_finish = &rs600_pm_finish, | |
ce8f5370 AD |
755 | .pm_init_profile = &rs780_pm_init_profile, |
756 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | |
6f34be50 AD |
757 | .pre_page_flip = &rs600_pre_page_flip, |
758 | .page_flip = &rs600_page_flip, | |
759 | .post_page_flip = &rs600_post_page_flip, | |
3ae19b75 | 760 | .wait_for_vblank = &avivo_wait_for_vblank, |
f47299c5 AD |
761 | }; |
762 | ||
48e7a5f1 DV |
763 | static struct radeon_asic rv770_asic = { |
764 | .init = &rv770_init, | |
765 | .fini = &rv770_fini, | |
766 | .suspend = &rv770_suspend, | |
767 | .resume = &rv770_resume, | |
a2d07b74 | 768 | .asic_reset = &r600_asic_reset, |
225758d8 | 769 | .gpu_is_lockup = &r600_gpu_is_lockup, |
48e7a5f1 DV |
770 | .vga_set_state = &r600_vga_set_state, |
771 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, | |
772 | .gart_set_page = &rs600_gart_set_page, | |
773 | .ring_test = &r600_ring_test, | |
4c87bc26 CK |
774 | .ring = { |
775 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
776 | .ib_execute = &r600_ring_ib_execute, | |
777 | .emit_fence = &r600_fence_ring_emit, | |
778 | .emit_semaphore = &r600_semaphore_ring_emit, | |
779 | } | |
780 | }, | |
48e7a5f1 DV |
781 | .irq_set = &r600_irq_set, |
782 | .irq_process = &r600_irq_process, | |
783 | .get_vblank_counter = &rs600_get_vblank_counter, | |
48e7a5f1 DV |
784 | .cs_parse = &r600_cs_parse, |
785 | .copy_blit = &r600_copy_blit, | |
20633442 | 786 | .copy_dma = NULL, |
48e7a5f1 DV |
787 | .copy = &r600_copy_blit, |
788 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
789 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
790 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
791 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
3313e3d4 AD |
792 | .get_pcie_lanes = &r600_get_pcie_lanes, |
793 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
48e7a5f1 DV |
794 | .set_clock_gating = &radeon_atom_set_clock_gating, |
795 | .set_surface_reg = r600_set_surface_reg, | |
796 | .clear_surface_reg = r600_clear_surface_reg, | |
797 | .bandwidth_update = &rv515_bandwidth_update, | |
798 | .hpd_init = &r600_hpd_init, | |
799 | .hpd_fini = &r600_hpd_fini, | |
800 | .hpd_sense = &r600_hpd_sense, | |
801 | .hpd_set_polarity = &r600_hpd_set_polarity, | |
802 | .ioctl_wait_idle = r600_ioctl_wait_idle, | |
def9ba9c | 803 | .gui_idle = &r600_gui_idle, |
49e02b73 AD |
804 | .pm_misc = &rv770_pm_misc, |
805 | .pm_prepare = &rs600_pm_prepare, | |
806 | .pm_finish = &rs600_pm_finish, | |
ce8f5370 AD |
807 | .pm_init_profile = &r600_pm_init_profile, |
808 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | |
6f34be50 AD |
809 | .pre_page_flip = &rs600_pre_page_flip, |
810 | .page_flip = &rv770_page_flip, | |
811 | .post_page_flip = &rs600_post_page_flip, | |
3ae19b75 | 812 | .wait_for_vblank = &avivo_wait_for_vblank, |
48e7a5f1 DV |
813 | }; |
814 | ||
815 | static struct radeon_asic evergreen_asic = { | |
816 | .init = &evergreen_init, | |
817 | .fini = &evergreen_fini, | |
818 | .suspend = &evergreen_suspend, | |
819 | .resume = &evergreen_resume, | |
225758d8 | 820 | .gpu_is_lockup = &evergreen_gpu_is_lockup, |
a2d07b74 | 821 | .asic_reset = &evergreen_asic_reset, |
48e7a5f1 | 822 | .vga_set_state = &r600_vga_set_state, |
0fcdb61e | 823 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
48e7a5f1 | 824 | .gart_set_page = &rs600_gart_set_page, |
fe251e2f | 825 | .ring_test = &r600_ring_test, |
4c87bc26 CK |
826 | .ring = { |
827 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
828 | .ib_execute = &evergreen_ring_ib_execute, | |
829 | .emit_fence = &r600_fence_ring_emit, | |
830 | .emit_semaphore = &r600_semaphore_ring_emit, | |
831 | } | |
832 | }, | |
45f9a39b AD |
833 | .irq_set = &evergreen_irq_set, |
834 | .irq_process = &evergreen_irq_process, | |
835 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
cb5fcbd5 | 836 | .cs_parse = &evergreen_cs_parse, |
fb3d9e97 | 837 | .copy_blit = &r600_copy_blit, |
20633442 | 838 | .copy_dma = NULL, |
fb3d9e97 | 839 | .copy = &r600_copy_blit, |
48e7a5f1 DV |
840 | .get_engine_clock = &radeon_atom_get_engine_clock, |
841 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
842 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
843 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
3313e3d4 AD |
844 | .get_pcie_lanes = &r600_get_pcie_lanes, |
845 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
48e7a5f1 DV |
846 | .set_clock_gating = NULL, |
847 | .set_surface_reg = r600_set_surface_reg, | |
848 | .clear_surface_reg = r600_clear_surface_reg, | |
849 | .bandwidth_update = &evergreen_bandwidth_update, | |
850 | .hpd_init = &evergreen_hpd_init, | |
851 | .hpd_fini = &evergreen_hpd_fini, | |
852 | .hpd_sense = &evergreen_hpd_sense, | |
853 | .hpd_set_polarity = &evergreen_hpd_set_polarity, | |
97bfd0ac | 854 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
def9ba9c | 855 | .gui_idle = &r600_gui_idle, |
49e02b73 AD |
856 | .pm_misc = &evergreen_pm_misc, |
857 | .pm_prepare = &evergreen_pm_prepare, | |
858 | .pm_finish = &evergreen_pm_finish, | |
ce8f5370 AD |
859 | .pm_init_profile = &r600_pm_init_profile, |
860 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | |
6f34be50 AD |
861 | .pre_page_flip = &evergreen_pre_page_flip, |
862 | .page_flip = &evergreen_page_flip, | |
863 | .post_page_flip = &evergreen_post_page_flip, | |
3ae19b75 | 864 | .wait_for_vblank = &dce4_wait_for_vblank, |
48e7a5f1 DV |
865 | }; |
866 | ||
958261d1 AD |
867 | static struct radeon_asic sumo_asic = { |
868 | .init = &evergreen_init, | |
869 | .fini = &evergreen_fini, | |
870 | .suspend = &evergreen_suspend, | |
871 | .resume = &evergreen_resume, | |
958261d1 AD |
872 | .gpu_is_lockup = &evergreen_gpu_is_lockup, |
873 | .asic_reset = &evergreen_asic_reset, | |
874 | .vga_set_state = &r600_vga_set_state, | |
875 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
876 | .gart_set_page = &rs600_gart_set_page, | |
877 | .ring_test = &r600_ring_test, | |
4c87bc26 CK |
878 | .ring = { |
879 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
880 | .ib_execute = &evergreen_ring_ib_execute, | |
881 | .emit_fence = &r600_fence_ring_emit, | |
882 | .emit_semaphore = &r600_semaphore_ring_emit, | |
883 | } | |
884 | }, | |
958261d1 AD |
885 | .irq_set = &evergreen_irq_set, |
886 | .irq_process = &evergreen_irq_process, | |
887 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
958261d1 | 888 | .cs_parse = &evergreen_cs_parse, |
fb3d9e97 | 889 | .copy_blit = &r600_copy_blit, |
20633442 | 890 | .copy_dma = NULL, |
fb3d9e97 | 891 | .copy = &r600_copy_blit, |
958261d1 AD |
892 | .get_engine_clock = &radeon_atom_get_engine_clock, |
893 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
894 | .get_memory_clock = NULL, | |
895 | .set_memory_clock = NULL, | |
896 | .get_pcie_lanes = NULL, | |
897 | .set_pcie_lanes = NULL, | |
898 | .set_clock_gating = NULL, | |
899 | .set_surface_reg = r600_set_surface_reg, | |
900 | .clear_surface_reg = r600_clear_surface_reg, | |
901 | .bandwidth_update = &evergreen_bandwidth_update, | |
902 | .hpd_init = &evergreen_hpd_init, | |
903 | .hpd_fini = &evergreen_hpd_fini, | |
904 | .hpd_sense = &evergreen_hpd_sense, | |
905 | .hpd_set_polarity = &evergreen_hpd_set_polarity, | |
97bfd0ac | 906 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
958261d1 AD |
907 | .gui_idle = &r600_gui_idle, |
908 | .pm_misc = &evergreen_pm_misc, | |
909 | .pm_prepare = &evergreen_pm_prepare, | |
910 | .pm_finish = &evergreen_pm_finish, | |
a4c9e2ee | 911 | .pm_init_profile = &sumo_pm_init_profile, |
958261d1 | 912 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, |
fdc315a1 DA |
913 | .pre_page_flip = &evergreen_pre_page_flip, |
914 | .page_flip = &evergreen_page_flip, | |
915 | .post_page_flip = &evergreen_post_page_flip, | |
3ae19b75 | 916 | .wait_for_vblank = &dce4_wait_for_vblank, |
958261d1 AD |
917 | }; |
918 | ||
a43b7665 AD |
919 | static struct radeon_asic btc_asic = { |
920 | .init = &evergreen_init, | |
921 | .fini = &evergreen_fini, | |
922 | .suspend = &evergreen_suspend, | |
923 | .resume = &evergreen_resume, | |
a43b7665 AD |
924 | .gpu_is_lockup = &evergreen_gpu_is_lockup, |
925 | .asic_reset = &evergreen_asic_reset, | |
926 | .vga_set_state = &r600_vga_set_state, | |
927 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
928 | .gart_set_page = &rs600_gart_set_page, | |
929 | .ring_test = &r600_ring_test, | |
4c87bc26 CK |
930 | .ring = { |
931 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
932 | .ib_execute = &evergreen_ring_ib_execute, | |
933 | .emit_fence = &r600_fence_ring_emit, | |
934 | .emit_semaphore = &r600_semaphore_ring_emit, | |
935 | } | |
936 | }, | |
a43b7665 AD |
937 | .irq_set = &evergreen_irq_set, |
938 | .irq_process = &evergreen_irq_process, | |
939 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
a43b7665 | 940 | .cs_parse = &evergreen_cs_parse, |
fb3d9e97 | 941 | .copy_blit = &r600_copy_blit, |
20633442 | 942 | .copy_dma = NULL, |
fb3d9e97 | 943 | .copy = &r600_copy_blit, |
a43b7665 AD |
944 | .get_engine_clock = &radeon_atom_get_engine_clock, |
945 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
946 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
947 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
948 | .get_pcie_lanes = NULL, | |
949 | .set_pcie_lanes = NULL, | |
950 | .set_clock_gating = NULL, | |
951 | .set_surface_reg = r600_set_surface_reg, | |
952 | .clear_surface_reg = r600_clear_surface_reg, | |
953 | .bandwidth_update = &evergreen_bandwidth_update, | |
954 | .hpd_init = &evergreen_hpd_init, | |
955 | .hpd_fini = &evergreen_hpd_fini, | |
956 | .hpd_sense = &evergreen_hpd_sense, | |
957 | .hpd_set_polarity = &evergreen_hpd_set_polarity, | |
97bfd0ac | 958 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
a43b7665 AD |
959 | .gui_idle = &r600_gui_idle, |
960 | .pm_misc = &evergreen_pm_misc, | |
961 | .pm_prepare = &evergreen_pm_prepare, | |
962 | .pm_finish = &evergreen_pm_finish, | |
963 | .pm_init_profile = &r600_pm_init_profile, | |
964 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | |
965 | .pre_page_flip = &evergreen_pre_page_flip, | |
966 | .page_flip = &evergreen_page_flip, | |
967 | .post_page_flip = &evergreen_post_page_flip, | |
3ae19b75 | 968 | .wait_for_vblank = &dce4_wait_for_vblank, |
a43b7665 AD |
969 | }; |
970 | ||
721604a1 JG |
971 | static const struct radeon_vm_funcs cayman_vm_funcs = { |
972 | .init = &cayman_vm_init, | |
973 | .fini = &cayman_vm_fini, | |
974 | .bind = &cayman_vm_bind, | |
975 | .unbind = &cayman_vm_unbind, | |
976 | .tlb_flush = &cayman_vm_tlb_flush, | |
977 | .page_flags = &cayman_vm_page_flags, | |
978 | .set_page = &cayman_vm_set_page, | |
979 | }; | |
980 | ||
e3487629 AD |
981 | static struct radeon_asic cayman_asic = { |
982 | .init = &cayman_init, | |
983 | .fini = &cayman_fini, | |
984 | .suspend = &cayman_suspend, | |
985 | .resume = &cayman_resume, | |
e3487629 AD |
986 | .gpu_is_lockup = &cayman_gpu_is_lockup, |
987 | .asic_reset = &cayman_asic_reset, | |
988 | .vga_set_state = &r600_vga_set_state, | |
989 | .gart_tlb_flush = &cayman_pcie_gart_tlb_flush, | |
990 | .gart_set_page = &rs600_gart_set_page, | |
991 | .ring_test = &r600_ring_test, | |
4c87bc26 CK |
992 | .ring = { |
993 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
721604a1 JG |
994 | .ib_execute = &cayman_ring_ib_execute, |
995 | .ib_parse = &evergreen_ib_parse, | |
b40e7e16 | 996 | .emit_fence = &cayman_fence_ring_emit, |
4c87bc26 CK |
997 | .emit_semaphore = &r600_semaphore_ring_emit, |
998 | }, | |
999 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | |
721604a1 JG |
1000 | .ib_execute = &cayman_ring_ib_execute, |
1001 | .ib_parse = &evergreen_ib_parse, | |
b40e7e16 | 1002 | .emit_fence = &cayman_fence_ring_emit, |
4c87bc26 CK |
1003 | .emit_semaphore = &r600_semaphore_ring_emit, |
1004 | }, | |
1005 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | |
721604a1 JG |
1006 | .ib_execute = &cayman_ring_ib_execute, |
1007 | .ib_parse = &evergreen_ib_parse, | |
b40e7e16 | 1008 | .emit_fence = &cayman_fence_ring_emit, |
4c87bc26 CK |
1009 | .emit_semaphore = &r600_semaphore_ring_emit, |
1010 | } | |
1011 | }, | |
e3487629 AD |
1012 | .irq_set = &evergreen_irq_set, |
1013 | .irq_process = &evergreen_irq_process, | |
1014 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
e3487629 | 1015 | .cs_parse = &evergreen_cs_parse, |
fb3d9e97 | 1016 | .copy_blit = &r600_copy_blit, |
20633442 | 1017 | .copy_dma = NULL, |
fb3d9e97 | 1018 | .copy = &r600_copy_blit, |
e3487629 AD |
1019 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1020 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1021 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1022 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1023 | .get_pcie_lanes = NULL, | |
1024 | .set_pcie_lanes = NULL, | |
1025 | .set_clock_gating = NULL, | |
1026 | .set_surface_reg = r600_set_surface_reg, | |
1027 | .clear_surface_reg = r600_clear_surface_reg, | |
1028 | .bandwidth_update = &evergreen_bandwidth_update, | |
1029 | .hpd_init = &evergreen_hpd_init, | |
1030 | .hpd_fini = &evergreen_hpd_fini, | |
1031 | .hpd_sense = &evergreen_hpd_sense, | |
1032 | .hpd_set_polarity = &evergreen_hpd_set_polarity, | |
97bfd0ac | 1033 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
e3487629 AD |
1034 | .gui_idle = &r600_gui_idle, |
1035 | .pm_misc = &evergreen_pm_misc, | |
1036 | .pm_prepare = &evergreen_pm_prepare, | |
1037 | .pm_finish = &evergreen_pm_finish, | |
1038 | .pm_init_profile = &r600_pm_init_profile, | |
1039 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | |
1040 | .pre_page_flip = &evergreen_pre_page_flip, | |
1041 | .page_flip = &evergreen_page_flip, | |
1042 | .post_page_flip = &evergreen_post_page_flip, | |
3ae19b75 | 1043 | .wait_for_vblank = &dce4_wait_for_vblank, |
e3487629 AD |
1044 | }; |
1045 | ||
0a10c851 DV |
1046 | int radeon_asic_init(struct radeon_device *rdev) |
1047 | { | |
1048 | radeon_register_accessor_init(rdev); | |
ba7e05e9 AD |
1049 | |
1050 | /* set the number of crtcs */ | |
1051 | if (rdev->flags & RADEON_SINGLE_CRTC) | |
1052 | rdev->num_crtc = 1; | |
1053 | else | |
1054 | rdev->num_crtc = 2; | |
1055 | ||
3000bf39 AD |
1056 | /* set the ring used for bo copies */ |
1057 | rdev->copy_ring = RADEON_RING_TYPE_GFX_INDEX; | |
1058 | ||
0a10c851 DV |
1059 | switch (rdev->family) { |
1060 | case CHIP_R100: | |
1061 | case CHIP_RV100: | |
1062 | case CHIP_RS100: | |
1063 | case CHIP_RV200: | |
1064 | case CHIP_RS200: | |
1065 | rdev->asic = &r100_asic; | |
1066 | break; | |
1067 | case CHIP_R200: | |
1068 | case CHIP_RV250: | |
1069 | case CHIP_RS300: | |
1070 | case CHIP_RV280: | |
1071 | rdev->asic = &r200_asic; | |
1072 | break; | |
1073 | case CHIP_R300: | |
1074 | case CHIP_R350: | |
1075 | case CHIP_RV350: | |
1076 | case CHIP_RV380: | |
1077 | if (rdev->flags & RADEON_IS_PCIE) | |
1078 | rdev->asic = &r300_asic_pcie; | |
1079 | else | |
1080 | rdev->asic = &r300_asic; | |
1081 | break; | |
1082 | case CHIP_R420: | |
1083 | case CHIP_R423: | |
1084 | case CHIP_RV410: | |
1085 | rdev->asic = &r420_asic; | |
07bb084c AD |
1086 | /* handle macs */ |
1087 | if (rdev->bios == NULL) { | |
1088 | rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock; | |
1089 | rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock; | |
1090 | rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock; | |
1091 | rdev->asic->set_memory_clock = NULL; | |
1092 | } | |
0a10c851 DV |
1093 | break; |
1094 | case CHIP_RS400: | |
1095 | case CHIP_RS480: | |
1096 | rdev->asic = &rs400_asic; | |
1097 | break; | |
1098 | case CHIP_RS600: | |
1099 | rdev->asic = &rs600_asic; | |
1100 | break; | |
1101 | case CHIP_RS690: | |
1102 | case CHIP_RS740: | |
1103 | rdev->asic = &rs690_asic; | |
1104 | break; | |
1105 | case CHIP_RV515: | |
1106 | rdev->asic = &rv515_asic; | |
1107 | break; | |
1108 | case CHIP_R520: | |
1109 | case CHIP_RV530: | |
1110 | case CHIP_RV560: | |
1111 | case CHIP_RV570: | |
1112 | case CHIP_R580: | |
1113 | rdev->asic = &r520_asic; | |
1114 | break; | |
1115 | case CHIP_R600: | |
1116 | case CHIP_RV610: | |
1117 | case CHIP_RV630: | |
1118 | case CHIP_RV620: | |
1119 | case CHIP_RV635: | |
1120 | case CHIP_RV670: | |
f47299c5 AD |
1121 | rdev->asic = &r600_asic; |
1122 | break; | |
0a10c851 DV |
1123 | case CHIP_RS780: |
1124 | case CHIP_RS880: | |
f47299c5 | 1125 | rdev->asic = &rs780_asic; |
0a10c851 DV |
1126 | break; |
1127 | case CHIP_RV770: | |
1128 | case CHIP_RV730: | |
1129 | case CHIP_RV710: | |
1130 | case CHIP_RV740: | |
1131 | rdev->asic = &rv770_asic; | |
1132 | break; | |
1133 | case CHIP_CEDAR: | |
1134 | case CHIP_REDWOOD: | |
1135 | case CHIP_JUNIPER: | |
1136 | case CHIP_CYPRESS: | |
1137 | case CHIP_HEMLOCK: | |
ba7e05e9 AD |
1138 | /* set num crtcs */ |
1139 | if (rdev->family == CHIP_CEDAR) | |
1140 | rdev->num_crtc = 4; | |
1141 | else | |
1142 | rdev->num_crtc = 6; | |
0a10c851 DV |
1143 | rdev->asic = &evergreen_asic; |
1144 | break; | |
958261d1 | 1145 | case CHIP_PALM: |
89da5a37 AD |
1146 | case CHIP_SUMO: |
1147 | case CHIP_SUMO2: | |
958261d1 AD |
1148 | rdev->asic = &sumo_asic; |
1149 | break; | |
a43b7665 AD |
1150 | case CHIP_BARTS: |
1151 | case CHIP_TURKS: | |
1152 | case CHIP_CAICOS: | |
ba7e05e9 AD |
1153 | /* set num crtcs */ |
1154 | if (rdev->family == CHIP_CAICOS) | |
1155 | rdev->num_crtc = 4; | |
1156 | else | |
1157 | rdev->num_crtc = 6; | |
a43b7665 AD |
1158 | rdev->asic = &btc_asic; |
1159 | break; | |
e3487629 AD |
1160 | case CHIP_CAYMAN: |
1161 | rdev->asic = &cayman_asic; | |
ba7e05e9 AD |
1162 | /* set num crtcs */ |
1163 | rdev->num_crtc = 6; | |
721604a1 | 1164 | rdev->vm_manager.funcs = &cayman_vm_funcs; |
e3487629 | 1165 | break; |
0a10c851 DV |
1166 | default: |
1167 | /* FIXME: not supported yet */ | |
1168 | return -EINVAL; | |
1169 | } | |
1170 | ||
1171 | if (rdev->flags & RADEON_IS_IGP) { | |
1172 | rdev->asic->get_memory_clock = NULL; | |
1173 | rdev->asic->set_memory_clock = NULL; | |
1174 | } | |
1175 | ||
1176 | return 0; | |
1177 | } | |
1178 |