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0a10c851 DV |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | ||
29 | #include <linux/console.h> | |
30 | #include <drm/drmP.h> | |
31 | #include <drm/drm_crtc_helper.h> | |
32 | #include <drm/radeon_drm.h> | |
33 | #include <linux/vgaarb.h> | |
34 | #include <linux/vga_switcheroo.h> | |
35 | #include "radeon_reg.h" | |
36 | #include "radeon.h" | |
37 | #include "radeon_asic.h" | |
38 | #include "atom.h" | |
39 | ||
40 | /* | |
41 | * Registers accessors functions. | |
42 | */ | |
abf1dc67 AD |
43 | /** |
44 | * radeon_invalid_rreg - dummy reg read function | |
45 | * | |
46 | * @rdev: radeon device pointer | |
47 | * @reg: offset of register | |
48 | * | |
49 | * Dummy register read function. Used for register blocks | |
50 | * that certain asics don't have (all asics). | |
51 | * Returns the value in the register. | |
52 | */ | |
0a10c851 DV |
53 | static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
54 | { | |
55 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
56 | BUG_ON(1); | |
57 | return 0; | |
58 | } | |
59 | ||
abf1dc67 AD |
60 | /** |
61 | * radeon_invalid_wreg - dummy reg write function | |
62 | * | |
63 | * @rdev: radeon device pointer | |
64 | * @reg: offset of register | |
65 | * @v: value to write to the register | |
66 | * | |
67 | * Dummy register read function. Used for register blocks | |
68 | * that certain asics don't have (all asics). | |
69 | */ | |
0a10c851 DV |
70 | static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
71 | { | |
72 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
73 | reg, v); | |
74 | BUG_ON(1); | |
75 | } | |
76 | ||
abf1dc67 AD |
77 | /** |
78 | * radeon_register_accessor_init - sets up the register accessor callbacks | |
79 | * | |
80 | * @rdev: radeon device pointer | |
81 | * | |
82 | * Sets up the register accessor callbacks for various register | |
83 | * apertures. Not all asics have all apertures (all asics). | |
84 | */ | |
0a10c851 DV |
85 | static void radeon_register_accessor_init(struct radeon_device *rdev) |
86 | { | |
87 | rdev->mc_rreg = &radeon_invalid_rreg; | |
88 | rdev->mc_wreg = &radeon_invalid_wreg; | |
89 | rdev->pll_rreg = &radeon_invalid_rreg; | |
90 | rdev->pll_wreg = &radeon_invalid_wreg; | |
91 | rdev->pciep_rreg = &radeon_invalid_rreg; | |
92 | rdev->pciep_wreg = &radeon_invalid_wreg; | |
93 | ||
94 | /* Don't change order as we are overridding accessor. */ | |
95 | if (rdev->family < CHIP_RV515) { | |
96 | rdev->pcie_reg_mask = 0xff; | |
97 | } else { | |
98 | rdev->pcie_reg_mask = 0x7ff; | |
99 | } | |
100 | /* FIXME: not sure here */ | |
101 | if (rdev->family <= CHIP_R580) { | |
102 | rdev->pll_rreg = &r100_pll_rreg; | |
103 | rdev->pll_wreg = &r100_pll_wreg; | |
104 | } | |
105 | if (rdev->family >= CHIP_R420) { | |
106 | rdev->mc_rreg = &r420_mc_rreg; | |
107 | rdev->mc_wreg = &r420_mc_wreg; | |
108 | } | |
109 | if (rdev->family >= CHIP_RV515) { | |
110 | rdev->mc_rreg = &rv515_mc_rreg; | |
111 | rdev->mc_wreg = &rv515_mc_wreg; | |
112 | } | |
113 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { | |
114 | rdev->mc_rreg = &rs400_mc_rreg; | |
115 | rdev->mc_wreg = &rs400_mc_wreg; | |
116 | } | |
117 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { | |
118 | rdev->mc_rreg = &rs690_mc_rreg; | |
119 | rdev->mc_wreg = &rs690_mc_wreg; | |
120 | } | |
121 | if (rdev->family == CHIP_RS600) { | |
122 | rdev->mc_rreg = &rs600_mc_rreg; | |
123 | rdev->mc_wreg = &rs600_mc_wreg; | |
124 | } | |
65337e60 SL |
125 | if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { |
126 | rdev->mc_rreg = &rs780_mc_rreg; | |
127 | rdev->mc_wreg = &rs780_mc_wreg; | |
128 | } | |
6e2c3c0a AD |
129 | |
130 | if (rdev->family >= CHIP_BONAIRE) { | |
131 | rdev->pciep_rreg = &cik_pciep_rreg; | |
132 | rdev->pciep_wreg = &cik_pciep_wreg; | |
133 | } else if (rdev->family >= CHIP_R600) { | |
0a10c851 DV |
134 | rdev->pciep_rreg = &r600_pciep_rreg; |
135 | rdev->pciep_wreg = &r600_pciep_wreg; | |
136 | } | |
137 | } | |
138 | ||
139 | ||
140 | /* helper to disable agp */ | |
abf1dc67 AD |
141 | /** |
142 | * radeon_agp_disable - AGP disable helper function | |
143 | * | |
144 | * @rdev: radeon device pointer | |
145 | * | |
146 | * Removes AGP flags and changes the gart callbacks on AGP | |
147 | * cards when using the internal gart rather than AGP (all asics). | |
148 | */ | |
0a10c851 DV |
149 | void radeon_agp_disable(struct radeon_device *rdev) |
150 | { | |
151 | rdev->flags &= ~RADEON_IS_AGP; | |
152 | if (rdev->family >= CHIP_R600) { | |
153 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
154 | rdev->flags |= RADEON_IS_PCIE; | |
155 | } else if (rdev->family >= CHIP_RV515 || | |
156 | rdev->family == CHIP_RV380 || | |
157 | rdev->family == CHIP_RV410 || | |
158 | rdev->family == CHIP_R423) { | |
159 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
160 | rdev->flags |= RADEON_IS_PCIE; | |
c5b3b850 AD |
161 | rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; |
162 | rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; | |
0a10c851 DV |
163 | } else { |
164 | DRM_INFO("Forcing AGP to PCI mode\n"); | |
165 | rdev->flags |= RADEON_IS_PCI; | |
c5b3b850 AD |
166 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
167 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; | |
0a10c851 DV |
168 | } |
169 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
170 | } | |
171 | ||
172 | /* | |
173 | * ASIC | |
174 | */ | |
48e7a5f1 DV |
175 | static struct radeon_asic r100_asic = { |
176 | .init = &r100_init, | |
177 | .fini = &r100_fini, | |
178 | .suspend = &r100_suspend, | |
179 | .resume = &r100_resume, | |
180 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 181 | .asic_reset = &r100_asic_reset, |
54e88e06 AD |
182 | .ioctl_wait_idle = NULL, |
183 | .gui_idle = &r100_gui_idle, | |
184 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | |
c5b3b850 AD |
185 | .gart = { |
186 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
187 | .set_page = &r100_pci_gart_set_page, | |
188 | }, | |
4c87bc26 CK |
189 | .ring = { |
190 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
191 | .ib_execute = &r100_ring_ib_execute, | |
192 | .emit_fence = &r100_fence_ring_emit, | |
193 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 194 | .cs_parse = &r100_cs_parse, |
f712812e AD |
195 | .ring_start = &r100_ring_start, |
196 | .ring_test = &r100_ring_test, | |
197 | .ib_test = &r100_ib_test, | |
312c4a8c | 198 | .is_lockup = &r100_gpu_is_lockup, |
f93bdefe AD |
199 | .get_rptr = &radeon_ring_generic_get_rptr, |
200 | .get_wptr = &radeon_ring_generic_get_wptr, | |
201 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4c87bc26 CK |
202 | } |
203 | }, | |
b35ea4ab AD |
204 | .irq = { |
205 | .set = &r100_irq_set, | |
206 | .process = &r100_irq_process, | |
207 | }, | |
c79a49ca AD |
208 | .display = { |
209 | .bandwidth_update = &r100_bandwidth_update, | |
210 | .get_vblank_counter = &r100_get_vblank_counter, | |
211 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 212 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 213 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 214 | }, |
27cd7769 AD |
215 | .copy = { |
216 | .blit = &r100_copy_blit, | |
217 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
218 | .dma = NULL, | |
219 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
220 | .copy = &r100_copy_blit, | |
221 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
222 | }, | |
9e6f3d02 AD |
223 | .surface = { |
224 | .set_reg = r100_set_surface_reg, | |
225 | .clear_reg = r100_clear_surface_reg, | |
226 | }, | |
901ea57d AD |
227 | .hpd = { |
228 | .init = &r100_hpd_init, | |
229 | .fini = &r100_hpd_fini, | |
230 | .sense = &r100_hpd_sense, | |
231 | .set_polarity = &r100_hpd_set_polarity, | |
232 | }, | |
a02fa397 AD |
233 | .pm = { |
234 | .misc = &r100_pm_misc, | |
235 | .prepare = &r100_pm_prepare, | |
236 | .finish = &r100_pm_finish, | |
237 | .init_profile = &r100_pm_init_profile, | |
238 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
239 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
240 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
241 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
242 | .set_memory_clock = NULL, | |
243 | .get_pcie_lanes = NULL, | |
244 | .set_pcie_lanes = NULL, | |
245 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 246 | }, |
0f9e006c AD |
247 | .pflip = { |
248 | .pre_page_flip = &r100_pre_page_flip, | |
249 | .page_flip = &r100_page_flip, | |
250 | .post_page_flip = &r100_post_page_flip, | |
251 | }, | |
48e7a5f1 DV |
252 | }; |
253 | ||
254 | static struct radeon_asic r200_asic = { | |
255 | .init = &r100_init, | |
256 | .fini = &r100_fini, | |
257 | .suspend = &r100_suspend, | |
258 | .resume = &r100_resume, | |
259 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 260 | .asic_reset = &r100_asic_reset, |
54e88e06 AD |
261 | .ioctl_wait_idle = NULL, |
262 | .gui_idle = &r100_gui_idle, | |
263 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | |
c5b3b850 AD |
264 | .gart = { |
265 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
266 | .set_page = &r100_pci_gart_set_page, | |
267 | }, | |
4c87bc26 CK |
268 | .ring = { |
269 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
270 | .ib_execute = &r100_ring_ib_execute, | |
271 | .emit_fence = &r100_fence_ring_emit, | |
272 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 273 | .cs_parse = &r100_cs_parse, |
f712812e AD |
274 | .ring_start = &r100_ring_start, |
275 | .ring_test = &r100_ring_test, | |
276 | .ib_test = &r100_ib_test, | |
312c4a8c | 277 | .is_lockup = &r100_gpu_is_lockup, |
f93bdefe AD |
278 | .get_rptr = &radeon_ring_generic_get_rptr, |
279 | .get_wptr = &radeon_ring_generic_get_wptr, | |
280 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4c87bc26 CK |
281 | } |
282 | }, | |
b35ea4ab AD |
283 | .irq = { |
284 | .set = &r100_irq_set, | |
285 | .process = &r100_irq_process, | |
286 | }, | |
c79a49ca AD |
287 | .display = { |
288 | .bandwidth_update = &r100_bandwidth_update, | |
289 | .get_vblank_counter = &r100_get_vblank_counter, | |
290 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 291 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 292 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 293 | }, |
27cd7769 AD |
294 | .copy = { |
295 | .blit = &r100_copy_blit, | |
296 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
297 | .dma = &r200_copy_dma, | |
298 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
299 | .copy = &r100_copy_blit, | |
300 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
301 | }, | |
9e6f3d02 AD |
302 | .surface = { |
303 | .set_reg = r100_set_surface_reg, | |
304 | .clear_reg = r100_clear_surface_reg, | |
305 | }, | |
901ea57d AD |
306 | .hpd = { |
307 | .init = &r100_hpd_init, | |
308 | .fini = &r100_hpd_fini, | |
309 | .sense = &r100_hpd_sense, | |
310 | .set_polarity = &r100_hpd_set_polarity, | |
311 | }, | |
a02fa397 AD |
312 | .pm = { |
313 | .misc = &r100_pm_misc, | |
314 | .prepare = &r100_pm_prepare, | |
315 | .finish = &r100_pm_finish, | |
316 | .init_profile = &r100_pm_init_profile, | |
317 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
318 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
319 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
320 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
321 | .set_memory_clock = NULL, | |
322 | .get_pcie_lanes = NULL, | |
323 | .set_pcie_lanes = NULL, | |
324 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 325 | }, |
0f9e006c AD |
326 | .pflip = { |
327 | .pre_page_flip = &r100_pre_page_flip, | |
328 | .page_flip = &r100_page_flip, | |
329 | .post_page_flip = &r100_post_page_flip, | |
330 | }, | |
48e7a5f1 DV |
331 | }; |
332 | ||
333 | static struct radeon_asic r300_asic = { | |
334 | .init = &r300_init, | |
335 | .fini = &r300_fini, | |
336 | .suspend = &r300_suspend, | |
337 | .resume = &r300_resume, | |
338 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 339 | .asic_reset = &r300_asic_reset, |
54e88e06 AD |
340 | .ioctl_wait_idle = NULL, |
341 | .gui_idle = &r100_gui_idle, | |
342 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
c5b3b850 AD |
343 | .gart = { |
344 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
345 | .set_page = &r100_pci_gart_set_page, | |
346 | }, | |
4c87bc26 CK |
347 | .ring = { |
348 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
349 | .ib_execute = &r100_ring_ib_execute, | |
350 | .emit_fence = &r300_fence_ring_emit, | |
351 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 352 | .cs_parse = &r300_cs_parse, |
f712812e AD |
353 | .ring_start = &r300_ring_start, |
354 | .ring_test = &r100_ring_test, | |
355 | .ib_test = &r100_ib_test, | |
8ba957b5 | 356 | .is_lockup = &r100_gpu_is_lockup, |
f93bdefe AD |
357 | .get_rptr = &radeon_ring_generic_get_rptr, |
358 | .get_wptr = &radeon_ring_generic_get_wptr, | |
359 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4c87bc26 CK |
360 | } |
361 | }, | |
b35ea4ab AD |
362 | .irq = { |
363 | .set = &r100_irq_set, | |
364 | .process = &r100_irq_process, | |
365 | }, | |
c79a49ca AD |
366 | .display = { |
367 | .bandwidth_update = &r100_bandwidth_update, | |
368 | .get_vblank_counter = &r100_get_vblank_counter, | |
369 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 370 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 371 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 372 | }, |
27cd7769 AD |
373 | .copy = { |
374 | .blit = &r100_copy_blit, | |
375 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
376 | .dma = &r200_copy_dma, | |
377 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
378 | .copy = &r100_copy_blit, | |
379 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
380 | }, | |
9e6f3d02 AD |
381 | .surface = { |
382 | .set_reg = r100_set_surface_reg, | |
383 | .clear_reg = r100_clear_surface_reg, | |
384 | }, | |
901ea57d AD |
385 | .hpd = { |
386 | .init = &r100_hpd_init, | |
387 | .fini = &r100_hpd_fini, | |
388 | .sense = &r100_hpd_sense, | |
389 | .set_polarity = &r100_hpd_set_polarity, | |
390 | }, | |
a02fa397 AD |
391 | .pm = { |
392 | .misc = &r100_pm_misc, | |
393 | .prepare = &r100_pm_prepare, | |
394 | .finish = &r100_pm_finish, | |
395 | .init_profile = &r100_pm_init_profile, | |
396 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
397 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
398 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
399 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
400 | .set_memory_clock = NULL, | |
401 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
402 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
403 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 404 | }, |
0f9e006c AD |
405 | .pflip = { |
406 | .pre_page_flip = &r100_pre_page_flip, | |
407 | .page_flip = &r100_page_flip, | |
408 | .post_page_flip = &r100_post_page_flip, | |
409 | }, | |
48e7a5f1 DV |
410 | }; |
411 | ||
412 | static struct radeon_asic r300_asic_pcie = { | |
413 | .init = &r300_init, | |
414 | .fini = &r300_fini, | |
415 | .suspend = &r300_suspend, | |
416 | .resume = &r300_resume, | |
417 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 418 | .asic_reset = &r300_asic_reset, |
54e88e06 AD |
419 | .ioctl_wait_idle = NULL, |
420 | .gui_idle = &r100_gui_idle, | |
421 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
c5b3b850 AD |
422 | .gart = { |
423 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
424 | .set_page = &rv370_pcie_gart_set_page, | |
425 | }, | |
4c87bc26 CK |
426 | .ring = { |
427 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
428 | .ib_execute = &r100_ring_ib_execute, | |
429 | .emit_fence = &r300_fence_ring_emit, | |
430 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 431 | .cs_parse = &r300_cs_parse, |
f712812e AD |
432 | .ring_start = &r300_ring_start, |
433 | .ring_test = &r100_ring_test, | |
434 | .ib_test = &r100_ib_test, | |
8ba957b5 | 435 | .is_lockup = &r100_gpu_is_lockup, |
f93bdefe AD |
436 | .get_rptr = &radeon_ring_generic_get_rptr, |
437 | .get_wptr = &radeon_ring_generic_get_wptr, | |
438 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4c87bc26 CK |
439 | } |
440 | }, | |
b35ea4ab AD |
441 | .irq = { |
442 | .set = &r100_irq_set, | |
443 | .process = &r100_irq_process, | |
444 | }, | |
c79a49ca AD |
445 | .display = { |
446 | .bandwidth_update = &r100_bandwidth_update, | |
447 | .get_vblank_counter = &r100_get_vblank_counter, | |
448 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 449 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 450 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 451 | }, |
27cd7769 AD |
452 | .copy = { |
453 | .blit = &r100_copy_blit, | |
454 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
455 | .dma = &r200_copy_dma, | |
456 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
457 | .copy = &r100_copy_blit, | |
458 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
459 | }, | |
9e6f3d02 AD |
460 | .surface = { |
461 | .set_reg = r100_set_surface_reg, | |
462 | .clear_reg = r100_clear_surface_reg, | |
463 | }, | |
901ea57d AD |
464 | .hpd = { |
465 | .init = &r100_hpd_init, | |
466 | .fini = &r100_hpd_fini, | |
467 | .sense = &r100_hpd_sense, | |
468 | .set_polarity = &r100_hpd_set_polarity, | |
469 | }, | |
a02fa397 AD |
470 | .pm = { |
471 | .misc = &r100_pm_misc, | |
472 | .prepare = &r100_pm_prepare, | |
473 | .finish = &r100_pm_finish, | |
474 | .init_profile = &r100_pm_init_profile, | |
475 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
476 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
477 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
478 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
479 | .set_memory_clock = NULL, | |
480 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
481 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
482 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 483 | }, |
0f9e006c AD |
484 | .pflip = { |
485 | .pre_page_flip = &r100_pre_page_flip, | |
486 | .page_flip = &r100_page_flip, | |
487 | .post_page_flip = &r100_post_page_flip, | |
488 | }, | |
48e7a5f1 DV |
489 | }; |
490 | ||
491 | static struct radeon_asic r420_asic = { | |
492 | .init = &r420_init, | |
493 | .fini = &r420_fini, | |
494 | .suspend = &r420_suspend, | |
495 | .resume = &r420_resume, | |
496 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 497 | .asic_reset = &r300_asic_reset, |
54e88e06 AD |
498 | .ioctl_wait_idle = NULL, |
499 | .gui_idle = &r100_gui_idle, | |
500 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
c5b3b850 AD |
501 | .gart = { |
502 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
503 | .set_page = &rv370_pcie_gart_set_page, | |
504 | }, | |
4c87bc26 CK |
505 | .ring = { |
506 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
507 | .ib_execute = &r100_ring_ib_execute, | |
508 | .emit_fence = &r300_fence_ring_emit, | |
509 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 510 | .cs_parse = &r300_cs_parse, |
f712812e AD |
511 | .ring_start = &r300_ring_start, |
512 | .ring_test = &r100_ring_test, | |
513 | .ib_test = &r100_ib_test, | |
8ba957b5 | 514 | .is_lockup = &r100_gpu_is_lockup, |
f93bdefe AD |
515 | .get_rptr = &radeon_ring_generic_get_rptr, |
516 | .get_wptr = &radeon_ring_generic_get_wptr, | |
517 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4c87bc26 CK |
518 | } |
519 | }, | |
b35ea4ab AD |
520 | .irq = { |
521 | .set = &r100_irq_set, | |
522 | .process = &r100_irq_process, | |
523 | }, | |
c79a49ca AD |
524 | .display = { |
525 | .bandwidth_update = &r100_bandwidth_update, | |
526 | .get_vblank_counter = &r100_get_vblank_counter, | |
527 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 528 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 529 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 530 | }, |
27cd7769 AD |
531 | .copy = { |
532 | .blit = &r100_copy_blit, | |
533 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
534 | .dma = &r200_copy_dma, | |
535 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
536 | .copy = &r100_copy_blit, | |
537 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
538 | }, | |
9e6f3d02 AD |
539 | .surface = { |
540 | .set_reg = r100_set_surface_reg, | |
541 | .clear_reg = r100_clear_surface_reg, | |
542 | }, | |
901ea57d AD |
543 | .hpd = { |
544 | .init = &r100_hpd_init, | |
545 | .fini = &r100_hpd_fini, | |
546 | .sense = &r100_hpd_sense, | |
547 | .set_polarity = &r100_hpd_set_polarity, | |
548 | }, | |
a02fa397 AD |
549 | .pm = { |
550 | .misc = &r100_pm_misc, | |
551 | .prepare = &r100_pm_prepare, | |
552 | .finish = &r100_pm_finish, | |
553 | .init_profile = &r420_pm_init_profile, | |
554 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
555 | .get_engine_clock = &radeon_atom_get_engine_clock, |
556 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
557 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
558 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
559 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
560 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
561 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 562 | }, |
0f9e006c AD |
563 | .pflip = { |
564 | .pre_page_flip = &r100_pre_page_flip, | |
565 | .page_flip = &r100_page_flip, | |
566 | .post_page_flip = &r100_post_page_flip, | |
567 | }, | |
48e7a5f1 DV |
568 | }; |
569 | ||
570 | static struct radeon_asic rs400_asic = { | |
571 | .init = &rs400_init, | |
572 | .fini = &rs400_fini, | |
573 | .suspend = &rs400_suspend, | |
574 | .resume = &rs400_resume, | |
575 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 576 | .asic_reset = &r300_asic_reset, |
54e88e06 AD |
577 | .ioctl_wait_idle = NULL, |
578 | .gui_idle = &r100_gui_idle, | |
579 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, | |
c5b3b850 AD |
580 | .gart = { |
581 | .tlb_flush = &rs400_gart_tlb_flush, | |
582 | .set_page = &rs400_gart_set_page, | |
583 | }, | |
4c87bc26 CK |
584 | .ring = { |
585 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
586 | .ib_execute = &r100_ring_ib_execute, | |
587 | .emit_fence = &r300_fence_ring_emit, | |
588 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 589 | .cs_parse = &r300_cs_parse, |
f712812e AD |
590 | .ring_start = &r300_ring_start, |
591 | .ring_test = &r100_ring_test, | |
592 | .ib_test = &r100_ib_test, | |
8ba957b5 | 593 | .is_lockup = &r100_gpu_is_lockup, |
f93bdefe AD |
594 | .get_rptr = &radeon_ring_generic_get_rptr, |
595 | .get_wptr = &radeon_ring_generic_get_wptr, | |
596 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4c87bc26 CK |
597 | } |
598 | }, | |
b35ea4ab AD |
599 | .irq = { |
600 | .set = &r100_irq_set, | |
601 | .process = &r100_irq_process, | |
602 | }, | |
c79a49ca AD |
603 | .display = { |
604 | .bandwidth_update = &r100_bandwidth_update, | |
605 | .get_vblank_counter = &r100_get_vblank_counter, | |
606 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 607 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 608 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 609 | }, |
27cd7769 AD |
610 | .copy = { |
611 | .blit = &r100_copy_blit, | |
612 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
613 | .dma = &r200_copy_dma, | |
614 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
615 | .copy = &r100_copy_blit, | |
616 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
617 | }, | |
9e6f3d02 AD |
618 | .surface = { |
619 | .set_reg = r100_set_surface_reg, | |
620 | .clear_reg = r100_clear_surface_reg, | |
621 | }, | |
901ea57d AD |
622 | .hpd = { |
623 | .init = &r100_hpd_init, | |
624 | .fini = &r100_hpd_fini, | |
625 | .sense = &r100_hpd_sense, | |
626 | .set_polarity = &r100_hpd_set_polarity, | |
627 | }, | |
a02fa397 AD |
628 | .pm = { |
629 | .misc = &r100_pm_misc, | |
630 | .prepare = &r100_pm_prepare, | |
631 | .finish = &r100_pm_finish, | |
632 | .init_profile = &r100_pm_init_profile, | |
633 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
634 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
635 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
636 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
637 | .set_memory_clock = NULL, | |
638 | .get_pcie_lanes = NULL, | |
639 | .set_pcie_lanes = NULL, | |
640 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 641 | }, |
0f9e006c AD |
642 | .pflip = { |
643 | .pre_page_flip = &r100_pre_page_flip, | |
644 | .page_flip = &r100_page_flip, | |
645 | .post_page_flip = &r100_post_page_flip, | |
646 | }, | |
48e7a5f1 DV |
647 | }; |
648 | ||
649 | static struct radeon_asic rs600_asic = { | |
650 | .init = &rs600_init, | |
651 | .fini = &rs600_fini, | |
652 | .suspend = &rs600_suspend, | |
653 | .resume = &rs600_resume, | |
654 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 655 | .asic_reset = &rs600_asic_reset, |
54e88e06 AD |
656 | .ioctl_wait_idle = NULL, |
657 | .gui_idle = &r100_gui_idle, | |
658 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, | |
c5b3b850 AD |
659 | .gart = { |
660 | .tlb_flush = &rs600_gart_tlb_flush, | |
661 | .set_page = &rs600_gart_set_page, | |
662 | }, | |
4c87bc26 CK |
663 | .ring = { |
664 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
665 | .ib_execute = &r100_ring_ib_execute, | |
666 | .emit_fence = &r300_fence_ring_emit, | |
667 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 668 | .cs_parse = &r300_cs_parse, |
f712812e AD |
669 | .ring_start = &r300_ring_start, |
670 | .ring_test = &r100_ring_test, | |
671 | .ib_test = &r100_ib_test, | |
8ba957b5 | 672 | .is_lockup = &r100_gpu_is_lockup, |
f93bdefe AD |
673 | .get_rptr = &radeon_ring_generic_get_rptr, |
674 | .get_wptr = &radeon_ring_generic_get_wptr, | |
675 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4c87bc26 CK |
676 | } |
677 | }, | |
b35ea4ab AD |
678 | .irq = { |
679 | .set = &rs600_irq_set, | |
680 | .process = &rs600_irq_process, | |
681 | }, | |
c79a49ca AD |
682 | .display = { |
683 | .bandwidth_update = &rs600_bandwidth_update, | |
684 | .get_vblank_counter = &rs600_get_vblank_counter, | |
685 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 686 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 687 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
688 | .hdmi_enable = &r600_hdmi_enable, |
689 | .hdmi_setmode = &r600_hdmi_setmode, | |
c79a49ca | 690 | }, |
27cd7769 AD |
691 | .copy = { |
692 | .blit = &r100_copy_blit, | |
693 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
694 | .dma = &r200_copy_dma, | |
695 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
696 | .copy = &r100_copy_blit, | |
697 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
698 | }, | |
9e6f3d02 AD |
699 | .surface = { |
700 | .set_reg = r100_set_surface_reg, | |
701 | .clear_reg = r100_clear_surface_reg, | |
702 | }, | |
901ea57d AD |
703 | .hpd = { |
704 | .init = &rs600_hpd_init, | |
705 | .fini = &rs600_hpd_fini, | |
706 | .sense = &rs600_hpd_sense, | |
707 | .set_polarity = &rs600_hpd_set_polarity, | |
708 | }, | |
a02fa397 AD |
709 | .pm = { |
710 | .misc = &rs600_pm_misc, | |
711 | .prepare = &rs600_pm_prepare, | |
712 | .finish = &rs600_pm_finish, | |
713 | .init_profile = &r420_pm_init_profile, | |
714 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
715 | .get_engine_clock = &radeon_atom_get_engine_clock, |
716 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
717 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
718 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
719 | .get_pcie_lanes = NULL, | |
720 | .set_pcie_lanes = NULL, | |
721 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 722 | }, |
0f9e006c AD |
723 | .pflip = { |
724 | .pre_page_flip = &rs600_pre_page_flip, | |
725 | .page_flip = &rs600_page_flip, | |
726 | .post_page_flip = &rs600_post_page_flip, | |
727 | }, | |
48e7a5f1 DV |
728 | }; |
729 | ||
730 | static struct radeon_asic rs690_asic = { | |
731 | .init = &rs690_init, | |
732 | .fini = &rs690_fini, | |
733 | .suspend = &rs690_suspend, | |
734 | .resume = &rs690_resume, | |
735 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 736 | .asic_reset = &rs600_asic_reset, |
54e88e06 AD |
737 | .ioctl_wait_idle = NULL, |
738 | .gui_idle = &r100_gui_idle, | |
739 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, | |
c5b3b850 AD |
740 | .gart = { |
741 | .tlb_flush = &rs400_gart_tlb_flush, | |
742 | .set_page = &rs400_gart_set_page, | |
743 | }, | |
4c87bc26 CK |
744 | .ring = { |
745 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
746 | .ib_execute = &r100_ring_ib_execute, | |
747 | .emit_fence = &r300_fence_ring_emit, | |
748 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 749 | .cs_parse = &r300_cs_parse, |
f712812e AD |
750 | .ring_start = &r300_ring_start, |
751 | .ring_test = &r100_ring_test, | |
752 | .ib_test = &r100_ib_test, | |
8ba957b5 | 753 | .is_lockup = &r100_gpu_is_lockup, |
f93bdefe AD |
754 | .get_rptr = &radeon_ring_generic_get_rptr, |
755 | .get_wptr = &radeon_ring_generic_get_wptr, | |
756 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4c87bc26 CK |
757 | } |
758 | }, | |
b35ea4ab AD |
759 | .irq = { |
760 | .set = &rs600_irq_set, | |
761 | .process = &rs600_irq_process, | |
762 | }, | |
c79a49ca AD |
763 | .display = { |
764 | .get_vblank_counter = &rs600_get_vblank_counter, | |
765 | .bandwidth_update = &rs690_bandwidth_update, | |
766 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 767 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 768 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
769 | .hdmi_enable = &r600_hdmi_enable, |
770 | .hdmi_setmode = &r600_hdmi_setmode, | |
c79a49ca | 771 | }, |
27cd7769 AD |
772 | .copy = { |
773 | .blit = &r100_copy_blit, | |
774 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
775 | .dma = &r200_copy_dma, | |
776 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
777 | .copy = &r200_copy_dma, | |
778 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
779 | }, | |
9e6f3d02 AD |
780 | .surface = { |
781 | .set_reg = r100_set_surface_reg, | |
782 | .clear_reg = r100_clear_surface_reg, | |
783 | }, | |
901ea57d AD |
784 | .hpd = { |
785 | .init = &rs600_hpd_init, | |
786 | .fini = &rs600_hpd_fini, | |
787 | .sense = &rs600_hpd_sense, | |
788 | .set_polarity = &rs600_hpd_set_polarity, | |
789 | }, | |
a02fa397 AD |
790 | .pm = { |
791 | .misc = &rs600_pm_misc, | |
792 | .prepare = &rs600_pm_prepare, | |
793 | .finish = &rs600_pm_finish, | |
794 | .init_profile = &r420_pm_init_profile, | |
795 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
796 | .get_engine_clock = &radeon_atom_get_engine_clock, |
797 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
798 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
799 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
800 | .get_pcie_lanes = NULL, | |
801 | .set_pcie_lanes = NULL, | |
802 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 803 | }, |
0f9e006c AD |
804 | .pflip = { |
805 | .pre_page_flip = &rs600_pre_page_flip, | |
806 | .page_flip = &rs600_page_flip, | |
807 | .post_page_flip = &rs600_post_page_flip, | |
808 | }, | |
48e7a5f1 DV |
809 | }; |
810 | ||
811 | static struct radeon_asic rv515_asic = { | |
812 | .init = &rv515_init, | |
813 | .fini = &rv515_fini, | |
814 | .suspend = &rv515_suspend, | |
815 | .resume = &rv515_resume, | |
816 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 817 | .asic_reset = &rs600_asic_reset, |
54e88e06 AD |
818 | .ioctl_wait_idle = NULL, |
819 | .gui_idle = &r100_gui_idle, | |
820 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, | |
c5b3b850 AD |
821 | .gart = { |
822 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
823 | .set_page = &rv370_pcie_gart_set_page, | |
824 | }, | |
4c87bc26 CK |
825 | .ring = { |
826 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
827 | .ib_execute = &r100_ring_ib_execute, | |
828 | .emit_fence = &r300_fence_ring_emit, | |
829 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 830 | .cs_parse = &r300_cs_parse, |
f712812e AD |
831 | .ring_start = &rv515_ring_start, |
832 | .ring_test = &r100_ring_test, | |
833 | .ib_test = &r100_ib_test, | |
8ba957b5 | 834 | .is_lockup = &r100_gpu_is_lockup, |
f93bdefe AD |
835 | .get_rptr = &radeon_ring_generic_get_rptr, |
836 | .get_wptr = &radeon_ring_generic_get_wptr, | |
837 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4c87bc26 CK |
838 | } |
839 | }, | |
b35ea4ab AD |
840 | .irq = { |
841 | .set = &rs600_irq_set, | |
842 | .process = &rs600_irq_process, | |
843 | }, | |
c79a49ca AD |
844 | .display = { |
845 | .get_vblank_counter = &rs600_get_vblank_counter, | |
846 | .bandwidth_update = &rv515_bandwidth_update, | |
847 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 848 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 849 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 850 | }, |
27cd7769 AD |
851 | .copy = { |
852 | .blit = &r100_copy_blit, | |
853 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
854 | .dma = &r200_copy_dma, | |
855 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
856 | .copy = &r100_copy_blit, | |
857 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
858 | }, | |
9e6f3d02 AD |
859 | .surface = { |
860 | .set_reg = r100_set_surface_reg, | |
861 | .clear_reg = r100_clear_surface_reg, | |
862 | }, | |
901ea57d AD |
863 | .hpd = { |
864 | .init = &rs600_hpd_init, | |
865 | .fini = &rs600_hpd_fini, | |
866 | .sense = &rs600_hpd_sense, | |
867 | .set_polarity = &rs600_hpd_set_polarity, | |
868 | }, | |
a02fa397 AD |
869 | .pm = { |
870 | .misc = &rs600_pm_misc, | |
871 | .prepare = &rs600_pm_prepare, | |
872 | .finish = &rs600_pm_finish, | |
873 | .init_profile = &r420_pm_init_profile, | |
874 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
875 | .get_engine_clock = &radeon_atom_get_engine_clock, |
876 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
877 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
878 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
879 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
880 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
881 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 882 | }, |
0f9e006c AD |
883 | .pflip = { |
884 | .pre_page_flip = &rs600_pre_page_flip, | |
885 | .page_flip = &rs600_page_flip, | |
886 | .post_page_flip = &rs600_post_page_flip, | |
887 | }, | |
48e7a5f1 DV |
888 | }; |
889 | ||
890 | static struct radeon_asic r520_asic = { | |
891 | .init = &r520_init, | |
892 | .fini = &rv515_fini, | |
893 | .suspend = &rv515_suspend, | |
894 | .resume = &r520_resume, | |
895 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 896 | .asic_reset = &rs600_asic_reset, |
54e88e06 AD |
897 | .ioctl_wait_idle = NULL, |
898 | .gui_idle = &r100_gui_idle, | |
899 | .mc_wait_for_idle = &r520_mc_wait_for_idle, | |
c5b3b850 AD |
900 | .gart = { |
901 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
902 | .set_page = &rv370_pcie_gart_set_page, | |
903 | }, | |
4c87bc26 CK |
904 | .ring = { |
905 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
906 | .ib_execute = &r100_ring_ib_execute, | |
907 | .emit_fence = &r300_fence_ring_emit, | |
908 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 909 | .cs_parse = &r300_cs_parse, |
f712812e AD |
910 | .ring_start = &rv515_ring_start, |
911 | .ring_test = &r100_ring_test, | |
912 | .ib_test = &r100_ib_test, | |
8ba957b5 | 913 | .is_lockup = &r100_gpu_is_lockup, |
f93bdefe AD |
914 | .get_rptr = &radeon_ring_generic_get_rptr, |
915 | .get_wptr = &radeon_ring_generic_get_wptr, | |
916 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4c87bc26 CK |
917 | } |
918 | }, | |
b35ea4ab AD |
919 | .irq = { |
920 | .set = &rs600_irq_set, | |
921 | .process = &rs600_irq_process, | |
922 | }, | |
c79a49ca AD |
923 | .display = { |
924 | .bandwidth_update = &rv515_bandwidth_update, | |
925 | .get_vblank_counter = &rs600_get_vblank_counter, | |
926 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 927 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 928 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 929 | }, |
27cd7769 AD |
930 | .copy = { |
931 | .blit = &r100_copy_blit, | |
932 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
933 | .dma = &r200_copy_dma, | |
934 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
935 | .copy = &r100_copy_blit, | |
936 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
937 | }, | |
9e6f3d02 AD |
938 | .surface = { |
939 | .set_reg = r100_set_surface_reg, | |
940 | .clear_reg = r100_clear_surface_reg, | |
941 | }, | |
901ea57d AD |
942 | .hpd = { |
943 | .init = &rs600_hpd_init, | |
944 | .fini = &rs600_hpd_fini, | |
945 | .sense = &rs600_hpd_sense, | |
946 | .set_polarity = &rs600_hpd_set_polarity, | |
947 | }, | |
a02fa397 AD |
948 | .pm = { |
949 | .misc = &rs600_pm_misc, | |
950 | .prepare = &rs600_pm_prepare, | |
951 | .finish = &rs600_pm_finish, | |
952 | .init_profile = &r420_pm_init_profile, | |
953 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
954 | .get_engine_clock = &radeon_atom_get_engine_clock, |
955 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
956 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
957 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
958 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
959 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
960 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 961 | }, |
0f9e006c AD |
962 | .pflip = { |
963 | .pre_page_flip = &rs600_pre_page_flip, | |
964 | .page_flip = &rs600_page_flip, | |
965 | .post_page_flip = &rs600_post_page_flip, | |
966 | }, | |
48e7a5f1 DV |
967 | }; |
968 | ||
969 | static struct radeon_asic r600_asic = { | |
970 | .init = &r600_init, | |
971 | .fini = &r600_fini, | |
972 | .suspend = &r600_suspend, | |
973 | .resume = &r600_resume, | |
48e7a5f1 | 974 | .vga_set_state = &r600_vga_set_state, |
a2d07b74 | 975 | .asic_reset = &r600_asic_reset, |
54e88e06 AD |
976 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
977 | .gui_idle = &r600_gui_idle, | |
978 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
454d2e2a | 979 | .get_xclk = &r600_get_xclk, |
d0418894 | 980 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
981 | .gart = { |
982 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
983 | .set_page = &rs600_gart_set_page, | |
984 | }, | |
4c87bc26 CK |
985 | .ring = { |
986 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
987 | .ib_execute = &r600_ring_ib_execute, | |
988 | .emit_fence = &r600_fence_ring_emit, | |
989 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 990 | .cs_parse = &r600_cs_parse, |
f712812e AD |
991 | .ring_test = &r600_ring_test, |
992 | .ib_test = &r600_ib_test, | |
123bc183 | 993 | .is_lockup = &r600_gfx_is_lockup, |
f93bdefe AD |
994 | .get_rptr = &radeon_ring_generic_get_rptr, |
995 | .get_wptr = &radeon_ring_generic_get_wptr, | |
996 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4d75658b AD |
997 | }, |
998 | [R600_RING_TYPE_DMA_INDEX] = { | |
999 | .ib_execute = &r600_dma_ring_ib_execute, | |
1000 | .emit_fence = &r600_dma_fence_ring_emit, | |
1001 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
cf4ccd01 | 1002 | .cs_parse = &r600_dma_cs_parse, |
4d75658b AD |
1003 | .ring_test = &r600_dma_ring_test, |
1004 | .ib_test = &r600_dma_ib_test, | |
1005 | .is_lockup = &r600_dma_is_lockup, | |
f93bdefe AD |
1006 | .get_rptr = &radeon_ring_generic_get_rptr, |
1007 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1008 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4c87bc26 CK |
1009 | } |
1010 | }, | |
b35ea4ab AD |
1011 | .irq = { |
1012 | .set = &r600_irq_set, | |
1013 | .process = &r600_irq_process, | |
1014 | }, | |
c79a49ca AD |
1015 | .display = { |
1016 | .bandwidth_update = &rv515_bandwidth_update, | |
1017 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1018 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 1019 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1020 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
1021 | .hdmi_enable = &r600_hdmi_enable, |
1022 | .hdmi_setmode = &r600_hdmi_setmode, | |
c79a49ca | 1023 | }, |
27cd7769 AD |
1024 | .copy = { |
1025 | .blit = &r600_copy_blit, | |
1026 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
4d75658b AD |
1027 | .dma = &r600_copy_dma, |
1028 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1029 | .copy = &r600_copy_dma, |
1030 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1031 | }, |
9e6f3d02 AD |
1032 | .surface = { |
1033 | .set_reg = r600_set_surface_reg, | |
1034 | .clear_reg = r600_clear_surface_reg, | |
1035 | }, | |
901ea57d AD |
1036 | .hpd = { |
1037 | .init = &r600_hpd_init, | |
1038 | .fini = &r600_hpd_fini, | |
1039 | .sense = &r600_hpd_sense, | |
1040 | .set_polarity = &r600_hpd_set_polarity, | |
1041 | }, | |
a02fa397 AD |
1042 | .pm = { |
1043 | .misc = &r600_pm_misc, | |
1044 | .prepare = &rs600_pm_prepare, | |
1045 | .finish = &rs600_pm_finish, | |
1046 | .init_profile = &r600_pm_init_profile, | |
1047 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1048 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1049 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1050 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1051 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1052 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1053 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1054 | .set_clock_gating = NULL, | |
6bd1c385 | 1055 | .get_temperature = &rv6xx_get_temp, |
a02fa397 | 1056 | }, |
0f9e006c AD |
1057 | .pflip = { |
1058 | .pre_page_flip = &rs600_pre_page_flip, | |
1059 | .page_flip = &rs600_page_flip, | |
1060 | .post_page_flip = &rs600_post_page_flip, | |
1061 | }, | |
48e7a5f1 DV |
1062 | }; |
1063 | ||
ca361b65 AD |
1064 | static struct radeon_asic rv6xx_asic = { |
1065 | .init = &r600_init, | |
1066 | .fini = &r600_fini, | |
1067 | .suspend = &r600_suspend, | |
1068 | .resume = &r600_resume, | |
1069 | .vga_set_state = &r600_vga_set_state, | |
1070 | .asic_reset = &r600_asic_reset, | |
1071 | .ioctl_wait_idle = r600_ioctl_wait_idle, | |
1072 | .gui_idle = &r600_gui_idle, | |
1073 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
1074 | .get_xclk = &r600_get_xclk, | |
1075 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, | |
1076 | .gart = { | |
1077 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
1078 | .set_page = &rs600_gart_set_page, | |
1079 | }, | |
1080 | .ring = { | |
1081 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1082 | .ib_execute = &r600_ring_ib_execute, | |
1083 | .emit_fence = &r600_fence_ring_emit, | |
1084 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1085 | .cs_parse = &r600_cs_parse, | |
1086 | .ring_test = &r600_ring_test, | |
1087 | .ib_test = &r600_ib_test, | |
1088 | .is_lockup = &r600_gfx_is_lockup, | |
1089 | .get_rptr = &radeon_ring_generic_get_rptr, | |
1090 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1091 | .set_wptr = &radeon_ring_generic_set_wptr, | |
1092 | }, | |
1093 | [R600_RING_TYPE_DMA_INDEX] = { | |
1094 | .ib_execute = &r600_dma_ring_ib_execute, | |
1095 | .emit_fence = &r600_dma_fence_ring_emit, | |
1096 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
1097 | .cs_parse = &r600_dma_cs_parse, | |
1098 | .ring_test = &r600_dma_ring_test, | |
1099 | .ib_test = &r600_dma_ib_test, | |
1100 | .is_lockup = &r600_dma_is_lockup, | |
1101 | .get_rptr = &radeon_ring_generic_get_rptr, | |
1102 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1103 | .set_wptr = &radeon_ring_generic_set_wptr, | |
1104 | } | |
1105 | }, | |
1106 | .irq = { | |
1107 | .set = &r600_irq_set, | |
1108 | .process = &r600_irq_process, | |
1109 | }, | |
1110 | .display = { | |
1111 | .bandwidth_update = &rv515_bandwidth_update, | |
1112 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1113 | .wait_for_vblank = &avivo_wait_for_vblank, | |
1114 | .set_backlight_level = &atombios_set_backlight_level, | |
1115 | .get_backlight_level = &atombios_get_backlight_level, | |
1116 | }, | |
1117 | .copy = { | |
1118 | .blit = &r600_copy_blit, | |
1119 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1120 | .dma = &r600_copy_dma, | |
1121 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
1122 | .copy = &r600_copy_dma, | |
1123 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
1124 | }, | |
1125 | .surface = { | |
1126 | .set_reg = r600_set_surface_reg, | |
1127 | .clear_reg = r600_clear_surface_reg, | |
1128 | }, | |
1129 | .hpd = { | |
1130 | .init = &r600_hpd_init, | |
1131 | .fini = &r600_hpd_fini, | |
1132 | .sense = &r600_hpd_sense, | |
1133 | .set_polarity = &r600_hpd_set_polarity, | |
1134 | }, | |
1135 | .pm = { | |
1136 | .misc = &r600_pm_misc, | |
1137 | .prepare = &rs600_pm_prepare, | |
1138 | .finish = &rs600_pm_finish, | |
1139 | .init_profile = &r600_pm_init_profile, | |
1140 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
1141 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
1142 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1143 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1144 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1145 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1146 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1147 | .set_clock_gating = NULL, | |
1148 | .get_temperature = &rv6xx_get_temp, | |
1149 | }, | |
4a6369e9 AD |
1150 | .dpm = { |
1151 | .init = &rv6xx_dpm_init, | |
1152 | .setup_asic = &rv6xx_setup_asic, | |
1153 | .enable = &rv6xx_dpm_enable, | |
1154 | .disable = &rv6xx_dpm_disable, | |
1155 | .set_power_state = &rv6xx_dpm_set_power_state, | |
1156 | .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, | |
1157 | .fini = &rv6xx_dpm_fini, | |
1158 | .get_sclk = &rv6xx_dpm_get_sclk, | |
1159 | .get_mclk = &rv6xx_dpm_get_mclk, | |
1160 | .print_power_state = &rv6xx_dpm_print_power_state, | |
1161 | }, | |
ca361b65 AD |
1162 | .pflip = { |
1163 | .pre_page_flip = &rs600_pre_page_flip, | |
1164 | .page_flip = &rs600_page_flip, | |
1165 | .post_page_flip = &rs600_post_page_flip, | |
1166 | }, | |
1167 | }; | |
1168 | ||
f47299c5 AD |
1169 | static struct radeon_asic rs780_asic = { |
1170 | .init = &r600_init, | |
1171 | .fini = &r600_fini, | |
1172 | .suspend = &r600_suspend, | |
1173 | .resume = &r600_resume, | |
f47299c5 | 1174 | .vga_set_state = &r600_vga_set_state, |
a2d07b74 | 1175 | .asic_reset = &r600_asic_reset, |
54e88e06 AD |
1176 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1177 | .gui_idle = &r600_gui_idle, | |
1178 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
454d2e2a | 1179 | .get_xclk = &r600_get_xclk, |
d0418894 | 1180 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1181 | .gart = { |
1182 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
1183 | .set_page = &rs600_gart_set_page, | |
1184 | }, | |
4c87bc26 CK |
1185 | .ring = { |
1186 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1187 | .ib_execute = &r600_ring_ib_execute, | |
1188 | .emit_fence = &r600_fence_ring_emit, | |
1189 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 1190 | .cs_parse = &r600_cs_parse, |
f712812e AD |
1191 | .ring_test = &r600_ring_test, |
1192 | .ib_test = &r600_ib_test, | |
123bc183 | 1193 | .is_lockup = &r600_gfx_is_lockup, |
f93bdefe AD |
1194 | .get_rptr = &radeon_ring_generic_get_rptr, |
1195 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1196 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4d75658b AD |
1197 | }, |
1198 | [R600_RING_TYPE_DMA_INDEX] = { | |
1199 | .ib_execute = &r600_dma_ring_ib_execute, | |
1200 | .emit_fence = &r600_dma_fence_ring_emit, | |
1201 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
cf4ccd01 | 1202 | .cs_parse = &r600_dma_cs_parse, |
4d75658b AD |
1203 | .ring_test = &r600_dma_ring_test, |
1204 | .ib_test = &r600_dma_ib_test, | |
1205 | .is_lockup = &r600_dma_is_lockup, | |
f93bdefe AD |
1206 | .get_rptr = &radeon_ring_generic_get_rptr, |
1207 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1208 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4c87bc26 CK |
1209 | } |
1210 | }, | |
b35ea4ab AD |
1211 | .irq = { |
1212 | .set = &r600_irq_set, | |
1213 | .process = &r600_irq_process, | |
1214 | }, | |
c79a49ca AD |
1215 | .display = { |
1216 | .bandwidth_update = &rs690_bandwidth_update, | |
1217 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1218 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 1219 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1220 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
1221 | .hdmi_enable = &r600_hdmi_enable, |
1222 | .hdmi_setmode = &r600_hdmi_setmode, | |
c79a49ca | 1223 | }, |
27cd7769 AD |
1224 | .copy = { |
1225 | .blit = &r600_copy_blit, | |
1226 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
4d75658b AD |
1227 | .dma = &r600_copy_dma, |
1228 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1229 | .copy = &r600_copy_dma, |
1230 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1231 | }, |
9e6f3d02 AD |
1232 | .surface = { |
1233 | .set_reg = r600_set_surface_reg, | |
1234 | .clear_reg = r600_clear_surface_reg, | |
1235 | }, | |
901ea57d AD |
1236 | .hpd = { |
1237 | .init = &r600_hpd_init, | |
1238 | .fini = &r600_hpd_fini, | |
1239 | .sense = &r600_hpd_sense, | |
1240 | .set_polarity = &r600_hpd_set_polarity, | |
1241 | }, | |
a02fa397 AD |
1242 | .pm = { |
1243 | .misc = &r600_pm_misc, | |
1244 | .prepare = &rs600_pm_prepare, | |
1245 | .finish = &rs600_pm_finish, | |
1246 | .init_profile = &rs780_pm_init_profile, | |
1247 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1248 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1249 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1250 | .get_memory_clock = NULL, | |
1251 | .set_memory_clock = NULL, | |
1252 | .get_pcie_lanes = NULL, | |
1253 | .set_pcie_lanes = NULL, | |
1254 | .set_clock_gating = NULL, | |
6bd1c385 | 1255 | .get_temperature = &rv6xx_get_temp, |
a02fa397 | 1256 | }, |
9d67006e AD |
1257 | .dpm = { |
1258 | .init = &rs780_dpm_init, | |
1259 | .setup_asic = &rs780_dpm_setup_asic, | |
1260 | .enable = &rs780_dpm_enable, | |
1261 | .disable = &rs780_dpm_disable, | |
1262 | .set_power_state = &rs780_dpm_set_power_state, | |
1263 | .display_configuration_changed = &rs780_dpm_display_configuration_changed, | |
1264 | .fini = &rs780_dpm_fini, | |
1265 | .get_sclk = &rs780_dpm_get_sclk, | |
1266 | .get_mclk = &rs780_dpm_get_mclk, | |
1267 | .print_power_state = &rs780_dpm_print_power_state, | |
1268 | }, | |
0f9e006c AD |
1269 | .pflip = { |
1270 | .pre_page_flip = &rs600_pre_page_flip, | |
1271 | .page_flip = &rs600_page_flip, | |
1272 | .post_page_flip = &rs600_post_page_flip, | |
1273 | }, | |
f47299c5 AD |
1274 | }; |
1275 | ||
48e7a5f1 DV |
1276 | static struct radeon_asic rv770_asic = { |
1277 | .init = &rv770_init, | |
1278 | .fini = &rv770_fini, | |
1279 | .suspend = &rv770_suspend, | |
1280 | .resume = &rv770_resume, | |
a2d07b74 | 1281 | .asic_reset = &r600_asic_reset, |
48e7a5f1 | 1282 | .vga_set_state = &r600_vga_set_state, |
54e88e06 AD |
1283 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1284 | .gui_idle = &r600_gui_idle, | |
1285 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
454d2e2a | 1286 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1287 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1288 | .gart = { |
1289 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
1290 | .set_page = &rs600_gart_set_page, | |
1291 | }, | |
4c87bc26 CK |
1292 | .ring = { |
1293 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1294 | .ib_execute = &r600_ring_ib_execute, | |
1295 | .emit_fence = &r600_fence_ring_emit, | |
1296 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 1297 | .cs_parse = &r600_cs_parse, |
f712812e AD |
1298 | .ring_test = &r600_ring_test, |
1299 | .ib_test = &r600_ib_test, | |
123bc183 | 1300 | .is_lockup = &r600_gfx_is_lockup, |
f93bdefe AD |
1301 | .get_rptr = &radeon_ring_generic_get_rptr, |
1302 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1303 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4d75658b AD |
1304 | }, |
1305 | [R600_RING_TYPE_DMA_INDEX] = { | |
1306 | .ib_execute = &r600_dma_ring_ib_execute, | |
1307 | .emit_fence = &r600_dma_fence_ring_emit, | |
1308 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
cf4ccd01 | 1309 | .cs_parse = &r600_dma_cs_parse, |
4d75658b AD |
1310 | .ring_test = &r600_dma_ring_test, |
1311 | .ib_test = &r600_dma_ib_test, | |
1312 | .is_lockup = &r600_dma_is_lockup, | |
f93bdefe AD |
1313 | .get_rptr = &radeon_ring_generic_get_rptr, |
1314 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1315 | .set_wptr = &radeon_ring_generic_set_wptr, | |
f2ba57b5 CK |
1316 | }, |
1317 | [R600_RING_TYPE_UVD_INDEX] = { | |
1318 | .ib_execute = &r600_uvd_ib_execute, | |
1319 | .emit_fence = &r600_uvd_fence_emit, | |
1320 | .emit_semaphore = &r600_uvd_semaphore_emit, | |
1321 | .cs_parse = &radeon_uvd_cs_parse, | |
1322 | .ring_test = &r600_uvd_ring_test, | |
1323 | .ib_test = &r600_uvd_ib_test, | |
1324 | .is_lockup = &radeon_ring_test_lockup, | |
f93bdefe AD |
1325 | .get_rptr = &radeon_ring_generic_get_rptr, |
1326 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1327 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4c87bc26 CK |
1328 | } |
1329 | }, | |
b35ea4ab AD |
1330 | .irq = { |
1331 | .set = &r600_irq_set, | |
1332 | .process = &r600_irq_process, | |
1333 | }, | |
c79a49ca AD |
1334 | .display = { |
1335 | .bandwidth_update = &rv515_bandwidth_update, | |
1336 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1337 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 1338 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1339 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
1340 | .hdmi_enable = &r600_hdmi_enable, |
1341 | .hdmi_setmode = &r600_hdmi_setmode, | |
c79a49ca | 1342 | }, |
27cd7769 AD |
1343 | .copy = { |
1344 | .blit = &r600_copy_blit, | |
1345 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
43fb7787 | 1346 | .dma = &rv770_copy_dma, |
4d75658b | 1347 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
43fb7787 | 1348 | .copy = &rv770_copy_dma, |
2d6cc729 | 1349 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
27cd7769 | 1350 | }, |
9e6f3d02 AD |
1351 | .surface = { |
1352 | .set_reg = r600_set_surface_reg, | |
1353 | .clear_reg = r600_clear_surface_reg, | |
1354 | }, | |
901ea57d AD |
1355 | .hpd = { |
1356 | .init = &r600_hpd_init, | |
1357 | .fini = &r600_hpd_fini, | |
1358 | .sense = &r600_hpd_sense, | |
1359 | .set_polarity = &r600_hpd_set_polarity, | |
1360 | }, | |
a02fa397 AD |
1361 | .pm = { |
1362 | .misc = &rv770_pm_misc, | |
1363 | .prepare = &rs600_pm_prepare, | |
1364 | .finish = &rs600_pm_finish, | |
1365 | .init_profile = &r600_pm_init_profile, | |
1366 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1367 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1368 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1369 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1370 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1371 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1372 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1373 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
ef0e6e65 | 1374 | .set_uvd_clocks = &rv770_set_uvd_clocks, |
6bd1c385 | 1375 | .get_temperature = &rv770_get_temp, |
a02fa397 | 1376 | }, |
66229b20 AD |
1377 | .dpm = { |
1378 | .init = &rv770_dpm_init, | |
1379 | .setup_asic = &rv770_dpm_setup_asic, | |
1380 | .enable = &rv770_dpm_enable, | |
1381 | .disable = &rv770_dpm_disable, | |
1382 | .set_power_state = &rv770_dpm_set_power_state, | |
1383 | .display_configuration_changed = &rv770_dpm_display_configuration_changed, | |
1384 | .fini = &rv770_dpm_fini, | |
1385 | .get_sclk = &rv770_dpm_get_sclk, | |
1386 | .get_mclk = &rv770_dpm_get_mclk, | |
1387 | .print_power_state = &rv770_dpm_print_power_state, | |
1388 | }, | |
0f9e006c AD |
1389 | .pflip = { |
1390 | .pre_page_flip = &rs600_pre_page_flip, | |
1391 | .page_flip = &rv770_page_flip, | |
1392 | .post_page_flip = &rs600_post_page_flip, | |
1393 | }, | |
48e7a5f1 DV |
1394 | }; |
1395 | ||
1396 | static struct radeon_asic evergreen_asic = { | |
1397 | .init = &evergreen_init, | |
1398 | .fini = &evergreen_fini, | |
1399 | .suspend = &evergreen_suspend, | |
1400 | .resume = &evergreen_resume, | |
a2d07b74 | 1401 | .asic_reset = &evergreen_asic_reset, |
48e7a5f1 | 1402 | .vga_set_state = &r600_vga_set_state, |
54e88e06 AD |
1403 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1404 | .gui_idle = &r600_gui_idle, | |
1405 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1406 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1407 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1408 | .gart = { |
1409 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
1410 | .set_page = &rs600_gart_set_page, | |
1411 | }, | |
4c87bc26 CK |
1412 | .ring = { |
1413 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1414 | .ib_execute = &evergreen_ring_ib_execute, | |
1415 | .emit_fence = &r600_fence_ring_emit, | |
1416 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 1417 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1418 | .ring_test = &r600_ring_test, |
1419 | .ib_test = &r600_ib_test, | |
123bc183 | 1420 | .is_lockup = &evergreen_gfx_is_lockup, |
f93bdefe AD |
1421 | .get_rptr = &radeon_ring_generic_get_rptr, |
1422 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1423 | .set_wptr = &radeon_ring_generic_set_wptr, | |
233d1ad5 AD |
1424 | }, |
1425 | [R600_RING_TYPE_DMA_INDEX] = { | |
1426 | .ib_execute = &evergreen_dma_ring_ib_execute, | |
1427 | .emit_fence = &evergreen_dma_fence_ring_emit, | |
1428 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
d2ead3ea | 1429 | .cs_parse = &evergreen_dma_cs_parse, |
233d1ad5 AD |
1430 | .ring_test = &r600_dma_ring_test, |
1431 | .ib_test = &r600_dma_ib_test, | |
123bc183 | 1432 | .is_lockup = &evergreen_dma_is_lockup, |
f93bdefe AD |
1433 | .get_rptr = &radeon_ring_generic_get_rptr, |
1434 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1435 | .set_wptr = &radeon_ring_generic_set_wptr, | |
f2ba57b5 CK |
1436 | }, |
1437 | [R600_RING_TYPE_UVD_INDEX] = { | |
1438 | .ib_execute = &r600_uvd_ib_execute, | |
1439 | .emit_fence = &r600_uvd_fence_emit, | |
1440 | .emit_semaphore = &r600_uvd_semaphore_emit, | |
1441 | .cs_parse = &radeon_uvd_cs_parse, | |
1442 | .ring_test = &r600_uvd_ring_test, | |
1443 | .ib_test = &r600_uvd_ib_test, | |
1444 | .is_lockup = &radeon_ring_test_lockup, | |
f93bdefe AD |
1445 | .get_rptr = &radeon_ring_generic_get_rptr, |
1446 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1447 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4c87bc26 CK |
1448 | } |
1449 | }, | |
b35ea4ab AD |
1450 | .irq = { |
1451 | .set = &evergreen_irq_set, | |
1452 | .process = &evergreen_irq_process, | |
1453 | }, | |
c79a49ca AD |
1454 | .display = { |
1455 | .bandwidth_update = &evergreen_bandwidth_update, | |
1456 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1457 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1458 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1459 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
1460 | .hdmi_enable = &evergreen_hdmi_enable, |
1461 | .hdmi_setmode = &evergreen_hdmi_setmode, | |
c79a49ca | 1462 | }, |
27cd7769 AD |
1463 | .copy = { |
1464 | .blit = &r600_copy_blit, | |
1465 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
233d1ad5 AD |
1466 | .dma = &evergreen_copy_dma, |
1467 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1468 | .copy = &evergreen_copy_dma, |
1469 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1470 | }, |
9e6f3d02 AD |
1471 | .surface = { |
1472 | .set_reg = r600_set_surface_reg, | |
1473 | .clear_reg = r600_clear_surface_reg, | |
1474 | }, | |
901ea57d AD |
1475 | .hpd = { |
1476 | .init = &evergreen_hpd_init, | |
1477 | .fini = &evergreen_hpd_fini, | |
1478 | .sense = &evergreen_hpd_sense, | |
1479 | .set_polarity = &evergreen_hpd_set_polarity, | |
1480 | }, | |
a02fa397 AD |
1481 | .pm = { |
1482 | .misc = &evergreen_pm_misc, | |
1483 | .prepare = &evergreen_pm_prepare, | |
1484 | .finish = &evergreen_pm_finish, | |
1485 | .init_profile = &r600_pm_init_profile, | |
1486 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1487 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1488 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1489 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1490 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1491 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1492 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1493 | .set_clock_gating = NULL, | |
a8b4925c | 1494 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
6bd1c385 | 1495 | .get_temperature = &evergreen_get_temp, |
a02fa397 | 1496 | }, |
dc50ba7f AD |
1497 | .dpm = { |
1498 | .init = &cypress_dpm_init, | |
1499 | .setup_asic = &cypress_dpm_setup_asic, | |
1500 | .enable = &cypress_dpm_enable, | |
1501 | .disable = &cypress_dpm_disable, | |
1502 | .set_power_state = &cypress_dpm_set_power_state, | |
1503 | .display_configuration_changed = &cypress_dpm_display_configuration_changed, | |
1504 | .fini = &cypress_dpm_fini, | |
1505 | .get_sclk = &rv770_dpm_get_sclk, | |
1506 | .get_mclk = &rv770_dpm_get_mclk, | |
1507 | .print_power_state = &rv770_dpm_print_power_state, | |
1508 | }, | |
0f9e006c AD |
1509 | .pflip = { |
1510 | .pre_page_flip = &evergreen_pre_page_flip, | |
1511 | .page_flip = &evergreen_page_flip, | |
1512 | .post_page_flip = &evergreen_post_page_flip, | |
1513 | }, | |
48e7a5f1 DV |
1514 | }; |
1515 | ||
958261d1 AD |
1516 | static struct radeon_asic sumo_asic = { |
1517 | .init = &evergreen_init, | |
1518 | .fini = &evergreen_fini, | |
1519 | .suspend = &evergreen_suspend, | |
1520 | .resume = &evergreen_resume, | |
958261d1 AD |
1521 | .asic_reset = &evergreen_asic_reset, |
1522 | .vga_set_state = &r600_vga_set_state, | |
54e88e06 AD |
1523 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1524 | .gui_idle = &r600_gui_idle, | |
1525 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1526 | .get_xclk = &r600_get_xclk, |
d0418894 | 1527 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1528 | .gart = { |
1529 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
1530 | .set_page = &rs600_gart_set_page, | |
1531 | }, | |
4c87bc26 CK |
1532 | .ring = { |
1533 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1534 | .ib_execute = &evergreen_ring_ib_execute, | |
1535 | .emit_fence = &r600_fence_ring_emit, | |
1536 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 1537 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1538 | .ring_test = &r600_ring_test, |
1539 | .ib_test = &r600_ib_test, | |
123bc183 | 1540 | .is_lockup = &evergreen_gfx_is_lockup, |
f93bdefe AD |
1541 | .get_rptr = &radeon_ring_generic_get_rptr, |
1542 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1543 | .set_wptr = &radeon_ring_generic_set_wptr, | |
eb0c19c5 | 1544 | }, |
233d1ad5 AD |
1545 | [R600_RING_TYPE_DMA_INDEX] = { |
1546 | .ib_execute = &evergreen_dma_ring_ib_execute, | |
1547 | .emit_fence = &evergreen_dma_fence_ring_emit, | |
1548 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
d2ead3ea | 1549 | .cs_parse = &evergreen_dma_cs_parse, |
233d1ad5 AD |
1550 | .ring_test = &r600_dma_ring_test, |
1551 | .ib_test = &r600_dma_ib_test, | |
123bc183 | 1552 | .is_lockup = &evergreen_dma_is_lockup, |
f93bdefe AD |
1553 | .get_rptr = &radeon_ring_generic_get_rptr, |
1554 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1555 | .set_wptr = &radeon_ring_generic_set_wptr, | |
f2ba57b5 CK |
1556 | }, |
1557 | [R600_RING_TYPE_UVD_INDEX] = { | |
1558 | .ib_execute = &r600_uvd_ib_execute, | |
1559 | .emit_fence = &r600_uvd_fence_emit, | |
1560 | .emit_semaphore = &r600_uvd_semaphore_emit, | |
1561 | .cs_parse = &radeon_uvd_cs_parse, | |
1562 | .ring_test = &r600_uvd_ring_test, | |
1563 | .ib_test = &r600_uvd_ib_test, | |
1564 | .is_lockup = &radeon_ring_test_lockup, | |
f93bdefe AD |
1565 | .get_rptr = &radeon_ring_generic_get_rptr, |
1566 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1567 | .set_wptr = &radeon_ring_generic_set_wptr, | |
233d1ad5 | 1568 | } |
4c87bc26 | 1569 | }, |
b35ea4ab AD |
1570 | .irq = { |
1571 | .set = &evergreen_irq_set, | |
1572 | .process = &evergreen_irq_process, | |
1573 | }, | |
c79a49ca AD |
1574 | .display = { |
1575 | .bandwidth_update = &evergreen_bandwidth_update, | |
1576 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1577 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1578 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1579 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
1580 | .hdmi_enable = &evergreen_hdmi_enable, |
1581 | .hdmi_setmode = &evergreen_hdmi_setmode, | |
c79a49ca | 1582 | }, |
27cd7769 AD |
1583 | .copy = { |
1584 | .blit = &r600_copy_blit, | |
1585 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
233d1ad5 AD |
1586 | .dma = &evergreen_copy_dma, |
1587 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1588 | .copy = &evergreen_copy_dma, |
1589 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1590 | }, |
9e6f3d02 AD |
1591 | .surface = { |
1592 | .set_reg = r600_set_surface_reg, | |
1593 | .clear_reg = r600_clear_surface_reg, | |
1594 | }, | |
901ea57d AD |
1595 | .hpd = { |
1596 | .init = &evergreen_hpd_init, | |
1597 | .fini = &evergreen_hpd_fini, | |
1598 | .sense = &evergreen_hpd_sense, | |
1599 | .set_polarity = &evergreen_hpd_set_polarity, | |
1600 | }, | |
a02fa397 AD |
1601 | .pm = { |
1602 | .misc = &evergreen_pm_misc, | |
1603 | .prepare = &evergreen_pm_prepare, | |
1604 | .finish = &evergreen_pm_finish, | |
1605 | .init_profile = &sumo_pm_init_profile, | |
1606 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1607 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1608 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1609 | .get_memory_clock = NULL, | |
1610 | .set_memory_clock = NULL, | |
1611 | .get_pcie_lanes = NULL, | |
1612 | .set_pcie_lanes = NULL, | |
1613 | .set_clock_gating = NULL, | |
23d33ba3 | 1614 | .set_uvd_clocks = &sumo_set_uvd_clocks, |
6bd1c385 | 1615 | .get_temperature = &sumo_get_temp, |
a02fa397 | 1616 | }, |
80ea2c12 AD |
1617 | .dpm = { |
1618 | .init = &sumo_dpm_init, | |
1619 | .setup_asic = &sumo_dpm_setup_asic, | |
1620 | .enable = &sumo_dpm_enable, | |
1621 | .disable = &sumo_dpm_disable, | |
1622 | .set_power_state = &sumo_dpm_set_power_state, | |
1623 | .display_configuration_changed = &sumo_dpm_display_configuration_changed, | |
1624 | .fini = &sumo_dpm_fini, | |
1625 | .get_sclk = &sumo_dpm_get_sclk, | |
1626 | .get_mclk = &sumo_dpm_get_mclk, | |
1627 | .print_power_state = &sumo_dpm_print_power_state, | |
1628 | }, | |
0f9e006c AD |
1629 | .pflip = { |
1630 | .pre_page_flip = &evergreen_pre_page_flip, | |
1631 | .page_flip = &evergreen_page_flip, | |
1632 | .post_page_flip = &evergreen_post_page_flip, | |
1633 | }, | |
958261d1 AD |
1634 | }; |
1635 | ||
a43b7665 AD |
1636 | static struct radeon_asic btc_asic = { |
1637 | .init = &evergreen_init, | |
1638 | .fini = &evergreen_fini, | |
1639 | .suspend = &evergreen_suspend, | |
1640 | .resume = &evergreen_resume, | |
a43b7665 AD |
1641 | .asic_reset = &evergreen_asic_reset, |
1642 | .vga_set_state = &r600_vga_set_state, | |
54e88e06 AD |
1643 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1644 | .gui_idle = &r600_gui_idle, | |
1645 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1646 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1647 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1648 | .gart = { |
1649 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
1650 | .set_page = &rs600_gart_set_page, | |
1651 | }, | |
4c87bc26 CK |
1652 | .ring = { |
1653 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1654 | .ib_execute = &evergreen_ring_ib_execute, | |
1655 | .emit_fence = &r600_fence_ring_emit, | |
1656 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 1657 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1658 | .ring_test = &r600_ring_test, |
1659 | .ib_test = &r600_ib_test, | |
123bc183 | 1660 | .is_lockup = &evergreen_gfx_is_lockup, |
f93bdefe AD |
1661 | .get_rptr = &radeon_ring_generic_get_rptr, |
1662 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1663 | .set_wptr = &radeon_ring_generic_set_wptr, | |
233d1ad5 AD |
1664 | }, |
1665 | [R600_RING_TYPE_DMA_INDEX] = { | |
1666 | .ib_execute = &evergreen_dma_ring_ib_execute, | |
1667 | .emit_fence = &evergreen_dma_fence_ring_emit, | |
1668 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
d2ead3ea | 1669 | .cs_parse = &evergreen_dma_cs_parse, |
233d1ad5 AD |
1670 | .ring_test = &r600_dma_ring_test, |
1671 | .ib_test = &r600_dma_ib_test, | |
123bc183 | 1672 | .is_lockup = &evergreen_dma_is_lockup, |
f93bdefe AD |
1673 | .get_rptr = &radeon_ring_generic_get_rptr, |
1674 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1675 | .set_wptr = &radeon_ring_generic_set_wptr, | |
f2ba57b5 CK |
1676 | }, |
1677 | [R600_RING_TYPE_UVD_INDEX] = { | |
1678 | .ib_execute = &r600_uvd_ib_execute, | |
1679 | .emit_fence = &r600_uvd_fence_emit, | |
1680 | .emit_semaphore = &r600_uvd_semaphore_emit, | |
1681 | .cs_parse = &radeon_uvd_cs_parse, | |
1682 | .ring_test = &r600_uvd_ring_test, | |
1683 | .ib_test = &r600_uvd_ib_test, | |
1684 | .is_lockup = &radeon_ring_test_lockup, | |
f93bdefe AD |
1685 | .get_rptr = &radeon_ring_generic_get_rptr, |
1686 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1687 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4c87bc26 CK |
1688 | } |
1689 | }, | |
b35ea4ab AD |
1690 | .irq = { |
1691 | .set = &evergreen_irq_set, | |
1692 | .process = &evergreen_irq_process, | |
1693 | }, | |
c79a49ca AD |
1694 | .display = { |
1695 | .bandwidth_update = &evergreen_bandwidth_update, | |
1696 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1697 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1698 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1699 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
1700 | .hdmi_enable = &evergreen_hdmi_enable, |
1701 | .hdmi_setmode = &evergreen_hdmi_setmode, | |
c79a49ca | 1702 | }, |
27cd7769 AD |
1703 | .copy = { |
1704 | .blit = &r600_copy_blit, | |
1705 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
233d1ad5 AD |
1706 | .dma = &evergreen_copy_dma, |
1707 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1708 | .copy = &evergreen_copy_dma, |
1709 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1710 | }, |
9e6f3d02 AD |
1711 | .surface = { |
1712 | .set_reg = r600_set_surface_reg, | |
1713 | .clear_reg = r600_clear_surface_reg, | |
1714 | }, | |
901ea57d AD |
1715 | .hpd = { |
1716 | .init = &evergreen_hpd_init, | |
1717 | .fini = &evergreen_hpd_fini, | |
1718 | .sense = &evergreen_hpd_sense, | |
1719 | .set_polarity = &evergreen_hpd_set_polarity, | |
1720 | }, | |
a02fa397 AD |
1721 | .pm = { |
1722 | .misc = &evergreen_pm_misc, | |
1723 | .prepare = &evergreen_pm_prepare, | |
1724 | .finish = &evergreen_pm_finish, | |
27810fb2 | 1725 | .init_profile = &btc_pm_init_profile, |
a02fa397 | 1726 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
798bcf73 AD |
1727 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1728 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1729 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1730 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
55b615ae AD |
1731 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1732 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
798bcf73 | 1733 | .set_clock_gating = NULL, |
a8b4925c | 1734 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
6bd1c385 | 1735 | .get_temperature = &evergreen_get_temp, |
a02fa397 | 1736 | }, |
6596afd4 AD |
1737 | .dpm = { |
1738 | .init = &btc_dpm_init, | |
1739 | .setup_asic = &btc_dpm_setup_asic, | |
1740 | .enable = &btc_dpm_enable, | |
1741 | .disable = &btc_dpm_disable, | |
1742 | .set_power_state = &btc_dpm_set_power_state, | |
1743 | .display_configuration_changed = &cypress_dpm_display_configuration_changed, | |
1744 | .fini = &btc_dpm_fini, | |
1745 | .get_sclk = &rv770_dpm_get_sclk, | |
1746 | .get_mclk = &rv770_dpm_get_mclk, | |
1747 | .print_power_state = &rv770_dpm_print_power_state, | |
1748 | }, | |
0f9e006c AD |
1749 | .pflip = { |
1750 | .pre_page_flip = &evergreen_pre_page_flip, | |
1751 | .page_flip = &evergreen_page_flip, | |
1752 | .post_page_flip = &evergreen_post_page_flip, | |
1753 | }, | |
a43b7665 AD |
1754 | }; |
1755 | ||
e3487629 AD |
1756 | static struct radeon_asic cayman_asic = { |
1757 | .init = &cayman_init, | |
1758 | .fini = &cayman_fini, | |
1759 | .suspend = &cayman_suspend, | |
1760 | .resume = &cayman_resume, | |
e3487629 AD |
1761 | .asic_reset = &cayman_asic_reset, |
1762 | .vga_set_state = &r600_vga_set_state, | |
54e88e06 AD |
1763 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1764 | .gui_idle = &r600_gui_idle, | |
1765 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1766 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1767 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1768 | .gart = { |
1769 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | |
1770 | .set_page = &rs600_gart_set_page, | |
1771 | }, | |
05b07147 CK |
1772 | .vm = { |
1773 | .init = &cayman_vm_init, | |
1774 | .fini = &cayman_vm_fini, | |
df160044 | 1775 | .pt_ring_index = R600_RING_TYPE_DMA_INDEX, |
05b07147 CK |
1776 | .set_page = &cayman_vm_set_page, |
1777 | }, | |
4c87bc26 CK |
1778 | .ring = { |
1779 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
721604a1 JG |
1780 | .ib_execute = &cayman_ring_ib_execute, |
1781 | .ib_parse = &evergreen_ib_parse, | |
b40e7e16 | 1782 | .emit_fence = &cayman_fence_ring_emit, |
4c87bc26 | 1783 | .emit_semaphore = &r600_semaphore_ring_emit, |
eb0c19c5 | 1784 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1785 | .ring_test = &r600_ring_test, |
1786 | .ib_test = &r600_ib_test, | |
123bc183 | 1787 | .is_lockup = &cayman_gfx_is_lockup, |
9b40e5d8 | 1788 | .vm_flush = &cayman_vm_flush, |
f93bdefe AD |
1789 | .get_rptr = &radeon_ring_generic_get_rptr, |
1790 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1791 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4c87bc26 CK |
1792 | }, |
1793 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | |
721604a1 JG |
1794 | .ib_execute = &cayman_ring_ib_execute, |
1795 | .ib_parse = &evergreen_ib_parse, | |
b40e7e16 | 1796 | .emit_fence = &cayman_fence_ring_emit, |
4c87bc26 | 1797 | .emit_semaphore = &r600_semaphore_ring_emit, |
eb0c19c5 | 1798 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1799 | .ring_test = &r600_ring_test, |
1800 | .ib_test = &r600_ib_test, | |
123bc183 | 1801 | .is_lockup = &cayman_gfx_is_lockup, |
9b40e5d8 | 1802 | .vm_flush = &cayman_vm_flush, |
f93bdefe AD |
1803 | .get_rptr = &radeon_ring_generic_get_rptr, |
1804 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1805 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4c87bc26 CK |
1806 | }, |
1807 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | |
721604a1 JG |
1808 | .ib_execute = &cayman_ring_ib_execute, |
1809 | .ib_parse = &evergreen_ib_parse, | |
b40e7e16 | 1810 | .emit_fence = &cayman_fence_ring_emit, |
4c87bc26 | 1811 | .emit_semaphore = &r600_semaphore_ring_emit, |
eb0c19c5 | 1812 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1813 | .ring_test = &r600_ring_test, |
1814 | .ib_test = &r600_ib_test, | |
123bc183 | 1815 | .is_lockup = &cayman_gfx_is_lockup, |
9b40e5d8 | 1816 | .vm_flush = &cayman_vm_flush, |
f93bdefe AD |
1817 | .get_rptr = &radeon_ring_generic_get_rptr, |
1818 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1819 | .set_wptr = &radeon_ring_generic_set_wptr, | |
f60cbd11 AD |
1820 | }, |
1821 | [R600_RING_TYPE_DMA_INDEX] = { | |
1822 | .ib_execute = &cayman_dma_ring_ib_execute, | |
cd459e52 | 1823 | .ib_parse = &evergreen_dma_ib_parse, |
f60cbd11 AD |
1824 | .emit_fence = &evergreen_dma_fence_ring_emit, |
1825 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
d2ead3ea | 1826 | .cs_parse = &evergreen_dma_cs_parse, |
f60cbd11 AD |
1827 | .ring_test = &r600_dma_ring_test, |
1828 | .ib_test = &r600_dma_ib_test, | |
1829 | .is_lockup = &cayman_dma_is_lockup, | |
1830 | .vm_flush = &cayman_dma_vm_flush, | |
f93bdefe AD |
1831 | .get_rptr = &radeon_ring_generic_get_rptr, |
1832 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1833 | .set_wptr = &radeon_ring_generic_set_wptr, | |
f60cbd11 AD |
1834 | }, |
1835 | [CAYMAN_RING_TYPE_DMA1_INDEX] = { | |
1836 | .ib_execute = &cayman_dma_ring_ib_execute, | |
cd459e52 | 1837 | .ib_parse = &evergreen_dma_ib_parse, |
f60cbd11 AD |
1838 | .emit_fence = &evergreen_dma_fence_ring_emit, |
1839 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
d2ead3ea | 1840 | .cs_parse = &evergreen_dma_cs_parse, |
f60cbd11 AD |
1841 | .ring_test = &r600_dma_ring_test, |
1842 | .ib_test = &r600_dma_ib_test, | |
1843 | .is_lockup = &cayman_dma_is_lockup, | |
1844 | .vm_flush = &cayman_dma_vm_flush, | |
f93bdefe AD |
1845 | .get_rptr = &radeon_ring_generic_get_rptr, |
1846 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1847 | .set_wptr = &radeon_ring_generic_set_wptr, | |
f2ba57b5 CK |
1848 | }, |
1849 | [R600_RING_TYPE_UVD_INDEX] = { | |
1850 | .ib_execute = &r600_uvd_ib_execute, | |
1851 | .emit_fence = &r600_uvd_fence_emit, | |
1852 | .emit_semaphore = &cayman_uvd_semaphore_emit, | |
1853 | .cs_parse = &radeon_uvd_cs_parse, | |
1854 | .ring_test = &r600_uvd_ring_test, | |
1855 | .ib_test = &r600_uvd_ib_test, | |
1856 | .is_lockup = &radeon_ring_test_lockup, | |
f93bdefe AD |
1857 | .get_rptr = &radeon_ring_generic_get_rptr, |
1858 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1859 | .set_wptr = &radeon_ring_generic_set_wptr, | |
4c87bc26 CK |
1860 | } |
1861 | }, | |
b35ea4ab AD |
1862 | .irq = { |
1863 | .set = &evergreen_irq_set, | |
1864 | .process = &evergreen_irq_process, | |
1865 | }, | |
c79a49ca AD |
1866 | .display = { |
1867 | .bandwidth_update = &evergreen_bandwidth_update, | |
1868 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1869 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1870 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1871 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
1872 | .hdmi_enable = &evergreen_hdmi_enable, |
1873 | .hdmi_setmode = &evergreen_hdmi_setmode, | |
c79a49ca | 1874 | }, |
27cd7769 AD |
1875 | .copy = { |
1876 | .blit = &r600_copy_blit, | |
1877 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
f60cbd11 AD |
1878 | .dma = &evergreen_copy_dma, |
1879 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1880 | .copy = &evergreen_copy_dma, |
1881 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1882 | }, |
9e6f3d02 AD |
1883 | .surface = { |
1884 | .set_reg = r600_set_surface_reg, | |
1885 | .clear_reg = r600_clear_surface_reg, | |
1886 | }, | |
901ea57d AD |
1887 | .hpd = { |
1888 | .init = &evergreen_hpd_init, | |
1889 | .fini = &evergreen_hpd_fini, | |
1890 | .sense = &evergreen_hpd_sense, | |
1891 | .set_polarity = &evergreen_hpd_set_polarity, | |
1892 | }, | |
a02fa397 AD |
1893 | .pm = { |
1894 | .misc = &evergreen_pm_misc, | |
1895 | .prepare = &evergreen_pm_prepare, | |
1896 | .finish = &evergreen_pm_finish, | |
27810fb2 | 1897 | .init_profile = &btc_pm_init_profile, |
a02fa397 | 1898 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
798bcf73 AD |
1899 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1900 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1901 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1902 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
55b615ae AD |
1903 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1904 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
798bcf73 | 1905 | .set_clock_gating = NULL, |
a8b4925c | 1906 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
6bd1c385 | 1907 | .get_temperature = &evergreen_get_temp, |
a02fa397 | 1908 | }, |
69e0b57a AD |
1909 | .dpm = { |
1910 | .init = &ni_dpm_init, | |
1911 | .setup_asic = &ni_dpm_setup_asic, | |
1912 | .enable = &ni_dpm_enable, | |
1913 | .disable = &ni_dpm_disable, | |
1914 | .set_power_state = &ni_dpm_set_power_state, | |
1915 | .display_configuration_changed = &cypress_dpm_display_configuration_changed, | |
1916 | .fini = &ni_dpm_fini, | |
1917 | .get_sclk = &ni_dpm_get_sclk, | |
1918 | .get_mclk = &ni_dpm_get_mclk, | |
1919 | .print_power_state = &ni_dpm_print_power_state, | |
1920 | }, | |
0f9e006c AD |
1921 | .pflip = { |
1922 | .pre_page_flip = &evergreen_pre_page_flip, | |
1923 | .page_flip = &evergreen_page_flip, | |
1924 | .post_page_flip = &evergreen_post_page_flip, | |
1925 | }, | |
e3487629 AD |
1926 | }; |
1927 | ||
be63fe8c AD |
1928 | static struct radeon_asic trinity_asic = { |
1929 | .init = &cayman_init, | |
1930 | .fini = &cayman_fini, | |
1931 | .suspend = &cayman_suspend, | |
1932 | .resume = &cayman_resume, | |
be63fe8c AD |
1933 | .asic_reset = &cayman_asic_reset, |
1934 | .vga_set_state = &r600_vga_set_state, | |
1935 | .ioctl_wait_idle = r600_ioctl_wait_idle, | |
1936 | .gui_idle = &r600_gui_idle, | |
1937 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1938 | .get_xclk = &r600_get_xclk, |
d0418894 | 1939 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
be63fe8c AD |
1940 | .gart = { |
1941 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | |
1942 | .set_page = &rs600_gart_set_page, | |
1943 | }, | |
05b07147 CK |
1944 | .vm = { |
1945 | .init = &cayman_vm_init, | |
1946 | .fini = &cayman_vm_fini, | |
df160044 | 1947 | .pt_ring_index = R600_RING_TYPE_DMA_INDEX, |
05b07147 CK |
1948 | .set_page = &cayman_vm_set_page, |
1949 | }, | |
be63fe8c AD |
1950 | .ring = { |
1951 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1952 | .ib_execute = &cayman_ring_ib_execute, | |
1953 | .ib_parse = &evergreen_ib_parse, | |
1954 | .emit_fence = &cayman_fence_ring_emit, | |
1955 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1956 | .cs_parse = &evergreen_cs_parse, | |
1957 | .ring_test = &r600_ring_test, | |
1958 | .ib_test = &r600_ib_test, | |
123bc183 | 1959 | .is_lockup = &cayman_gfx_is_lockup, |
9b40e5d8 | 1960 | .vm_flush = &cayman_vm_flush, |
f93bdefe AD |
1961 | .get_rptr = &radeon_ring_generic_get_rptr, |
1962 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1963 | .set_wptr = &radeon_ring_generic_set_wptr, | |
be63fe8c AD |
1964 | }, |
1965 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | |
1966 | .ib_execute = &cayman_ring_ib_execute, | |
1967 | .ib_parse = &evergreen_ib_parse, | |
1968 | .emit_fence = &cayman_fence_ring_emit, | |
1969 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1970 | .cs_parse = &evergreen_cs_parse, | |
1971 | .ring_test = &r600_ring_test, | |
1972 | .ib_test = &r600_ib_test, | |
123bc183 | 1973 | .is_lockup = &cayman_gfx_is_lockup, |
9b40e5d8 | 1974 | .vm_flush = &cayman_vm_flush, |
f93bdefe AD |
1975 | .get_rptr = &radeon_ring_generic_get_rptr, |
1976 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1977 | .set_wptr = &radeon_ring_generic_set_wptr, | |
be63fe8c AD |
1978 | }, |
1979 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | |
1980 | .ib_execute = &cayman_ring_ib_execute, | |
1981 | .ib_parse = &evergreen_ib_parse, | |
1982 | .emit_fence = &cayman_fence_ring_emit, | |
1983 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1984 | .cs_parse = &evergreen_cs_parse, | |
1985 | .ring_test = &r600_ring_test, | |
1986 | .ib_test = &r600_ib_test, | |
123bc183 | 1987 | .is_lockup = &cayman_gfx_is_lockup, |
9b40e5d8 | 1988 | .vm_flush = &cayman_vm_flush, |
f93bdefe AD |
1989 | .get_rptr = &radeon_ring_generic_get_rptr, |
1990 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1991 | .set_wptr = &radeon_ring_generic_set_wptr, | |
f60cbd11 AD |
1992 | }, |
1993 | [R600_RING_TYPE_DMA_INDEX] = { | |
1994 | .ib_execute = &cayman_dma_ring_ib_execute, | |
cd459e52 | 1995 | .ib_parse = &evergreen_dma_ib_parse, |
f60cbd11 AD |
1996 | .emit_fence = &evergreen_dma_fence_ring_emit, |
1997 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
d2ead3ea | 1998 | .cs_parse = &evergreen_dma_cs_parse, |
f60cbd11 AD |
1999 | .ring_test = &r600_dma_ring_test, |
2000 | .ib_test = &r600_dma_ib_test, | |
2001 | .is_lockup = &cayman_dma_is_lockup, | |
2002 | .vm_flush = &cayman_dma_vm_flush, | |
f93bdefe AD |
2003 | .get_rptr = &radeon_ring_generic_get_rptr, |
2004 | .get_wptr = &radeon_ring_generic_get_wptr, | |
2005 | .set_wptr = &radeon_ring_generic_set_wptr, | |
f60cbd11 AD |
2006 | }, |
2007 | [CAYMAN_RING_TYPE_DMA1_INDEX] = { | |
2008 | .ib_execute = &cayman_dma_ring_ib_execute, | |
cd459e52 | 2009 | .ib_parse = &evergreen_dma_ib_parse, |
f60cbd11 AD |
2010 | .emit_fence = &evergreen_dma_fence_ring_emit, |
2011 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
d2ead3ea | 2012 | .cs_parse = &evergreen_dma_cs_parse, |
f60cbd11 AD |
2013 | .ring_test = &r600_dma_ring_test, |
2014 | .ib_test = &r600_dma_ib_test, | |
2015 | .is_lockup = &cayman_dma_is_lockup, | |
2016 | .vm_flush = &cayman_dma_vm_flush, | |
f93bdefe AD |
2017 | .get_rptr = &radeon_ring_generic_get_rptr, |
2018 | .get_wptr = &radeon_ring_generic_get_wptr, | |
2019 | .set_wptr = &radeon_ring_generic_set_wptr, | |
f2ba57b5 CK |
2020 | }, |
2021 | [R600_RING_TYPE_UVD_INDEX] = { | |
2022 | .ib_execute = &r600_uvd_ib_execute, | |
2023 | .emit_fence = &r600_uvd_fence_emit, | |
2024 | .emit_semaphore = &cayman_uvd_semaphore_emit, | |
2025 | .cs_parse = &radeon_uvd_cs_parse, | |
2026 | .ring_test = &r600_uvd_ring_test, | |
2027 | .ib_test = &r600_uvd_ib_test, | |
2028 | .is_lockup = &radeon_ring_test_lockup, | |
f93bdefe AD |
2029 | .get_rptr = &radeon_ring_generic_get_rptr, |
2030 | .get_wptr = &radeon_ring_generic_get_wptr, | |
2031 | .set_wptr = &radeon_ring_generic_set_wptr, | |
be63fe8c AD |
2032 | } |
2033 | }, | |
2034 | .irq = { | |
2035 | .set = &evergreen_irq_set, | |
2036 | .process = &evergreen_irq_process, | |
2037 | }, | |
2038 | .display = { | |
2039 | .bandwidth_update = &dce6_bandwidth_update, | |
2040 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
2041 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 2042 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 2043 | .get_backlight_level = &atombios_get_backlight_level, |
be63fe8c AD |
2044 | }, |
2045 | .copy = { | |
2046 | .blit = &r600_copy_blit, | |
2047 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
f60cbd11 AD |
2048 | .dma = &evergreen_copy_dma, |
2049 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
2050 | .copy = &evergreen_copy_dma, |
2051 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
be63fe8c AD |
2052 | }, |
2053 | .surface = { | |
2054 | .set_reg = r600_set_surface_reg, | |
2055 | .clear_reg = r600_clear_surface_reg, | |
2056 | }, | |
2057 | .hpd = { | |
2058 | .init = &evergreen_hpd_init, | |
2059 | .fini = &evergreen_hpd_fini, | |
2060 | .sense = &evergreen_hpd_sense, | |
2061 | .set_polarity = &evergreen_hpd_set_polarity, | |
2062 | }, | |
2063 | .pm = { | |
2064 | .misc = &evergreen_pm_misc, | |
2065 | .prepare = &evergreen_pm_prepare, | |
2066 | .finish = &evergreen_pm_finish, | |
2067 | .init_profile = &sumo_pm_init_profile, | |
2068 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
2069 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
2070 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
2071 | .get_memory_clock = NULL, | |
2072 | .set_memory_clock = NULL, | |
2073 | .get_pcie_lanes = NULL, | |
2074 | .set_pcie_lanes = NULL, | |
2075 | .set_clock_gating = NULL, | |
23d33ba3 | 2076 | .set_uvd_clocks = &sumo_set_uvd_clocks, |
29a15221 | 2077 | .get_temperature = &tn_get_temp, |
be63fe8c | 2078 | }, |
d70229f7 AD |
2079 | .dpm = { |
2080 | .init = &trinity_dpm_init, | |
2081 | .setup_asic = &trinity_dpm_setup_asic, | |
2082 | .enable = &trinity_dpm_enable, | |
2083 | .disable = &trinity_dpm_disable, | |
2084 | .set_power_state = &trinity_dpm_set_power_state, | |
2085 | .display_configuration_changed = &trinity_dpm_display_configuration_changed, | |
2086 | .fini = &trinity_dpm_fini, | |
2087 | .get_sclk = &trinity_dpm_get_sclk, | |
2088 | .get_mclk = &trinity_dpm_get_mclk, | |
2089 | .print_power_state = &trinity_dpm_print_power_state, | |
2090 | }, | |
be63fe8c AD |
2091 | .pflip = { |
2092 | .pre_page_flip = &evergreen_pre_page_flip, | |
2093 | .page_flip = &evergreen_page_flip, | |
2094 | .post_page_flip = &evergreen_post_page_flip, | |
2095 | }, | |
2096 | }; | |
2097 | ||
02779c08 AD |
2098 | static struct radeon_asic si_asic = { |
2099 | .init = &si_init, | |
2100 | .fini = &si_fini, | |
2101 | .suspend = &si_suspend, | |
2102 | .resume = &si_resume, | |
02779c08 AD |
2103 | .asic_reset = &si_asic_reset, |
2104 | .vga_set_state = &r600_vga_set_state, | |
2105 | .ioctl_wait_idle = r600_ioctl_wait_idle, | |
2106 | .gui_idle = &r600_gui_idle, | |
2107 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 2108 | .get_xclk = &si_get_xclk, |
d0418894 | 2109 | .get_gpu_clock_counter = &si_get_gpu_clock_counter, |
02779c08 AD |
2110 | .gart = { |
2111 | .tlb_flush = &si_pcie_gart_tlb_flush, | |
2112 | .set_page = &rs600_gart_set_page, | |
2113 | }, | |
05b07147 CK |
2114 | .vm = { |
2115 | .init = &si_vm_init, | |
2116 | .fini = &si_vm_fini, | |
df160044 | 2117 | .pt_ring_index = R600_RING_TYPE_DMA_INDEX, |
82ffd92b | 2118 | .set_page = &si_vm_set_page, |
05b07147 | 2119 | }, |
02779c08 AD |
2120 | .ring = { |
2121 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
2122 | .ib_execute = &si_ring_ib_execute, | |
2123 | .ib_parse = &si_ib_parse, | |
2124 | .emit_fence = &si_fence_ring_emit, | |
2125 | .emit_semaphore = &r600_semaphore_ring_emit, | |
2126 | .cs_parse = NULL, | |
2127 | .ring_test = &r600_ring_test, | |
2128 | .ib_test = &r600_ib_test, | |
123bc183 | 2129 | .is_lockup = &si_gfx_is_lockup, |
ee60e29f | 2130 | .vm_flush = &si_vm_flush, |
f93bdefe AD |
2131 | .get_rptr = &radeon_ring_generic_get_rptr, |
2132 | .get_wptr = &radeon_ring_generic_get_wptr, | |
2133 | .set_wptr = &radeon_ring_generic_set_wptr, | |
02779c08 AD |
2134 | }, |
2135 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | |
2136 | .ib_execute = &si_ring_ib_execute, | |
2137 | .ib_parse = &si_ib_parse, | |
2138 | .emit_fence = &si_fence_ring_emit, | |
2139 | .emit_semaphore = &r600_semaphore_ring_emit, | |
2140 | .cs_parse = NULL, | |
2141 | .ring_test = &r600_ring_test, | |
2142 | .ib_test = &r600_ib_test, | |
123bc183 | 2143 | .is_lockup = &si_gfx_is_lockup, |
ee60e29f | 2144 | .vm_flush = &si_vm_flush, |
f93bdefe AD |
2145 | .get_rptr = &radeon_ring_generic_get_rptr, |
2146 | .get_wptr = &radeon_ring_generic_get_wptr, | |
2147 | .set_wptr = &radeon_ring_generic_set_wptr, | |
02779c08 AD |
2148 | }, |
2149 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | |
2150 | .ib_execute = &si_ring_ib_execute, | |
2151 | .ib_parse = &si_ib_parse, | |
2152 | .emit_fence = &si_fence_ring_emit, | |
2153 | .emit_semaphore = &r600_semaphore_ring_emit, | |
2154 | .cs_parse = NULL, | |
2155 | .ring_test = &r600_ring_test, | |
2156 | .ib_test = &r600_ib_test, | |
123bc183 | 2157 | .is_lockup = &si_gfx_is_lockup, |
ee60e29f | 2158 | .vm_flush = &si_vm_flush, |
f93bdefe AD |
2159 | .get_rptr = &radeon_ring_generic_get_rptr, |
2160 | .get_wptr = &radeon_ring_generic_get_wptr, | |
2161 | .set_wptr = &radeon_ring_generic_set_wptr, | |
8c5fd7ef AD |
2162 | }, |
2163 | [R600_RING_TYPE_DMA_INDEX] = { | |
2164 | .ib_execute = &cayman_dma_ring_ib_execute, | |
cd459e52 | 2165 | .ib_parse = &evergreen_dma_ib_parse, |
8c5fd7ef AD |
2166 | .emit_fence = &evergreen_dma_fence_ring_emit, |
2167 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
2168 | .cs_parse = NULL, | |
2169 | .ring_test = &r600_dma_ring_test, | |
2170 | .ib_test = &r600_dma_ib_test, | |
123bc183 | 2171 | .is_lockup = &si_dma_is_lockup, |
8c5fd7ef | 2172 | .vm_flush = &si_dma_vm_flush, |
f93bdefe AD |
2173 | .get_rptr = &radeon_ring_generic_get_rptr, |
2174 | .get_wptr = &radeon_ring_generic_get_wptr, | |
2175 | .set_wptr = &radeon_ring_generic_set_wptr, | |
8c5fd7ef AD |
2176 | }, |
2177 | [CAYMAN_RING_TYPE_DMA1_INDEX] = { | |
2178 | .ib_execute = &cayman_dma_ring_ib_execute, | |
cd459e52 | 2179 | .ib_parse = &evergreen_dma_ib_parse, |
8c5fd7ef AD |
2180 | .emit_fence = &evergreen_dma_fence_ring_emit, |
2181 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
2182 | .cs_parse = NULL, | |
2183 | .ring_test = &r600_dma_ring_test, | |
2184 | .ib_test = &r600_dma_ib_test, | |
123bc183 | 2185 | .is_lockup = &si_dma_is_lockup, |
8c5fd7ef | 2186 | .vm_flush = &si_dma_vm_flush, |
f93bdefe AD |
2187 | .get_rptr = &radeon_ring_generic_get_rptr, |
2188 | .get_wptr = &radeon_ring_generic_get_wptr, | |
2189 | .set_wptr = &radeon_ring_generic_set_wptr, | |
f2ba57b5 CK |
2190 | }, |
2191 | [R600_RING_TYPE_UVD_INDEX] = { | |
2192 | .ib_execute = &r600_uvd_ib_execute, | |
2193 | .emit_fence = &r600_uvd_fence_emit, | |
2194 | .emit_semaphore = &cayman_uvd_semaphore_emit, | |
2195 | .cs_parse = &radeon_uvd_cs_parse, | |
2196 | .ring_test = &r600_uvd_ring_test, | |
2197 | .ib_test = &r600_uvd_ib_test, | |
2198 | .is_lockup = &radeon_ring_test_lockup, | |
f93bdefe AD |
2199 | .get_rptr = &radeon_ring_generic_get_rptr, |
2200 | .get_wptr = &radeon_ring_generic_get_wptr, | |
2201 | .set_wptr = &radeon_ring_generic_set_wptr, | |
02779c08 AD |
2202 | } |
2203 | }, | |
2204 | .irq = { | |
2205 | .set = &si_irq_set, | |
2206 | .process = &si_irq_process, | |
2207 | }, | |
2208 | .display = { | |
2209 | .bandwidth_update = &dce6_bandwidth_update, | |
2210 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
2211 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 2212 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 2213 | .get_backlight_level = &atombios_get_backlight_level, |
02779c08 AD |
2214 | }, |
2215 | .copy = { | |
2216 | .blit = NULL, | |
2217 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
8c5fd7ef AD |
2218 | .dma = &si_copy_dma, |
2219 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
2220 | .copy = &si_copy_dma, |
2221 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
02779c08 AD |
2222 | }, |
2223 | .surface = { | |
2224 | .set_reg = r600_set_surface_reg, | |
2225 | .clear_reg = r600_clear_surface_reg, | |
2226 | }, | |
2227 | .hpd = { | |
2228 | .init = &evergreen_hpd_init, | |
2229 | .fini = &evergreen_hpd_fini, | |
2230 | .sense = &evergreen_hpd_sense, | |
2231 | .set_polarity = &evergreen_hpd_set_polarity, | |
2232 | }, | |
2233 | .pm = { | |
2234 | .misc = &evergreen_pm_misc, | |
2235 | .prepare = &evergreen_pm_prepare, | |
2236 | .finish = &evergreen_pm_finish, | |
2237 | .init_profile = &sumo_pm_init_profile, | |
2238 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
2239 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
2240 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
2241 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
2242 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
55b615ae AD |
2243 | .get_pcie_lanes = &r600_get_pcie_lanes, |
2244 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
02779c08 | 2245 | .set_clock_gating = NULL, |
2539eb02 | 2246 | .set_uvd_clocks = &si_set_uvd_clocks, |
6bd1c385 | 2247 | .get_temperature = &si_get_temp, |
02779c08 AD |
2248 | }, |
2249 | .pflip = { | |
2250 | .pre_page_flip = &evergreen_pre_page_flip, | |
2251 | .page_flip = &evergreen_page_flip, | |
2252 | .post_page_flip = &evergreen_post_page_flip, | |
2253 | }, | |
2254 | }; | |
2255 | ||
0672e27b AD |
2256 | static struct radeon_asic ci_asic = { |
2257 | .init = &cik_init, | |
2258 | .fini = &cik_fini, | |
2259 | .suspend = &cik_suspend, | |
2260 | .resume = &cik_resume, | |
2261 | .asic_reset = &cik_asic_reset, | |
2262 | .vga_set_state = &r600_vga_set_state, | |
2263 | .ioctl_wait_idle = NULL, | |
2264 | .gui_idle = &r600_gui_idle, | |
2265 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
2266 | .get_xclk = &cik_get_xclk, | |
2267 | .get_gpu_clock_counter = &cik_get_gpu_clock_counter, | |
2268 | .gart = { | |
2269 | .tlb_flush = &cik_pcie_gart_tlb_flush, | |
2270 | .set_page = &rs600_gart_set_page, | |
2271 | }, | |
2272 | .vm = { | |
2273 | .init = &cik_vm_init, | |
2274 | .fini = &cik_vm_fini, | |
2275 | .pt_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2276 | .set_page = &cik_vm_set_page, | |
2277 | }, | |
2278 | .ring = { | |
2279 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
2280 | .ib_execute = &cik_ring_ib_execute, | |
2281 | .ib_parse = &cik_ib_parse, | |
2282 | .emit_fence = &cik_fence_gfx_ring_emit, | |
2283 | .emit_semaphore = &cik_semaphore_ring_emit, | |
2284 | .cs_parse = NULL, | |
2285 | .ring_test = &cik_ring_test, | |
2286 | .ib_test = &cik_ib_test, | |
2287 | .is_lockup = &cik_gfx_is_lockup, | |
2288 | .vm_flush = &cik_vm_flush, | |
2289 | .get_rptr = &radeon_ring_generic_get_rptr, | |
2290 | .get_wptr = &radeon_ring_generic_get_wptr, | |
2291 | .set_wptr = &radeon_ring_generic_set_wptr, | |
2292 | }, | |
2293 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | |
2294 | .ib_execute = &cik_ring_ib_execute, | |
2295 | .ib_parse = &cik_ib_parse, | |
2296 | .emit_fence = &cik_fence_compute_ring_emit, | |
2297 | .emit_semaphore = &cik_semaphore_ring_emit, | |
2298 | .cs_parse = NULL, | |
2299 | .ring_test = &cik_ring_test, | |
2300 | .ib_test = &cik_ib_test, | |
2301 | .is_lockup = &cik_gfx_is_lockup, | |
2302 | .vm_flush = &cik_vm_flush, | |
2303 | .get_rptr = &cik_compute_ring_get_rptr, | |
2304 | .get_wptr = &cik_compute_ring_get_wptr, | |
2305 | .set_wptr = &cik_compute_ring_set_wptr, | |
2306 | }, | |
2307 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | |
2308 | .ib_execute = &cik_ring_ib_execute, | |
2309 | .ib_parse = &cik_ib_parse, | |
2310 | .emit_fence = &cik_fence_compute_ring_emit, | |
2311 | .emit_semaphore = &cik_semaphore_ring_emit, | |
2312 | .cs_parse = NULL, | |
2313 | .ring_test = &cik_ring_test, | |
2314 | .ib_test = &cik_ib_test, | |
2315 | .is_lockup = &cik_gfx_is_lockup, | |
2316 | .vm_flush = &cik_vm_flush, | |
2317 | .get_rptr = &cik_compute_ring_get_rptr, | |
2318 | .get_wptr = &cik_compute_ring_get_wptr, | |
2319 | .set_wptr = &cik_compute_ring_set_wptr, | |
2320 | }, | |
2321 | [R600_RING_TYPE_DMA_INDEX] = { | |
2322 | .ib_execute = &cik_sdma_ring_ib_execute, | |
2323 | .ib_parse = &cik_ib_parse, | |
2324 | .emit_fence = &cik_sdma_fence_ring_emit, | |
2325 | .emit_semaphore = &cik_sdma_semaphore_ring_emit, | |
2326 | .cs_parse = NULL, | |
2327 | .ring_test = &cik_sdma_ring_test, | |
2328 | .ib_test = &cik_sdma_ib_test, | |
2329 | .is_lockup = &cik_sdma_is_lockup, | |
2330 | .vm_flush = &cik_dma_vm_flush, | |
2331 | .get_rptr = &radeon_ring_generic_get_rptr, | |
2332 | .get_wptr = &radeon_ring_generic_get_wptr, | |
2333 | .set_wptr = &radeon_ring_generic_set_wptr, | |
2334 | }, | |
2335 | [CAYMAN_RING_TYPE_DMA1_INDEX] = { | |
2336 | .ib_execute = &cik_sdma_ring_ib_execute, | |
2337 | .ib_parse = &cik_ib_parse, | |
2338 | .emit_fence = &cik_sdma_fence_ring_emit, | |
2339 | .emit_semaphore = &cik_sdma_semaphore_ring_emit, | |
2340 | .cs_parse = NULL, | |
2341 | .ring_test = &cik_sdma_ring_test, | |
2342 | .ib_test = &cik_sdma_ib_test, | |
2343 | .is_lockup = &cik_sdma_is_lockup, | |
2344 | .vm_flush = &cik_dma_vm_flush, | |
2345 | .get_rptr = &radeon_ring_generic_get_rptr, | |
2346 | .get_wptr = &radeon_ring_generic_get_wptr, | |
2347 | .set_wptr = &radeon_ring_generic_set_wptr, | |
2348 | }, | |
2349 | [R600_RING_TYPE_UVD_INDEX] = { | |
2350 | .ib_execute = &r600_uvd_ib_execute, | |
2351 | .emit_fence = &r600_uvd_fence_emit, | |
2352 | .emit_semaphore = &cayman_uvd_semaphore_emit, | |
2353 | .cs_parse = &radeon_uvd_cs_parse, | |
2354 | .ring_test = &r600_uvd_ring_test, | |
2355 | .ib_test = &r600_uvd_ib_test, | |
2356 | .is_lockup = &radeon_ring_test_lockup, | |
2357 | .get_rptr = &radeon_ring_generic_get_rptr, | |
2358 | .get_wptr = &radeon_ring_generic_get_wptr, | |
2359 | .set_wptr = &radeon_ring_generic_set_wptr, | |
2360 | } | |
2361 | }, | |
2362 | .irq = { | |
2363 | .set = &cik_irq_set, | |
2364 | .process = &cik_irq_process, | |
2365 | }, | |
2366 | .display = { | |
2367 | .bandwidth_update = &dce8_bandwidth_update, | |
2368 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
2369 | .wait_for_vblank = &dce4_wait_for_vblank, | |
2370 | }, | |
2371 | .copy = { | |
2372 | .blit = NULL, | |
2373 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
2374 | .dma = &cik_copy_dma, | |
2375 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2376 | .copy = &cik_copy_dma, | |
2377 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2378 | }, | |
2379 | .surface = { | |
2380 | .set_reg = r600_set_surface_reg, | |
2381 | .clear_reg = r600_clear_surface_reg, | |
2382 | }, | |
2383 | .hpd = { | |
2384 | .init = &evergreen_hpd_init, | |
2385 | .fini = &evergreen_hpd_fini, | |
2386 | .sense = &evergreen_hpd_sense, | |
2387 | .set_polarity = &evergreen_hpd_set_polarity, | |
2388 | }, | |
2389 | .pm = { | |
2390 | .misc = &evergreen_pm_misc, | |
2391 | .prepare = &evergreen_pm_prepare, | |
2392 | .finish = &evergreen_pm_finish, | |
2393 | .init_profile = &sumo_pm_init_profile, | |
2394 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
2395 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
2396 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
2397 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
2398 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
2399 | .get_pcie_lanes = NULL, | |
2400 | .set_pcie_lanes = NULL, | |
2401 | .set_clock_gating = NULL, | |
2402 | .set_uvd_clocks = &cik_set_uvd_clocks, | |
2403 | }, | |
2404 | .pflip = { | |
2405 | .pre_page_flip = &evergreen_pre_page_flip, | |
2406 | .page_flip = &evergreen_page_flip, | |
2407 | .post_page_flip = &evergreen_post_page_flip, | |
2408 | }, | |
2409 | }; | |
2410 | ||
2411 | static struct radeon_asic kv_asic = { | |
2412 | .init = &cik_init, | |
2413 | .fini = &cik_fini, | |
2414 | .suspend = &cik_suspend, | |
2415 | .resume = &cik_resume, | |
2416 | .asic_reset = &cik_asic_reset, | |
2417 | .vga_set_state = &r600_vga_set_state, | |
2418 | .ioctl_wait_idle = NULL, | |
2419 | .gui_idle = &r600_gui_idle, | |
2420 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
2421 | .get_xclk = &cik_get_xclk, | |
2422 | .get_gpu_clock_counter = &cik_get_gpu_clock_counter, | |
2423 | .gart = { | |
2424 | .tlb_flush = &cik_pcie_gart_tlb_flush, | |
2425 | .set_page = &rs600_gart_set_page, | |
2426 | }, | |
2427 | .vm = { | |
2428 | .init = &cik_vm_init, | |
2429 | .fini = &cik_vm_fini, | |
2430 | .pt_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2431 | .set_page = &cik_vm_set_page, | |
2432 | }, | |
2433 | .ring = { | |
2434 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
2435 | .ib_execute = &cik_ring_ib_execute, | |
2436 | .ib_parse = &cik_ib_parse, | |
2437 | .emit_fence = &cik_fence_gfx_ring_emit, | |
2438 | .emit_semaphore = &cik_semaphore_ring_emit, | |
2439 | .cs_parse = NULL, | |
2440 | .ring_test = &cik_ring_test, | |
2441 | .ib_test = &cik_ib_test, | |
2442 | .is_lockup = &cik_gfx_is_lockup, | |
2443 | .vm_flush = &cik_vm_flush, | |
2444 | .get_rptr = &radeon_ring_generic_get_rptr, | |
2445 | .get_wptr = &radeon_ring_generic_get_wptr, | |
2446 | .set_wptr = &radeon_ring_generic_set_wptr, | |
2447 | }, | |
2448 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | |
2449 | .ib_execute = &cik_ring_ib_execute, | |
2450 | .ib_parse = &cik_ib_parse, | |
2451 | .emit_fence = &cik_fence_compute_ring_emit, | |
2452 | .emit_semaphore = &cik_semaphore_ring_emit, | |
2453 | .cs_parse = NULL, | |
2454 | .ring_test = &cik_ring_test, | |
2455 | .ib_test = &cik_ib_test, | |
2456 | .is_lockup = &cik_gfx_is_lockup, | |
2457 | .vm_flush = &cik_vm_flush, | |
2458 | .get_rptr = &cik_compute_ring_get_rptr, | |
2459 | .get_wptr = &cik_compute_ring_get_wptr, | |
2460 | .set_wptr = &cik_compute_ring_set_wptr, | |
2461 | }, | |
2462 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | |
2463 | .ib_execute = &cik_ring_ib_execute, | |
2464 | .ib_parse = &cik_ib_parse, | |
2465 | .emit_fence = &cik_fence_compute_ring_emit, | |
2466 | .emit_semaphore = &cik_semaphore_ring_emit, | |
2467 | .cs_parse = NULL, | |
2468 | .ring_test = &cik_ring_test, | |
2469 | .ib_test = &cik_ib_test, | |
2470 | .is_lockup = &cik_gfx_is_lockup, | |
2471 | .vm_flush = &cik_vm_flush, | |
2472 | .get_rptr = &cik_compute_ring_get_rptr, | |
2473 | .get_wptr = &cik_compute_ring_get_wptr, | |
2474 | .set_wptr = &cik_compute_ring_set_wptr, | |
2475 | }, | |
2476 | [R600_RING_TYPE_DMA_INDEX] = { | |
2477 | .ib_execute = &cik_sdma_ring_ib_execute, | |
2478 | .ib_parse = &cik_ib_parse, | |
2479 | .emit_fence = &cik_sdma_fence_ring_emit, | |
2480 | .emit_semaphore = &cik_sdma_semaphore_ring_emit, | |
2481 | .cs_parse = NULL, | |
2482 | .ring_test = &cik_sdma_ring_test, | |
2483 | .ib_test = &cik_sdma_ib_test, | |
2484 | .is_lockup = &cik_sdma_is_lockup, | |
2485 | .vm_flush = &cik_dma_vm_flush, | |
2486 | .get_rptr = &radeon_ring_generic_get_rptr, | |
2487 | .get_wptr = &radeon_ring_generic_get_wptr, | |
2488 | .set_wptr = &radeon_ring_generic_set_wptr, | |
2489 | }, | |
2490 | [CAYMAN_RING_TYPE_DMA1_INDEX] = { | |
2491 | .ib_execute = &cik_sdma_ring_ib_execute, | |
2492 | .ib_parse = &cik_ib_parse, | |
2493 | .emit_fence = &cik_sdma_fence_ring_emit, | |
2494 | .emit_semaphore = &cik_sdma_semaphore_ring_emit, | |
2495 | .cs_parse = NULL, | |
2496 | .ring_test = &cik_sdma_ring_test, | |
2497 | .ib_test = &cik_sdma_ib_test, | |
2498 | .is_lockup = &cik_sdma_is_lockup, | |
2499 | .vm_flush = &cik_dma_vm_flush, | |
2500 | .get_rptr = &radeon_ring_generic_get_rptr, | |
2501 | .get_wptr = &radeon_ring_generic_get_wptr, | |
2502 | .set_wptr = &radeon_ring_generic_set_wptr, | |
2503 | }, | |
2504 | [R600_RING_TYPE_UVD_INDEX] = { | |
2505 | .ib_execute = &r600_uvd_ib_execute, | |
2506 | .emit_fence = &r600_uvd_fence_emit, | |
2507 | .emit_semaphore = &cayman_uvd_semaphore_emit, | |
2508 | .cs_parse = &radeon_uvd_cs_parse, | |
2509 | .ring_test = &r600_uvd_ring_test, | |
2510 | .ib_test = &r600_uvd_ib_test, | |
2511 | .is_lockup = &radeon_ring_test_lockup, | |
2512 | .get_rptr = &radeon_ring_generic_get_rptr, | |
2513 | .get_wptr = &radeon_ring_generic_get_wptr, | |
2514 | .set_wptr = &radeon_ring_generic_set_wptr, | |
2515 | } | |
2516 | }, | |
2517 | .irq = { | |
2518 | .set = &cik_irq_set, | |
2519 | .process = &cik_irq_process, | |
2520 | }, | |
2521 | .display = { | |
2522 | .bandwidth_update = &dce8_bandwidth_update, | |
2523 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
2524 | .wait_for_vblank = &dce4_wait_for_vblank, | |
2525 | }, | |
2526 | .copy = { | |
2527 | .blit = NULL, | |
2528 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
2529 | .dma = &cik_copy_dma, | |
2530 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2531 | .copy = &cik_copy_dma, | |
2532 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2533 | }, | |
2534 | .surface = { | |
2535 | .set_reg = r600_set_surface_reg, | |
2536 | .clear_reg = r600_clear_surface_reg, | |
2537 | }, | |
2538 | .hpd = { | |
2539 | .init = &evergreen_hpd_init, | |
2540 | .fini = &evergreen_hpd_fini, | |
2541 | .sense = &evergreen_hpd_sense, | |
2542 | .set_polarity = &evergreen_hpd_set_polarity, | |
2543 | }, | |
2544 | .pm = { | |
2545 | .misc = &evergreen_pm_misc, | |
2546 | .prepare = &evergreen_pm_prepare, | |
2547 | .finish = &evergreen_pm_finish, | |
2548 | .init_profile = &sumo_pm_init_profile, | |
2549 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
2550 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
2551 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
2552 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
2553 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
2554 | .get_pcie_lanes = NULL, | |
2555 | .set_pcie_lanes = NULL, | |
2556 | .set_clock_gating = NULL, | |
2557 | .set_uvd_clocks = &cik_set_uvd_clocks, | |
2558 | }, | |
2559 | .pflip = { | |
2560 | .pre_page_flip = &evergreen_pre_page_flip, | |
2561 | .page_flip = &evergreen_page_flip, | |
2562 | .post_page_flip = &evergreen_post_page_flip, | |
2563 | }, | |
2564 | }; | |
2565 | ||
abf1dc67 AD |
2566 | /** |
2567 | * radeon_asic_init - register asic specific callbacks | |
2568 | * | |
2569 | * @rdev: radeon device pointer | |
2570 | * | |
2571 | * Registers the appropriate asic specific callbacks for each | |
2572 | * chip family. Also sets other asics specific info like the number | |
2573 | * of crtcs and the register aperture accessors (all asics). | |
2574 | * Returns 0 for success. | |
2575 | */ | |
0a10c851 DV |
2576 | int radeon_asic_init(struct radeon_device *rdev) |
2577 | { | |
2578 | radeon_register_accessor_init(rdev); | |
ba7e05e9 AD |
2579 | |
2580 | /* set the number of crtcs */ | |
2581 | if (rdev->flags & RADEON_SINGLE_CRTC) | |
2582 | rdev->num_crtc = 1; | |
2583 | else | |
2584 | rdev->num_crtc = 2; | |
2585 | ||
948bee3f AD |
2586 | rdev->has_uvd = false; |
2587 | ||
0a10c851 DV |
2588 | switch (rdev->family) { |
2589 | case CHIP_R100: | |
2590 | case CHIP_RV100: | |
2591 | case CHIP_RS100: | |
2592 | case CHIP_RV200: | |
2593 | case CHIP_RS200: | |
2594 | rdev->asic = &r100_asic; | |
2595 | break; | |
2596 | case CHIP_R200: | |
2597 | case CHIP_RV250: | |
2598 | case CHIP_RS300: | |
2599 | case CHIP_RV280: | |
2600 | rdev->asic = &r200_asic; | |
2601 | break; | |
2602 | case CHIP_R300: | |
2603 | case CHIP_R350: | |
2604 | case CHIP_RV350: | |
2605 | case CHIP_RV380: | |
2606 | if (rdev->flags & RADEON_IS_PCIE) | |
2607 | rdev->asic = &r300_asic_pcie; | |
2608 | else | |
2609 | rdev->asic = &r300_asic; | |
2610 | break; | |
2611 | case CHIP_R420: | |
2612 | case CHIP_R423: | |
2613 | case CHIP_RV410: | |
2614 | rdev->asic = &r420_asic; | |
07bb084c AD |
2615 | /* handle macs */ |
2616 | if (rdev->bios == NULL) { | |
798bcf73 AD |
2617 | rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; |
2618 | rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; | |
2619 | rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; | |
2620 | rdev->asic->pm.set_memory_clock = NULL; | |
37e9b6a6 | 2621 | rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; |
07bb084c | 2622 | } |
0a10c851 DV |
2623 | break; |
2624 | case CHIP_RS400: | |
2625 | case CHIP_RS480: | |
2626 | rdev->asic = &rs400_asic; | |
2627 | break; | |
2628 | case CHIP_RS600: | |
2629 | rdev->asic = &rs600_asic; | |
2630 | break; | |
2631 | case CHIP_RS690: | |
2632 | case CHIP_RS740: | |
2633 | rdev->asic = &rs690_asic; | |
2634 | break; | |
2635 | case CHIP_RV515: | |
2636 | rdev->asic = &rv515_asic; | |
2637 | break; | |
2638 | case CHIP_R520: | |
2639 | case CHIP_RV530: | |
2640 | case CHIP_RV560: | |
2641 | case CHIP_RV570: | |
2642 | case CHIP_R580: | |
2643 | rdev->asic = &r520_asic; | |
2644 | break; | |
2645 | case CHIP_R600: | |
ca361b65 AD |
2646 | rdev->asic = &r600_asic; |
2647 | break; | |
0a10c851 DV |
2648 | case CHIP_RV610: |
2649 | case CHIP_RV630: | |
2650 | case CHIP_RV620: | |
2651 | case CHIP_RV635: | |
2652 | case CHIP_RV670: | |
ca361b65 AD |
2653 | rdev->asic = &rv6xx_asic; |
2654 | rdev->has_uvd = true; | |
f47299c5 | 2655 | break; |
0a10c851 DV |
2656 | case CHIP_RS780: |
2657 | case CHIP_RS880: | |
f47299c5 | 2658 | rdev->asic = &rs780_asic; |
948bee3f | 2659 | rdev->has_uvd = true; |
0a10c851 DV |
2660 | break; |
2661 | case CHIP_RV770: | |
2662 | case CHIP_RV730: | |
2663 | case CHIP_RV710: | |
2664 | case CHIP_RV740: | |
2665 | rdev->asic = &rv770_asic; | |
948bee3f | 2666 | rdev->has_uvd = true; |
0a10c851 DV |
2667 | break; |
2668 | case CHIP_CEDAR: | |
2669 | case CHIP_REDWOOD: | |
2670 | case CHIP_JUNIPER: | |
2671 | case CHIP_CYPRESS: | |
2672 | case CHIP_HEMLOCK: | |
ba7e05e9 AD |
2673 | /* set num crtcs */ |
2674 | if (rdev->family == CHIP_CEDAR) | |
2675 | rdev->num_crtc = 4; | |
2676 | else | |
2677 | rdev->num_crtc = 6; | |
0a10c851 | 2678 | rdev->asic = &evergreen_asic; |
948bee3f | 2679 | rdev->has_uvd = true; |
0a10c851 | 2680 | break; |
958261d1 | 2681 | case CHIP_PALM: |
89da5a37 AD |
2682 | case CHIP_SUMO: |
2683 | case CHIP_SUMO2: | |
958261d1 | 2684 | rdev->asic = &sumo_asic; |
948bee3f | 2685 | rdev->has_uvd = true; |
958261d1 | 2686 | break; |
a43b7665 AD |
2687 | case CHIP_BARTS: |
2688 | case CHIP_TURKS: | |
2689 | case CHIP_CAICOS: | |
ba7e05e9 AD |
2690 | /* set num crtcs */ |
2691 | if (rdev->family == CHIP_CAICOS) | |
2692 | rdev->num_crtc = 4; | |
2693 | else | |
2694 | rdev->num_crtc = 6; | |
a43b7665 | 2695 | rdev->asic = &btc_asic; |
948bee3f | 2696 | rdev->has_uvd = true; |
a43b7665 | 2697 | break; |
e3487629 AD |
2698 | case CHIP_CAYMAN: |
2699 | rdev->asic = &cayman_asic; | |
ba7e05e9 AD |
2700 | /* set num crtcs */ |
2701 | rdev->num_crtc = 6; | |
948bee3f | 2702 | rdev->has_uvd = true; |
e3487629 | 2703 | break; |
be63fe8c AD |
2704 | case CHIP_ARUBA: |
2705 | rdev->asic = &trinity_asic; | |
2706 | /* set num crtcs */ | |
2707 | rdev->num_crtc = 4; | |
948bee3f | 2708 | rdev->has_uvd = true; |
be63fe8c | 2709 | break; |
02779c08 AD |
2710 | case CHIP_TAHITI: |
2711 | case CHIP_PITCAIRN: | |
2712 | case CHIP_VERDE: | |
e737a14c | 2713 | case CHIP_OLAND: |
86a45cac | 2714 | case CHIP_HAINAN: |
02779c08 AD |
2715 | rdev->asic = &si_asic; |
2716 | /* set num crtcs */ | |
86a45cac AD |
2717 | if (rdev->family == CHIP_HAINAN) |
2718 | rdev->num_crtc = 0; | |
2719 | else if (rdev->family == CHIP_OLAND) | |
e737a14c AD |
2720 | rdev->num_crtc = 2; |
2721 | else | |
2722 | rdev->num_crtc = 6; | |
948bee3f AD |
2723 | if (rdev->family == CHIP_HAINAN) |
2724 | rdev->has_uvd = false; | |
2725 | else | |
2726 | rdev->has_uvd = true; | |
02779c08 | 2727 | break; |
0672e27b AD |
2728 | case CHIP_BONAIRE: |
2729 | rdev->asic = &ci_asic; | |
2730 | rdev->num_crtc = 6; | |
2731 | break; | |
2732 | case CHIP_KAVERI: | |
2733 | case CHIP_KABINI: | |
2734 | rdev->asic = &kv_asic; | |
2735 | /* set num crtcs */ | |
2736 | if (rdev->family == CHIP_KAVERI) | |
2737 | rdev->num_crtc = 4; | |
2738 | else | |
2739 | rdev->num_crtc = 2; | |
2740 | break; | |
0a10c851 DV |
2741 | default: |
2742 | /* FIXME: not supported yet */ | |
2743 | return -EINVAL; | |
2744 | } | |
2745 | ||
2746 | if (rdev->flags & RADEON_IS_IGP) { | |
798bcf73 AD |
2747 | rdev->asic->pm.get_memory_clock = NULL; |
2748 | rdev->asic->pm.set_memory_clock = NULL; | |
0a10c851 DV |
2749 | } |
2750 | ||
2751 | return 0; | |
2752 | } | |
2753 |