]>
Commit | Line | Data |
---|---|---|
0a10c851 DV |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | ||
29 | #include <linux/console.h> | |
30 | #include <drm/drmP.h> | |
31 | #include <drm/drm_crtc_helper.h> | |
32 | #include <drm/radeon_drm.h> | |
33 | #include <linux/vgaarb.h> | |
34 | #include <linux/vga_switcheroo.h> | |
35 | #include "radeon_reg.h" | |
36 | #include "radeon.h" | |
37 | #include "radeon_asic.h" | |
38 | #include "atom.h" | |
39 | ||
40 | /* | |
41 | * Registers accessors functions. | |
42 | */ | |
43 | static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) | |
44 | { | |
45 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
46 | BUG_ON(1); | |
47 | return 0; | |
48 | } | |
49 | ||
50 | static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
51 | { | |
52 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
53 | reg, v); | |
54 | BUG_ON(1); | |
55 | } | |
56 | ||
57 | static void radeon_register_accessor_init(struct radeon_device *rdev) | |
58 | { | |
59 | rdev->mc_rreg = &radeon_invalid_rreg; | |
60 | rdev->mc_wreg = &radeon_invalid_wreg; | |
61 | rdev->pll_rreg = &radeon_invalid_rreg; | |
62 | rdev->pll_wreg = &radeon_invalid_wreg; | |
63 | rdev->pciep_rreg = &radeon_invalid_rreg; | |
64 | rdev->pciep_wreg = &radeon_invalid_wreg; | |
65 | ||
66 | /* Don't change order as we are overridding accessor. */ | |
67 | if (rdev->family < CHIP_RV515) { | |
68 | rdev->pcie_reg_mask = 0xff; | |
69 | } else { | |
70 | rdev->pcie_reg_mask = 0x7ff; | |
71 | } | |
72 | /* FIXME: not sure here */ | |
73 | if (rdev->family <= CHIP_R580) { | |
74 | rdev->pll_rreg = &r100_pll_rreg; | |
75 | rdev->pll_wreg = &r100_pll_wreg; | |
76 | } | |
77 | if (rdev->family >= CHIP_R420) { | |
78 | rdev->mc_rreg = &r420_mc_rreg; | |
79 | rdev->mc_wreg = &r420_mc_wreg; | |
80 | } | |
81 | if (rdev->family >= CHIP_RV515) { | |
82 | rdev->mc_rreg = &rv515_mc_rreg; | |
83 | rdev->mc_wreg = &rv515_mc_wreg; | |
84 | } | |
85 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { | |
86 | rdev->mc_rreg = &rs400_mc_rreg; | |
87 | rdev->mc_wreg = &rs400_mc_wreg; | |
88 | } | |
89 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { | |
90 | rdev->mc_rreg = &rs690_mc_rreg; | |
91 | rdev->mc_wreg = &rs690_mc_wreg; | |
92 | } | |
93 | if (rdev->family == CHIP_RS600) { | |
94 | rdev->mc_rreg = &rs600_mc_rreg; | |
95 | rdev->mc_wreg = &rs600_mc_wreg; | |
96 | } | |
b4df8be1 | 97 | if (rdev->family >= CHIP_R600) { |
0a10c851 DV |
98 | rdev->pciep_rreg = &r600_pciep_rreg; |
99 | rdev->pciep_wreg = &r600_pciep_wreg; | |
100 | } | |
101 | } | |
102 | ||
103 | ||
104 | /* helper to disable agp */ | |
105 | void radeon_agp_disable(struct radeon_device *rdev) | |
106 | { | |
107 | rdev->flags &= ~RADEON_IS_AGP; | |
108 | if (rdev->family >= CHIP_R600) { | |
109 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
110 | rdev->flags |= RADEON_IS_PCIE; | |
111 | } else if (rdev->family >= CHIP_RV515 || | |
112 | rdev->family == CHIP_RV380 || | |
113 | rdev->family == CHIP_RV410 || | |
114 | rdev->family == CHIP_R423) { | |
115 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
116 | rdev->flags |= RADEON_IS_PCIE; | |
c5b3b850 AD |
117 | rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; |
118 | rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; | |
0a10c851 DV |
119 | } else { |
120 | DRM_INFO("Forcing AGP to PCI mode\n"); | |
121 | rdev->flags |= RADEON_IS_PCI; | |
c5b3b850 AD |
122 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
123 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; | |
0a10c851 DV |
124 | } |
125 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
126 | } | |
127 | ||
128 | /* | |
129 | * ASIC | |
130 | */ | |
48e7a5f1 DV |
131 | static struct radeon_asic r100_asic = { |
132 | .init = &r100_init, | |
133 | .fini = &r100_fini, | |
134 | .suspend = &r100_suspend, | |
135 | .resume = &r100_resume, | |
136 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 137 | .gpu_is_lockup = &r100_gpu_is_lockup, |
a2d07b74 | 138 | .asic_reset = &r100_asic_reset, |
c5b3b850 AD |
139 | .gart = { |
140 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
141 | .set_page = &r100_pci_gart_set_page, | |
142 | }, | |
4c87bc26 CK |
143 | .ring = { |
144 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
145 | .ib_execute = &r100_ring_ib_execute, | |
146 | .emit_fence = &r100_fence_ring_emit, | |
147 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 148 | .cs_parse = &r100_cs_parse, |
f712812e AD |
149 | .ring_start = &r100_ring_start, |
150 | .ring_test = &r100_ring_test, | |
151 | .ib_test = &r100_ib_test, | |
4c87bc26 CK |
152 | } |
153 | }, | |
b35ea4ab AD |
154 | .irq = { |
155 | .set = &r100_irq_set, | |
156 | .process = &r100_irq_process, | |
157 | }, | |
c79a49ca AD |
158 | .display = { |
159 | .bandwidth_update = &r100_bandwidth_update, | |
160 | .get_vblank_counter = &r100_get_vblank_counter, | |
161 | .wait_for_vblank = &r100_wait_for_vblank, | |
162 | }, | |
27cd7769 AD |
163 | .copy = { |
164 | .blit = &r100_copy_blit, | |
165 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
166 | .dma = NULL, | |
167 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
168 | .copy = &r100_copy_blit, | |
169 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
170 | }, | |
9e6f3d02 AD |
171 | .surface = { |
172 | .set_reg = r100_set_surface_reg, | |
173 | .clear_reg = r100_clear_surface_reg, | |
174 | }, | |
901ea57d AD |
175 | .hpd = { |
176 | .init = &r100_hpd_init, | |
177 | .fini = &r100_hpd_fini, | |
178 | .sense = &r100_hpd_sense, | |
179 | .set_polarity = &r100_hpd_set_polarity, | |
180 | }, | |
48e7a5f1 | 181 | .ioctl_wait_idle = NULL, |
def9ba9c | 182 | .gui_idle = &r100_gui_idle, |
a02fa397 AD |
183 | .pm = { |
184 | .misc = &r100_pm_misc, | |
185 | .prepare = &r100_pm_prepare, | |
186 | .finish = &r100_pm_finish, | |
187 | .init_profile = &r100_pm_init_profile, | |
188 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
189 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
190 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
191 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
192 | .set_memory_clock = NULL, | |
193 | .get_pcie_lanes = NULL, | |
194 | .set_pcie_lanes = NULL, | |
195 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 196 | }, |
0f9e006c AD |
197 | .pflip = { |
198 | .pre_page_flip = &r100_pre_page_flip, | |
199 | .page_flip = &r100_page_flip, | |
200 | .post_page_flip = &r100_post_page_flip, | |
201 | }, | |
89e5181f | 202 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
48e7a5f1 DV |
203 | }; |
204 | ||
205 | static struct radeon_asic r200_asic = { | |
206 | .init = &r100_init, | |
207 | .fini = &r100_fini, | |
208 | .suspend = &r100_suspend, | |
209 | .resume = &r100_resume, | |
210 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 211 | .gpu_is_lockup = &r100_gpu_is_lockup, |
a2d07b74 | 212 | .asic_reset = &r100_asic_reset, |
c5b3b850 AD |
213 | .gart = { |
214 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
215 | .set_page = &r100_pci_gart_set_page, | |
216 | }, | |
4c87bc26 CK |
217 | .ring = { |
218 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
219 | .ib_execute = &r100_ring_ib_execute, | |
220 | .emit_fence = &r100_fence_ring_emit, | |
221 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 222 | .cs_parse = &r100_cs_parse, |
f712812e AD |
223 | .ring_start = &r100_ring_start, |
224 | .ring_test = &r100_ring_test, | |
225 | .ib_test = &r100_ib_test, | |
4c87bc26 CK |
226 | } |
227 | }, | |
b35ea4ab AD |
228 | .irq = { |
229 | .set = &r100_irq_set, | |
230 | .process = &r100_irq_process, | |
231 | }, | |
c79a49ca AD |
232 | .display = { |
233 | .bandwidth_update = &r100_bandwidth_update, | |
234 | .get_vblank_counter = &r100_get_vblank_counter, | |
235 | .wait_for_vblank = &r100_wait_for_vblank, | |
236 | }, | |
27cd7769 AD |
237 | .copy = { |
238 | .blit = &r100_copy_blit, | |
239 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
240 | .dma = &r200_copy_dma, | |
241 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
242 | .copy = &r100_copy_blit, | |
243 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
244 | }, | |
9e6f3d02 AD |
245 | .surface = { |
246 | .set_reg = r100_set_surface_reg, | |
247 | .clear_reg = r100_clear_surface_reg, | |
248 | }, | |
901ea57d AD |
249 | .hpd = { |
250 | .init = &r100_hpd_init, | |
251 | .fini = &r100_hpd_fini, | |
252 | .sense = &r100_hpd_sense, | |
253 | .set_polarity = &r100_hpd_set_polarity, | |
254 | }, | |
48e7a5f1 | 255 | .ioctl_wait_idle = NULL, |
def9ba9c | 256 | .gui_idle = &r100_gui_idle, |
a02fa397 AD |
257 | .pm = { |
258 | .misc = &r100_pm_misc, | |
259 | .prepare = &r100_pm_prepare, | |
260 | .finish = &r100_pm_finish, | |
261 | .init_profile = &r100_pm_init_profile, | |
262 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
263 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
264 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
265 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
266 | .set_memory_clock = NULL, | |
267 | .get_pcie_lanes = NULL, | |
268 | .set_pcie_lanes = NULL, | |
269 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 270 | }, |
0f9e006c AD |
271 | .pflip = { |
272 | .pre_page_flip = &r100_pre_page_flip, | |
273 | .page_flip = &r100_page_flip, | |
274 | .post_page_flip = &r100_post_page_flip, | |
275 | }, | |
89e5181f | 276 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
48e7a5f1 DV |
277 | }; |
278 | ||
279 | static struct radeon_asic r300_asic = { | |
280 | .init = &r300_init, | |
281 | .fini = &r300_fini, | |
282 | .suspend = &r300_suspend, | |
283 | .resume = &r300_resume, | |
284 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 285 | .gpu_is_lockup = &r300_gpu_is_lockup, |
a2d07b74 | 286 | .asic_reset = &r300_asic_reset, |
c5b3b850 AD |
287 | .gart = { |
288 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
289 | .set_page = &r100_pci_gart_set_page, | |
290 | }, | |
4c87bc26 CK |
291 | .ring = { |
292 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
293 | .ib_execute = &r100_ring_ib_execute, | |
294 | .emit_fence = &r300_fence_ring_emit, | |
295 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 296 | .cs_parse = &r300_cs_parse, |
f712812e AD |
297 | .ring_start = &r300_ring_start, |
298 | .ring_test = &r100_ring_test, | |
299 | .ib_test = &r100_ib_test, | |
4c87bc26 CK |
300 | } |
301 | }, | |
b35ea4ab AD |
302 | .irq = { |
303 | .set = &r100_irq_set, | |
304 | .process = &r100_irq_process, | |
305 | }, | |
c79a49ca AD |
306 | .display = { |
307 | .bandwidth_update = &r100_bandwidth_update, | |
308 | .get_vblank_counter = &r100_get_vblank_counter, | |
309 | .wait_for_vblank = &r100_wait_for_vblank, | |
310 | }, | |
27cd7769 AD |
311 | .copy = { |
312 | .blit = &r100_copy_blit, | |
313 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
314 | .dma = &r200_copy_dma, | |
315 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
316 | .copy = &r100_copy_blit, | |
317 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
318 | }, | |
9e6f3d02 AD |
319 | .surface = { |
320 | .set_reg = r100_set_surface_reg, | |
321 | .clear_reg = r100_clear_surface_reg, | |
322 | }, | |
901ea57d AD |
323 | .hpd = { |
324 | .init = &r100_hpd_init, | |
325 | .fini = &r100_hpd_fini, | |
326 | .sense = &r100_hpd_sense, | |
327 | .set_polarity = &r100_hpd_set_polarity, | |
328 | }, | |
48e7a5f1 | 329 | .ioctl_wait_idle = NULL, |
def9ba9c | 330 | .gui_idle = &r100_gui_idle, |
a02fa397 AD |
331 | .pm = { |
332 | .misc = &r100_pm_misc, | |
333 | .prepare = &r100_pm_prepare, | |
334 | .finish = &r100_pm_finish, | |
335 | .init_profile = &r100_pm_init_profile, | |
336 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
337 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
338 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
339 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
340 | .set_memory_clock = NULL, | |
341 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
342 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
343 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 344 | }, |
0f9e006c AD |
345 | .pflip = { |
346 | .pre_page_flip = &r100_pre_page_flip, | |
347 | .page_flip = &r100_page_flip, | |
348 | .post_page_flip = &r100_post_page_flip, | |
349 | }, | |
89e5181f | 350 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
48e7a5f1 DV |
351 | }; |
352 | ||
353 | static struct radeon_asic r300_asic_pcie = { | |
354 | .init = &r300_init, | |
355 | .fini = &r300_fini, | |
356 | .suspend = &r300_suspend, | |
357 | .resume = &r300_resume, | |
358 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 359 | .gpu_is_lockup = &r300_gpu_is_lockup, |
a2d07b74 | 360 | .asic_reset = &r300_asic_reset, |
c5b3b850 AD |
361 | .gart = { |
362 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
363 | .set_page = &rv370_pcie_gart_set_page, | |
364 | }, | |
4c87bc26 CK |
365 | .ring = { |
366 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
367 | .ib_execute = &r100_ring_ib_execute, | |
368 | .emit_fence = &r300_fence_ring_emit, | |
369 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 370 | .cs_parse = &r300_cs_parse, |
f712812e AD |
371 | .ring_start = &r300_ring_start, |
372 | .ring_test = &r100_ring_test, | |
373 | .ib_test = &r100_ib_test, | |
4c87bc26 CK |
374 | } |
375 | }, | |
b35ea4ab AD |
376 | .irq = { |
377 | .set = &r100_irq_set, | |
378 | .process = &r100_irq_process, | |
379 | }, | |
c79a49ca AD |
380 | .display = { |
381 | .bandwidth_update = &r100_bandwidth_update, | |
382 | .get_vblank_counter = &r100_get_vblank_counter, | |
383 | .wait_for_vblank = &r100_wait_for_vblank, | |
384 | }, | |
27cd7769 AD |
385 | .copy = { |
386 | .blit = &r100_copy_blit, | |
387 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
388 | .dma = &r200_copy_dma, | |
389 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
390 | .copy = &r100_copy_blit, | |
391 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
392 | }, | |
9e6f3d02 AD |
393 | .surface = { |
394 | .set_reg = r100_set_surface_reg, | |
395 | .clear_reg = r100_clear_surface_reg, | |
396 | }, | |
901ea57d AD |
397 | .hpd = { |
398 | .init = &r100_hpd_init, | |
399 | .fini = &r100_hpd_fini, | |
400 | .sense = &r100_hpd_sense, | |
401 | .set_polarity = &r100_hpd_set_polarity, | |
402 | }, | |
48e7a5f1 | 403 | .ioctl_wait_idle = NULL, |
def9ba9c | 404 | .gui_idle = &r100_gui_idle, |
a02fa397 AD |
405 | .pm = { |
406 | .misc = &r100_pm_misc, | |
407 | .prepare = &r100_pm_prepare, | |
408 | .finish = &r100_pm_finish, | |
409 | .init_profile = &r100_pm_init_profile, | |
410 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
411 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
412 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
413 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
414 | .set_memory_clock = NULL, | |
415 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
416 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
417 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 418 | }, |
0f9e006c AD |
419 | .pflip = { |
420 | .pre_page_flip = &r100_pre_page_flip, | |
421 | .page_flip = &r100_page_flip, | |
422 | .post_page_flip = &r100_post_page_flip, | |
423 | }, | |
89e5181f | 424 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
48e7a5f1 DV |
425 | }; |
426 | ||
427 | static struct radeon_asic r420_asic = { | |
428 | .init = &r420_init, | |
429 | .fini = &r420_fini, | |
430 | .suspend = &r420_suspend, | |
431 | .resume = &r420_resume, | |
432 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 433 | .gpu_is_lockup = &r300_gpu_is_lockup, |
a2d07b74 | 434 | .asic_reset = &r300_asic_reset, |
c5b3b850 AD |
435 | .gart = { |
436 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
437 | .set_page = &rv370_pcie_gart_set_page, | |
438 | }, | |
4c87bc26 CK |
439 | .ring = { |
440 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
441 | .ib_execute = &r100_ring_ib_execute, | |
442 | .emit_fence = &r300_fence_ring_emit, | |
443 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 444 | .cs_parse = &r300_cs_parse, |
f712812e AD |
445 | .ring_start = &r300_ring_start, |
446 | .ring_test = &r100_ring_test, | |
447 | .ib_test = &r100_ib_test, | |
4c87bc26 CK |
448 | } |
449 | }, | |
b35ea4ab AD |
450 | .irq = { |
451 | .set = &r100_irq_set, | |
452 | .process = &r100_irq_process, | |
453 | }, | |
c79a49ca AD |
454 | .display = { |
455 | .bandwidth_update = &r100_bandwidth_update, | |
456 | .get_vblank_counter = &r100_get_vblank_counter, | |
457 | .wait_for_vblank = &r100_wait_for_vblank, | |
458 | }, | |
27cd7769 AD |
459 | .copy = { |
460 | .blit = &r100_copy_blit, | |
461 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
462 | .dma = &r200_copy_dma, | |
463 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
464 | .copy = &r100_copy_blit, | |
465 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
466 | }, | |
9e6f3d02 AD |
467 | .surface = { |
468 | .set_reg = r100_set_surface_reg, | |
469 | .clear_reg = r100_clear_surface_reg, | |
470 | }, | |
901ea57d AD |
471 | .hpd = { |
472 | .init = &r100_hpd_init, | |
473 | .fini = &r100_hpd_fini, | |
474 | .sense = &r100_hpd_sense, | |
475 | .set_polarity = &r100_hpd_set_polarity, | |
476 | }, | |
48e7a5f1 | 477 | .ioctl_wait_idle = NULL, |
def9ba9c | 478 | .gui_idle = &r100_gui_idle, |
a02fa397 AD |
479 | .pm = { |
480 | .misc = &r100_pm_misc, | |
481 | .prepare = &r100_pm_prepare, | |
482 | .finish = &r100_pm_finish, | |
483 | .init_profile = &r420_pm_init_profile, | |
484 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
485 | .get_engine_clock = &radeon_atom_get_engine_clock, |
486 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
487 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
488 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
489 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
490 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
491 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 492 | }, |
0f9e006c AD |
493 | .pflip = { |
494 | .pre_page_flip = &r100_pre_page_flip, | |
495 | .page_flip = &r100_page_flip, | |
496 | .post_page_flip = &r100_post_page_flip, | |
497 | }, | |
89e5181f | 498 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
48e7a5f1 DV |
499 | }; |
500 | ||
501 | static struct radeon_asic rs400_asic = { | |
502 | .init = &rs400_init, | |
503 | .fini = &rs400_fini, | |
504 | .suspend = &rs400_suspend, | |
505 | .resume = &rs400_resume, | |
506 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 507 | .gpu_is_lockup = &r300_gpu_is_lockup, |
a2d07b74 | 508 | .asic_reset = &r300_asic_reset, |
c5b3b850 AD |
509 | .gart = { |
510 | .tlb_flush = &rs400_gart_tlb_flush, | |
511 | .set_page = &rs400_gart_set_page, | |
512 | }, | |
4c87bc26 CK |
513 | .ring = { |
514 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
515 | .ib_execute = &r100_ring_ib_execute, | |
516 | .emit_fence = &r300_fence_ring_emit, | |
517 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 518 | .cs_parse = &r300_cs_parse, |
f712812e AD |
519 | .ring_start = &r300_ring_start, |
520 | .ring_test = &r100_ring_test, | |
521 | .ib_test = &r100_ib_test, | |
4c87bc26 CK |
522 | } |
523 | }, | |
b35ea4ab AD |
524 | .irq = { |
525 | .set = &r100_irq_set, | |
526 | .process = &r100_irq_process, | |
527 | }, | |
c79a49ca AD |
528 | .display = { |
529 | .bandwidth_update = &r100_bandwidth_update, | |
530 | .get_vblank_counter = &r100_get_vblank_counter, | |
531 | .wait_for_vblank = &r100_wait_for_vblank, | |
532 | }, | |
27cd7769 AD |
533 | .copy = { |
534 | .blit = &r100_copy_blit, | |
535 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
536 | .dma = &r200_copy_dma, | |
537 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
538 | .copy = &r100_copy_blit, | |
539 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
540 | }, | |
9e6f3d02 AD |
541 | .surface = { |
542 | .set_reg = r100_set_surface_reg, | |
543 | .clear_reg = r100_clear_surface_reg, | |
544 | }, | |
901ea57d AD |
545 | .hpd = { |
546 | .init = &r100_hpd_init, | |
547 | .fini = &r100_hpd_fini, | |
548 | .sense = &r100_hpd_sense, | |
549 | .set_polarity = &r100_hpd_set_polarity, | |
550 | }, | |
48e7a5f1 | 551 | .ioctl_wait_idle = NULL, |
def9ba9c | 552 | .gui_idle = &r100_gui_idle, |
a02fa397 AD |
553 | .pm = { |
554 | .misc = &r100_pm_misc, | |
555 | .prepare = &r100_pm_prepare, | |
556 | .finish = &r100_pm_finish, | |
557 | .init_profile = &r100_pm_init_profile, | |
558 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
559 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
560 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
561 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
562 | .set_memory_clock = NULL, | |
563 | .get_pcie_lanes = NULL, | |
564 | .set_pcie_lanes = NULL, | |
565 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 566 | }, |
0f9e006c AD |
567 | .pflip = { |
568 | .pre_page_flip = &r100_pre_page_flip, | |
569 | .page_flip = &r100_page_flip, | |
570 | .post_page_flip = &r100_post_page_flip, | |
571 | }, | |
89e5181f | 572 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, |
48e7a5f1 DV |
573 | }; |
574 | ||
575 | static struct radeon_asic rs600_asic = { | |
576 | .init = &rs600_init, | |
577 | .fini = &rs600_fini, | |
578 | .suspend = &rs600_suspend, | |
579 | .resume = &rs600_resume, | |
580 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 581 | .gpu_is_lockup = &r300_gpu_is_lockup, |
90aca4d2 | 582 | .asic_reset = &rs600_asic_reset, |
c5b3b850 AD |
583 | .gart = { |
584 | .tlb_flush = &rs600_gart_tlb_flush, | |
585 | .set_page = &rs600_gart_set_page, | |
586 | }, | |
4c87bc26 CK |
587 | .ring = { |
588 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
589 | .ib_execute = &r100_ring_ib_execute, | |
590 | .emit_fence = &r300_fence_ring_emit, | |
591 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 592 | .cs_parse = &r300_cs_parse, |
f712812e AD |
593 | .ring_start = &r300_ring_start, |
594 | .ring_test = &r100_ring_test, | |
595 | .ib_test = &r100_ib_test, | |
4c87bc26 CK |
596 | } |
597 | }, | |
b35ea4ab AD |
598 | .irq = { |
599 | .set = &rs600_irq_set, | |
600 | .process = &rs600_irq_process, | |
601 | }, | |
c79a49ca AD |
602 | .display = { |
603 | .bandwidth_update = &rs600_bandwidth_update, | |
604 | .get_vblank_counter = &rs600_get_vblank_counter, | |
605 | .wait_for_vblank = &avivo_wait_for_vblank, | |
606 | }, | |
27cd7769 AD |
607 | .copy = { |
608 | .blit = &r100_copy_blit, | |
609 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
610 | .dma = &r200_copy_dma, | |
611 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
612 | .copy = &r100_copy_blit, | |
613 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
614 | }, | |
9e6f3d02 AD |
615 | .surface = { |
616 | .set_reg = r100_set_surface_reg, | |
617 | .clear_reg = r100_clear_surface_reg, | |
618 | }, | |
901ea57d AD |
619 | .hpd = { |
620 | .init = &rs600_hpd_init, | |
621 | .fini = &rs600_hpd_fini, | |
622 | .sense = &rs600_hpd_sense, | |
623 | .set_polarity = &rs600_hpd_set_polarity, | |
624 | }, | |
48e7a5f1 | 625 | .ioctl_wait_idle = NULL, |
def9ba9c | 626 | .gui_idle = &r100_gui_idle, |
a02fa397 AD |
627 | .pm = { |
628 | .misc = &rs600_pm_misc, | |
629 | .prepare = &rs600_pm_prepare, | |
630 | .finish = &rs600_pm_finish, | |
631 | .init_profile = &r420_pm_init_profile, | |
632 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
633 | .get_engine_clock = &radeon_atom_get_engine_clock, |
634 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
635 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
636 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
637 | .get_pcie_lanes = NULL, | |
638 | .set_pcie_lanes = NULL, | |
639 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 640 | }, |
0f9e006c AD |
641 | .pflip = { |
642 | .pre_page_flip = &rs600_pre_page_flip, | |
643 | .page_flip = &rs600_page_flip, | |
644 | .post_page_flip = &rs600_post_page_flip, | |
645 | }, | |
89e5181f | 646 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, |
48e7a5f1 DV |
647 | }; |
648 | ||
649 | static struct radeon_asic rs690_asic = { | |
650 | .init = &rs690_init, | |
651 | .fini = &rs690_fini, | |
652 | .suspend = &rs690_suspend, | |
653 | .resume = &rs690_resume, | |
654 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 655 | .gpu_is_lockup = &r300_gpu_is_lockup, |
90aca4d2 | 656 | .asic_reset = &rs600_asic_reset, |
c5b3b850 AD |
657 | .gart = { |
658 | .tlb_flush = &rs400_gart_tlb_flush, | |
659 | .set_page = &rs400_gart_set_page, | |
660 | }, | |
4c87bc26 CK |
661 | .ring = { |
662 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
663 | .ib_execute = &r100_ring_ib_execute, | |
664 | .emit_fence = &r300_fence_ring_emit, | |
665 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 666 | .cs_parse = &r300_cs_parse, |
f712812e AD |
667 | .ring_start = &r300_ring_start, |
668 | .ring_test = &r100_ring_test, | |
669 | .ib_test = &r100_ib_test, | |
4c87bc26 CK |
670 | } |
671 | }, | |
b35ea4ab AD |
672 | .irq = { |
673 | .set = &rs600_irq_set, | |
674 | .process = &rs600_irq_process, | |
675 | }, | |
c79a49ca AD |
676 | .display = { |
677 | .get_vblank_counter = &rs600_get_vblank_counter, | |
678 | .bandwidth_update = &rs690_bandwidth_update, | |
679 | .wait_for_vblank = &avivo_wait_for_vblank, | |
680 | }, | |
27cd7769 AD |
681 | .copy = { |
682 | .blit = &r100_copy_blit, | |
683 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
684 | .dma = &r200_copy_dma, | |
685 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
686 | .copy = &r200_copy_dma, | |
687 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
688 | }, | |
9e6f3d02 AD |
689 | .surface = { |
690 | .set_reg = r100_set_surface_reg, | |
691 | .clear_reg = r100_clear_surface_reg, | |
692 | }, | |
901ea57d AD |
693 | .hpd = { |
694 | .init = &rs600_hpd_init, | |
695 | .fini = &rs600_hpd_fini, | |
696 | .sense = &rs600_hpd_sense, | |
697 | .set_polarity = &rs600_hpd_set_polarity, | |
698 | }, | |
48e7a5f1 | 699 | .ioctl_wait_idle = NULL, |
def9ba9c | 700 | .gui_idle = &r100_gui_idle, |
a02fa397 AD |
701 | .pm = { |
702 | .misc = &rs600_pm_misc, | |
703 | .prepare = &rs600_pm_prepare, | |
704 | .finish = &rs600_pm_finish, | |
705 | .init_profile = &r420_pm_init_profile, | |
706 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
707 | .get_engine_clock = &radeon_atom_get_engine_clock, |
708 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
709 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
710 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
711 | .get_pcie_lanes = NULL, | |
712 | .set_pcie_lanes = NULL, | |
713 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 714 | }, |
0f9e006c AD |
715 | .pflip = { |
716 | .pre_page_flip = &rs600_pre_page_flip, | |
717 | .page_flip = &rs600_page_flip, | |
718 | .post_page_flip = &rs600_post_page_flip, | |
719 | }, | |
89e5181f | 720 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, |
48e7a5f1 DV |
721 | }; |
722 | ||
723 | static struct radeon_asic rv515_asic = { | |
724 | .init = &rv515_init, | |
725 | .fini = &rv515_fini, | |
726 | .suspend = &rv515_suspend, | |
727 | .resume = &rv515_resume, | |
728 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 729 | .gpu_is_lockup = &r300_gpu_is_lockup, |
90aca4d2 | 730 | .asic_reset = &rs600_asic_reset, |
c5b3b850 AD |
731 | .gart = { |
732 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
733 | .set_page = &rv370_pcie_gart_set_page, | |
734 | }, | |
4c87bc26 CK |
735 | .ring = { |
736 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
737 | .ib_execute = &r100_ring_ib_execute, | |
738 | .emit_fence = &r300_fence_ring_emit, | |
739 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 740 | .cs_parse = &r300_cs_parse, |
f712812e AD |
741 | .ring_start = &rv515_ring_start, |
742 | .ring_test = &r100_ring_test, | |
743 | .ib_test = &r100_ib_test, | |
4c87bc26 CK |
744 | } |
745 | }, | |
b35ea4ab AD |
746 | .irq = { |
747 | .set = &rs600_irq_set, | |
748 | .process = &rs600_irq_process, | |
749 | }, | |
c79a49ca AD |
750 | .display = { |
751 | .get_vblank_counter = &rs600_get_vblank_counter, | |
752 | .bandwidth_update = &rv515_bandwidth_update, | |
753 | .wait_for_vblank = &avivo_wait_for_vblank, | |
754 | }, | |
27cd7769 AD |
755 | .copy = { |
756 | .blit = &r100_copy_blit, | |
757 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
758 | .dma = &r200_copy_dma, | |
759 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
760 | .copy = &r100_copy_blit, | |
761 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
762 | }, | |
9e6f3d02 AD |
763 | .surface = { |
764 | .set_reg = r100_set_surface_reg, | |
765 | .clear_reg = r100_clear_surface_reg, | |
766 | }, | |
901ea57d AD |
767 | .hpd = { |
768 | .init = &rs600_hpd_init, | |
769 | .fini = &rs600_hpd_fini, | |
770 | .sense = &rs600_hpd_sense, | |
771 | .set_polarity = &rs600_hpd_set_polarity, | |
772 | }, | |
48e7a5f1 | 773 | .ioctl_wait_idle = NULL, |
def9ba9c | 774 | .gui_idle = &r100_gui_idle, |
a02fa397 AD |
775 | .pm = { |
776 | .misc = &rs600_pm_misc, | |
777 | .prepare = &rs600_pm_prepare, | |
778 | .finish = &rs600_pm_finish, | |
779 | .init_profile = &r420_pm_init_profile, | |
780 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
781 | .get_engine_clock = &radeon_atom_get_engine_clock, |
782 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
783 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
784 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
785 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
786 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
787 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 788 | }, |
0f9e006c AD |
789 | .pflip = { |
790 | .pre_page_flip = &rs600_pre_page_flip, | |
791 | .page_flip = &rs600_page_flip, | |
792 | .post_page_flip = &rs600_post_page_flip, | |
793 | }, | |
89e5181f | 794 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, |
48e7a5f1 DV |
795 | }; |
796 | ||
797 | static struct radeon_asic r520_asic = { | |
798 | .init = &r520_init, | |
799 | .fini = &rv515_fini, | |
800 | .suspend = &rv515_suspend, | |
801 | .resume = &r520_resume, | |
802 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 803 | .gpu_is_lockup = &r300_gpu_is_lockup, |
90aca4d2 | 804 | .asic_reset = &rs600_asic_reset, |
c5b3b850 AD |
805 | .gart = { |
806 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
807 | .set_page = &rv370_pcie_gart_set_page, | |
808 | }, | |
4c87bc26 CK |
809 | .ring = { |
810 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
811 | .ib_execute = &r100_ring_ib_execute, | |
812 | .emit_fence = &r300_fence_ring_emit, | |
813 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 814 | .cs_parse = &r300_cs_parse, |
f712812e AD |
815 | .ring_start = &rv515_ring_start, |
816 | .ring_test = &r100_ring_test, | |
817 | .ib_test = &r100_ib_test, | |
4c87bc26 CK |
818 | } |
819 | }, | |
b35ea4ab AD |
820 | .irq = { |
821 | .set = &rs600_irq_set, | |
822 | .process = &rs600_irq_process, | |
823 | }, | |
c79a49ca AD |
824 | .display = { |
825 | .bandwidth_update = &rv515_bandwidth_update, | |
826 | .get_vblank_counter = &rs600_get_vblank_counter, | |
827 | .wait_for_vblank = &avivo_wait_for_vblank, | |
828 | }, | |
27cd7769 AD |
829 | .copy = { |
830 | .blit = &r100_copy_blit, | |
831 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
832 | .dma = &r200_copy_dma, | |
833 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
834 | .copy = &r100_copy_blit, | |
835 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
836 | }, | |
9e6f3d02 AD |
837 | .surface = { |
838 | .set_reg = r100_set_surface_reg, | |
839 | .clear_reg = r100_clear_surface_reg, | |
840 | }, | |
901ea57d AD |
841 | .hpd = { |
842 | .init = &rs600_hpd_init, | |
843 | .fini = &rs600_hpd_fini, | |
844 | .sense = &rs600_hpd_sense, | |
845 | .set_polarity = &rs600_hpd_set_polarity, | |
846 | }, | |
48e7a5f1 | 847 | .ioctl_wait_idle = NULL, |
def9ba9c | 848 | .gui_idle = &r100_gui_idle, |
a02fa397 AD |
849 | .pm = { |
850 | .misc = &rs600_pm_misc, | |
851 | .prepare = &rs600_pm_prepare, | |
852 | .finish = &rs600_pm_finish, | |
853 | .init_profile = &r420_pm_init_profile, | |
854 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
855 | .get_engine_clock = &radeon_atom_get_engine_clock, |
856 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
857 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
858 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
859 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
860 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
861 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 862 | }, |
0f9e006c AD |
863 | .pflip = { |
864 | .pre_page_flip = &rs600_pre_page_flip, | |
865 | .page_flip = &rs600_page_flip, | |
866 | .post_page_flip = &rs600_post_page_flip, | |
867 | }, | |
89e5181f | 868 | .mc_wait_for_idle = &r520_mc_wait_for_idle, |
48e7a5f1 DV |
869 | }; |
870 | ||
871 | static struct radeon_asic r600_asic = { | |
872 | .init = &r600_init, | |
873 | .fini = &r600_fini, | |
874 | .suspend = &r600_suspend, | |
875 | .resume = &r600_resume, | |
48e7a5f1 | 876 | .vga_set_state = &r600_vga_set_state, |
225758d8 | 877 | .gpu_is_lockup = &r600_gpu_is_lockup, |
a2d07b74 | 878 | .asic_reset = &r600_asic_reset, |
c5b3b850 AD |
879 | .gart = { |
880 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
881 | .set_page = &rs600_gart_set_page, | |
882 | }, | |
4c87bc26 CK |
883 | .ring = { |
884 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
885 | .ib_execute = &r600_ring_ib_execute, | |
886 | .emit_fence = &r600_fence_ring_emit, | |
887 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 888 | .cs_parse = &r600_cs_parse, |
f712812e AD |
889 | .ring_test = &r600_ring_test, |
890 | .ib_test = &r600_ib_test, | |
4c87bc26 CK |
891 | } |
892 | }, | |
b35ea4ab AD |
893 | .irq = { |
894 | .set = &r600_irq_set, | |
895 | .process = &r600_irq_process, | |
896 | }, | |
c79a49ca AD |
897 | .display = { |
898 | .bandwidth_update = &rv515_bandwidth_update, | |
899 | .get_vblank_counter = &rs600_get_vblank_counter, | |
900 | .wait_for_vblank = &avivo_wait_for_vblank, | |
901 | }, | |
27cd7769 AD |
902 | .copy = { |
903 | .blit = &r600_copy_blit, | |
904 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
905 | .dma = NULL, | |
906 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
907 | .copy = &r600_copy_blit, | |
908 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
909 | }, | |
9e6f3d02 AD |
910 | .surface = { |
911 | .set_reg = r600_set_surface_reg, | |
912 | .clear_reg = r600_clear_surface_reg, | |
913 | }, | |
901ea57d AD |
914 | .hpd = { |
915 | .init = &r600_hpd_init, | |
916 | .fini = &r600_hpd_fini, | |
917 | .sense = &r600_hpd_sense, | |
918 | .set_polarity = &r600_hpd_set_polarity, | |
919 | }, | |
48e7a5f1 | 920 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
def9ba9c | 921 | .gui_idle = &r600_gui_idle, |
a02fa397 AD |
922 | .pm = { |
923 | .misc = &r600_pm_misc, | |
924 | .prepare = &rs600_pm_prepare, | |
925 | .finish = &rs600_pm_finish, | |
926 | .init_profile = &r600_pm_init_profile, | |
927 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
928 | .get_engine_clock = &radeon_atom_get_engine_clock, |
929 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
930 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
931 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
932 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
933 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
934 | .set_clock_gating = NULL, | |
a02fa397 | 935 | }, |
0f9e006c AD |
936 | .pflip = { |
937 | .pre_page_flip = &rs600_pre_page_flip, | |
938 | .page_flip = &rs600_page_flip, | |
939 | .post_page_flip = &rs600_post_page_flip, | |
940 | }, | |
89e5181f | 941 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
48e7a5f1 DV |
942 | }; |
943 | ||
f47299c5 AD |
944 | static struct radeon_asic rs780_asic = { |
945 | .init = &r600_init, | |
946 | .fini = &r600_fini, | |
947 | .suspend = &r600_suspend, | |
948 | .resume = &r600_resume, | |
90aca4d2 | 949 | .gpu_is_lockup = &r600_gpu_is_lockup, |
f47299c5 | 950 | .vga_set_state = &r600_vga_set_state, |
a2d07b74 | 951 | .asic_reset = &r600_asic_reset, |
c5b3b850 AD |
952 | .gart = { |
953 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
954 | .set_page = &rs600_gart_set_page, | |
955 | }, | |
4c87bc26 CK |
956 | .ring = { |
957 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
958 | .ib_execute = &r600_ring_ib_execute, | |
959 | .emit_fence = &r600_fence_ring_emit, | |
960 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 961 | .cs_parse = &r600_cs_parse, |
f712812e AD |
962 | .ring_test = &r600_ring_test, |
963 | .ib_test = &r600_ib_test, | |
4c87bc26 CK |
964 | } |
965 | }, | |
b35ea4ab AD |
966 | .irq = { |
967 | .set = &r600_irq_set, | |
968 | .process = &r600_irq_process, | |
969 | }, | |
c79a49ca AD |
970 | .display = { |
971 | .bandwidth_update = &rs690_bandwidth_update, | |
972 | .get_vblank_counter = &rs600_get_vblank_counter, | |
973 | .wait_for_vblank = &avivo_wait_for_vblank, | |
974 | }, | |
27cd7769 AD |
975 | .copy = { |
976 | .blit = &r600_copy_blit, | |
977 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
978 | .dma = NULL, | |
979 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
980 | .copy = &r600_copy_blit, | |
981 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
982 | }, | |
9e6f3d02 AD |
983 | .surface = { |
984 | .set_reg = r600_set_surface_reg, | |
985 | .clear_reg = r600_clear_surface_reg, | |
986 | }, | |
901ea57d AD |
987 | .hpd = { |
988 | .init = &r600_hpd_init, | |
989 | .fini = &r600_hpd_fini, | |
990 | .sense = &r600_hpd_sense, | |
991 | .set_polarity = &r600_hpd_set_polarity, | |
992 | }, | |
f47299c5 | 993 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
def9ba9c | 994 | .gui_idle = &r600_gui_idle, |
a02fa397 AD |
995 | .pm = { |
996 | .misc = &r600_pm_misc, | |
997 | .prepare = &rs600_pm_prepare, | |
998 | .finish = &rs600_pm_finish, | |
999 | .init_profile = &rs780_pm_init_profile, | |
1000 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1001 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1002 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1003 | .get_memory_clock = NULL, | |
1004 | .set_memory_clock = NULL, | |
1005 | .get_pcie_lanes = NULL, | |
1006 | .set_pcie_lanes = NULL, | |
1007 | .set_clock_gating = NULL, | |
a02fa397 | 1008 | }, |
0f9e006c AD |
1009 | .pflip = { |
1010 | .pre_page_flip = &rs600_pre_page_flip, | |
1011 | .page_flip = &rs600_page_flip, | |
1012 | .post_page_flip = &rs600_post_page_flip, | |
1013 | }, | |
89e5181f | 1014 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
f47299c5 AD |
1015 | }; |
1016 | ||
48e7a5f1 DV |
1017 | static struct radeon_asic rv770_asic = { |
1018 | .init = &rv770_init, | |
1019 | .fini = &rv770_fini, | |
1020 | .suspend = &rv770_suspend, | |
1021 | .resume = &rv770_resume, | |
a2d07b74 | 1022 | .asic_reset = &r600_asic_reset, |
225758d8 | 1023 | .gpu_is_lockup = &r600_gpu_is_lockup, |
48e7a5f1 | 1024 | .vga_set_state = &r600_vga_set_state, |
c5b3b850 AD |
1025 | .gart = { |
1026 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
1027 | .set_page = &rs600_gart_set_page, | |
1028 | }, | |
4c87bc26 CK |
1029 | .ring = { |
1030 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1031 | .ib_execute = &r600_ring_ib_execute, | |
1032 | .emit_fence = &r600_fence_ring_emit, | |
1033 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 1034 | .cs_parse = &r600_cs_parse, |
f712812e AD |
1035 | .ring_test = &r600_ring_test, |
1036 | .ib_test = &r600_ib_test, | |
4c87bc26 CK |
1037 | } |
1038 | }, | |
b35ea4ab AD |
1039 | .irq = { |
1040 | .set = &r600_irq_set, | |
1041 | .process = &r600_irq_process, | |
1042 | }, | |
c79a49ca AD |
1043 | .display = { |
1044 | .bandwidth_update = &rv515_bandwidth_update, | |
1045 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1046 | .wait_for_vblank = &avivo_wait_for_vblank, | |
1047 | }, | |
27cd7769 AD |
1048 | .copy = { |
1049 | .blit = &r600_copy_blit, | |
1050 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1051 | .dma = NULL, | |
1052 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1053 | .copy = &r600_copy_blit, | |
1054 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1055 | }, | |
9e6f3d02 AD |
1056 | .surface = { |
1057 | .set_reg = r600_set_surface_reg, | |
1058 | .clear_reg = r600_clear_surface_reg, | |
1059 | }, | |
901ea57d AD |
1060 | .hpd = { |
1061 | .init = &r600_hpd_init, | |
1062 | .fini = &r600_hpd_fini, | |
1063 | .sense = &r600_hpd_sense, | |
1064 | .set_polarity = &r600_hpd_set_polarity, | |
1065 | }, | |
48e7a5f1 | 1066 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
def9ba9c | 1067 | .gui_idle = &r600_gui_idle, |
a02fa397 AD |
1068 | .pm = { |
1069 | .misc = &rv770_pm_misc, | |
1070 | .prepare = &rs600_pm_prepare, | |
1071 | .finish = &rs600_pm_finish, | |
1072 | .init_profile = &r600_pm_init_profile, | |
1073 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1074 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1075 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1076 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1077 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1078 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1079 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1080 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 1081 | }, |
0f9e006c AD |
1082 | .pflip = { |
1083 | .pre_page_flip = &rs600_pre_page_flip, | |
1084 | .page_flip = &rv770_page_flip, | |
1085 | .post_page_flip = &rs600_post_page_flip, | |
1086 | }, | |
89e5181f | 1087 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
48e7a5f1 DV |
1088 | }; |
1089 | ||
1090 | static struct radeon_asic evergreen_asic = { | |
1091 | .init = &evergreen_init, | |
1092 | .fini = &evergreen_fini, | |
1093 | .suspend = &evergreen_suspend, | |
1094 | .resume = &evergreen_resume, | |
225758d8 | 1095 | .gpu_is_lockup = &evergreen_gpu_is_lockup, |
a2d07b74 | 1096 | .asic_reset = &evergreen_asic_reset, |
48e7a5f1 | 1097 | .vga_set_state = &r600_vga_set_state, |
c5b3b850 AD |
1098 | .gart = { |
1099 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
1100 | .set_page = &rs600_gart_set_page, | |
1101 | }, | |
4c87bc26 CK |
1102 | .ring = { |
1103 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1104 | .ib_execute = &evergreen_ring_ib_execute, | |
1105 | .emit_fence = &r600_fence_ring_emit, | |
1106 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 1107 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1108 | .ring_test = &r600_ring_test, |
1109 | .ib_test = &r600_ib_test, | |
4c87bc26 CK |
1110 | } |
1111 | }, | |
b35ea4ab AD |
1112 | .irq = { |
1113 | .set = &evergreen_irq_set, | |
1114 | .process = &evergreen_irq_process, | |
1115 | }, | |
c79a49ca AD |
1116 | .display = { |
1117 | .bandwidth_update = &evergreen_bandwidth_update, | |
1118 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1119 | .wait_for_vblank = &dce4_wait_for_vblank, | |
1120 | }, | |
27cd7769 AD |
1121 | .copy = { |
1122 | .blit = &r600_copy_blit, | |
1123 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1124 | .dma = NULL, | |
1125 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1126 | .copy = &r600_copy_blit, | |
1127 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1128 | }, | |
9e6f3d02 AD |
1129 | .surface = { |
1130 | .set_reg = r600_set_surface_reg, | |
1131 | .clear_reg = r600_clear_surface_reg, | |
1132 | }, | |
901ea57d AD |
1133 | .hpd = { |
1134 | .init = &evergreen_hpd_init, | |
1135 | .fini = &evergreen_hpd_fini, | |
1136 | .sense = &evergreen_hpd_sense, | |
1137 | .set_polarity = &evergreen_hpd_set_polarity, | |
1138 | }, | |
97bfd0ac | 1139 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
def9ba9c | 1140 | .gui_idle = &r600_gui_idle, |
a02fa397 AD |
1141 | .pm = { |
1142 | .misc = &evergreen_pm_misc, | |
1143 | .prepare = &evergreen_pm_prepare, | |
1144 | .finish = &evergreen_pm_finish, | |
1145 | .init_profile = &r600_pm_init_profile, | |
1146 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1147 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1148 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1149 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1150 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1151 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1152 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1153 | .set_clock_gating = NULL, | |
a02fa397 | 1154 | }, |
0f9e006c AD |
1155 | .pflip = { |
1156 | .pre_page_flip = &evergreen_pre_page_flip, | |
1157 | .page_flip = &evergreen_page_flip, | |
1158 | .post_page_flip = &evergreen_post_page_flip, | |
1159 | }, | |
89e5181f | 1160 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
48e7a5f1 DV |
1161 | }; |
1162 | ||
958261d1 AD |
1163 | static struct radeon_asic sumo_asic = { |
1164 | .init = &evergreen_init, | |
1165 | .fini = &evergreen_fini, | |
1166 | .suspend = &evergreen_suspend, | |
1167 | .resume = &evergreen_resume, | |
958261d1 AD |
1168 | .gpu_is_lockup = &evergreen_gpu_is_lockup, |
1169 | .asic_reset = &evergreen_asic_reset, | |
1170 | .vga_set_state = &r600_vga_set_state, | |
c5b3b850 AD |
1171 | .gart = { |
1172 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
1173 | .set_page = &rs600_gart_set_page, | |
1174 | }, | |
4c87bc26 CK |
1175 | .ring = { |
1176 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1177 | .ib_execute = &evergreen_ring_ib_execute, | |
1178 | .emit_fence = &r600_fence_ring_emit, | |
1179 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 1180 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1181 | .ring_test = &r600_ring_test, |
1182 | .ib_test = &r600_ib_test, | |
eb0c19c5 | 1183 | }, |
4c87bc26 | 1184 | }, |
b35ea4ab AD |
1185 | .irq = { |
1186 | .set = &evergreen_irq_set, | |
1187 | .process = &evergreen_irq_process, | |
1188 | }, | |
c79a49ca AD |
1189 | .display = { |
1190 | .bandwidth_update = &evergreen_bandwidth_update, | |
1191 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1192 | .wait_for_vblank = &dce4_wait_for_vblank, | |
1193 | }, | |
27cd7769 AD |
1194 | .copy = { |
1195 | .blit = &r600_copy_blit, | |
1196 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1197 | .dma = NULL, | |
1198 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1199 | .copy = &r600_copy_blit, | |
1200 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1201 | }, | |
9e6f3d02 AD |
1202 | .surface = { |
1203 | .set_reg = r600_set_surface_reg, | |
1204 | .clear_reg = r600_clear_surface_reg, | |
1205 | }, | |
901ea57d AD |
1206 | .hpd = { |
1207 | .init = &evergreen_hpd_init, | |
1208 | .fini = &evergreen_hpd_fini, | |
1209 | .sense = &evergreen_hpd_sense, | |
1210 | .set_polarity = &evergreen_hpd_set_polarity, | |
1211 | }, | |
97bfd0ac | 1212 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
958261d1 | 1213 | .gui_idle = &r600_gui_idle, |
a02fa397 AD |
1214 | .pm = { |
1215 | .misc = &evergreen_pm_misc, | |
1216 | .prepare = &evergreen_pm_prepare, | |
1217 | .finish = &evergreen_pm_finish, | |
1218 | .init_profile = &sumo_pm_init_profile, | |
1219 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1220 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1221 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1222 | .get_memory_clock = NULL, | |
1223 | .set_memory_clock = NULL, | |
1224 | .get_pcie_lanes = NULL, | |
1225 | .set_pcie_lanes = NULL, | |
1226 | .set_clock_gating = NULL, | |
a02fa397 | 1227 | }, |
0f9e006c AD |
1228 | .pflip = { |
1229 | .pre_page_flip = &evergreen_pre_page_flip, | |
1230 | .page_flip = &evergreen_page_flip, | |
1231 | .post_page_flip = &evergreen_post_page_flip, | |
1232 | }, | |
89e5181f | 1233 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
958261d1 AD |
1234 | }; |
1235 | ||
a43b7665 AD |
1236 | static struct radeon_asic btc_asic = { |
1237 | .init = &evergreen_init, | |
1238 | .fini = &evergreen_fini, | |
1239 | .suspend = &evergreen_suspend, | |
1240 | .resume = &evergreen_resume, | |
a43b7665 AD |
1241 | .gpu_is_lockup = &evergreen_gpu_is_lockup, |
1242 | .asic_reset = &evergreen_asic_reset, | |
1243 | .vga_set_state = &r600_vga_set_state, | |
c5b3b850 AD |
1244 | .gart = { |
1245 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
1246 | .set_page = &rs600_gart_set_page, | |
1247 | }, | |
4c87bc26 CK |
1248 | .ring = { |
1249 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1250 | .ib_execute = &evergreen_ring_ib_execute, | |
1251 | .emit_fence = &r600_fence_ring_emit, | |
1252 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 1253 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1254 | .ring_test = &r600_ring_test, |
1255 | .ib_test = &r600_ib_test, | |
4c87bc26 CK |
1256 | } |
1257 | }, | |
b35ea4ab AD |
1258 | .irq = { |
1259 | .set = &evergreen_irq_set, | |
1260 | .process = &evergreen_irq_process, | |
1261 | }, | |
c79a49ca AD |
1262 | .display = { |
1263 | .bandwidth_update = &evergreen_bandwidth_update, | |
1264 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1265 | .wait_for_vblank = &dce4_wait_for_vblank, | |
1266 | }, | |
27cd7769 AD |
1267 | .copy = { |
1268 | .blit = &r600_copy_blit, | |
1269 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1270 | .dma = NULL, | |
1271 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1272 | .copy = &r600_copy_blit, | |
1273 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1274 | }, | |
9e6f3d02 AD |
1275 | .surface = { |
1276 | .set_reg = r600_set_surface_reg, | |
1277 | .clear_reg = r600_clear_surface_reg, | |
1278 | }, | |
901ea57d AD |
1279 | .hpd = { |
1280 | .init = &evergreen_hpd_init, | |
1281 | .fini = &evergreen_hpd_fini, | |
1282 | .sense = &evergreen_hpd_sense, | |
1283 | .set_polarity = &evergreen_hpd_set_polarity, | |
1284 | }, | |
97bfd0ac | 1285 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
a43b7665 | 1286 | .gui_idle = &r600_gui_idle, |
a02fa397 AD |
1287 | .pm = { |
1288 | .misc = &evergreen_pm_misc, | |
1289 | .prepare = &evergreen_pm_prepare, | |
1290 | .finish = &evergreen_pm_finish, | |
1291 | .init_profile = &r600_pm_init_profile, | |
1292 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1293 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1294 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1295 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1296 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1297 | .get_pcie_lanes = NULL, | |
1298 | .set_pcie_lanes = NULL, | |
1299 | .set_clock_gating = NULL, | |
a02fa397 | 1300 | }, |
0f9e006c AD |
1301 | .pflip = { |
1302 | .pre_page_flip = &evergreen_pre_page_flip, | |
1303 | .page_flip = &evergreen_page_flip, | |
1304 | .post_page_flip = &evergreen_post_page_flip, | |
1305 | }, | |
89e5181f | 1306 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
a43b7665 AD |
1307 | }; |
1308 | ||
721604a1 JG |
1309 | static const struct radeon_vm_funcs cayman_vm_funcs = { |
1310 | .init = &cayman_vm_init, | |
1311 | .fini = &cayman_vm_fini, | |
1312 | .bind = &cayman_vm_bind, | |
1313 | .unbind = &cayman_vm_unbind, | |
1314 | .tlb_flush = &cayman_vm_tlb_flush, | |
1315 | .page_flags = &cayman_vm_page_flags, | |
1316 | .set_page = &cayman_vm_set_page, | |
1317 | }; | |
1318 | ||
e3487629 AD |
1319 | static struct radeon_asic cayman_asic = { |
1320 | .init = &cayman_init, | |
1321 | .fini = &cayman_fini, | |
1322 | .suspend = &cayman_suspend, | |
1323 | .resume = &cayman_resume, | |
e3487629 AD |
1324 | .gpu_is_lockup = &cayman_gpu_is_lockup, |
1325 | .asic_reset = &cayman_asic_reset, | |
1326 | .vga_set_state = &r600_vga_set_state, | |
c5b3b850 AD |
1327 | .gart = { |
1328 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | |
1329 | .set_page = &rs600_gart_set_page, | |
1330 | }, | |
4c87bc26 CK |
1331 | .ring = { |
1332 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
721604a1 JG |
1333 | .ib_execute = &cayman_ring_ib_execute, |
1334 | .ib_parse = &evergreen_ib_parse, | |
b40e7e16 | 1335 | .emit_fence = &cayman_fence_ring_emit, |
4c87bc26 | 1336 | .emit_semaphore = &r600_semaphore_ring_emit, |
eb0c19c5 | 1337 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1338 | .ring_test = &r600_ring_test, |
1339 | .ib_test = &r600_ib_test, | |
4c87bc26 CK |
1340 | }, |
1341 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | |
721604a1 JG |
1342 | .ib_execute = &cayman_ring_ib_execute, |
1343 | .ib_parse = &evergreen_ib_parse, | |
b40e7e16 | 1344 | .emit_fence = &cayman_fence_ring_emit, |
4c87bc26 | 1345 | .emit_semaphore = &r600_semaphore_ring_emit, |
eb0c19c5 | 1346 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1347 | .ring_test = &r600_ring_test, |
1348 | .ib_test = &r600_ib_test, | |
4c87bc26 CK |
1349 | }, |
1350 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | |
721604a1 JG |
1351 | .ib_execute = &cayman_ring_ib_execute, |
1352 | .ib_parse = &evergreen_ib_parse, | |
b40e7e16 | 1353 | .emit_fence = &cayman_fence_ring_emit, |
4c87bc26 | 1354 | .emit_semaphore = &r600_semaphore_ring_emit, |
eb0c19c5 | 1355 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1356 | .ring_test = &r600_ring_test, |
1357 | .ib_test = &r600_ib_test, | |
4c87bc26 CK |
1358 | } |
1359 | }, | |
b35ea4ab AD |
1360 | .irq = { |
1361 | .set = &evergreen_irq_set, | |
1362 | .process = &evergreen_irq_process, | |
1363 | }, | |
c79a49ca AD |
1364 | .display = { |
1365 | .bandwidth_update = &evergreen_bandwidth_update, | |
1366 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1367 | .wait_for_vblank = &dce4_wait_for_vblank, | |
1368 | }, | |
27cd7769 AD |
1369 | .copy = { |
1370 | .blit = &r600_copy_blit, | |
1371 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1372 | .dma = NULL, | |
1373 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1374 | .copy = &r600_copy_blit, | |
1375 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1376 | }, | |
9e6f3d02 AD |
1377 | .surface = { |
1378 | .set_reg = r600_set_surface_reg, | |
1379 | .clear_reg = r600_clear_surface_reg, | |
1380 | }, | |
901ea57d AD |
1381 | .hpd = { |
1382 | .init = &evergreen_hpd_init, | |
1383 | .fini = &evergreen_hpd_fini, | |
1384 | .sense = &evergreen_hpd_sense, | |
1385 | .set_polarity = &evergreen_hpd_set_polarity, | |
1386 | }, | |
97bfd0ac | 1387 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
e3487629 | 1388 | .gui_idle = &r600_gui_idle, |
a02fa397 AD |
1389 | .pm = { |
1390 | .misc = &evergreen_pm_misc, | |
1391 | .prepare = &evergreen_pm_prepare, | |
1392 | .finish = &evergreen_pm_finish, | |
1393 | .init_profile = &r600_pm_init_profile, | |
1394 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1395 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1396 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1397 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1398 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1399 | .get_pcie_lanes = NULL, | |
1400 | .set_pcie_lanes = NULL, | |
1401 | .set_clock_gating = NULL, | |
a02fa397 | 1402 | }, |
0f9e006c AD |
1403 | .pflip = { |
1404 | .pre_page_flip = &evergreen_pre_page_flip, | |
1405 | .page_flip = &evergreen_page_flip, | |
1406 | .post_page_flip = &evergreen_post_page_flip, | |
1407 | }, | |
89e5181f | 1408 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
e3487629 AD |
1409 | }; |
1410 | ||
0a10c851 DV |
1411 | int radeon_asic_init(struct radeon_device *rdev) |
1412 | { | |
1413 | radeon_register_accessor_init(rdev); | |
ba7e05e9 AD |
1414 | |
1415 | /* set the number of crtcs */ | |
1416 | if (rdev->flags & RADEON_SINGLE_CRTC) | |
1417 | rdev->num_crtc = 1; | |
1418 | else | |
1419 | rdev->num_crtc = 2; | |
1420 | ||
0a10c851 DV |
1421 | switch (rdev->family) { |
1422 | case CHIP_R100: | |
1423 | case CHIP_RV100: | |
1424 | case CHIP_RS100: | |
1425 | case CHIP_RV200: | |
1426 | case CHIP_RS200: | |
1427 | rdev->asic = &r100_asic; | |
1428 | break; | |
1429 | case CHIP_R200: | |
1430 | case CHIP_RV250: | |
1431 | case CHIP_RS300: | |
1432 | case CHIP_RV280: | |
1433 | rdev->asic = &r200_asic; | |
1434 | break; | |
1435 | case CHIP_R300: | |
1436 | case CHIP_R350: | |
1437 | case CHIP_RV350: | |
1438 | case CHIP_RV380: | |
1439 | if (rdev->flags & RADEON_IS_PCIE) | |
1440 | rdev->asic = &r300_asic_pcie; | |
1441 | else | |
1442 | rdev->asic = &r300_asic; | |
1443 | break; | |
1444 | case CHIP_R420: | |
1445 | case CHIP_R423: | |
1446 | case CHIP_RV410: | |
1447 | rdev->asic = &r420_asic; | |
07bb084c AD |
1448 | /* handle macs */ |
1449 | if (rdev->bios == NULL) { | |
798bcf73 AD |
1450 | rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; |
1451 | rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; | |
1452 | rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; | |
1453 | rdev->asic->pm.set_memory_clock = NULL; | |
07bb084c | 1454 | } |
0a10c851 DV |
1455 | break; |
1456 | case CHIP_RS400: | |
1457 | case CHIP_RS480: | |
1458 | rdev->asic = &rs400_asic; | |
1459 | break; | |
1460 | case CHIP_RS600: | |
1461 | rdev->asic = &rs600_asic; | |
1462 | break; | |
1463 | case CHIP_RS690: | |
1464 | case CHIP_RS740: | |
1465 | rdev->asic = &rs690_asic; | |
1466 | break; | |
1467 | case CHIP_RV515: | |
1468 | rdev->asic = &rv515_asic; | |
1469 | break; | |
1470 | case CHIP_R520: | |
1471 | case CHIP_RV530: | |
1472 | case CHIP_RV560: | |
1473 | case CHIP_RV570: | |
1474 | case CHIP_R580: | |
1475 | rdev->asic = &r520_asic; | |
1476 | break; | |
1477 | case CHIP_R600: | |
1478 | case CHIP_RV610: | |
1479 | case CHIP_RV630: | |
1480 | case CHIP_RV620: | |
1481 | case CHIP_RV635: | |
1482 | case CHIP_RV670: | |
f47299c5 AD |
1483 | rdev->asic = &r600_asic; |
1484 | break; | |
0a10c851 DV |
1485 | case CHIP_RS780: |
1486 | case CHIP_RS880: | |
f47299c5 | 1487 | rdev->asic = &rs780_asic; |
0a10c851 DV |
1488 | break; |
1489 | case CHIP_RV770: | |
1490 | case CHIP_RV730: | |
1491 | case CHIP_RV710: | |
1492 | case CHIP_RV740: | |
1493 | rdev->asic = &rv770_asic; | |
1494 | break; | |
1495 | case CHIP_CEDAR: | |
1496 | case CHIP_REDWOOD: | |
1497 | case CHIP_JUNIPER: | |
1498 | case CHIP_CYPRESS: | |
1499 | case CHIP_HEMLOCK: | |
ba7e05e9 AD |
1500 | /* set num crtcs */ |
1501 | if (rdev->family == CHIP_CEDAR) | |
1502 | rdev->num_crtc = 4; | |
1503 | else | |
1504 | rdev->num_crtc = 6; | |
0a10c851 DV |
1505 | rdev->asic = &evergreen_asic; |
1506 | break; | |
958261d1 | 1507 | case CHIP_PALM: |
89da5a37 AD |
1508 | case CHIP_SUMO: |
1509 | case CHIP_SUMO2: | |
958261d1 AD |
1510 | rdev->asic = &sumo_asic; |
1511 | break; | |
a43b7665 AD |
1512 | case CHIP_BARTS: |
1513 | case CHIP_TURKS: | |
1514 | case CHIP_CAICOS: | |
ba7e05e9 AD |
1515 | /* set num crtcs */ |
1516 | if (rdev->family == CHIP_CAICOS) | |
1517 | rdev->num_crtc = 4; | |
1518 | else | |
1519 | rdev->num_crtc = 6; | |
a43b7665 AD |
1520 | rdev->asic = &btc_asic; |
1521 | break; | |
e3487629 AD |
1522 | case CHIP_CAYMAN: |
1523 | rdev->asic = &cayman_asic; | |
ba7e05e9 AD |
1524 | /* set num crtcs */ |
1525 | rdev->num_crtc = 6; | |
721604a1 | 1526 | rdev->vm_manager.funcs = &cayman_vm_funcs; |
e3487629 | 1527 | break; |
0a10c851 DV |
1528 | default: |
1529 | /* FIXME: not supported yet */ | |
1530 | return -EINVAL; | |
1531 | } | |
1532 | ||
1533 | if (rdev->flags & RADEON_IS_IGP) { | |
798bcf73 AD |
1534 | rdev->asic->pm.get_memory_clock = NULL; |
1535 | rdev->asic->pm.set_memory_clock = NULL; | |
0a10c851 DV |
1536 | } |
1537 | ||
1538 | return 0; | |
1539 | } | |
1540 |