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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
760285e7 DH |
26 | #include <drm/drmP.h> |
27 | #include <drm/radeon_drm.h> | |
771fe6b9 JG |
28 | #include "radeon.h" |
29 | ||
30 | #include "atom.h" | |
31 | #include "atom-bits.h" | |
297b1286 | 32 | #include "radeon_asic.h" |
771fe6b9 | 33 | |
771fe6b9 | 34 | extern void |
5137ee94 | 35 | radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, |
36868bda | 36 | uint32_t supported_device, u16 caps); |
771fe6b9 | 37 | |
771fe6b9 JG |
38 | /* from radeon_legacy_encoder.c */ |
39 | extern void | |
5137ee94 | 40 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, |
771fe6b9 JG |
41 | uint32_t supported_device); |
42 | ||
43 | union atom_supported_devices { | |
44 | struct _ATOM_SUPPORTED_DEVICES_INFO info; | |
45 | struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; | |
46 | struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; | |
47 | }; | |
48 | ||
21240f9b AD |
49 | static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev, |
50 | ATOM_GPIO_I2C_ASSIGMENT *gpio, | |
51 | u8 index) | |
52 | { | |
53 | /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */ | |
54 | if ((rdev->family == CHIP_R420) || | |
55 | (rdev->family == CHIP_R423) || | |
56 | (rdev->family == CHIP_RV410)) { | |
57 | if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) || | |
58 | (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) || | |
59 | (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) { | |
60 | gpio->ucClkMaskShift = 0x19; | |
61 | gpio->ucDataMaskShift = 0x18; | |
62 | } | |
63 | } | |
64 | ||
65 | /* some evergreen boards have bad data for this entry */ | |
66 | if (ASIC_IS_DCE4(rdev)) { | |
67 | if ((index == 7) && | |
68 | (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && | |
69 | (gpio->sucI2cId.ucAccess == 0)) { | |
70 | gpio->sucI2cId.ucAccess = 0x97; | |
71 | gpio->ucDataMaskShift = 8; | |
72 | gpio->ucDataEnShift = 8; | |
73 | gpio->ucDataY_Shift = 8; | |
74 | gpio->ucDataA_Shift = 8; | |
75 | } | |
76 | } | |
77 | ||
78 | /* some DCE3 boards have bad data for this entry */ | |
79 | if (ASIC_IS_DCE3(rdev)) { | |
80 | if ((index == 4) && | |
81 | (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && | |
82 | (gpio->sucI2cId.ucAccess == 0x94)) | |
83 | gpio->sucI2cId.ucAccess = 0x14; | |
84 | } | |
85 | } | |
86 | ||
87 | static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) | |
88 | { | |
89 | struct radeon_i2c_bus_rec i2c; | |
90 | ||
91 | memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); | |
92 | ||
93 | i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; | |
94 | i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; | |
95 | i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; | |
96 | i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; | |
97 | i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; | |
98 | i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; | |
99 | i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; | |
100 | i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; | |
101 | i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); | |
102 | i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); | |
103 | i2c.en_clk_mask = (1 << gpio->ucClkEnShift); | |
104 | i2c.en_data_mask = (1 << gpio->ucDataEnShift); | |
105 | i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); | |
106 | i2c.y_data_mask = (1 << gpio->ucDataY_Shift); | |
107 | i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); | |
108 | i2c.a_data_mask = (1 << gpio->ucDataA_Shift); | |
109 | ||
110 | if (gpio->sucI2cId.sbfAccess.bfHW_Capable) | |
111 | i2c.hw_capable = true; | |
112 | else | |
113 | i2c.hw_capable = false; | |
114 | ||
115 | if (gpio->sucI2cId.ucAccess == 0xa0) | |
116 | i2c.mm_i2c = true; | |
117 | else | |
118 | i2c.mm_i2c = false; | |
119 | ||
120 | i2c.i2c_id = gpio->sucI2cId.ucAccess; | |
121 | ||
122 | if (i2c.mask_clk_reg) | |
123 | i2c.valid = true; | |
124 | else | |
125 | i2c.valid = false; | |
126 | ||
127 | return i2c; | |
128 | } | |
129 | ||
ce580fab | 130 | static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev, |
eed45b30 | 131 | uint8_t id) |
771fe6b9 | 132 | { |
771fe6b9 | 133 | struct atom_context *ctx = rdev->mode_info.atom_context; |
6a93cb25 | 134 | ATOM_GPIO_I2C_ASSIGMENT *gpio; |
771fe6b9 JG |
135 | struct radeon_i2c_bus_rec i2c; |
136 | int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); | |
137 | struct _ATOM_GPIO_I2C_INFO *i2c_info; | |
95beb690 AD |
138 | uint16_t data_offset, size; |
139 | int i, num_indices; | |
771fe6b9 JG |
140 | |
141 | memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); | |
142 | i2c.valid = false; | |
143 | ||
95beb690 | 144 | if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { |
a084e6ee AD |
145 | i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); |
146 | ||
95beb690 AD |
147 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
148 | sizeof(ATOM_GPIO_I2C_ASSIGMENT); | |
149 | ||
607f2c27 | 150 | gpio = &i2c_info->asGPIO_Info[0]; |
95beb690 | 151 | for (i = 0; i < num_indices; i++) { |
a084e6ee | 152 | |
21240f9b | 153 | radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); |
3074adc8 | 154 | |
a084e6ee | 155 | if (gpio->sucI2cId.ucAccess == id) { |
21240f9b | 156 | i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); |
a084e6ee AD |
157 | break; |
158 | } | |
607f2c27 AD |
159 | gpio = (ATOM_GPIO_I2C_ASSIGMENT *) |
160 | ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); | |
d3f420d1 AD |
161 | } |
162 | } | |
771fe6b9 JG |
163 | |
164 | return i2c; | |
165 | } | |
166 | ||
f376b94f AD |
167 | void radeon_atombios_i2c_init(struct radeon_device *rdev) |
168 | { | |
169 | struct atom_context *ctx = rdev->mode_info.atom_context; | |
170 | ATOM_GPIO_I2C_ASSIGMENT *gpio; | |
171 | struct radeon_i2c_bus_rec i2c; | |
172 | int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); | |
173 | struct _ATOM_GPIO_I2C_INFO *i2c_info; | |
174 | uint16_t data_offset, size; | |
175 | int i, num_indices; | |
176 | char stmp[32]; | |
177 | ||
f376b94f AD |
178 | if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { |
179 | i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); | |
180 | ||
181 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / | |
182 | sizeof(ATOM_GPIO_I2C_ASSIGMENT); | |
183 | ||
607f2c27 | 184 | gpio = &i2c_info->asGPIO_Info[0]; |
f376b94f | 185 | for (i = 0; i < num_indices; i++) { |
21240f9b | 186 | radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); |
ea39302b | 187 | |
21240f9b | 188 | i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); |
3074adc8 | 189 | |
21240f9b | 190 | if (i2c.valid) { |
f376b94f AD |
191 | sprintf(stmp, "0x%x", i2c.i2c_id); |
192 | rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp); | |
193 | } | |
607f2c27 AD |
194 | gpio = (ATOM_GPIO_I2C_ASSIGMENT *) |
195 | ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); | |
f376b94f AD |
196 | } |
197 | } | |
198 | } | |
199 | ||
09e619c0 AD |
200 | struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, |
201 | u8 id) | |
eed45b30 AD |
202 | { |
203 | struct atom_context *ctx = rdev->mode_info.atom_context; | |
204 | struct radeon_gpio_rec gpio; | |
205 | int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); | |
206 | struct _ATOM_GPIO_PIN_LUT *gpio_info; | |
207 | ATOM_GPIO_PIN_ASSIGNMENT *pin; | |
208 | u16 data_offset, size; | |
209 | int i, num_indices; | |
210 | ||
211 | memset(&gpio, 0, sizeof(struct radeon_gpio_rec)); | |
212 | gpio.valid = false; | |
213 | ||
a084e6ee AD |
214 | if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { |
215 | gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); | |
eed45b30 | 216 | |
a084e6ee AD |
217 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
218 | sizeof(ATOM_GPIO_PIN_ASSIGNMENT); | |
eed45b30 | 219 | |
607f2c27 | 220 | pin = gpio_info->asGPIO_Pin; |
a084e6ee | 221 | for (i = 0; i < num_indices; i++) { |
a084e6ee AD |
222 | if (id == pin->ucGPIO_ID) { |
223 | gpio.id = pin->ucGPIO_ID; | |
4589433c | 224 | gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4; |
727b3d25 | 225 | gpio.shift = pin->ucGpioPinBitShift; |
a084e6ee AD |
226 | gpio.mask = (1 << pin->ucGpioPinBitShift); |
227 | gpio.valid = true; | |
228 | break; | |
229 | } | |
607f2c27 AD |
230 | pin = (ATOM_GPIO_PIN_ASSIGNMENT *) |
231 | ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT)); | |
eed45b30 AD |
232 | } |
233 | } | |
234 | ||
235 | return gpio; | |
236 | } | |
237 | ||
238 | static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev, | |
239 | struct radeon_gpio_rec *gpio) | |
240 | { | |
241 | struct radeon_hpd hpd; | |
bcc1c2a1 AD |
242 | u32 reg; |
243 | ||
1d978dac JD |
244 | memset(&hpd, 0, sizeof(struct radeon_hpd)); |
245 | ||
82d118ef AD |
246 | if (ASIC_IS_DCE6(rdev)) |
247 | reg = SI_DC_GPIO_HPD_A; | |
248 | else if (ASIC_IS_DCE4(rdev)) | |
bcc1c2a1 AD |
249 | reg = EVERGREEN_DC_GPIO_HPD_A; |
250 | else | |
251 | reg = AVIVO_DC_GPIO_HPD_A; | |
252 | ||
eed45b30 | 253 | hpd.gpio = *gpio; |
bcc1c2a1 | 254 | if (gpio->reg == reg) { |
eed45b30 AD |
255 | switch(gpio->mask) { |
256 | case (1 << 0): | |
257 | hpd.hpd = RADEON_HPD_1; | |
258 | break; | |
259 | case (1 << 8): | |
260 | hpd.hpd = RADEON_HPD_2; | |
261 | break; | |
262 | case (1 << 16): | |
263 | hpd.hpd = RADEON_HPD_3; | |
264 | break; | |
265 | case (1 << 24): | |
266 | hpd.hpd = RADEON_HPD_4; | |
267 | break; | |
268 | case (1 << 26): | |
269 | hpd.hpd = RADEON_HPD_5; | |
270 | break; | |
271 | case (1 << 28): | |
272 | hpd.hpd = RADEON_HPD_6; | |
273 | break; | |
274 | default: | |
275 | hpd.hpd = RADEON_HPD_NONE; | |
276 | break; | |
277 | } | |
278 | } else | |
279 | hpd.hpd = RADEON_HPD_NONE; | |
280 | return hpd; | |
281 | } | |
282 | ||
771fe6b9 JG |
283 | static bool radeon_atom_apply_quirks(struct drm_device *dev, |
284 | uint32_t supported_device, | |
285 | int *connector_type, | |
848577ee | 286 | struct radeon_i2c_bus_rec *i2c_bus, |
eed45b30 AD |
287 | uint16_t *line_mux, |
288 | struct radeon_hpd *hpd) | |
771fe6b9 JG |
289 | { |
290 | ||
291 | /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ | |
292 | if ((dev->pdev->device == 0x791e) && | |
293 | (dev->pdev->subsystem_vendor == 0x1043) && | |
294 | (dev->pdev->subsystem_device == 0x826d)) { | |
295 | if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && | |
296 | (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) | |
297 | *connector_type = DRM_MODE_CONNECTOR_DVID; | |
298 | } | |
299 | ||
c86a9038 AD |
300 | /* Asrock RS600 board lists the DVI port as HDMI */ |
301 | if ((dev->pdev->device == 0x7941) && | |
302 | (dev->pdev->subsystem_vendor == 0x1849) && | |
303 | (dev->pdev->subsystem_device == 0x7941)) { | |
304 | if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && | |
305 | (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) | |
306 | *connector_type = DRM_MODE_CONNECTOR_DVID; | |
307 | } | |
308 | ||
f36fce0f AD |
309 | /* MSI K9A2GM V2/V3 board has no HDMI or DVI */ |
310 | if ((dev->pdev->device == 0x796e) && | |
311 | (dev->pdev->subsystem_vendor == 0x1462) && | |
312 | (dev->pdev->subsystem_device == 0x7302)) { | |
313 | if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) || | |
314 | (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) | |
315 | return false; | |
316 | } | |
317 | ||
771fe6b9 JG |
318 | /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ |
319 | if ((dev->pdev->device == 0x7941) && | |
320 | (dev->pdev->subsystem_vendor == 0x147b) && | |
321 | (dev->pdev->subsystem_device == 0x2412)) { | |
322 | if (*connector_type == DRM_MODE_CONNECTOR_DVII) | |
323 | return false; | |
324 | } | |
325 | ||
326 | /* Falcon NW laptop lists vga ddc line for LVDS */ | |
327 | if ((dev->pdev->device == 0x5653) && | |
328 | (dev->pdev->subsystem_vendor == 0x1462) && | |
329 | (dev->pdev->subsystem_device == 0x0291)) { | |
848577ee | 330 | if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { |
771fe6b9 | 331 | i2c_bus->valid = false; |
848577ee AD |
332 | *line_mux = 53; |
333 | } | |
771fe6b9 JG |
334 | } |
335 | ||
4e3f9b78 AD |
336 | /* HIS X1300 is DVI+VGA, not DVI+DVI */ |
337 | if ((dev->pdev->device == 0x7146) && | |
338 | (dev->pdev->subsystem_vendor == 0x17af) && | |
339 | (dev->pdev->subsystem_device == 0x2058)) { | |
340 | if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) | |
341 | return false; | |
342 | } | |
343 | ||
aa1a750e DA |
344 | /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */ |
345 | if ((dev->pdev->device == 0x7142) && | |
346 | (dev->pdev->subsystem_vendor == 0x1458) && | |
347 | (dev->pdev->subsystem_device == 0x2134)) { | |
348 | if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) | |
349 | return false; | |
350 | } | |
351 | ||
352 | ||
771fe6b9 JG |
353 | /* Funky macbooks */ |
354 | if ((dev->pdev->device == 0x71C5) && | |
355 | (dev->pdev->subsystem_vendor == 0x106b) && | |
356 | (dev->pdev->subsystem_device == 0x0080)) { | |
357 | if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || | |
358 | (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) | |
359 | return false; | |
e1e8a5dd AD |
360 | if (supported_device == ATOM_DEVICE_CRT2_SUPPORT) |
361 | *line_mux = 0x90; | |
771fe6b9 JG |
362 | } |
363 | ||
be23da8a AD |
364 | /* mac rv630, rv730, others */ |
365 | if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) && | |
366 | (*connector_type == DRM_MODE_CONNECTOR_DVII)) { | |
367 | *connector_type = DRM_MODE_CONNECTOR_9PinDIN; | |
368 | *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1; | |
f598aa75 AD |
369 | } |
370 | ||
771fe6b9 JG |
371 | /* ASUS HD 3600 XT board lists the DVI port as HDMI */ |
372 | if ((dev->pdev->device == 0x9598) && | |
373 | (dev->pdev->subsystem_vendor == 0x1043) && | |
374 | (dev->pdev->subsystem_device == 0x01da)) { | |
705af9c7 | 375 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
d42571ef | 376 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
705af9c7 AD |
377 | } |
378 | } | |
379 | ||
e153b70b AD |
380 | /* ASUS HD 3600 board lists the DVI port as HDMI */ |
381 | if ((dev->pdev->device == 0x9598) && | |
382 | (dev->pdev->subsystem_vendor == 0x1043) && | |
383 | (dev->pdev->subsystem_device == 0x01e4)) { | |
384 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { | |
385 | *connector_type = DRM_MODE_CONNECTOR_DVII; | |
386 | } | |
387 | } | |
388 | ||
705af9c7 AD |
389 | /* ASUS HD 3450 board lists the DVI port as HDMI */ |
390 | if ((dev->pdev->device == 0x95C5) && | |
391 | (dev->pdev->subsystem_vendor == 0x1043) && | |
392 | (dev->pdev->subsystem_device == 0x01e2)) { | |
393 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { | |
d42571ef | 394 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
771fe6b9 JG |
395 | } |
396 | } | |
397 | ||
705af9c7 AD |
398 | /* some BIOSes seem to report DAC on HDMI - usually this is a board with |
399 | * HDMI + VGA reporting as HDMI | |
400 | */ | |
401 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { | |
402 | if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { | |
403 | *connector_type = DRM_MODE_CONNECTOR_VGA; | |
404 | *line_mux = 0; | |
405 | } | |
406 | } | |
407 | ||
4f87af46 | 408 | /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port |
2f299d5d AD |
409 | * on the laptop and a DVI port on the docking station and |
410 | * both share the same encoder, hpd pin, and ddc line. | |
411 | * So while the bios table is technically correct, | |
412 | * we drop the DVI port here since xrandr has no concept of | |
413 | * encoders and will try and drive both connectors | |
414 | * with different crtcs which isn't possible on the hardware | |
415 | * side and leaves no crtcs for LVDS or VGA. | |
416 | */ | |
4f87af46 | 417 | if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) && |
3e5f8ff3 AD |
418 | (dev->pdev->subsystem_vendor == 0x1025) && |
419 | (dev->pdev->subsystem_device == 0x013c)) { | |
420 | if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && | |
9ea2c4be | 421 | (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) { |
2f299d5d | 422 | /* actually it's a DVI-D port not DVI-I */ |
3e5f8ff3 | 423 | *connector_type = DRM_MODE_CONNECTOR_DVID; |
2f299d5d | 424 | return false; |
9ea2c4be | 425 | } |
3e5f8ff3 AD |
426 | } |
427 | ||
efa8450f DA |
428 | /* XFX Pine Group device rv730 reports no VGA DDC lines |
429 | * even though they are wired up to record 0x93 | |
430 | */ | |
431 | if ((dev->pdev->device == 0x9498) && | |
432 | (dev->pdev->subsystem_vendor == 0x1682) && | |
1ebf169a AD |
433 | (dev->pdev->subsystem_device == 0x2452) && |
434 | (i2c_bus->valid == false) && | |
435 | !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) { | |
efa8450f DA |
436 | struct radeon_device *rdev = dev->dev_private; |
437 | *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93); | |
438 | } | |
4c1b2d2d AD |
439 | |
440 | /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */ | |
0eb1c3d4 AD |
441 | if (((dev->pdev->device == 0x9802) || |
442 | (dev->pdev->device == 0x9805) || | |
443 | (dev->pdev->device == 0x9806)) && | |
4c1b2d2d AD |
444 | (dev->pdev->subsystem_vendor == 0x1734) && |
445 | (dev->pdev->subsystem_device == 0x11bd)) { | |
446 | if (*connector_type == DRM_MODE_CONNECTOR_VGA) { | |
447 | *connector_type = DRM_MODE_CONNECTOR_DVII; | |
448 | *line_mux = 0x3103; | |
449 | } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) { | |
450 | *connector_type = DRM_MODE_CONNECTOR_DVII; | |
451 | } | |
452 | } | |
453 | ||
771fe6b9 JG |
454 | return true; |
455 | } | |
456 | ||
7f6bf72a | 457 | static const int supported_devices_connector_convert[] = { |
771fe6b9 JG |
458 | DRM_MODE_CONNECTOR_Unknown, |
459 | DRM_MODE_CONNECTOR_VGA, | |
460 | DRM_MODE_CONNECTOR_DVII, | |
461 | DRM_MODE_CONNECTOR_DVID, | |
462 | DRM_MODE_CONNECTOR_DVIA, | |
463 | DRM_MODE_CONNECTOR_SVIDEO, | |
464 | DRM_MODE_CONNECTOR_Composite, | |
465 | DRM_MODE_CONNECTOR_LVDS, | |
466 | DRM_MODE_CONNECTOR_Unknown, | |
467 | DRM_MODE_CONNECTOR_Unknown, | |
468 | DRM_MODE_CONNECTOR_HDMIA, | |
469 | DRM_MODE_CONNECTOR_HDMIB, | |
470 | DRM_MODE_CONNECTOR_Unknown, | |
471 | DRM_MODE_CONNECTOR_Unknown, | |
472 | DRM_MODE_CONNECTOR_9PinDIN, | |
473 | DRM_MODE_CONNECTOR_DisplayPort | |
474 | }; | |
475 | ||
7f6bf72a | 476 | static const uint16_t supported_devices_connector_object_id_convert[] = { |
b75fad06 AD |
477 | CONNECTOR_OBJECT_ID_NONE, |
478 | CONNECTOR_OBJECT_ID_VGA, | |
479 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ | |
480 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ | |
481 | CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ | |
482 | CONNECTOR_OBJECT_ID_COMPOSITE, | |
483 | CONNECTOR_OBJECT_ID_SVIDEO, | |
484 | CONNECTOR_OBJECT_ID_LVDS, | |
485 | CONNECTOR_OBJECT_ID_9PIN_DIN, | |
486 | CONNECTOR_OBJECT_ID_9PIN_DIN, | |
487 | CONNECTOR_OBJECT_ID_DISPLAYPORT, | |
488 | CONNECTOR_OBJECT_ID_HDMI_TYPE_A, | |
489 | CONNECTOR_OBJECT_ID_HDMI_TYPE_B, | |
490 | CONNECTOR_OBJECT_ID_SVIDEO | |
491 | }; | |
492 | ||
7f6bf72a | 493 | static const int object_connector_convert[] = { |
771fe6b9 JG |
494 | DRM_MODE_CONNECTOR_Unknown, |
495 | DRM_MODE_CONNECTOR_DVII, | |
496 | DRM_MODE_CONNECTOR_DVII, | |
497 | DRM_MODE_CONNECTOR_DVID, | |
498 | DRM_MODE_CONNECTOR_DVID, | |
499 | DRM_MODE_CONNECTOR_VGA, | |
500 | DRM_MODE_CONNECTOR_Composite, | |
501 | DRM_MODE_CONNECTOR_SVIDEO, | |
502 | DRM_MODE_CONNECTOR_Unknown, | |
705af9c7 | 503 | DRM_MODE_CONNECTOR_Unknown, |
771fe6b9 JG |
504 | DRM_MODE_CONNECTOR_9PinDIN, |
505 | DRM_MODE_CONNECTOR_Unknown, | |
506 | DRM_MODE_CONNECTOR_HDMIA, | |
507 | DRM_MODE_CONNECTOR_HDMIB, | |
771fe6b9 JG |
508 | DRM_MODE_CONNECTOR_LVDS, |
509 | DRM_MODE_CONNECTOR_9PinDIN, | |
510 | DRM_MODE_CONNECTOR_Unknown, | |
511 | DRM_MODE_CONNECTOR_Unknown, | |
512 | DRM_MODE_CONNECTOR_Unknown, | |
196c58d2 AD |
513 | DRM_MODE_CONNECTOR_DisplayPort, |
514 | DRM_MODE_CONNECTOR_eDP, | |
515 | DRM_MODE_CONNECTOR_Unknown | |
771fe6b9 JG |
516 | }; |
517 | ||
518 | bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) | |
519 | { | |
520 | struct radeon_device *rdev = dev->dev_private; | |
521 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
522 | struct atom_context *ctx = mode_info->atom_context; | |
523 | int index = GetIndexIntoMasterTable(DATA, Object_Header); | |
eed45b30 AD |
524 | u16 size, data_offset; |
525 | u8 frev, crev; | |
771fe6b9 | 526 | ATOM_CONNECTOR_OBJECT_TABLE *con_obj; |
36868bda | 527 | ATOM_ENCODER_OBJECT_TABLE *enc_obj; |
26b5bc98 | 528 | ATOM_OBJECT_TABLE *router_obj; |
771fe6b9 JG |
529 | ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; |
530 | ATOM_OBJECT_HEADER *obj_header; | |
26b5bc98 | 531 | int i, j, k, path_size, device_support; |
771fe6b9 | 532 | int connector_type; |
eed45b30 | 533 | u16 igp_lane_info, conn_id, connector_object_id; |
771fe6b9 | 534 | struct radeon_i2c_bus_rec ddc_bus; |
26b5bc98 | 535 | struct radeon_router router; |
eed45b30 AD |
536 | struct radeon_gpio_rec gpio; |
537 | struct radeon_hpd hpd; | |
538 | ||
a084e6ee | 539 | if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) |
771fe6b9 JG |
540 | return false; |
541 | ||
542 | if (crev < 2) | |
543 | return false; | |
544 | ||
545 | obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); | |
546 | path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) | |
547 | (ctx->bios + data_offset + | |
548 | le16_to_cpu(obj_header->usDisplayPathTableOffset)); | |
549 | con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) | |
550 | (ctx->bios + data_offset + | |
551 | le16_to_cpu(obj_header->usConnectorObjectTableOffset)); | |
36868bda AD |
552 | enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) |
553 | (ctx->bios + data_offset + | |
554 | le16_to_cpu(obj_header->usEncoderObjectTableOffset)); | |
26b5bc98 AD |
555 | router_obj = (ATOM_OBJECT_TABLE *) |
556 | (ctx->bios + data_offset + | |
557 | le16_to_cpu(obj_header->usRouterObjectTableOffset)); | |
771fe6b9 JG |
558 | device_support = le16_to_cpu(obj_header->usDeviceSupport); |
559 | ||
560 | path_size = 0; | |
561 | for (i = 0; i < path_obj->ucNumOfDispPath; i++) { | |
562 | uint8_t *addr = (uint8_t *) path_obj->asDispPath; | |
563 | ATOM_DISPLAY_OBJECT_PATH *path; | |
564 | addr += path_size; | |
565 | path = (ATOM_DISPLAY_OBJECT_PATH *) addr; | |
566 | path_size += le16_to_cpu(path->usSize); | |
5137ee94 | 567 | |
771fe6b9 JG |
568 | if (device_support & le16_to_cpu(path->usDeviceTag)) { |
569 | uint8_t con_obj_id, con_obj_num, con_obj_type; | |
570 | ||
571 | con_obj_id = | |
572 | (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) | |
573 | >> OBJECT_ID_SHIFT; | |
574 | con_obj_num = | |
575 | (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) | |
576 | >> ENUM_ID_SHIFT; | |
577 | con_obj_type = | |
578 | (le16_to_cpu(path->usConnObjectId) & | |
579 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; | |
580 | ||
4bbd4973 DA |
581 | /* TODO CV support */ |
582 | if (le16_to_cpu(path->usDeviceTag) == | |
583 | ATOM_DEVICE_CV_SUPPORT) | |
771fe6b9 JG |
584 | continue; |
585 | ||
ee59f2b4 AD |
586 | /* IGP chips */ |
587 | if ((rdev->flags & RADEON_IS_IGP) && | |
771fe6b9 JG |
588 | (con_obj_id == |
589 | CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { | |
590 | uint16_t igp_offset = 0; | |
591 | ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; | |
592 | ||
593 | index = | |
594 | GetIndexIntoMasterTable(DATA, | |
595 | IntegratedSystemInfo); | |
596 | ||
a084e6ee AD |
597 | if (atom_parse_data_header(ctx, index, &size, &frev, |
598 | &crev, &igp_offset)) { | |
599 | ||
600 | if (crev >= 2) { | |
601 | igp_obj = | |
602 | (ATOM_INTEGRATED_SYSTEM_INFO_V2 | |
603 | *) (ctx->bios + igp_offset); | |
604 | ||
605 | if (igp_obj) { | |
606 | uint32_t slot_config, ct; | |
607 | ||
608 | if (con_obj_num == 1) | |
609 | slot_config = | |
610 | igp_obj-> | |
611 | ulDDISlot1Config; | |
612 | else | |
613 | slot_config = | |
614 | igp_obj-> | |
615 | ulDDISlot2Config; | |
616 | ||
617 | ct = (slot_config >> 16) & 0xff; | |
618 | connector_type = | |
619 | object_connector_convert | |
620 | [ct]; | |
621 | connector_object_id = ct; | |
622 | igp_lane_info = | |
623 | slot_config & 0xffff; | |
624 | } else | |
625 | continue; | |
771fe6b9 JG |
626 | } else |
627 | continue; | |
a084e6ee AD |
628 | } else { |
629 | igp_lane_info = 0; | |
630 | connector_type = | |
631 | object_connector_convert[con_obj_id]; | |
632 | connector_object_id = con_obj_id; | |
633 | } | |
771fe6b9 JG |
634 | } else { |
635 | igp_lane_info = 0; | |
636 | connector_type = | |
637 | object_connector_convert[con_obj_id]; | |
b75fad06 | 638 | connector_object_id = con_obj_id; |
771fe6b9 JG |
639 | } |
640 | ||
641 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) | |
642 | continue; | |
643 | ||
bdd91b2b TW |
644 | router.ddc_valid = false; |
645 | router.cd_valid = false; | |
26b5bc98 AD |
646 | for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { |
647 | uint8_t grph_obj_id, grph_obj_num, grph_obj_type; | |
771fe6b9 | 648 | |
26b5bc98 | 649 | grph_obj_id = |
771fe6b9 JG |
650 | (le16_to_cpu(path->usGraphicObjIds[j]) & |
651 | OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | |
26b5bc98 | 652 | grph_obj_num = |
771fe6b9 JG |
653 | (le16_to_cpu(path->usGraphicObjIds[j]) & |
654 | ENUM_ID_MASK) >> ENUM_ID_SHIFT; | |
26b5bc98 | 655 | grph_obj_type = |
771fe6b9 JG |
656 | (le16_to_cpu(path->usGraphicObjIds[j]) & |
657 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; | |
658 | ||
26b5bc98 | 659 | if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { |
36868bda AD |
660 | for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { |
661 | u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); | |
662 | if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { | |
663 | ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) | |
664 | (ctx->bios + data_offset + | |
665 | le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); | |
666 | ATOM_ENCODER_CAP_RECORD *cap_record; | |
667 | u16 caps = 0; | |
771fe6b9 | 668 | |
97ea530f JL |
669 | while (record->ucRecordSize > 0 && |
670 | record->ucRecordType > 0 && | |
36868bda AD |
671 | record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { |
672 | switch (record->ucRecordType) { | |
673 | case ATOM_ENCODER_CAP_RECORD_TYPE: | |
674 | cap_record =(ATOM_ENCODER_CAP_RECORD *) | |
675 | record; | |
676 | caps = le16_to_cpu(cap_record->usEncoderCap); | |
677 | break; | |
678 | } | |
679 | record = (ATOM_COMMON_RECORD_HEADER *) | |
680 | ((char *)record + record->ucRecordSize); | |
681 | } | |
682 | radeon_add_atom_encoder(dev, | |
683 | encoder_obj, | |
684 | le16_to_cpu | |
685 | (path-> | |
686 | usDeviceTag), | |
687 | caps); | |
688 | } | |
689 | } | |
26b5bc98 | 690 | } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { |
26b5bc98 | 691 | for (k = 0; k < router_obj->ucNumberOfObjects; k++) { |
bdd91b2b | 692 | u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); |
26b5bc98 AD |
693 | if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { |
694 | ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) | |
695 | (ctx->bios + data_offset + | |
696 | le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); | |
697 | ATOM_I2C_RECORD *i2c_record; | |
698 | ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; | |
699 | ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; | |
fb939dfc | 700 | ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; |
26b5bc98 AD |
701 | ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = |
702 | (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) | |
703 | (ctx->bios + data_offset + | |
704 | le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); | |
fb93df1c AD |
705 | u8 *num_dst_objs = (u8 *) |
706 | ((u8 *)router_src_dst_table + 1 + | |
707 | (router_src_dst_table->ucNumberOfSrc * 2)); | |
708 | u16 *dst_objs = (u16 *)(num_dst_objs + 1); | |
26b5bc98 AD |
709 | int enum_id; |
710 | ||
711 | router.router_id = router_obj_id; | |
fb93df1c | 712 | for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { |
26b5bc98 | 713 | if (le16_to_cpu(path->usConnObjectId) == |
fb93df1c | 714 | le16_to_cpu(dst_objs[enum_id])) |
26b5bc98 AD |
715 | break; |
716 | } | |
717 | ||
97ea530f JL |
718 | while (record->ucRecordSize > 0 && |
719 | record->ucRecordType > 0 && | |
26b5bc98 AD |
720 | record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { |
721 | switch (record->ucRecordType) { | |
722 | case ATOM_I2C_RECORD_TYPE: | |
723 | i2c_record = | |
724 | (ATOM_I2C_RECORD *) | |
725 | record; | |
726 | i2c_config = | |
727 | (ATOM_I2C_ID_CONFIG_ACCESS *) | |
728 | &i2c_record->sucI2cId; | |
729 | router.i2c_info = | |
730 | radeon_lookup_i2c_gpio(rdev, | |
731 | i2c_config-> | |
732 | ucAccess); | |
733 | router.i2c_addr = i2c_record->ucI2CAddr >> 1; | |
734 | break; | |
735 | case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: | |
736 | ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) | |
737 | record; | |
fb939dfc AD |
738 | router.ddc_valid = true; |
739 | router.ddc_mux_type = ddc_path->ucMuxType; | |
740 | router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; | |
741 | router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; | |
742 | break; | |
743 | case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: | |
744 | cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) | |
745 | record; | |
746 | router.cd_valid = true; | |
747 | router.cd_mux_type = cd_path->ucMuxType; | |
748 | router.cd_mux_control_pin = cd_path->ucMuxControlPin; | |
749 | router.cd_mux_state = cd_path->ucMuxState[enum_id]; | |
26b5bc98 AD |
750 | break; |
751 | } | |
752 | record = (ATOM_COMMON_RECORD_HEADER *) | |
753 | ((char *)record + record->ucRecordSize); | |
754 | } | |
755 | } | |
756 | } | |
771fe6b9 JG |
757 | } |
758 | } | |
759 | ||
eed45b30 | 760 | /* look up gpio for ddc, hpd */ |
2bfcc0fc AD |
761 | ddc_bus.valid = false; |
762 | hpd.hpd = RADEON_HPD_NONE; | |
771fe6b9 | 763 | if ((le16_to_cpu(path->usDeviceTag) & |
eed45b30 | 764 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { |
771fe6b9 JG |
765 | for (j = 0; j < con_obj->ucNumberOfObjects; j++) { |
766 | if (le16_to_cpu(path->usConnObjectId) == | |
767 | le16_to_cpu(con_obj->asObjects[j]. | |
768 | usObjectID)) { | |
769 | ATOM_COMMON_RECORD_HEADER | |
770 | *record = | |
771 | (ATOM_COMMON_RECORD_HEADER | |
772 | *) | |
773 | (ctx->bios + data_offset + | |
774 | le16_to_cpu(con_obj-> | |
775 | asObjects[j]. | |
776 | usRecordOffset)); | |
777 | ATOM_I2C_RECORD *i2c_record; | |
eed45b30 | 778 | ATOM_HPD_INT_RECORD *hpd_record; |
d3f420d1 | 779 | ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; |
6a93cb25 | 780 | |
97ea530f JL |
781 | while (record->ucRecordSize > 0 && |
782 | record->ucRecordType > 0 && | |
783 | record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { | |
eed45b30 | 784 | switch (record->ucRecordType) { |
771fe6b9 JG |
785 | case ATOM_I2C_RECORD_TYPE: |
786 | i2c_record = | |
eed45b30 AD |
787 | (ATOM_I2C_RECORD *) |
788 | record; | |
d3f420d1 AD |
789 | i2c_config = |
790 | (ATOM_I2C_ID_CONFIG_ACCESS *) | |
791 | &i2c_record->sucI2cId; | |
eed45b30 | 792 | ddc_bus = radeon_lookup_i2c_gpio(rdev, |
d3f420d1 AD |
793 | i2c_config-> |
794 | ucAccess); | |
eed45b30 AD |
795 | break; |
796 | case ATOM_HPD_INT_RECORD_TYPE: | |
797 | hpd_record = | |
798 | (ATOM_HPD_INT_RECORD *) | |
799 | record; | |
09e619c0 | 800 | gpio = radeon_atombios_lookup_gpio(rdev, |
eed45b30 AD |
801 | hpd_record->ucHPDIntGPIOID); |
802 | hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio); | |
803 | hpd.plugged_state = hpd_record->ucPlugged_PinState; | |
771fe6b9 JG |
804 | break; |
805 | } | |
806 | record = | |
807 | (ATOM_COMMON_RECORD_HEADER | |
808 | *) ((char *)record | |
809 | + | |
810 | record-> | |
811 | ucRecordSize); | |
812 | } | |
813 | break; | |
814 | } | |
815 | } | |
eed45b30 | 816 | } |
771fe6b9 | 817 | |
bcc1c2a1 | 818 | /* needed for aux chan transactions */ |
8e36ed00 | 819 | ddc_bus.hpd = hpd.hpd; |
bcc1c2a1 | 820 | |
705af9c7 AD |
821 | conn_id = le16_to_cpu(path->usConnObjectId); |
822 | ||
823 | if (!radeon_atom_apply_quirks | |
824 | (dev, le16_to_cpu(path->usDeviceTag), &connector_type, | |
eed45b30 | 825 | &ddc_bus, &conn_id, &hpd)) |
705af9c7 AD |
826 | continue; |
827 | ||
771fe6b9 | 828 | radeon_add_atom_connector(dev, |
705af9c7 | 829 | conn_id, |
771fe6b9 JG |
830 | le16_to_cpu(path-> |
831 | usDeviceTag), | |
832 | connector_type, &ddc_bus, | |
5137ee94 | 833 | igp_lane_info, |
eed45b30 | 834 | connector_object_id, |
26b5bc98 AD |
835 | &hpd, |
836 | &router); | |
771fe6b9 JG |
837 | |
838 | } | |
839 | } | |
840 | ||
841 | radeon_link_encoder_connector(dev); | |
842 | ||
9843ead0 | 843 | radeon_setup_mst_connector(dev); |
771fe6b9 JG |
844 | return true; |
845 | } | |
846 | ||
b75fad06 AD |
847 | static uint16_t atombios_get_connector_object_id(struct drm_device *dev, |
848 | int connector_type, | |
849 | uint16_t devices) | |
850 | { | |
851 | struct radeon_device *rdev = dev->dev_private; | |
852 | ||
853 | if (rdev->flags & RADEON_IS_IGP) { | |
854 | return supported_devices_connector_object_id_convert | |
855 | [connector_type]; | |
856 | } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || | |
857 | (connector_type == DRM_MODE_CONNECTOR_DVID)) && | |
858 | (devices & ATOM_DEVICE_DFP2_SUPPORT)) { | |
859 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
860 | struct atom_context *ctx = mode_info->atom_context; | |
861 | int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); | |
862 | uint16_t size, data_offset; | |
863 | uint8_t frev, crev; | |
864 | ATOM_XTMDS_INFO *xtmds; | |
865 | ||
a084e6ee AD |
866 | if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) { |
867 | xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset); | |
b75fad06 | 868 | |
a084e6ee AD |
869 | if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { |
870 | if (connector_type == DRM_MODE_CONNECTOR_DVII) | |
871 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; | |
872 | else | |
873 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; | |
874 | } else { | |
875 | if (connector_type == DRM_MODE_CONNECTOR_DVII) | |
876 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; | |
877 | else | |
878 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; | |
879 | } | |
880 | } else | |
881 | return supported_devices_connector_object_id_convert | |
882 | [connector_type]; | |
b75fad06 AD |
883 | } else { |
884 | return supported_devices_connector_object_id_convert | |
885 | [connector_type]; | |
886 | } | |
887 | } | |
888 | ||
771fe6b9 JG |
889 | struct bios_connector { |
890 | bool valid; | |
705af9c7 | 891 | uint16_t line_mux; |
771fe6b9 JG |
892 | uint16_t devices; |
893 | int connector_type; | |
894 | struct radeon_i2c_bus_rec ddc_bus; | |
eed45b30 | 895 | struct radeon_hpd hpd; |
771fe6b9 JG |
896 | }; |
897 | ||
898 | bool radeon_get_atom_connector_info_from_supported_devices_table(struct | |
899 | drm_device | |
900 | *dev) | |
901 | { | |
902 | struct radeon_device *rdev = dev->dev_private; | |
903 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
904 | struct atom_context *ctx = mode_info->atom_context; | |
905 | int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); | |
906 | uint16_t size, data_offset; | |
907 | uint8_t frev, crev; | |
908 | uint16_t device_support; | |
909 | uint8_t dac; | |
910 | union atom_supported_devices *supported_devices; | |
eed45b30 | 911 | int i, j, max_device; |
f49d273d PB |
912 | struct bios_connector *bios_connectors; |
913 | size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE; | |
26b5bc98 AD |
914 | struct radeon_router router; |
915 | ||
fb939dfc AD |
916 | router.ddc_valid = false; |
917 | router.cd_valid = false; | |
771fe6b9 | 918 | |
f49d273d PB |
919 | bios_connectors = kzalloc(bc_size, GFP_KERNEL); |
920 | if (!bios_connectors) | |
921 | return false; | |
922 | ||
923 | if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, | |
924 | &data_offset)) { | |
925 | kfree(bios_connectors); | |
a084e6ee | 926 | return false; |
f49d273d | 927 | } |
771fe6b9 JG |
928 | |
929 | supported_devices = | |
930 | (union atom_supported_devices *)(ctx->bios + data_offset); | |
931 | ||
932 | device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); | |
933 | ||
eed45b30 AD |
934 | if (frev > 1) |
935 | max_device = ATOM_MAX_SUPPORTED_DEVICE; | |
936 | else | |
937 | max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO; | |
938 | ||
939 | for (i = 0; i < max_device; i++) { | |
771fe6b9 JG |
940 | ATOM_CONNECTOR_INFO_I2C ci = |
941 | supported_devices->info.asConnInfo[i]; | |
942 | ||
943 | bios_connectors[i].valid = false; | |
944 | ||
945 | if (!(device_support & (1 << i))) { | |
946 | continue; | |
947 | } | |
948 | ||
949 | if (i == ATOM_DEVICE_CV_INDEX) { | |
d9fdaafb | 950 | DRM_DEBUG_KMS("Skipping Component Video\n"); |
771fe6b9 JG |
951 | continue; |
952 | } | |
953 | ||
771fe6b9 JG |
954 | bios_connectors[i].connector_type = |
955 | supported_devices_connector_convert[ci.sucConnectorInfo. | |
956 | sbfAccess. | |
957 | bfConnectorType]; | |
958 | ||
959 | if (bios_connectors[i].connector_type == | |
960 | DRM_MODE_CONNECTOR_Unknown) | |
961 | continue; | |
962 | ||
963 | dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; | |
964 | ||
d3f420d1 AD |
965 | bios_connectors[i].line_mux = |
966 | ci.sucI2cId.ucAccess; | |
771fe6b9 JG |
967 | |
968 | /* give tv unique connector ids */ | |
969 | if (i == ATOM_DEVICE_TV1_INDEX) { | |
970 | bios_connectors[i].ddc_bus.valid = false; | |
971 | bios_connectors[i].line_mux = 50; | |
972 | } else if (i == ATOM_DEVICE_TV2_INDEX) { | |
973 | bios_connectors[i].ddc_bus.valid = false; | |
974 | bios_connectors[i].line_mux = 51; | |
975 | } else if (i == ATOM_DEVICE_CV_INDEX) { | |
976 | bios_connectors[i].ddc_bus.valid = false; | |
977 | bios_connectors[i].line_mux = 52; | |
978 | } else | |
979 | bios_connectors[i].ddc_bus = | |
eed45b30 AD |
980 | radeon_lookup_i2c_gpio(rdev, |
981 | bios_connectors[i].line_mux); | |
982 | ||
983 | if ((crev > 1) && (frev > 1)) { | |
984 | u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap; | |
985 | switch (isb) { | |
986 | case 0x4: | |
987 | bios_connectors[i].hpd.hpd = RADEON_HPD_1; | |
988 | break; | |
989 | case 0xa: | |
990 | bios_connectors[i].hpd.hpd = RADEON_HPD_2; | |
991 | break; | |
992 | default: | |
993 | bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; | |
994 | break; | |
995 | } | |
996 | } else { | |
997 | if (i == ATOM_DEVICE_DFP1_INDEX) | |
998 | bios_connectors[i].hpd.hpd = RADEON_HPD_1; | |
999 | else if (i == ATOM_DEVICE_DFP2_INDEX) | |
1000 | bios_connectors[i].hpd.hpd = RADEON_HPD_2; | |
1001 | else | |
1002 | bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; | |
1003 | } | |
771fe6b9 JG |
1004 | |
1005 | /* Always set the connector type to VGA for CRT1/CRT2. if they are | |
1006 | * shared with a DVI port, we'll pick up the DVI connector when we | |
1007 | * merge the outputs. Some bioses incorrectly list VGA ports as DVI. | |
1008 | */ | |
1009 | if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) | |
1010 | bios_connectors[i].connector_type = | |
1011 | DRM_MODE_CONNECTOR_VGA; | |
1012 | ||
1013 | if (!radeon_atom_apply_quirks | |
1014 | (dev, (1 << i), &bios_connectors[i].connector_type, | |
eed45b30 AD |
1015 | &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux, |
1016 | &bios_connectors[i].hpd)) | |
771fe6b9 JG |
1017 | continue; |
1018 | ||
1019 | bios_connectors[i].valid = true; | |
1020 | bios_connectors[i].devices = (1 << i); | |
1021 | ||
1022 | if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) | |
1023 | radeon_add_atom_encoder(dev, | |
5137ee94 | 1024 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1025 | (1 << i), |
1026 | dac), | |
36868bda AD |
1027 | (1 << i), |
1028 | 0); | |
771fe6b9 JG |
1029 | else |
1030 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 1031 | radeon_get_encoder_enum(dev, |
f56cd64f | 1032 | (1 << i), |
771fe6b9 JG |
1033 | dac), |
1034 | (1 << i)); | |
1035 | } | |
1036 | ||
1037 | /* combine shared connectors */ | |
eed45b30 | 1038 | for (i = 0; i < max_device; i++) { |
771fe6b9 | 1039 | if (bios_connectors[i].valid) { |
eed45b30 | 1040 | for (j = 0; j < max_device; j++) { |
771fe6b9 JG |
1041 | if (bios_connectors[j].valid && (i != j)) { |
1042 | if (bios_connectors[i].line_mux == | |
1043 | bios_connectors[j].line_mux) { | |
f56cd64f AD |
1044 | /* make sure not to combine LVDS */ |
1045 | if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
1046 | bios_connectors[i].line_mux = 53; | |
1047 | bios_connectors[i].ddc_bus.valid = false; | |
1048 | continue; | |
1049 | } | |
1050 | if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
1051 | bios_connectors[j].line_mux = 53; | |
1052 | bios_connectors[j].ddc_bus.valid = false; | |
1053 | continue; | |
1054 | } | |
1055 | /* combine analog and digital for DVI-I */ | |
1056 | if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) && | |
1057 | (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) || | |
1058 | ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) && | |
1059 | (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) { | |
1060 | bios_connectors[i].devices |= | |
1061 | bios_connectors[j].devices; | |
1062 | bios_connectors[i].connector_type = | |
1063 | DRM_MODE_CONNECTOR_DVII; | |
1064 | if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) | |
eed45b30 AD |
1065 | bios_connectors[i].hpd = |
1066 | bios_connectors[j].hpd; | |
f56cd64f | 1067 | bios_connectors[j].valid = false; |
771fe6b9 JG |
1068 | } |
1069 | } | |
1070 | } | |
1071 | } | |
1072 | } | |
1073 | } | |
1074 | ||
1075 | /* add the connectors */ | |
eed45b30 | 1076 | for (i = 0; i < max_device; i++) { |
b75fad06 AD |
1077 | if (bios_connectors[i].valid) { |
1078 | uint16_t connector_object_id = | |
1079 | atombios_get_connector_object_id(dev, | |
1080 | bios_connectors[i].connector_type, | |
1081 | bios_connectors[i].devices); | |
771fe6b9 JG |
1082 | radeon_add_atom_connector(dev, |
1083 | bios_connectors[i].line_mux, | |
1084 | bios_connectors[i].devices, | |
1085 | bios_connectors[i]. | |
1086 | connector_type, | |
1087 | &bios_connectors[i].ddc_bus, | |
5137ee94 | 1088 | 0, |
eed45b30 | 1089 | connector_object_id, |
26b5bc98 AD |
1090 | &bios_connectors[i].hpd, |
1091 | &router); | |
b75fad06 | 1092 | } |
771fe6b9 JG |
1093 | } |
1094 | ||
1095 | radeon_link_encoder_connector(dev); | |
1096 | ||
f49d273d | 1097 | kfree(bios_connectors); |
771fe6b9 JG |
1098 | return true; |
1099 | } | |
1100 | ||
1101 | union firmware_info { | |
1102 | ATOM_FIRMWARE_INFO info; | |
1103 | ATOM_FIRMWARE_INFO_V1_2 info_12; | |
1104 | ATOM_FIRMWARE_INFO_V1_3 info_13; | |
1105 | ATOM_FIRMWARE_INFO_V1_4 info_14; | |
bcc1c2a1 | 1106 | ATOM_FIRMWARE_INFO_V2_1 info_21; |
f82b3ddc | 1107 | ATOM_FIRMWARE_INFO_V2_2 info_22; |
771fe6b9 JG |
1108 | }; |
1109 | ||
fe6fc1f1 SG |
1110 | union igp_info { |
1111 | struct _ATOM_INTEGRATED_SYSTEM_INFO info; | |
1112 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; | |
1113 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; | |
1114 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; | |
1115 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; | |
1116 | }; | |
1117 | ||
1118 | static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev) | |
1119 | { | |
1120 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1121 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); | |
1122 | union igp_info *igp_info; | |
1123 | u8 frev, crev; | |
1124 | u16 data_offset; | |
1125 | ||
1126 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, | |
1127 | &frev, &crev, &data_offset)) { | |
1128 | igp_info = (union igp_info *)(mode_info->atom_context->bios + | |
1129 | data_offset); | |
1130 | rdev->clock.vco_freq = | |
1131 | le32_to_cpu(igp_info->info_6.ulDentistVCOFreq); | |
1132 | } | |
1133 | } | |
1134 | ||
771fe6b9 JG |
1135 | bool radeon_atom_get_clock_info(struct drm_device *dev) |
1136 | { | |
1137 | struct radeon_device *rdev = dev->dev_private; | |
1138 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1139 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); | |
1140 | union firmware_info *firmware_info; | |
1141 | uint8_t frev, crev; | |
1142 | struct radeon_pll *p1pll = &rdev->clock.p1pll; | |
1143 | struct radeon_pll *p2pll = &rdev->clock.p2pll; | |
bcc1c2a1 | 1144 | struct radeon_pll *dcpll = &rdev->clock.dcpll; |
771fe6b9 JG |
1145 | struct radeon_pll *spll = &rdev->clock.spll; |
1146 | struct radeon_pll *mpll = &rdev->clock.mpll; | |
1147 | uint16_t data_offset; | |
1148 | ||
a084e6ee AD |
1149 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1150 | &frev, &crev, &data_offset)) { | |
1151 | firmware_info = | |
1152 | (union firmware_info *)(mode_info->atom_context->bios + | |
1153 | data_offset); | |
771fe6b9 JG |
1154 | /* pixel clocks */ |
1155 | p1pll->reference_freq = | |
1156 | le16_to_cpu(firmware_info->info.usReferenceClock); | |
1157 | p1pll->reference_div = 0; | |
1158 | ||
3edc38a0 | 1159 | if ((frev < 2) && (crev < 2)) |
bc293e58 MF |
1160 | p1pll->pll_out_min = |
1161 | le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); | |
1162 | else | |
1163 | p1pll->pll_out_min = | |
1164 | le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); | |
771fe6b9 JG |
1165 | p1pll->pll_out_max = |
1166 | le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); | |
1167 | ||
3edc38a0 | 1168 | if (((frev < 2) && (crev >= 4)) || (frev >= 2)) { |
86cb2bbf AD |
1169 | p1pll->lcd_pll_out_min = |
1170 | le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; | |
1171 | if (p1pll->lcd_pll_out_min == 0) | |
1172 | p1pll->lcd_pll_out_min = p1pll->pll_out_min; | |
1173 | p1pll->lcd_pll_out_max = | |
1174 | le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; | |
1175 | if (p1pll->lcd_pll_out_max == 0) | |
1176 | p1pll->lcd_pll_out_max = p1pll->pll_out_max; | |
1177 | } else { | |
1178 | p1pll->lcd_pll_out_min = p1pll->pll_out_min; | |
1179 | p1pll->lcd_pll_out_max = p1pll->pll_out_max; | |
1180 | } | |
1181 | ||
771fe6b9 JG |
1182 | if (p1pll->pll_out_min == 0) { |
1183 | if (ASIC_IS_AVIVO(rdev)) | |
1184 | p1pll->pll_out_min = 64800; | |
1185 | else | |
1186 | p1pll->pll_out_min = 20000; | |
1187 | } | |
1188 | ||
1189 | p1pll->pll_in_min = | |
1190 | le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); | |
1191 | p1pll->pll_in_max = | |
1192 | le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); | |
1193 | ||
1194 | *p2pll = *p1pll; | |
1195 | ||
1196 | /* system clock */ | |
f82b3ddc AD |
1197 | if (ASIC_IS_DCE4(rdev)) |
1198 | spll->reference_freq = | |
1199 | le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); | |
1200 | else | |
1201 | spll->reference_freq = | |
1202 | le16_to_cpu(firmware_info->info.usReferenceClock); | |
771fe6b9 JG |
1203 | spll->reference_div = 0; |
1204 | ||
1205 | spll->pll_out_min = | |
1206 | le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); | |
1207 | spll->pll_out_max = | |
1208 | le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); | |
1209 | ||
1210 | /* ??? */ | |
1211 | if (spll->pll_out_min == 0) { | |
1212 | if (ASIC_IS_AVIVO(rdev)) | |
1213 | spll->pll_out_min = 64800; | |
1214 | else | |
1215 | spll->pll_out_min = 20000; | |
1216 | } | |
1217 | ||
1218 | spll->pll_in_min = | |
1219 | le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); | |
1220 | spll->pll_in_max = | |
1221 | le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); | |
1222 | ||
1223 | /* memory clock */ | |
f82b3ddc AD |
1224 | if (ASIC_IS_DCE4(rdev)) |
1225 | mpll->reference_freq = | |
1226 | le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); | |
1227 | else | |
1228 | mpll->reference_freq = | |
1229 | le16_to_cpu(firmware_info->info.usReferenceClock); | |
771fe6b9 JG |
1230 | mpll->reference_div = 0; |
1231 | ||
1232 | mpll->pll_out_min = | |
1233 | le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); | |
1234 | mpll->pll_out_max = | |
1235 | le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); | |
1236 | ||
1237 | /* ??? */ | |
1238 | if (mpll->pll_out_min == 0) { | |
1239 | if (ASIC_IS_AVIVO(rdev)) | |
1240 | mpll->pll_out_min = 64800; | |
1241 | else | |
1242 | mpll->pll_out_min = 20000; | |
1243 | } | |
1244 | ||
1245 | mpll->pll_in_min = | |
1246 | le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); | |
1247 | mpll->pll_in_max = | |
1248 | le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); | |
1249 | ||
1250 | rdev->clock.default_sclk = | |
1251 | le32_to_cpu(firmware_info->info.ulDefaultEngineClock); | |
1252 | rdev->clock.default_mclk = | |
1253 | le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); | |
1254 | ||
bcc1c2a1 AD |
1255 | if (ASIC_IS_DCE4(rdev)) { |
1256 | rdev->clock.default_dispclk = | |
1257 | le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); | |
f82b3ddc | 1258 | if (rdev->clock.default_dispclk == 0) { |
9368931d AD |
1259 | if (ASIC_IS_DCE6(rdev)) |
1260 | rdev->clock.default_dispclk = 60000; /* 600 Mhz */ | |
1261 | else if (ASIC_IS_DCE5(rdev)) | |
f82b3ddc AD |
1262 | rdev->clock.default_dispclk = 54000; /* 540 Mhz */ |
1263 | else | |
1264 | rdev->clock.default_dispclk = 60000; /* 600 Mhz */ | |
1265 | } | |
9368931d AD |
1266 | /* set a reasonable default for DP */ |
1267 | if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) { | |
1268 | DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n", | |
1269 | rdev->clock.default_dispclk / 100); | |
1270 | rdev->clock.default_dispclk = 60000; | |
1271 | } | |
bcc1c2a1 AD |
1272 | rdev->clock.dp_extclk = |
1273 | le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); | |
4489cd62 | 1274 | rdev->clock.current_dispclk = rdev->clock.default_dispclk; |
bcc1c2a1 AD |
1275 | } |
1276 | *dcpll = *p1pll; | |
1277 | ||
b20f9bef AD |
1278 | rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); |
1279 | if (rdev->clock.max_pixel_clock == 0) | |
1280 | rdev->clock.max_pixel_clock = 40000; | |
1281 | ||
af7912e5 AD |
1282 | /* not technically a clock, but... */ |
1283 | rdev->mode_info.firmware_flags = | |
1284 | le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); | |
1285 | ||
c9a392ea SG |
1286 | if (ASIC_IS_DCE8(rdev)) |
1287 | rdev->clock.vco_freq = | |
ac4a9350 | 1288 | le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq); |
fe6fc1f1 SG |
1289 | else if (ASIC_IS_DCE5(rdev)) |
1290 | rdev->clock.vco_freq = rdev->clock.current_dispclk; | |
1291 | else if (ASIC_IS_DCE41(rdev)) | |
1292 | radeon_atombios_get_dentist_vco_freq(rdev); | |
c9a392ea SG |
1293 | else |
1294 | rdev->clock.vco_freq = rdev->clock.current_dispclk; | |
1295 | ||
1296 | if (rdev->clock.vco_freq == 0) | |
1297 | rdev->clock.vco_freq = 360000; /* 3.6 GHz */ | |
ac4a9350 | 1298 | |
771fe6b9 JG |
1299 | return true; |
1300 | } | |
bcc1c2a1 | 1301 | |
771fe6b9 JG |
1302 | return false; |
1303 | } | |
1304 | ||
06b6476d AD |
1305 | bool radeon_atombios_sideport_present(struct radeon_device *rdev) |
1306 | { | |
1307 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1308 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); | |
1309 | union igp_info *igp_info; | |
1310 | u8 frev, crev; | |
1311 | u16 data_offset; | |
1312 | ||
4c70b2ea AD |
1313 | /* sideport is AMD only */ |
1314 | if (rdev->family == CHIP_RS600) | |
1315 | return false; | |
1316 | ||
a084e6ee AD |
1317 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1318 | &frev, &crev, &data_offset)) { | |
1319 | igp_info = (union igp_info *)(mode_info->atom_context->bios + | |
06b6476d | 1320 | data_offset); |
06b6476d AD |
1321 | switch (crev) { |
1322 | case 1: | |
4589433c | 1323 | if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock)) |
4c70b2ea | 1324 | return true; |
06b6476d AD |
1325 | break; |
1326 | case 2: | |
4589433c | 1327 | if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock)) |
06b6476d AD |
1328 | return true; |
1329 | break; | |
1330 | default: | |
1331 | DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); | |
1332 | break; | |
1333 | } | |
1334 | } | |
1335 | return false; | |
1336 | } | |
1337 | ||
445282db DA |
1338 | bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
1339 | struct radeon_encoder_int_tmds *tmds) | |
771fe6b9 JG |
1340 | { |
1341 | struct drm_device *dev = encoder->base.dev; | |
1342 | struct radeon_device *rdev = dev->dev_private; | |
1343 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1344 | int index = GetIndexIntoMasterTable(DATA, TMDS_Info); | |
1345 | uint16_t data_offset; | |
1346 | struct _ATOM_TMDS_INFO *tmds_info; | |
1347 | uint8_t frev, crev; | |
1348 | uint16_t maxfreq; | |
1349 | int i; | |
771fe6b9 | 1350 | |
a084e6ee AD |
1351 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1352 | &frev, &crev, &data_offset)) { | |
1353 | tmds_info = | |
1354 | (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + | |
1355 | data_offset); | |
771fe6b9 | 1356 | |
771fe6b9 JG |
1357 | maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); |
1358 | for (i = 0; i < 4; i++) { | |
1359 | tmds->tmds_pll[i].freq = | |
1360 | le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); | |
1361 | tmds->tmds_pll[i].value = | |
1362 | tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; | |
1363 | tmds->tmds_pll[i].value |= | |
1364 | (tmds_info->asMiscInfo[i]. | |
1365 | ucPLL_VCO_Gain & 0x3f) << 6; | |
1366 | tmds->tmds_pll[i].value |= | |
1367 | (tmds_info->asMiscInfo[i]. | |
1368 | ucPLL_DutyCycle & 0xf) << 12; | |
1369 | tmds->tmds_pll[i].value |= | |
1370 | (tmds_info->asMiscInfo[i]. | |
1371 | ucPLL_VoltageSwing & 0xf) << 16; | |
1372 | ||
d9fdaafb | 1373 | DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n", |
771fe6b9 JG |
1374 | tmds->tmds_pll[i].freq, |
1375 | tmds->tmds_pll[i].value); | |
1376 | ||
1377 | if (maxfreq == tmds->tmds_pll[i].freq) { | |
1378 | tmds->tmds_pll[i].freq = 0xffffffff; | |
1379 | break; | |
1380 | } | |
1381 | } | |
445282db | 1382 | return true; |
771fe6b9 | 1383 | } |
445282db | 1384 | return false; |
771fe6b9 JG |
1385 | } |
1386 | ||
ba032a58 AD |
1387 | bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, |
1388 | struct radeon_atom_ss *ss, | |
1389 | int id) | |
ebbe1cb9 | 1390 | { |
ebbe1cb9 AD |
1391 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
1392 | int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); | |
ba032a58 | 1393 | uint16_t data_offset, size; |
ebbe1cb9 | 1394 | struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; |
a7ee824a | 1395 | struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign; |
ebbe1cb9 | 1396 | uint8_t frev, crev; |
ba032a58 | 1397 | int i, num_indices; |
ebbe1cb9 | 1398 | |
ba032a58 AD |
1399 | memset(ss, 0, sizeof(struct radeon_atom_ss)); |
1400 | if (atom_parse_data_header(mode_info->atom_context, index, &size, | |
a084e6ee AD |
1401 | &frev, &crev, &data_offset)) { |
1402 | ss_info = | |
1403 | (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset); | |
ebbe1cb9 | 1404 | |
ba032a58 AD |
1405 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
1406 | sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT); | |
a7ee824a AD |
1407 | ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*) |
1408 | ((u8 *)&ss_info->asSS_Info[0]); | |
ba032a58 | 1409 | for (i = 0; i < num_indices; i++) { |
a7ee824a | 1410 | if (ss_assign->ucSS_Id == id) { |
279b215e | 1411 | ss->percentage = |
a7ee824a AD |
1412 | le16_to_cpu(ss_assign->usSpreadSpectrumPercentage); |
1413 | ss->type = ss_assign->ucSpreadSpectrumType; | |
1414 | ss->step = ss_assign->ucSS_Step; | |
1415 | ss->delay = ss_assign->ucSS_Delay; | |
1416 | ss->range = ss_assign->ucSS_Range; | |
1417 | ss->refdiv = ss_assign->ucRecommendedRef_Div; | |
ba032a58 AD |
1418 | return true; |
1419 | } | |
a7ee824a AD |
1420 | ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*) |
1421 | ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT)); | |
ba032a58 AD |
1422 | } |
1423 | } | |
1424 | return false; | |
1425 | } | |
1426 | ||
4339c442 AD |
1427 | static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev, |
1428 | struct radeon_atom_ss *ss, | |
1429 | int id) | |
1430 | { | |
1431 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1432 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); | |
1433 | u16 data_offset, size; | |
3838f46e | 1434 | union igp_info *igp_info; |
4339c442 AD |
1435 | u8 frev, crev; |
1436 | u16 percentage = 0, rate = 0; | |
1437 | ||
1438 | /* get any igp specific overrides */ | |
1439 | if (atom_parse_data_header(mode_info->atom_context, index, &size, | |
1440 | &frev, &crev, &data_offset)) { | |
3838f46e | 1441 | igp_info = (union igp_info *) |
4339c442 | 1442 | (mode_info->atom_context->bios + data_offset); |
3838f46e AD |
1443 | switch (crev) { |
1444 | case 6: | |
1445 | switch (id) { | |
1446 | case ASIC_INTERNAL_SS_ON_TMDS: | |
1447 | percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); | |
1448 | rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); | |
1449 | break; | |
1450 | case ASIC_INTERNAL_SS_ON_HDMI: | |
1451 | percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); | |
1452 | rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); | |
1453 | break; | |
1454 | case ASIC_INTERNAL_SS_ON_LVDS: | |
1455 | percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); | |
1456 | rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); | |
1457 | break; | |
1458 | } | |
4339c442 | 1459 | break; |
3838f46e AD |
1460 | case 7: |
1461 | switch (id) { | |
1462 | case ASIC_INTERNAL_SS_ON_TMDS: | |
1463 | percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); | |
1464 | rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); | |
1465 | break; | |
1466 | case ASIC_INTERNAL_SS_ON_HDMI: | |
1467 | percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); | |
1468 | rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); | |
1469 | break; | |
1470 | case ASIC_INTERNAL_SS_ON_LVDS: | |
1471 | percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); | |
1472 | rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); | |
1473 | break; | |
1474 | } | |
4339c442 | 1475 | break; |
c2037ad1 AD |
1476 | case 8: |
1477 | switch (id) { | |
1478 | case ASIC_INTERNAL_SS_ON_TMDS: | |
1479 | percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); | |
1480 | rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); | |
1481 | break; | |
1482 | case ASIC_INTERNAL_SS_ON_HDMI: | |
1483 | percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); | |
1484 | rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); | |
1485 | break; | |
1486 | case ASIC_INTERNAL_SS_ON_LVDS: | |
1487 | percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); | |
1488 | rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); | |
1489 | break; | |
1490 | } | |
1491 | break; | |
3838f46e AD |
1492 | default: |
1493 | DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); | |
4339c442 AD |
1494 | break; |
1495 | } | |
1496 | if (percentage) | |
1497 | ss->percentage = percentage; | |
1498 | if (rate) | |
1499 | ss->rate = rate; | |
1500 | } | |
1501 | } | |
1502 | ||
ba032a58 AD |
1503 | union asic_ss_info { |
1504 | struct _ATOM_ASIC_INTERNAL_SS_INFO info; | |
1505 | struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; | |
1506 | struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; | |
1507 | }; | |
1508 | ||
a7ee824a AD |
1509 | union asic_ss_assignment { |
1510 | struct _ATOM_ASIC_SS_ASSIGNMENT v1; | |
1511 | struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2; | |
1512 | struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; | |
1513 | }; | |
1514 | ||
ba032a58 AD |
1515 | bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, |
1516 | struct radeon_atom_ss *ss, | |
1517 | int id, u32 clock) | |
1518 | { | |
1519 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1520 | int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); | |
1521 | uint16_t data_offset, size; | |
1522 | union asic_ss_info *ss_info; | |
a7ee824a | 1523 | union asic_ss_assignment *ss_assign; |
ba032a58 AD |
1524 | uint8_t frev, crev; |
1525 | int i, num_indices; | |
1526 | ||
9cb84ab0 AD |
1527 | if (id == ASIC_INTERNAL_MEMORY_SS) { |
1528 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT)) | |
1529 | return false; | |
1530 | } | |
1531 | if (id == ASIC_INTERNAL_ENGINE_SS) { | |
1532 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT)) | |
1533 | return false; | |
1534 | } | |
1535 | ||
ba032a58 AD |
1536 | memset(ss, 0, sizeof(struct radeon_atom_ss)); |
1537 | if (atom_parse_data_header(mode_info->atom_context, index, &size, | |
1538 | &frev, &crev, &data_offset)) { | |
1539 | ||
1540 | ss_info = | |
1541 | (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); | |
1542 | ||
1543 | switch (frev) { | |
1544 | case 1: | |
1545 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / | |
1546 | sizeof(ATOM_ASIC_SS_ASSIGNMENT); | |
1547 | ||
a7ee824a | 1548 | ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]); |
ba032a58 | 1549 | for (i = 0; i < num_indices; i++) { |
a7ee824a AD |
1550 | if ((ss_assign->v1.ucClockIndication == id) && |
1551 | (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) { | |
ba032a58 | 1552 | ss->percentage = |
a7ee824a AD |
1553 | le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); |
1554 | ss->type = ss_assign->v1.ucSpreadSpectrumMode; | |
1555 | ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); | |
18f8f52b | 1556 | ss->percentage_divider = 100; |
ba032a58 AD |
1557 | return true; |
1558 | } | |
a7ee824a AD |
1559 | ss_assign = (union asic_ss_assignment *) |
1560 | ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT)); | |
279b215e | 1561 | } |
ba032a58 AD |
1562 | break; |
1563 | case 2: | |
1564 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / | |
1565 | sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); | |
a7ee824a | 1566 | ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]); |
ba032a58 | 1567 | for (i = 0; i < num_indices; i++) { |
a7ee824a AD |
1568 | if ((ss_assign->v2.ucClockIndication == id) && |
1569 | (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) { | |
ba032a58 | 1570 | ss->percentage = |
a7ee824a AD |
1571 | le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); |
1572 | ss->type = ss_assign->v2.ucSpreadSpectrumMode; | |
1573 | ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); | |
18f8f52b | 1574 | ss->percentage_divider = 100; |
ae5b0abb AD |
1575 | if ((crev == 2) && |
1576 | ((id == ASIC_INTERNAL_ENGINE_SS) || | |
1577 | (id == ASIC_INTERNAL_MEMORY_SS))) | |
1578 | ss->rate /= 100; | |
ba032a58 AD |
1579 | return true; |
1580 | } | |
a7ee824a AD |
1581 | ss_assign = (union asic_ss_assignment *) |
1582 | ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2)); | |
ba032a58 AD |
1583 | } |
1584 | break; | |
1585 | case 3: | |
1586 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / | |
1587 | sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); | |
a7ee824a | 1588 | ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]); |
ba032a58 | 1589 | for (i = 0; i < num_indices; i++) { |
a7ee824a AD |
1590 | if ((ss_assign->v3.ucClockIndication == id) && |
1591 | (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { | |
ba032a58 | 1592 | ss->percentage = |
a7ee824a AD |
1593 | le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); |
1594 | ss->type = ss_assign->v3.ucSpreadSpectrumMode; | |
1595 | ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); | |
18f8f52b AD |
1596 | if (ss_assign->v3.ucSpreadSpectrumMode & |
1597 | SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK) | |
1598 | ss->percentage_divider = 1000; | |
1599 | else | |
1600 | ss->percentage_divider = 100; | |
ae5b0abb AD |
1601 | if ((id == ASIC_INTERNAL_ENGINE_SS) || |
1602 | (id == ASIC_INTERNAL_MEMORY_SS)) | |
1603 | ss->rate /= 100; | |
4339c442 AD |
1604 | if (rdev->flags & RADEON_IS_IGP) |
1605 | radeon_atombios_get_igp_ss_overrides(rdev, ss, id); | |
ba032a58 AD |
1606 | return true; |
1607 | } | |
a7ee824a AD |
1608 | ss_assign = (union asic_ss_assignment *) |
1609 | ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3)); | |
ba032a58 AD |
1610 | } |
1611 | break; | |
1612 | default: | |
1613 | DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); | |
1614 | break; | |
279b215e | 1615 | } |
ba032a58 | 1616 | |
ebbe1cb9 | 1617 | } |
ba032a58 | 1618 | return false; |
ebbe1cb9 AD |
1619 | } |
1620 | ||
771fe6b9 JG |
1621 | union lvds_info { |
1622 | struct _ATOM_LVDS_INFO info; | |
1623 | struct _ATOM_LVDS_INFO_V12 info_12; | |
1624 | }; | |
1625 | ||
1626 | struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct | |
1627 | radeon_encoder | |
1628 | *encoder) | |
1629 | { | |
1630 | struct drm_device *dev = encoder->base.dev; | |
1631 | struct radeon_device *rdev = dev->dev_private; | |
1632 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1633 | int index = GetIndexIntoMasterTable(DATA, LVDS_Info); | |
7dde8a19 | 1634 | uint16_t data_offset, misc; |
771fe6b9 JG |
1635 | union lvds_info *lvds_info; |
1636 | uint8_t frev, crev; | |
1637 | struct radeon_encoder_atom_dig *lvds = NULL; | |
5137ee94 | 1638 | int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
771fe6b9 | 1639 | |
a084e6ee AD |
1640 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1641 | &frev, &crev, &data_offset)) { | |
1642 | lvds_info = | |
1643 | (union lvds_info *)(mode_info->atom_context->bios + data_offset); | |
771fe6b9 JG |
1644 | lvds = |
1645 | kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); | |
1646 | ||
1647 | if (!lvds) | |
1648 | return NULL; | |
1649 | ||
de2103e4 | 1650 | lvds->native_mode.clock = |
771fe6b9 | 1651 | le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; |
de2103e4 | 1652 | lvds->native_mode.hdisplay = |
771fe6b9 | 1653 | le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); |
de2103e4 | 1654 | lvds->native_mode.vdisplay = |
771fe6b9 | 1655 | le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); |
de2103e4 AD |
1656 | lvds->native_mode.htotal = lvds->native_mode.hdisplay + |
1657 | le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); | |
1658 | lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + | |
1659 | le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); | |
1660 | lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + | |
1661 | le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); | |
1662 | lvds->native_mode.vtotal = lvds->native_mode.vdisplay + | |
1663 | le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); | |
1664 | lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + | |
1ff26a36 | 1665 | le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); |
de2103e4 AD |
1666 | lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + |
1667 | le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); | |
771fe6b9 JG |
1668 | lvds->panel_pwr_delay = |
1669 | le16_to_cpu(lvds_info->info.usOffDelayInMs); | |
ba032a58 | 1670 | lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; |
7dde8a19 AD |
1671 | |
1672 | misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); | |
1673 | if (misc & ATOM_VSYNC_POLARITY) | |
1674 | lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
1675 | if (misc & ATOM_HSYNC_POLARITY) | |
1676 | lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
1677 | if (misc & ATOM_COMPOSITESYNC) | |
1678 | lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; | |
1679 | if (misc & ATOM_INTERLACE) | |
1680 | lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
1681 | if (misc & ATOM_DOUBLE_CLOCK_MODE) | |
1682 | lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; | |
1683 | ||
4589433c CC |
1684 | lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); |
1685 | lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); | |
7a868e18 | 1686 | |
de2103e4 AD |
1687 | /* set crtc values */ |
1688 | drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); | |
771fe6b9 | 1689 | |
ba032a58 | 1690 | lvds->lcd_ss_id = lvds_info->info.ucSS_Id; |
ebbe1cb9 | 1691 | |
771fe6b9 | 1692 | encoder->native_mode = lvds->native_mode; |
5137ee94 AD |
1693 | |
1694 | if (encoder_enum == 2) | |
1695 | lvds->linkb = true; | |
1696 | else | |
1697 | lvds->linkb = false; | |
1698 | ||
c324acd5 | 1699 | /* parse the lcd record table */ |
4589433c | 1700 | if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) { |
c324acd5 AD |
1701 | ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; |
1702 | ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; | |
1703 | bool bad_record = false; | |
05fa7ea7 AD |
1704 | u8 *record; |
1705 | ||
1706 | if ((frev == 1) && (crev < 2)) | |
1707 | /* absolute */ | |
1708 | record = (u8 *)(mode_info->atom_context->bios + | |
1709 | le16_to_cpu(lvds_info->info.usModePatchTableOffset)); | |
1710 | else | |
1711 | /* relative */ | |
1712 | record = (u8 *)(mode_info->atom_context->bios + | |
1713 | data_offset + | |
1714 | le16_to_cpu(lvds_info->info.usModePatchTableOffset)); | |
c324acd5 AD |
1715 | while (*record != ATOM_RECORD_END_TYPE) { |
1716 | switch (*record) { | |
1717 | case LCD_MODE_PATCH_RECORD_MODE_TYPE: | |
1718 | record += sizeof(ATOM_PATCH_RECORD_MODE); | |
1719 | break; | |
1720 | case LCD_RTS_RECORD_TYPE: | |
1721 | record += sizeof(ATOM_LCD_RTS_RECORD); | |
1722 | break; | |
1723 | case LCD_CAP_RECORD_TYPE: | |
1724 | record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); | |
1725 | break; | |
1726 | case LCD_FAKE_EDID_PATCH_RECORD_TYPE: | |
1727 | fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record; | |
1728 | if (fake_edid_record->ucFakeEDIDLength) { | |
1729 | struct edid *edid; | |
1730 | int edid_size = | |
1731 | max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength); | |
1732 | edid = kmalloc(edid_size, GFP_KERNEL); | |
1733 | if (edid) { | |
1734 | memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0], | |
1735 | fake_edid_record->ucFakeEDIDLength); | |
1736 | ||
eaa4f5e1 | 1737 | if (drm_edid_is_valid(edid)) { |
c324acd5 | 1738 | rdev->mode_info.bios_hardcoded_edid = edid; |
eaa4f5e1 DA |
1739 | rdev->mode_info.bios_hardcoded_edid_size = edid_size; |
1740 | } else | |
c324acd5 AD |
1741 | kfree(edid); |
1742 | } | |
1743 | } | |
95663948 AD |
1744 | record += fake_edid_record->ucFakeEDIDLength ? |
1745 | fake_edid_record->ucFakeEDIDLength + 2 : | |
1746 | sizeof(ATOM_FAKE_EDID_PATCH_RECORD); | |
c324acd5 AD |
1747 | break; |
1748 | case LCD_PANEL_RESOLUTION_RECORD_TYPE: | |
1749 | panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record; | |
1750 | lvds->native_mode.width_mm = panel_res_record->usHSize; | |
1751 | lvds->native_mode.height_mm = panel_res_record->usVSize; | |
1752 | record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); | |
1753 | break; | |
1754 | default: | |
1755 | DRM_ERROR("Bad LCD record %d\n", *record); | |
1756 | bad_record = true; | |
1757 | break; | |
1758 | } | |
1759 | if (bad_record) | |
1760 | break; | |
1761 | } | |
1762 | } | |
771fe6b9 JG |
1763 | } |
1764 | return lvds; | |
1765 | } | |
1766 | ||
6fe7ac3f AD |
1767 | struct radeon_encoder_primary_dac * |
1768 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) | |
1769 | { | |
1770 | struct drm_device *dev = encoder->base.dev; | |
1771 | struct radeon_device *rdev = dev->dev_private; | |
1772 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1773 | int index = GetIndexIntoMasterTable(DATA, CompassionateData); | |
1774 | uint16_t data_offset; | |
1775 | struct _COMPASSIONATE_DATA *dac_info; | |
1776 | uint8_t frev, crev; | |
1777 | uint8_t bg, dac; | |
6fe7ac3f AD |
1778 | struct radeon_encoder_primary_dac *p_dac = NULL; |
1779 | ||
a084e6ee AD |
1780 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1781 | &frev, &crev, &data_offset)) { | |
1782 | dac_info = (struct _COMPASSIONATE_DATA *) | |
1783 | (mode_info->atom_context->bios + data_offset); | |
6fe7ac3f | 1784 | |
6fe7ac3f AD |
1785 | p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); |
1786 | ||
1787 | if (!p_dac) | |
1788 | return NULL; | |
1789 | ||
1790 | bg = dac_info->ucDAC1_BG_Adjustment; | |
1791 | dac = dac_info->ucDAC1_DAC_Adjustment; | |
1792 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); | |
1793 | ||
1794 | } | |
1795 | return p_dac; | |
1796 | } | |
1797 | ||
4ce001ab | 1798 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
5a9bcacc | 1799 | struct drm_display_mode *mode) |
4ce001ab DA |
1800 | { |
1801 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1802 | ATOM_ANALOG_TV_INFO *tv_info; | |
1803 | ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; | |
1804 | ATOM_DTD_FORMAT *dtd_timings; | |
1805 | int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); | |
1806 | u8 frev, crev; | |
5a9bcacc | 1807 | u16 data_offset, misc; |
4ce001ab | 1808 | |
a084e6ee AD |
1809 | if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL, |
1810 | &frev, &crev, &data_offset)) | |
1811 | return false; | |
4ce001ab DA |
1812 | |
1813 | switch (crev) { | |
1814 | case 1: | |
1815 | tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); | |
0031c41b | 1816 | if (index >= MAX_SUPPORTED_TV_TIMING) |
4ce001ab DA |
1817 | return false; |
1818 | ||
5a9bcacc AD |
1819 | mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); |
1820 | mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); | |
1821 | mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); | |
1822 | mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + | |
1823 | le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); | |
1824 | ||
1825 | mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); | |
1826 | mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); | |
1827 | mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); | |
1828 | mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + | |
1829 | le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); | |
1830 | ||
1831 | mode->flags = 0; | |
1832 | misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); | |
1833 | if (misc & ATOM_VSYNC_POLARITY) | |
1834 | mode->flags |= DRM_MODE_FLAG_NVSYNC; | |
1835 | if (misc & ATOM_HSYNC_POLARITY) | |
1836 | mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
1837 | if (misc & ATOM_COMPOSITESYNC) | |
1838 | mode->flags |= DRM_MODE_FLAG_CSYNC; | |
1839 | if (misc & ATOM_INTERLACE) | |
1840 | mode->flags |= DRM_MODE_FLAG_INTERLACE; | |
1841 | if (misc & ATOM_DOUBLE_CLOCK_MODE) | |
1842 | mode->flags |= DRM_MODE_FLAG_DBLSCAN; | |
1843 | ||
265d09aa VS |
1844 | mode->crtc_clock = mode->clock = |
1845 | le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; | |
4ce001ab DA |
1846 | |
1847 | if (index == 1) { | |
1848 | /* PAL timings appear to have wrong values for totals */ | |
5a9bcacc AD |
1849 | mode->crtc_htotal -= 1; |
1850 | mode->crtc_vtotal -= 1; | |
4ce001ab DA |
1851 | } |
1852 | break; | |
1853 | case 2: | |
1854 | tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); | |
0031c41b | 1855 | if (index >= MAX_SUPPORTED_TV_TIMING_V1_2) |
4ce001ab DA |
1856 | return false; |
1857 | ||
1858 | dtd_timings = &tv_info_v1_2->aModeTimings[index]; | |
5a9bcacc AD |
1859 | mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + |
1860 | le16_to_cpu(dtd_timings->usHBlanking_Time); | |
1861 | mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); | |
1862 | mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + | |
1863 | le16_to_cpu(dtd_timings->usHSyncOffset); | |
1864 | mode->crtc_hsync_end = mode->crtc_hsync_start + | |
1865 | le16_to_cpu(dtd_timings->usHSyncWidth); | |
1866 | ||
1867 | mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + | |
1868 | le16_to_cpu(dtd_timings->usVBlanking_Time); | |
1869 | mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); | |
1870 | mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + | |
1871 | le16_to_cpu(dtd_timings->usVSyncOffset); | |
1872 | mode->crtc_vsync_end = mode->crtc_vsync_start + | |
1873 | le16_to_cpu(dtd_timings->usVSyncWidth); | |
1874 | ||
1875 | mode->flags = 0; | |
1876 | misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); | |
1877 | if (misc & ATOM_VSYNC_POLARITY) | |
1878 | mode->flags |= DRM_MODE_FLAG_NVSYNC; | |
1879 | if (misc & ATOM_HSYNC_POLARITY) | |
1880 | mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
1881 | if (misc & ATOM_COMPOSITESYNC) | |
1882 | mode->flags |= DRM_MODE_FLAG_CSYNC; | |
1883 | if (misc & ATOM_INTERLACE) | |
1884 | mode->flags |= DRM_MODE_FLAG_INTERLACE; | |
1885 | if (misc & ATOM_DOUBLE_CLOCK_MODE) | |
1886 | mode->flags |= DRM_MODE_FLAG_DBLSCAN; | |
1887 | ||
265d09aa VS |
1888 | mode->crtc_clock = mode->clock = |
1889 | le16_to_cpu(dtd_timings->usPixClk) * 10; | |
4ce001ab DA |
1890 | break; |
1891 | } | |
1892 | return true; | |
1893 | } | |
1894 | ||
d79766fa AD |
1895 | enum radeon_tv_std |
1896 | radeon_atombios_get_tv_info(struct radeon_device *rdev) | |
1897 | { | |
1898 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1899 | int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); | |
1900 | uint16_t data_offset; | |
1901 | uint8_t frev, crev; | |
1902 | struct _ATOM_ANALOG_TV_INFO *tv_info; | |
1903 | enum radeon_tv_std tv_std = TV_STD_NTSC; | |
1904 | ||
a084e6ee AD |
1905 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1906 | &frev, &crev, &data_offset)) { | |
d79766fa | 1907 | |
a084e6ee AD |
1908 | tv_info = (struct _ATOM_ANALOG_TV_INFO *) |
1909 | (mode_info->atom_context->bios + data_offset); | |
d79766fa | 1910 | |
a084e6ee AD |
1911 | switch (tv_info->ucTV_BootUpDefaultStandard) { |
1912 | case ATOM_TV_NTSC: | |
1913 | tv_std = TV_STD_NTSC; | |
40f76d81 | 1914 | DRM_DEBUG_KMS("Default TV standard: NTSC\n"); |
a084e6ee AD |
1915 | break; |
1916 | case ATOM_TV_NTSCJ: | |
1917 | tv_std = TV_STD_NTSC_J; | |
40f76d81 | 1918 | DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); |
a084e6ee AD |
1919 | break; |
1920 | case ATOM_TV_PAL: | |
1921 | tv_std = TV_STD_PAL; | |
40f76d81 | 1922 | DRM_DEBUG_KMS("Default TV standard: PAL\n"); |
a084e6ee AD |
1923 | break; |
1924 | case ATOM_TV_PALM: | |
1925 | tv_std = TV_STD_PAL_M; | |
40f76d81 | 1926 | DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); |
a084e6ee AD |
1927 | break; |
1928 | case ATOM_TV_PALN: | |
1929 | tv_std = TV_STD_PAL_N; | |
40f76d81 | 1930 | DRM_DEBUG_KMS("Default TV standard: PAL-N\n"); |
a084e6ee AD |
1931 | break; |
1932 | case ATOM_TV_PALCN: | |
1933 | tv_std = TV_STD_PAL_CN; | |
40f76d81 | 1934 | DRM_DEBUG_KMS("Default TV standard: PAL-CN\n"); |
a084e6ee AD |
1935 | break; |
1936 | case ATOM_TV_PAL60: | |
1937 | tv_std = TV_STD_PAL_60; | |
40f76d81 | 1938 | DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); |
a084e6ee AD |
1939 | break; |
1940 | case ATOM_TV_SECAM: | |
1941 | tv_std = TV_STD_SECAM; | |
40f76d81 | 1942 | DRM_DEBUG_KMS("Default TV standard: SECAM\n"); |
a084e6ee AD |
1943 | break; |
1944 | default: | |
1945 | tv_std = TV_STD_NTSC; | |
40f76d81 | 1946 | DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n"); |
a084e6ee AD |
1947 | break; |
1948 | } | |
d79766fa AD |
1949 | } |
1950 | return tv_std; | |
1951 | } | |
1952 | ||
6fe7ac3f AD |
1953 | struct radeon_encoder_tv_dac * |
1954 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) | |
1955 | { | |
1956 | struct drm_device *dev = encoder->base.dev; | |
1957 | struct radeon_device *rdev = dev->dev_private; | |
1958 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1959 | int index = GetIndexIntoMasterTable(DATA, CompassionateData); | |
1960 | uint16_t data_offset; | |
1961 | struct _COMPASSIONATE_DATA *dac_info; | |
1962 | uint8_t frev, crev; | |
1963 | uint8_t bg, dac; | |
6fe7ac3f AD |
1964 | struct radeon_encoder_tv_dac *tv_dac = NULL; |
1965 | ||
a084e6ee AD |
1966 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1967 | &frev, &crev, &data_offset)) { | |
6fe7ac3f | 1968 | |
a084e6ee AD |
1969 | dac_info = (struct _COMPASSIONATE_DATA *) |
1970 | (mode_info->atom_context->bios + data_offset); | |
6fe7ac3f | 1971 | |
6fe7ac3f AD |
1972 | tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); |
1973 | ||
1974 | if (!tv_dac) | |
1975 | return NULL; | |
1976 | ||
1977 | bg = dac_info->ucDAC2_CRT2_BG_Adjustment; | |
1978 | dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; | |
1979 | tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); | |
1980 | ||
1981 | bg = dac_info->ucDAC2_PAL_BG_Adjustment; | |
1982 | dac = dac_info->ucDAC2_PAL_DAC_Adjustment; | |
1983 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); | |
1984 | ||
1985 | bg = dac_info->ucDAC2_NTSC_BG_Adjustment; | |
1986 | dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; | |
1987 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); | |
1988 | ||
d79766fa | 1989 | tv_dac->tv_std = radeon_atombios_get_tv_info(rdev); |
6fe7ac3f AD |
1990 | } |
1991 | return tv_dac; | |
1992 | } | |
1993 | ||
29fb52ca AD |
1994 | static const char *thermal_controller_names[] = { |
1995 | "NONE", | |
678e7dfa AD |
1996 | "lm63", |
1997 | "adm1032", | |
1998 | "adm1030", | |
1999 | "max6649", | |
5dc35532 | 2000 | "lm63", /* lm64 */ |
678e7dfa AD |
2001 | "f75375", |
2002 | "asc7xxx", | |
29fb52ca AD |
2003 | }; |
2004 | ||
2005 | static const char *pp_lib_thermal_controller_names[] = { | |
2006 | "NONE", | |
678e7dfa AD |
2007 | "lm63", |
2008 | "adm1032", | |
2009 | "adm1030", | |
2010 | "max6649", | |
5dc35532 | 2011 | "lm63", /* lm64 */ |
678e7dfa | 2012 | "f75375", |
29fb52ca AD |
2013 | "RV6xx", |
2014 | "RV770", | |
678e7dfa | 2015 | "adt7473", |
560154e9 | 2016 | "NONE", |
49f65982 AD |
2017 | "External GPIO", |
2018 | "Evergreen", | |
b0e66414 AD |
2019 | "emc2103", |
2020 | "Sumo", | |
4fddba1f | 2021 | "Northern Islands", |
14607d08 AD |
2022 | "Southern Islands", |
2023 | "lm96163", | |
51150207 | 2024 | "Sea Islands", |
29fb52ca AD |
2025 | }; |
2026 | ||
56278a8e AD |
2027 | union power_info { |
2028 | struct _ATOM_POWERPLAY_INFO info; | |
2029 | struct _ATOM_POWERPLAY_INFO_V2 info_2; | |
2030 | struct _ATOM_POWERPLAY_INFO_V3 info_3; | |
560154e9 | 2031 | struct _ATOM_PPLIB_POWERPLAYTABLE pplib; |
b0e66414 AD |
2032 | struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; |
2033 | struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; | |
56278a8e AD |
2034 | }; |
2035 | ||
560154e9 AD |
2036 | union pplib_clock_info { |
2037 | struct _ATOM_PPLIB_R600_CLOCK_INFO r600; | |
2038 | struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; | |
2039 | struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; | |
b0e66414 | 2040 | struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; |
14607d08 | 2041 | struct _ATOM_PPLIB_SI_CLOCK_INFO si; |
bc19f597 | 2042 | struct _ATOM_PPLIB_CI_CLOCK_INFO ci; |
560154e9 AD |
2043 | }; |
2044 | ||
2045 | union pplib_power_state { | |
2046 | struct _ATOM_PPLIB_STATE v1; | |
2047 | struct _ATOM_PPLIB_STATE_V2 v2; | |
2048 | }; | |
2049 | ||
2050 | static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev, | |
2051 | int state_index, | |
2052 | u32 misc, u32 misc2) | |
2053 | { | |
2054 | rdev->pm.power_state[state_index].misc = misc; | |
2055 | rdev->pm.power_state[state_index].misc2 = misc2; | |
2056 | /* order matters! */ | |
2057 | if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) | |
2058 | rdev->pm.power_state[state_index].type = | |
2059 | POWER_STATE_TYPE_POWERSAVE; | |
2060 | if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) | |
2061 | rdev->pm.power_state[state_index].type = | |
2062 | POWER_STATE_TYPE_BATTERY; | |
2063 | if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) | |
2064 | rdev->pm.power_state[state_index].type = | |
2065 | POWER_STATE_TYPE_BATTERY; | |
2066 | if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) | |
2067 | rdev->pm.power_state[state_index].type = | |
2068 | POWER_STATE_TYPE_BALANCED; | |
2069 | if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) { | |
2070 | rdev->pm.power_state[state_index].type = | |
2071 | POWER_STATE_TYPE_PERFORMANCE; | |
2072 | rdev->pm.power_state[state_index].flags &= | |
2073 | ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; | |
2074 | } | |
2075 | if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) | |
2076 | rdev->pm.power_state[state_index].type = | |
2077 | POWER_STATE_TYPE_BALANCED; | |
2078 | if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { | |
2079 | rdev->pm.power_state[state_index].type = | |
2080 | POWER_STATE_TYPE_DEFAULT; | |
2081 | rdev->pm.default_power_state_index = state_index; | |
2082 | rdev->pm.power_state[state_index].default_clock_mode = | |
2083 | &rdev->pm.power_state[state_index].clock_info[0]; | |
2084 | } else if (state_index == 0) { | |
2085 | rdev->pm.power_state[state_index].clock_info[0].flags |= | |
2086 | RADEON_PM_MODE_NO_DISPLAY; | |
2087 | } | |
2088 | } | |
2089 | ||
2090 | static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev) | |
771fe6b9 | 2091 | { |
56278a8e | 2092 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
560154e9 AD |
2093 | u32 misc, misc2 = 0; |
2094 | int num_modes = 0, i; | |
2095 | int state_index = 0; | |
2096 | struct radeon_i2c_bus_rec i2c_bus; | |
2097 | union power_info *power_info; | |
56278a8e | 2098 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); |
3cf8bb1a | 2099 | u16 data_offset; |
56278a8e | 2100 | u8 frev, crev; |
771fe6b9 | 2101 | |
560154e9 AD |
2102 | if (!atom_parse_data_header(mode_info->atom_context, index, NULL, |
2103 | &frev, &crev, &data_offset)) | |
2104 | return state_index; | |
2105 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); | |
2106 | ||
2107 | /* add the i2c bus for thermal/fan chip */ | |
4755fab5 AD |
2108 | if ((power_info->info.ucOverdriveThermalController > 0) && |
2109 | (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) { | |
560154e9 AD |
2110 | DRM_INFO("Possible %s thermal controller at 0x%02x\n", |
2111 | thermal_controller_names[power_info->info.ucOverdriveThermalController], | |
2112 | power_info->info.ucOverdriveControllerAddress >> 1); | |
2113 | i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine); | |
2114 | rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); | |
2115 | if (rdev->pm.i2c_bus) { | |
2116 | struct i2c_board_info info = { }; | |
2117 | const char *name = thermal_controller_names[power_info->info. | |
2118 | ucOverdriveThermalController]; | |
2119 | info.addr = power_info->info.ucOverdriveControllerAddress >> 1; | |
2120 | strlcpy(info.type, name, sizeof(info.type)); | |
2121 | i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); | |
2122 | } | |
2123 | } | |
2124 | num_modes = power_info->info.ucNumOfPowerModeEntries; | |
2125 | if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) | |
2126 | num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; | |
f8e6bfc2 AD |
2127 | if (num_modes == 0) |
2128 | return state_index; | |
6396bb22 KC |
2129 | rdev->pm.power_state = kcalloc(num_modes, |
2130 | sizeof(struct radeon_power_state), | |
2131 | GFP_KERNEL); | |
0975b162 AD |
2132 | if (!rdev->pm.power_state) |
2133 | return state_index; | |
560154e9 AD |
2134 | /* last mode is usually default, array is low to high */ |
2135 | for (i = 0; i < num_modes; i++) { | |
6991b8f2 | 2136 | rdev->pm.power_state[state_index].clock_info = |
6396bb22 KC |
2137 | kcalloc(1, sizeof(struct radeon_pm_clock_info), |
2138 | GFP_KERNEL); | |
6991b8f2 AD |
2139 | if (!rdev->pm.power_state[state_index].clock_info) |
2140 | return state_index; | |
2141 | rdev->pm.power_state[state_index].num_clock_modes = 1; | |
560154e9 AD |
2142 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
2143 | switch (frev) { | |
2144 | case 1: | |
560154e9 AD |
2145 | rdev->pm.power_state[state_index].clock_info[0].mclk = |
2146 | le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); | |
2147 | rdev->pm.power_state[state_index].clock_info[0].sclk = | |
2148 | le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock); | |
2149 | /* skip invalid modes */ | |
2150 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || | |
2151 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) | |
2152 | continue; | |
2153 | rdev->pm.power_state[state_index].pcie_lanes = | |
2154 | power_info->info.asPowerPlayInfo[i].ucNumPciELanes; | |
2155 | misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); | |
2156 | if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || | |
2157 | (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { | |
2158 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = | |
2159 | VOLTAGE_GPIO; | |
2160 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = | |
09e619c0 | 2161 | radeon_atombios_lookup_gpio(rdev, |
560154e9 AD |
2162 | power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex); |
2163 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) | |
2164 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
2165 | true; | |
2166 | else | |
2167 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
2168 | false; | |
2169 | } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { | |
2170 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = | |
2171 | VOLTAGE_VDDC; | |
2172 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = | |
2173 | power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; | |
29fb52ca | 2174 | } |
560154e9 AD |
2175 | rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
2176 | radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0); | |
2177 | state_index++; | |
2178 | break; | |
2179 | case 2: | |
560154e9 AD |
2180 | rdev->pm.power_state[state_index].clock_info[0].mclk = |
2181 | le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock); | |
2182 | rdev->pm.power_state[state_index].clock_info[0].sclk = | |
2183 | le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock); | |
2184 | /* skip invalid modes */ | |
2185 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || | |
2186 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) | |
2187 | continue; | |
2188 | rdev->pm.power_state[state_index].pcie_lanes = | |
2189 | power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; | |
2190 | misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); | |
2191 | misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); | |
2192 | if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || | |
2193 | (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { | |
2194 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = | |
2195 | VOLTAGE_GPIO; | |
2196 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = | |
09e619c0 | 2197 | radeon_atombios_lookup_gpio(rdev, |
560154e9 AD |
2198 | power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex); |
2199 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) | |
2200 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
2201 | true; | |
2202 | else | |
2203 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
2204 | false; | |
2205 | } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { | |
2206 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = | |
2207 | VOLTAGE_VDDC; | |
2208 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = | |
2209 | power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; | |
56278a8e | 2210 | } |
560154e9 AD |
2211 | rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
2212 | radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); | |
2213 | state_index++; | |
2214 | break; | |
2215 | case 3: | |
560154e9 AD |
2216 | rdev->pm.power_state[state_index].clock_info[0].mclk = |
2217 | le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock); | |
2218 | rdev->pm.power_state[state_index].clock_info[0].sclk = | |
2219 | le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock); | |
2220 | /* skip invalid modes */ | |
2221 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || | |
2222 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) | |
2223 | continue; | |
2224 | rdev->pm.power_state[state_index].pcie_lanes = | |
2225 | power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; | |
2226 | misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); | |
2227 | misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); | |
2228 | if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || | |
2229 | (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { | |
2230 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = | |
2231 | VOLTAGE_GPIO; | |
2232 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = | |
09e619c0 | 2233 | radeon_atombios_lookup_gpio(rdev, |
560154e9 AD |
2234 | power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex); |
2235 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) | |
2236 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
2237 | true; | |
2238 | else | |
2239 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
2240 | false; | |
2241 | } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { | |
2242 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = | |
2243 | VOLTAGE_VDDC; | |
2244 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = | |
2245 | power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex; | |
2246 | if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) { | |
2247 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled = | |
2248 | true; | |
2249 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id = | |
2250 | power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; | |
2251 | } | |
02b17cc0 | 2252 | } |
560154e9 AD |
2253 | rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
2254 | radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); | |
2255 | state_index++; | |
2256 | break; | |
2257 | } | |
2258 | } | |
2259 | /* last mode is usually default */ | |
2260 | if (rdev->pm.default_power_state_index == -1) { | |
2261 | rdev->pm.power_state[state_index - 1].type = | |
2262 | POWER_STATE_TYPE_DEFAULT; | |
2263 | rdev->pm.default_power_state_index = state_index - 1; | |
2264 | rdev->pm.power_state[state_index - 1].default_clock_mode = | |
2265 | &rdev->pm.power_state[state_index - 1].clock_info[0]; | |
2266 | rdev->pm.power_state[state_index].flags &= | |
2267 | ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; | |
2268 | rdev->pm.power_state[state_index].misc = 0; | |
2269 | rdev->pm.power_state[state_index].misc2 = 0; | |
2270 | } | |
2271 | return state_index; | |
2272 | } | |
2273 | ||
2274 | static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev, | |
2275 | ATOM_PPLIB_THERMALCONTROLLER *controller) | |
2276 | { | |
2277 | struct radeon_i2c_bus_rec i2c_bus; | |
2278 | ||
2279 | /* add the i2c bus for thermal/fan chip */ | |
2280 | if (controller->ucType > 0) { | |
9b92d1ec AD |
2281 | if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN) |
2282 | rdev->pm.no_fan = true; | |
2283 | rdev->pm.fan_pulses_per_revolution = | |
2284 | controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; | |
2285 | if (rdev->pm.fan_pulses_per_revolution) { | |
2286 | rdev->pm.fan_min_rpm = controller->ucFanMinRPM; | |
2287 | rdev->pm.fan_max_rpm = controller->ucFanMaxRPM; | |
2288 | } | |
560154e9 AD |
2289 | if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { |
2290 | DRM_INFO("Internal thermal controller %s fan control\n", | |
2291 | (controller->ucFanParameters & | |
2292 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); | |
2293 | rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; | |
2294 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { | |
2295 | DRM_INFO("Internal thermal controller %s fan control\n", | |
2296 | (controller->ucFanParameters & | |
2297 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); | |
2298 | rdev->pm.int_thermal_type = THERMAL_TYPE_RV770; | |
2299 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) { | |
2300 | DRM_INFO("Internal thermal controller %s fan control\n", | |
2301 | (controller->ucFanParameters & | |
2302 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); | |
2303 | rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; | |
b0e66414 AD |
2304 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) { |
2305 | DRM_INFO("Internal thermal controller %s fan control\n", | |
2306 | (controller->ucFanParameters & | |
2307 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); | |
2308 | rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO; | |
4fddba1f AD |
2309 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) { |
2310 | DRM_INFO("Internal thermal controller %s fan control\n", | |
2311 | (controller->ucFanParameters & | |
2312 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); | |
2313 | rdev->pm.int_thermal_type = THERMAL_TYPE_NI; | |
14607d08 AD |
2314 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) { |
2315 | DRM_INFO("Internal thermal controller %s fan control\n", | |
2316 | (controller->ucFanParameters & | |
2317 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); | |
2318 | rdev->pm.int_thermal_type = THERMAL_TYPE_SI; | |
51150207 AD |
2319 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) { |
2320 | DRM_INFO("Internal thermal controller %s fan control\n", | |
2321 | (controller->ucFanParameters & | |
2322 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); | |
2323 | rdev->pm.int_thermal_type = THERMAL_TYPE_CI; | |
16fbe00d AD |
2324 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) { |
2325 | DRM_INFO("Internal thermal controller %s fan control\n", | |
2326 | (controller->ucFanParameters & | |
2327 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); | |
2328 | rdev->pm.int_thermal_type = THERMAL_TYPE_KV; | |
ff437792 AD |
2329 | } else if (controller->ucType == |
2330 | ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) { | |
2331 | DRM_INFO("External GPIO thermal controller %s fan control\n", | |
2332 | (controller->ucFanParameters & | |
2333 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); | |
2334 | rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO; | |
2335 | } else if (controller->ucType == | |
2336 | ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) { | |
2337 | DRM_INFO("ADT7473 with internal thermal controller %s fan control\n", | |
2338 | (controller->ucFanParameters & | |
2339 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); | |
2340 | rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL; | |
2341 | } else if (controller->ucType == | |
2342 | ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) { | |
2343 | DRM_INFO("EMC2103 with internal thermal controller %s fan control\n", | |
2344 | (controller->ucFanParameters & | |
2345 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); | |
2346 | rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL; | |
4755fab5 | 2347 | } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) { |
560154e9 AD |
2348 | DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n", |
2349 | pp_lib_thermal_controller_names[controller->ucType], | |
2350 | controller->ucI2cAddress >> 1, | |
2351 | (controller->ucFanParameters & | |
2352 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); | |
ff437792 | 2353 | rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL; |
560154e9 AD |
2354 | i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine); |
2355 | rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); | |
2356 | if (rdev->pm.i2c_bus) { | |
2357 | struct i2c_board_info info = { }; | |
2358 | const char *name = pp_lib_thermal_controller_names[controller->ucType]; | |
2359 | info.addr = controller->ucI2cAddress >> 1; | |
2360 | strlcpy(info.type, name, sizeof(info.type)); | |
2361 | i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); | |
c5e8ce61 | 2362 | } |
4755fab5 AD |
2363 | } else { |
2364 | DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n", | |
2365 | controller->ucType, | |
2366 | controller->ucI2cAddress >> 1, | |
2367 | (controller->ucFanParameters & | |
2368 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); | |
560154e9 AD |
2369 | } |
2370 | } | |
2371 | } | |
c5e8ce61 | 2372 | |
4a6369e9 | 2373 | void radeon_atombios_get_default_voltages(struct radeon_device *rdev, |
2abba66e | 2374 | u16 *vddc, u16 *vddci, u16 *mvdd) |
560154e9 AD |
2375 | { |
2376 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
2377 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); | |
2378 | u8 frev, crev; | |
2379 | u16 data_offset; | |
2380 | union firmware_info *firmware_info; | |
2feea49a AD |
2381 | |
2382 | *vddc = 0; | |
2383 | *vddci = 0; | |
2abba66e | 2384 | *mvdd = 0; |
678e7dfa | 2385 | |
560154e9 AD |
2386 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
2387 | &frev, &crev, &data_offset)) { | |
2388 | firmware_info = | |
2389 | (union firmware_info *)(mode_info->atom_context->bios + | |
2390 | data_offset); | |
2feea49a | 2391 | *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); |
2abba66e | 2392 | if ((frev == 2) && (crev >= 2)) { |
2feea49a | 2393 | *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); |
2abba66e AD |
2394 | *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage); |
2395 | } | |
560154e9 | 2396 | } |
560154e9 AD |
2397 | } |
2398 | ||
2399 | static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev, | |
2400 | int state_index, int mode_index, | |
2401 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info) | |
2402 | { | |
2403 | int j; | |
2404 | u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); | |
2405 | u32 misc2 = le16_to_cpu(non_clock_info->usClassification); | |
2abba66e | 2406 | u16 vddc, vddci, mvdd; |
2feea49a | 2407 | |
2abba66e | 2408 | radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); |
560154e9 AD |
2409 | |
2410 | rdev->pm.power_state[state_index].misc = misc; | |
2411 | rdev->pm.power_state[state_index].misc2 = misc2; | |
2412 | rdev->pm.power_state[state_index].pcie_lanes = | |
2413 | ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> | |
2414 | ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; | |
2415 | switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { | |
2416 | case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: | |
2417 | rdev->pm.power_state[state_index].type = | |
2418 | POWER_STATE_TYPE_BATTERY; | |
2419 | break; | |
2420 | case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: | |
2421 | rdev->pm.power_state[state_index].type = | |
2422 | POWER_STATE_TYPE_BALANCED; | |
2423 | break; | |
2424 | case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: | |
2425 | rdev->pm.power_state[state_index].type = | |
2426 | POWER_STATE_TYPE_PERFORMANCE; | |
2427 | break; | |
2428 | case ATOM_PPLIB_CLASSIFICATION_UI_NONE: | |
2429 | if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) | |
2430 | rdev->pm.power_state[state_index].type = | |
2431 | POWER_STATE_TYPE_PERFORMANCE; | |
2432 | break; | |
2433 | } | |
2434 | rdev->pm.power_state[state_index].flags = 0; | |
2435 | if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) | |
2436 | rdev->pm.power_state[state_index].flags |= | |
2437 | RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; | |
2438 | if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { | |
2439 | rdev->pm.power_state[state_index].type = | |
2440 | POWER_STATE_TYPE_DEFAULT; | |
2441 | rdev->pm.default_power_state_index = state_index; | |
2442 | rdev->pm.power_state[state_index].default_clock_mode = | |
2443 | &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; | |
982cb329 | 2444 | if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) { |
9ace9f7b AD |
2445 | /* NI chips post without MC ucode, so default clocks are strobe mode only */ |
2446 | rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; | |
2447 | rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; | |
2448 | rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage; | |
2feea49a | 2449 | rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci; |
9ace9f7b | 2450 | } else { |
ae5b0abb AD |
2451 | u16 max_vddci = 0; |
2452 | ||
2453 | if (ASIC_IS_DCE4(rdev)) | |
2454 | radeon_atom_get_max_voltage(rdev, | |
2455 | SET_VOLTAGE_TYPE_ASIC_VDDCI, | |
2456 | &max_vddci); | |
2457 | /* patch the table values with the default sclk/mclk from firmware info */ | |
9ace9f7b AD |
2458 | for (j = 0; j < mode_index; j++) { |
2459 | rdev->pm.power_state[state_index].clock_info[j].mclk = | |
2460 | rdev->clock.default_mclk; | |
2461 | rdev->pm.power_state[state_index].clock_info[j].sclk = | |
2462 | rdev->clock.default_sclk; | |
2463 | if (vddc) | |
2464 | rdev->pm.power_state[state_index].clock_info[j].voltage.voltage = | |
2465 | vddc; | |
ae5b0abb AD |
2466 | if (max_vddci) |
2467 | rdev->pm.power_state[state_index].clock_info[j].voltage.vddci = | |
2468 | max_vddci; | |
9ace9f7b | 2469 | } |
560154e9 AD |
2470 | } |
2471 | } | |
2472 | } | |
2473 | ||
2474 | static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, | |
2475 | int state_index, int mode_index, | |
2476 | union pplib_clock_info *clock_info) | |
2477 | { | |
2478 | u32 sclk, mclk; | |
e83753bb | 2479 | u16 vddc; |
560154e9 AD |
2480 | |
2481 | if (rdev->flags & RADEON_IS_IGP) { | |
b0e66414 AD |
2482 | if (rdev->family >= CHIP_PALM) { |
2483 | sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); | |
2484 | sclk |= clock_info->sumo.ucEngineClockHigh << 16; | |
2485 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; | |
2486 | } else { | |
2487 | sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); | |
2488 | sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; | |
2489 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; | |
2490 | } | |
bc19f597 AD |
2491 | } else if (rdev->family >= CHIP_BONAIRE) { |
2492 | sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); | |
2493 | sclk |= clock_info->ci.ucEngineClockHigh << 16; | |
2494 | mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); | |
2495 | mclk |= clock_info->ci.ucMemoryClockHigh << 16; | |
2496 | rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; | |
2497 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; | |
2498 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = | |
2499 | VOLTAGE_NONE; | |
982cb329 | 2500 | } else if (rdev->family >= CHIP_TAHITI) { |
14607d08 AD |
2501 | sclk = le16_to_cpu(clock_info->si.usEngineClockLow); |
2502 | sclk |= clock_info->si.ucEngineClockHigh << 16; | |
2503 | mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); | |
2504 | mclk |= clock_info->si.ucMemoryClockHigh << 16; | |
2505 | rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; | |
2506 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; | |
2507 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = | |
2508 | VOLTAGE_SW; | |
2509 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = | |
2510 | le16_to_cpu(clock_info->si.usVDDC); | |
2511 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = | |
2512 | le16_to_cpu(clock_info->si.usVDDCI); | |
982cb329 | 2513 | } else if (rdev->family >= CHIP_CEDAR) { |
560154e9 AD |
2514 | sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); |
2515 | sclk |= clock_info->evergreen.ucEngineClockHigh << 16; | |
2516 | mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); | |
2517 | mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; | |
2518 | rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; | |
2519 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; | |
2520 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = | |
2521 | VOLTAGE_SW; | |
2522 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = | |
4589433c | 2523 | le16_to_cpu(clock_info->evergreen.usVDDC); |
2feea49a AD |
2524 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = |
2525 | le16_to_cpu(clock_info->evergreen.usVDDCI); | |
560154e9 AD |
2526 | } else { |
2527 | sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); | |
2528 | sclk |= clock_info->r600.ucEngineClockHigh << 16; | |
2529 | mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow); | |
2530 | mclk |= clock_info->r600.ucMemoryClockHigh << 16; | |
2531 | rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; | |
2532 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; | |
2533 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = | |
2534 | VOLTAGE_SW; | |
2535 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = | |
4589433c | 2536 | le16_to_cpu(clock_info->r600.usVDDC); |
560154e9 AD |
2537 | } |
2538 | ||
ee4017f4 | 2539 | /* patch up vddc if necessary */ |
e83753bb AD |
2540 | switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) { |
2541 | case ATOM_VIRTUAL_VOLTAGE_ID0: | |
2542 | case ATOM_VIRTUAL_VOLTAGE_ID1: | |
2543 | case ATOM_VIRTUAL_VOLTAGE_ID2: | |
2544 | case ATOM_VIRTUAL_VOLTAGE_ID3: | |
c6cf7777 AD |
2545 | case ATOM_VIRTUAL_VOLTAGE_ID4: |
2546 | case ATOM_VIRTUAL_VOLTAGE_ID5: | |
2547 | case ATOM_VIRTUAL_VOLTAGE_ID6: | |
2548 | case ATOM_VIRTUAL_VOLTAGE_ID7: | |
e83753bb AD |
2549 | if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, |
2550 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage, | |
2551 | &vddc) == 0) | |
ee4017f4 | 2552 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc; |
e83753bb AD |
2553 | break; |
2554 | default: | |
2555 | break; | |
ee4017f4 AD |
2556 | } |
2557 | ||
560154e9 AD |
2558 | if (rdev->flags & RADEON_IS_IGP) { |
2559 | /* skip invalid modes */ | |
2560 | if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) | |
2561 | return false; | |
2562 | } else { | |
2563 | /* skip invalid modes */ | |
2564 | if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || | |
2565 | (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) | |
2566 | return false; | |
2567 | } | |
2568 | return true; | |
2569 | } | |
2570 | ||
2571 | static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev) | |
2572 | { | |
2573 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
2574 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; | |
2575 | union pplib_power_state *power_state; | |
2576 | int i, j; | |
2577 | int state_index = 0, mode_index = 0; | |
2578 | union pplib_clock_info *clock_info; | |
2579 | bool valid; | |
2580 | union power_info *power_info; | |
2581 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); | |
3cf8bb1a | 2582 | u16 data_offset; |
560154e9 AD |
2583 | u8 frev, crev; |
2584 | ||
2585 | if (!atom_parse_data_header(mode_info->atom_context, index, NULL, | |
2586 | &frev, &crev, &data_offset)) | |
2587 | return state_index; | |
2588 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); | |
2589 | ||
2590 | radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); | |
f8e6bfc2 AD |
2591 | if (power_info->pplib.ucNumStates == 0) |
2592 | return state_index; | |
6396bb22 KC |
2593 | rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates, |
2594 | sizeof(struct radeon_power_state), | |
2595 | GFP_KERNEL); | |
0975b162 AD |
2596 | if (!rdev->pm.power_state) |
2597 | return state_index; | |
560154e9 AD |
2598 | /* first mode is usually default, followed by low to high */ |
2599 | for (i = 0; i < power_info->pplib.ucNumStates; i++) { | |
2600 | mode_index = 0; | |
2601 | power_state = (union pplib_power_state *) | |
2602 | (mode_info->atom_context->bios + data_offset + | |
2603 | le16_to_cpu(power_info->pplib.usStateArrayOffset) + | |
2604 | i * power_info->pplib.ucStateEntrySize); | |
2605 | non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) | |
2606 | (mode_info->atom_context->bios + data_offset + | |
2607 | le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + | |
2608 | (power_state->v1.ucNonClockStateIndex * | |
2609 | power_info->pplib.ucNonClockSize)); | |
6396bb22 KC |
2610 | rdev->pm.power_state[i].clock_info = |
2611 | kcalloc((power_info->pplib.ucStateEntrySize - 1) ? | |
2612 | (power_info->pplib.ucStateEntrySize - 1) : 1, | |
2613 | sizeof(struct radeon_pm_clock_info), | |
2614 | GFP_KERNEL); | |
8f3f1c9a AD |
2615 | if (!rdev->pm.power_state[i].clock_info) |
2616 | return state_index; | |
2617 | if (power_info->pplib.ucStateEntrySize - 1) { | |
2618 | for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) { | |
2619 | clock_info = (union pplib_clock_info *) | |
2620 | (mode_info->atom_context->bios + data_offset + | |
2621 | le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + | |
2622 | (power_state->v1.ucClockStateIndices[j] * | |
2623 | power_info->pplib.ucClockInfoSize)); | |
2624 | valid = radeon_atombios_parse_pplib_clock_info(rdev, | |
2625 | state_index, mode_index, | |
2626 | clock_info); | |
2627 | if (valid) | |
2628 | mode_index++; | |
2629 | } | |
2630 | } else { | |
2631 | rdev->pm.power_state[state_index].clock_info[0].mclk = | |
2632 | rdev->clock.default_mclk; | |
2633 | rdev->pm.power_state[state_index].clock_info[0].sclk = | |
2634 | rdev->clock.default_sclk; | |
2635 | mode_index++; | |
560154e9 AD |
2636 | } |
2637 | rdev->pm.power_state[state_index].num_clock_modes = mode_index; | |
2638 | if (mode_index) { | |
2639 | radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, | |
2640 | non_clock_info); | |
2641 | state_index++; | |
2642 | } | |
2643 | } | |
2644 | /* if multiple clock modes, mark the lowest as no display */ | |
2645 | for (i = 0; i < state_index; i++) { | |
2646 | if (rdev->pm.power_state[i].num_clock_modes > 1) | |
2647 | rdev->pm.power_state[i].clock_info[0].flags |= | |
2648 | RADEON_PM_MODE_NO_DISPLAY; | |
2649 | } | |
2650 | /* first mode is usually default */ | |
2651 | if (rdev->pm.default_power_state_index == -1) { | |
2652 | rdev->pm.power_state[0].type = | |
2653 | POWER_STATE_TYPE_DEFAULT; | |
2654 | rdev->pm.default_power_state_index = 0; | |
2655 | rdev->pm.power_state[0].default_clock_mode = | |
2656 | &rdev->pm.power_state[0].clock_info[0]; | |
2657 | } | |
2658 | return state_index; | |
2659 | } | |
2660 | ||
b0e66414 AD |
2661 | static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) |
2662 | { | |
2663 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
2664 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; | |
2665 | union pplib_power_state *power_state; | |
2666 | int i, j, non_clock_array_index, clock_array_index; | |
2667 | int state_index = 0, mode_index = 0; | |
2668 | union pplib_clock_info *clock_info; | |
f7346881 AD |
2669 | struct _StateArray *state_array; |
2670 | struct _ClockInfoArray *clock_info_array; | |
2671 | struct _NonClockInfoArray *non_clock_info_array; | |
b0e66414 AD |
2672 | bool valid; |
2673 | union power_info *power_info; | |
2674 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); | |
3cf8bb1a | 2675 | u16 data_offset; |
b0e66414 | 2676 | u8 frev, crev; |
441e76ca | 2677 | u8 *power_state_offset; |
b0e66414 AD |
2678 | |
2679 | if (!atom_parse_data_header(mode_info->atom_context, index, NULL, | |
2680 | &frev, &crev, &data_offset)) | |
2681 | return state_index; | |
2682 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); | |
2683 | ||
2684 | radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); | |
f7346881 | 2685 | state_array = (struct _StateArray *) |
b0e66414 | 2686 | (mode_info->atom_context->bios + data_offset + |
4589433c | 2687 | le16_to_cpu(power_info->pplib.usStateArrayOffset)); |
f7346881 | 2688 | clock_info_array = (struct _ClockInfoArray *) |
b0e66414 | 2689 | (mode_info->atom_context->bios + data_offset + |
4589433c | 2690 | le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); |
f7346881 | 2691 | non_clock_info_array = (struct _NonClockInfoArray *) |
b0e66414 | 2692 | (mode_info->atom_context->bios + data_offset + |
4589433c | 2693 | le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); |
f8e6bfc2 AD |
2694 | if (state_array->ucNumEntries == 0) |
2695 | return state_index; | |
6396bb22 KC |
2696 | rdev->pm.power_state = kcalloc(state_array->ucNumEntries, |
2697 | sizeof(struct radeon_power_state), | |
2698 | GFP_KERNEL); | |
0975b162 AD |
2699 | if (!rdev->pm.power_state) |
2700 | return state_index; | |
441e76ca | 2701 | power_state_offset = (u8 *)state_array->states; |
b0e66414 AD |
2702 | for (i = 0; i < state_array->ucNumEntries; i++) { |
2703 | mode_index = 0; | |
441e76ca AD |
2704 | power_state = (union pplib_power_state *)power_state_offset; |
2705 | non_clock_array_index = power_state->v2.nonClockInfoIndex; | |
b0e66414 AD |
2706 | non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) |
2707 | &non_clock_info_array->nonClockInfo[non_clock_array_index]; | |
6396bb22 KC |
2708 | rdev->pm.power_state[i].clock_info = |
2709 | kcalloc(power_state->v2.ucNumDPMLevels ? | |
2710 | power_state->v2.ucNumDPMLevels : 1, | |
2711 | sizeof(struct radeon_pm_clock_info), | |
2712 | GFP_KERNEL); | |
8f3f1c9a AD |
2713 | if (!rdev->pm.power_state[i].clock_info) |
2714 | return state_index; | |
2715 | if (power_state->v2.ucNumDPMLevels) { | |
2716 | for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { | |
2717 | clock_array_index = power_state->v2.clockInfoIndex[j]; | |
8f3f1c9a | 2718 | clock_info = (union pplib_clock_info *) |
f7346881 | 2719 | &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; |
8f3f1c9a AD |
2720 | valid = radeon_atombios_parse_pplib_clock_info(rdev, |
2721 | state_index, mode_index, | |
2722 | clock_info); | |
2723 | if (valid) | |
2724 | mode_index++; | |
2725 | } | |
2726 | } else { | |
2727 | rdev->pm.power_state[state_index].clock_info[0].mclk = | |
2728 | rdev->clock.default_mclk; | |
2729 | rdev->pm.power_state[state_index].clock_info[0].sclk = | |
2730 | rdev->clock.default_sclk; | |
2731 | mode_index++; | |
b0e66414 AD |
2732 | } |
2733 | rdev->pm.power_state[state_index].num_clock_modes = mode_index; | |
2734 | if (mode_index) { | |
2735 | radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, | |
2736 | non_clock_info); | |
2737 | state_index++; | |
2738 | } | |
441e76ca | 2739 | power_state_offset += 2 + power_state->v2.ucNumDPMLevels; |
b0e66414 AD |
2740 | } |
2741 | /* if multiple clock modes, mark the lowest as no display */ | |
2742 | for (i = 0; i < state_index; i++) { | |
2743 | if (rdev->pm.power_state[i].num_clock_modes > 1) | |
2744 | rdev->pm.power_state[i].clock_info[0].flags |= | |
2745 | RADEON_PM_MODE_NO_DISPLAY; | |
2746 | } | |
2747 | /* first mode is usually default */ | |
2748 | if (rdev->pm.default_power_state_index == -1) { | |
2749 | rdev->pm.power_state[0].type = | |
2750 | POWER_STATE_TYPE_DEFAULT; | |
2751 | rdev->pm.default_power_state_index = 0; | |
2752 | rdev->pm.power_state[0].default_clock_mode = | |
2753 | &rdev->pm.power_state[0].clock_info[0]; | |
2754 | } | |
2755 | return state_index; | |
2756 | } | |
2757 | ||
560154e9 AD |
2758 | void radeon_atombios_get_power_modes(struct radeon_device *rdev) |
2759 | { | |
2760 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
2761 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); | |
2762 | u16 data_offset; | |
2763 | u8 frev, crev; | |
2764 | int state_index = 0; | |
2765 | ||
2766 | rdev->pm.default_power_state_index = -1; | |
2767 | ||
2768 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, | |
2769 | &frev, &crev, &data_offset)) { | |
2770 | switch (frev) { | |
2771 | case 1: | |
2772 | case 2: | |
2773 | case 3: | |
2774 | state_index = radeon_atombios_parse_power_table_1_3(rdev); | |
2775 | break; | |
2776 | case 4: | |
2777 | case 5: | |
2778 | state_index = radeon_atombios_parse_power_table_4_5(rdev); | |
2779 | break; | |
b0e66414 AD |
2780 | case 6: |
2781 | state_index = radeon_atombios_parse_power_table_6(rdev); | |
2782 | break; | |
560154e9 AD |
2783 | default: |
2784 | break; | |
56278a8e | 2785 | } |
f8e6bfc2 AD |
2786 | } |
2787 | ||
2788 | if (state_index == 0) { | |
0975b162 AD |
2789 | rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL); |
2790 | if (rdev->pm.power_state) { | |
8f3f1c9a | 2791 | rdev->pm.power_state[0].clock_info = |
6396bb22 KC |
2792 | kcalloc(1, |
2793 | sizeof(struct radeon_pm_clock_info), | |
2794 | GFP_KERNEL); | |
8f3f1c9a AD |
2795 | if (rdev->pm.power_state[0].clock_info) { |
2796 | /* add the default mode */ | |
2797 | rdev->pm.power_state[state_index].type = | |
2798 | POWER_STATE_TYPE_DEFAULT; | |
2799 | rdev->pm.power_state[state_index].num_clock_modes = 1; | |
2800 | rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; | |
2801 | rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; | |
2802 | rdev->pm.power_state[state_index].default_clock_mode = | |
2803 | &rdev->pm.power_state[state_index].clock_info[0]; | |
2804 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; | |
2805 | rdev->pm.power_state[state_index].pcie_lanes = 16; | |
2806 | rdev->pm.default_power_state_index = state_index; | |
2807 | rdev->pm.power_state[state_index].flags = 0; | |
2808 | state_index++; | |
2809 | } | |
0975b162 | 2810 | } |
56278a8e | 2811 | } |
02b17cc0 | 2812 | |
56278a8e | 2813 | rdev->pm.num_power_states = state_index; |
9038dfdf | 2814 | |
a48b9b4e AD |
2815 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
2816 | rdev->pm.current_clock_mode_index = 0; | |
4376eee9 AM |
2817 | if (rdev->pm.default_power_state_index >= 0) |
2818 | rdev->pm.current_vddc = | |
2819 | rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; | |
2820 | else | |
2821 | rdev->pm.current_vddc = 0; | |
771fe6b9 JG |
2822 | } |
2823 | ||
7062ab67 CK |
2824 | union get_clock_dividers { |
2825 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; | |
2826 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; | |
2827 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; | |
2828 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; | |
2829 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; | |
9219ed65 AD |
2830 | struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; |
2831 | struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; | |
7062ab67 CK |
2832 | }; |
2833 | ||
2834 | int radeon_atom_get_clock_dividers(struct radeon_device *rdev, | |
2835 | u8 clock_type, | |
2836 | u32 clock, | |
2837 | bool strobe_mode, | |
2838 | struct atom_clock_dividers *dividers) | |
2839 | { | |
2840 | union get_clock_dividers args; | |
2841 | int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); | |
2842 | u8 frev, crev; | |
2843 | ||
2844 | memset(&args, 0, sizeof(args)); | |
2845 | memset(dividers, 0, sizeof(struct atom_clock_dividers)); | |
2846 | ||
2847 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
2848 | return -EINVAL; | |
2849 | ||
2850 | switch (crev) { | |
2851 | case 1: | |
2852 | /* r4xx, r5xx */ | |
2853 | args.v1.ucAction = clock_type; | |
2854 | args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */ | |
2855 | ||
2856 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
2857 | ||
2858 | dividers->post_div = args.v1.ucPostDiv; | |
2859 | dividers->fb_div = args.v1.ucFbDiv; | |
2860 | dividers->enable_post_div = true; | |
2861 | break; | |
2862 | case 2: | |
2863 | case 3: | |
360b1f5e AD |
2864 | case 5: |
2865 | /* r6xx, r7xx, evergreen, ni, si */ | |
7062ab67 CK |
2866 | if (rdev->family <= CHIP_RV770) { |
2867 | args.v2.ucAction = clock_type; | |
2868 | args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */ | |
2869 | ||
2870 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
2871 | ||
2872 | dividers->post_div = args.v2.ucPostDiv; | |
2873 | dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); | |
2874 | dividers->ref_div = args.v2.ucAction; | |
2875 | if (rdev->family == CHIP_RV770) { | |
2876 | dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? | |
2877 | true : false; | |
2878 | dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; | |
2879 | } else | |
2880 | dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; | |
2881 | } else { | |
2882 | if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { | |
f4a2596c | 2883 | args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); |
7062ab67 CK |
2884 | |
2885 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
2886 | ||
2887 | dividers->post_div = args.v3.ucPostDiv; | |
2888 | dividers->enable_post_div = (args.v3.ucCntlFlag & | |
2889 | ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; | |
2890 | dividers->enable_dithen = (args.v3.ucCntlFlag & | |
2891 | ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; | |
20fab641 | 2892 | dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); |
7062ab67 CK |
2893 | dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); |
2894 | dividers->ref_div = args.v3.ucRefDiv; | |
2895 | dividers->vco_mode = (args.v3.ucCntlFlag & | |
2896 | ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; | |
2897 | } else { | |
360b1f5e AD |
2898 | /* for SI we use ComputeMemoryClockParam for memory plls */ |
2899 | if (rdev->family >= CHIP_TAHITI) | |
2900 | return -EINVAL; | |
f4a2596c | 2901 | args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); |
7062ab67 CK |
2902 | if (strobe_mode) |
2903 | args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; | |
2904 | ||
2905 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
2906 | ||
2907 | dividers->post_div = args.v5.ucPostDiv; | |
2908 | dividers->enable_post_div = (args.v5.ucCntlFlag & | |
2909 | ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; | |
2910 | dividers->enable_dithen = (args.v5.ucCntlFlag & | |
2911 | ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; | |
2912 | dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); | |
2913 | dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); | |
2914 | dividers->ref_div = args.v5.ucRefDiv; | |
2915 | dividers->vco_mode = (args.v5.ucCntlFlag & | |
2916 | ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; | |
2917 | } | |
2918 | } | |
2919 | break; | |
2920 | case 4: | |
2921 | /* fusion */ | |
2922 | args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ | |
2923 | ||
2924 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
2925 | ||
9219ed65 | 2926 | dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; |
7062ab67 CK |
2927 | dividers->real_clock = le32_to_cpu(args.v4.ulClock); |
2928 | break; | |
9219ed65 AD |
2929 | case 6: |
2930 | /* CI */ | |
2931 | /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ | |
2932 | args.v6_in.ulClock.ulComputeClockFlag = clock_type; | |
2933 | args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ | |
2934 | ||
2935 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
2936 | ||
2937 | dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); | |
2938 | dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); | |
2939 | dividers->ref_div = args.v6_out.ucPllRefDiv; | |
2940 | dividers->post_div = args.v6_out.ucPllPostDiv; | |
2941 | dividers->flags = args.v6_out.ucPllCntlFlag; | |
2942 | dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); | |
2943 | dividers->post_divider = args.v6_out.ulClock.ucPostDiv; | |
2944 | break; | |
7062ab67 CK |
2945 | default: |
2946 | return -EINVAL; | |
2947 | } | |
2948 | return 0; | |
2949 | } | |
2950 | ||
eaa778af AD |
2951 | int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, |
2952 | u32 clock, | |
2953 | bool strobe_mode, | |
2954 | struct atom_mpll_param *mpll_param) | |
2955 | { | |
2956 | COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; | |
2957 | int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); | |
2958 | u8 frev, crev; | |
2959 | ||
2960 | memset(&args, 0, sizeof(args)); | |
2961 | memset(mpll_param, 0, sizeof(struct atom_mpll_param)); | |
2962 | ||
2963 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
2964 | return -EINVAL; | |
2965 | ||
2966 | switch (frev) { | |
2967 | case 2: | |
2968 | switch (crev) { | |
2969 | case 1: | |
2970 | /* SI */ | |
2971 | args.ulClock = cpu_to_le32(clock); /* 10 khz */ | |
2972 | args.ucInputFlag = 0; | |
2973 | if (strobe_mode) | |
2974 | args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; | |
2975 | ||
2976 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
2977 | ||
2978 | mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); | |
2979 | mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); | |
2980 | mpll_param->post_div = args.ucPostDiv; | |
2981 | mpll_param->dll_speed = args.ucDllSpeed; | |
2982 | mpll_param->bwcntl = args.ucBWCntl; | |
2983 | mpll_param->vco_mode = | |
180f805f | 2984 | (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK); |
eaa778af AD |
2985 | mpll_param->yclk_sel = |
2986 | (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; | |
2987 | mpll_param->qdr = | |
2988 | (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; | |
2989 | mpll_param->half_rate = | |
2990 | (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; | |
2991 | break; | |
2992 | default: | |
2993 | return -EINVAL; | |
2994 | } | |
2995 | break; | |
2996 | default: | |
2997 | return -EINVAL; | |
2998 | } | |
2999 | return 0; | |
3000 | } | |
3001 | ||
771fe6b9 | 3002 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) |
771fe6b9 | 3003 | { |
771fe6b9 JG |
3004 | DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; |
3005 | int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); | |
771fe6b9 JG |
3006 | |
3007 | args.ucEnable = enable; | |
3008 | ||
3009 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
3010 | } | |
3011 | ||
7433874e RM |
3012 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) |
3013 | { | |
3014 | GET_ENGINE_CLOCK_PS_ALLOCATION args; | |
3015 | int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); | |
3016 | ||
3017 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
4589433c | 3018 | return le32_to_cpu(args.ulReturnEngineClock); |
7433874e RM |
3019 | } |
3020 | ||
3021 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) | |
3022 | { | |
3023 | GET_MEMORY_CLOCK_PS_ALLOCATION args; | |
3024 | int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); | |
3025 | ||
3026 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
4589433c | 3027 | return le32_to_cpu(args.ulReturnMemoryClock); |
7433874e RM |
3028 | } |
3029 | ||
771fe6b9 JG |
3030 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, |
3031 | uint32_t eng_clock) | |
3032 | { | |
3033 | SET_ENGINE_CLOCK_PS_ALLOCATION args; | |
3034 | int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); | |
3035 | ||
4589433c | 3036 | args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ |
771fe6b9 JG |
3037 | |
3038 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
3039 | } | |
3040 | ||
3041 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, | |
3042 | uint32_t mem_clock) | |
3043 | { | |
3044 | SET_MEMORY_CLOCK_PS_ALLOCATION args; | |
3045 | int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); | |
3046 | ||
3047 | if (rdev->flags & RADEON_IS_IGP) | |
3048 | return; | |
3049 | ||
4589433c | 3050 | args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ |
771fe6b9 JG |
3051 | |
3052 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
3053 | } | |
3054 | ||
ae5b0abb AD |
3055 | void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, |
3056 | u32 eng_clock, u32 mem_clock) | |
3057 | { | |
3058 | SET_ENGINE_CLOCK_PS_ALLOCATION args; | |
3059 | int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); | |
3060 | u32 tmp; | |
3061 | ||
3062 | memset(&args, 0, sizeof(args)); | |
3063 | ||
3064 | tmp = eng_clock & SET_CLOCK_FREQ_MASK; | |
3065 | tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); | |
3066 | ||
3067 | args.ulTargetEngineClock = cpu_to_le32(tmp); | |
3068 | if (mem_clock) | |
3069 | args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); | |
3070 | ||
3071 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
3072 | } | |
3073 | ||
3074 | void radeon_atom_update_memory_dll(struct radeon_device *rdev, | |
3075 | u32 mem_clock) | |
3076 | { | |
3077 | u32 args; | |
3078 | int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); | |
3079 | ||
3080 | args = cpu_to_le32(mem_clock); /* 10 khz */ | |
3081 | ||
3082 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
3083 | } | |
3084 | ||
3085 | void radeon_atom_set_ac_timing(struct radeon_device *rdev, | |
3086 | u32 mem_clock) | |
3087 | { | |
3088 | SET_MEMORY_CLOCK_PS_ALLOCATION args; | |
3089 | int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); | |
3090 | u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24); | |
3091 | ||
3092 | args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */ | |
3093 | ||
3094 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
3095 | } | |
3096 | ||
7ac9aa5a AD |
3097 | union set_voltage { |
3098 | struct _SET_VOLTAGE_PS_ALLOCATION alloc; | |
3099 | struct _SET_VOLTAGE_PARAMETERS v1; | |
3100 | struct _SET_VOLTAGE_PARAMETERS_V2 v2; | |
e83753bb | 3101 | struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; |
7ac9aa5a AD |
3102 | }; |
3103 | ||
8a83ec5e | 3104 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type) |
7ac9aa5a AD |
3105 | { |
3106 | union set_voltage args; | |
3107 | int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); | |
8a83ec5e | 3108 | u8 frev, crev, volt_index = voltage_level; |
7ac9aa5a AD |
3109 | |
3110 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
3111 | return; | |
3112 | ||
a377e187 AD |
3113 | /* 0xff01 is a flag rather then an actual voltage */ |
3114 | if (voltage_level == 0xff01) | |
3115 | return; | |
3116 | ||
7ac9aa5a AD |
3117 | switch (crev) { |
3118 | case 1: | |
8a83ec5e | 3119 | args.v1.ucVoltageType = voltage_type; |
7ac9aa5a AD |
3120 | args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; |
3121 | args.v1.ucVoltageIndex = volt_index; | |
3122 | break; | |
3123 | case 2: | |
8a83ec5e | 3124 | args.v2.ucVoltageType = voltage_type; |
7ac9aa5a | 3125 | args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; |
8a83ec5e | 3126 | args.v2.usVoltageLevel = cpu_to_le16(voltage_level); |
7ac9aa5a | 3127 | break; |
e83753bb AD |
3128 | case 3: |
3129 | args.v3.ucVoltageType = voltage_type; | |
3130 | args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; | |
3131 | args.v3.usVoltageLevel = cpu_to_le16(voltage_level); | |
3132 | break; | |
7ac9aa5a AD |
3133 | default: |
3134 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
3135 | return; | |
3136 | } | |
3137 | ||
3138 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
3139 | } | |
3140 | ||
ae5b0abb AD |
3141 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
3142 | u16 voltage_id, u16 *voltage) | |
ee4017f4 AD |
3143 | { |
3144 | union set_voltage args; | |
3145 | int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); | |
3146 | u8 frev, crev; | |
3147 | ||
3148 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
3149 | return -EINVAL; | |
3150 | ||
3151 | switch (crev) { | |
3152 | case 1: | |
3153 | return -EINVAL; | |
3154 | case 2: | |
3155 | args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE; | |
3156 | args.v2.ucVoltageMode = 0; | |
3157 | args.v2.usVoltageLevel = 0; | |
3158 | ||
3159 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
3160 | ||
3161 | *voltage = le16_to_cpu(args.v2.usVoltageLevel); | |
3162 | break; | |
e83753bb AD |
3163 | case 3: |
3164 | args.v3.ucVoltageType = voltage_type; | |
3165 | args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; | |
3166 | args.v3.usVoltageLevel = cpu_to_le16(voltage_id); | |
3167 | ||
3168 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
3169 | ||
3170 | *voltage = le16_to_cpu(args.v3.usVoltageLevel); | |
3171 | break; | |
ee4017f4 AD |
3172 | default: |
3173 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
3174 | return -EINVAL; | |
3175 | } | |
7ac9aa5a | 3176 | |
ee4017f4 AD |
3177 | return 0; |
3178 | } | |
7ac9aa5a | 3179 | |
beb79f40 AD |
3180 | int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, |
3181 | u16 *voltage, | |
3182 | u16 leakage_idx) | |
3183 | { | |
3184 | return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage); | |
3185 | } | |
3186 | ||
62c35fd7 AD |
3187 | int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, |
3188 | u16 *leakage_id) | |
3189 | { | |
3190 | union set_voltage args; | |
3191 | int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); | |
3192 | u8 frev, crev; | |
3193 | ||
3194 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
3195 | return -EINVAL; | |
3196 | ||
3197 | switch (crev) { | |
3198 | case 3: | |
3199 | case 4: | |
3200 | args.v3.ucVoltageType = 0; | |
3201 | args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; | |
3202 | args.v3.usVoltageLevel = 0; | |
3203 | ||
3204 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
3205 | ||
3206 | *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); | |
3207 | break; | |
3208 | default: | |
3209 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
3210 | return -EINVAL; | |
3211 | } | |
3212 | ||
3213 | return 0; | |
3214 | } | |
3215 | ||
3216 | int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, | |
3217 | u16 *vddc, u16 *vddci, | |
3218 | u16 virtual_voltage_id, | |
3219 | u16 vbios_voltage_id) | |
3220 | { | |
3221 | int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); | |
3222 | u8 frev, crev; | |
3223 | u16 data_offset, size; | |
3224 | int i, j; | |
3225 | ATOM_ASIC_PROFILING_INFO_V2_1 *profile; | |
3226 | u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; | |
3227 | ||
3228 | *vddc = 0; | |
3229 | *vddci = 0; | |
3230 | ||
3231 | if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size, | |
3232 | &frev, &crev, &data_offset)) | |
3233 | return -EINVAL; | |
3234 | ||
3235 | profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) | |
3236 | (rdev->mode_info.atom_context->bios + data_offset); | |
3237 | ||
3238 | switch (frev) { | |
3239 | case 1: | |
3240 | return -EINVAL; | |
3241 | case 2: | |
3242 | switch (crev) { | |
3243 | case 1: | |
3244 | if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1)) | |
3245 | return -EINVAL; | |
3246 | leakage_bin = (u16 *) | |
3247 | (rdev->mode_info.atom_context->bios + data_offset + | |
3248 | le16_to_cpu(profile->usLeakageBinArrayOffset)); | |
3249 | vddc_id_buf = (u16 *) | |
3250 | (rdev->mode_info.atom_context->bios + data_offset + | |
3251 | le16_to_cpu(profile->usElbVDDC_IdArrayOffset)); | |
3252 | vddc_buf = (u16 *) | |
3253 | (rdev->mode_info.atom_context->bios + data_offset + | |
3254 | le16_to_cpu(profile->usElbVDDC_LevelArrayOffset)); | |
3255 | vddci_id_buf = (u16 *) | |
3256 | (rdev->mode_info.atom_context->bios + data_offset + | |
3257 | le16_to_cpu(profile->usElbVDDCI_IdArrayOffset)); | |
3258 | vddci_buf = (u16 *) | |
3259 | (rdev->mode_info.atom_context->bios + data_offset + | |
3260 | le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset)); | |
3261 | ||
3262 | if (profile->ucElbVDDC_Num > 0) { | |
3263 | for (i = 0; i < profile->ucElbVDDC_Num; i++) { | |
3264 | if (vddc_id_buf[i] == virtual_voltage_id) { | |
3265 | for (j = 0; j < profile->ucLeakageBinNum; j++) { | |
3266 | if (vbios_voltage_id <= leakage_bin[j]) { | |
3267 | *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; | |
3268 | break; | |
3269 | } | |
3270 | } | |
3271 | break; | |
3272 | } | |
3273 | } | |
3274 | } | |
3275 | if (profile->ucElbVDDCI_Num > 0) { | |
3276 | for (i = 0; i < profile->ucElbVDDCI_Num; i++) { | |
3277 | if (vddci_id_buf[i] == virtual_voltage_id) { | |
3278 | for (j = 0; j < profile->ucLeakageBinNum; j++) { | |
3279 | if (vbios_voltage_id <= leakage_bin[j]) { | |
3280 | *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; | |
3281 | break; | |
3282 | } | |
3283 | } | |
3284 | break; | |
3285 | } | |
3286 | } | |
3287 | } | |
3288 | break; | |
3289 | default: | |
3290 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
3291 | return -EINVAL; | |
3292 | } | |
3293 | break; | |
3294 | default: | |
3295 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
3296 | return -EINVAL; | |
3297 | } | |
3298 | ||
3299 | return 0; | |
3300 | } | |
3301 | ||
e9f274b2 AD |
3302 | union get_voltage_info { |
3303 | struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in; | |
3304 | struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out; | |
3305 | }; | |
3306 | ||
3307 | int radeon_atom_get_voltage_evv(struct radeon_device *rdev, | |
3308 | u16 virtual_voltage_id, | |
3309 | u16 *voltage) | |
3310 | { | |
3311 | int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo); | |
3312 | u32 entry_id; | |
3313 | u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; | |
3314 | union get_voltage_info args; | |
3315 | ||
3316 | for (entry_id = 0; entry_id < count; entry_id++) { | |
3317 | if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == | |
3318 | virtual_voltage_id) | |
3319 | break; | |
3320 | } | |
3321 | ||
3322 | if (entry_id >= count) | |
3323 | return -EINVAL; | |
3324 | ||
3325 | args.in.ucVoltageType = VOLTAGE_TYPE_VDDC; | |
3326 | args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; | |
09b6e85f | 3327 | args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id); |
e9f274b2 AD |
3328 | args.in.ulSCLKFreq = |
3329 | cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); | |
3330 | ||
3331 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
3332 | ||
3333 | *voltage = le16_to_cpu(args.evv_out.usVoltageLevel); | |
3334 | ||
3335 | return 0; | |
3336 | } | |
3337 | ||
ae5b0abb AD |
3338 | int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, |
3339 | u16 voltage_level, u8 voltage_type, | |
3340 | u32 *gpio_value, u32 *gpio_mask) | |
3341 | { | |
3342 | union set_voltage args; | |
3343 | int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); | |
3344 | u8 frev, crev; | |
3345 | ||
3346 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
3347 | return -EINVAL; | |
3348 | ||
3349 | switch (crev) { | |
3350 | case 1: | |
3351 | return -EINVAL; | |
3352 | case 2: | |
3353 | args.v2.ucVoltageType = voltage_type; | |
3354 | args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK; | |
3355 | args.v2.usVoltageLevel = cpu_to_le16(voltage_level); | |
3356 | ||
3357 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
3358 | ||
3359 | *gpio_mask = le32_to_cpu(*(u32 *)&args.v2); | |
3360 | ||
3361 | args.v2.ucVoltageType = voltage_type; | |
3362 | args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL; | |
3363 | args.v2.usVoltageLevel = cpu_to_le16(voltage_level); | |
3364 | ||
3365 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
3366 | ||
3367 | *gpio_value = le32_to_cpu(*(u32 *)&args.v2); | |
3368 | break; | |
3369 | default: | |
3370 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
3371 | return -EINVAL; | |
3372 | } | |
3373 | ||
3374 | return 0; | |
3375 | } | |
3376 | ||
3377 | union voltage_object_info { | |
58653abd AD |
3378 | struct _ATOM_VOLTAGE_OBJECT_INFO v1; |
3379 | struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; | |
3380 | struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; | |
ae5b0abb AD |
3381 | }; |
3382 | ||
779187f2 AD |
3383 | union voltage_object { |
3384 | struct _ATOM_VOLTAGE_OBJECT v1; | |
3385 | struct _ATOM_VOLTAGE_OBJECT_V2 v2; | |
3386 | union _ATOM_VOLTAGE_OBJECT_V3 v3; | |
3387 | }; | |
3388 | ||
3389 | static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1, | |
3390 | u8 voltage_type) | |
3391 | { | |
6e764764 | 3392 | u32 size = le16_to_cpu(v1->sHeader.usStructureSize); |
779187f2 AD |
3393 | u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]); |
3394 | u8 *start = (u8 *)v1; | |
3395 | ||
3396 | while (offset < size) { | |
3397 | ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset); | |
3398 | if (vo->ucVoltageType == voltage_type) | |
3399 | return vo; | |
3400 | offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) + | |
3401 | vo->asFormula.ucNumOfVoltageEntries; | |
3402 | } | |
3403 | return NULL; | |
3404 | } | |
3405 | ||
3406 | static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2, | |
3407 | u8 voltage_type) | |
3408 | { | |
6e764764 | 3409 | u32 size = le16_to_cpu(v2->sHeader.usStructureSize); |
779187f2 AD |
3410 | u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]); |
3411 | u8 *start = (u8*)v2; | |
3412 | ||
3413 | while (offset < size) { | |
3414 | ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset); | |
3415 | if (vo->ucVoltageType == voltage_type) | |
3416 | return vo; | |
3417 | offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) + | |
3418 | (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY)); | |
3419 | } | |
3420 | return NULL; | |
3421 | } | |
3422 | ||
3423 | static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, | |
3424 | u8 voltage_type, u8 voltage_mode) | |
3425 | { | |
6e764764 | 3426 | u32 size = le16_to_cpu(v3->sHeader.usStructureSize); |
779187f2 AD |
3427 | u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); |
3428 | u8 *start = (u8*)v3; | |
3429 | ||
3430 | while (offset < size) { | |
3431 | ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); | |
3432 | if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && | |
3433 | (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) | |
3434 | return vo; | |
6e764764 | 3435 | offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); |
779187f2 AD |
3436 | } |
3437 | return NULL; | |
3438 | } | |
3439 | ||
ae5b0abb | 3440 | bool |
58653abd AD |
3441 | radeon_atom_is_voltage_gpio(struct radeon_device *rdev, |
3442 | u8 voltage_type, u8 voltage_mode) | |
ae5b0abb AD |
3443 | { |
3444 | int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); | |
3445 | u8 frev, crev; | |
3446 | u16 data_offset, size; | |
ae5b0abb | 3447 | union voltage_object_info *voltage_info; |
779187f2 | 3448 | union voltage_object *voltage_object = NULL; |
ae5b0abb AD |
3449 | |
3450 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, | |
3451 | &frev, &crev, &data_offset)) { | |
3452 | voltage_info = (union voltage_object_info *) | |
3453 | (rdev->mode_info.atom_context->bios + data_offset); | |
3454 | ||
58653abd | 3455 | switch (frev) { |
ae5b0abb | 3456 | case 1: |
58653abd AD |
3457 | case 2: |
3458 | switch (crev) { | |
3459 | case 1: | |
779187f2 AD |
3460 | voltage_object = (union voltage_object *) |
3461 | atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); | |
3462 | if (voltage_object && | |
3463 | (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) | |
3464 | return true; | |
58653abd AD |
3465 | break; |
3466 | case 2: | |
779187f2 AD |
3467 | voltage_object = (union voltage_object *) |
3468 | atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); | |
3469 | if (voltage_object && | |
3470 | (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) | |
3471 | return true; | |
58653abd AD |
3472 | break; |
3473 | default: | |
3474 | DRM_ERROR("unknown voltage object table\n"); | |
3475 | return false; | |
ae5b0abb AD |
3476 | } |
3477 | break; | |
58653abd AD |
3478 | case 3: |
3479 | switch (crev) { | |
3480 | case 1: | |
779187f2 AD |
3481 | if (atom_lookup_voltage_object_v3(&voltage_info->v3, |
3482 | voltage_type, voltage_mode)) | |
3483 | return true; | |
58653abd AD |
3484 | break; |
3485 | default: | |
3486 | DRM_ERROR("unknown voltage object table\n"); | |
3487 | return false; | |
ae5b0abb AD |
3488 | } |
3489 | break; | |
3490 | default: | |
3491 | DRM_ERROR("unknown voltage object table\n"); | |
3492 | return false; | |
3493 | } | |
3494 | ||
3495 | } | |
3496 | return false; | |
3497 | } | |
3498 | ||
636e2582 AD |
3499 | int radeon_atom_get_svi2_info(struct radeon_device *rdev, |
3500 | u8 voltage_type, | |
3501 | u8 *svd_gpio_id, u8 *svc_gpio_id) | |
3502 | { | |
3503 | int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); | |
3504 | u8 frev, crev; | |
3505 | u16 data_offset, size; | |
3506 | union voltage_object_info *voltage_info; | |
3507 | union voltage_object *voltage_object = NULL; | |
3508 | ||
3509 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, | |
3510 | &frev, &crev, &data_offset)) { | |
3511 | voltage_info = (union voltage_object_info *) | |
3512 | (rdev->mode_info.atom_context->bios + data_offset); | |
3513 | ||
3514 | switch (frev) { | |
3515 | case 3: | |
3516 | switch (crev) { | |
3517 | case 1: | |
3518 | voltage_object = (union voltage_object *) | |
3519 | atom_lookup_voltage_object_v3(&voltage_info->v3, | |
3520 | voltage_type, | |
3521 | VOLTAGE_OBJ_SVID2); | |
3522 | if (voltage_object) { | |
3523 | *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId; | |
3524 | *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId; | |
3525 | } else { | |
3526 | return -EINVAL; | |
3527 | } | |
3528 | break; | |
3529 | default: | |
3530 | DRM_ERROR("unknown voltage object table\n"); | |
3531 | return -EINVAL; | |
3532 | } | |
3533 | break; | |
3534 | default: | |
3535 | DRM_ERROR("unknown voltage object table\n"); | |
3536 | return -EINVAL; | |
3537 | } | |
3538 | ||
3539 | } | |
3540 | return 0; | |
3541 | } | |
3542 | ||
ae5b0abb AD |
3543 | int radeon_atom_get_max_voltage(struct radeon_device *rdev, |
3544 | u8 voltage_type, u16 *max_voltage) | |
3545 | { | |
3546 | int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); | |
3547 | u8 frev, crev; | |
3548 | u16 data_offset, size; | |
ae5b0abb | 3549 | union voltage_object_info *voltage_info; |
779187f2 | 3550 | union voltage_object *voltage_object = NULL; |
ae5b0abb AD |
3551 | |
3552 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, | |
3553 | &frev, &crev, &data_offset)) { | |
3554 | voltage_info = (union voltage_object_info *) | |
3555 | (rdev->mode_info.atom_context->bios + data_offset); | |
3556 | ||
3557 | switch (crev) { | |
3558 | case 1: | |
779187f2 AD |
3559 | voltage_object = (union voltage_object *) |
3560 | atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); | |
3561 | if (voltage_object) { | |
3562 | ATOM_VOLTAGE_FORMULA *formula = | |
3563 | &voltage_object->v1.asFormula; | |
3564 | if (formula->ucFlag & 1) | |
3565 | *max_voltage = | |
3566 | le16_to_cpu(formula->usVoltageBaseLevel) + | |
3567 | formula->ucNumOfVoltageEntries / 2 * | |
3568 | le16_to_cpu(formula->usVoltageStep); | |
3569 | else | |
3570 | *max_voltage = | |
3571 | le16_to_cpu(formula->usVoltageBaseLevel) + | |
3572 | (formula->ucNumOfVoltageEntries - 1) * | |
3573 | le16_to_cpu(formula->usVoltageStep); | |
3574 | return 0; | |
ae5b0abb AD |
3575 | } |
3576 | break; | |
3577 | case 2: | |
779187f2 AD |
3578 | voltage_object = (union voltage_object *) |
3579 | atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); | |
3580 | if (voltage_object) { | |
3581 | ATOM_VOLTAGE_FORMULA_V2 *formula = | |
3582 | &voltage_object->v2.asFormula; | |
3583 | if (formula->ucNumOfVoltageEntries) { | |
607f2c27 AD |
3584 | VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *) |
3585 | ((u8 *)&formula->asVIDAdjustEntries[0] + | |
3586 | (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1))); | |
779187f2 | 3587 | *max_voltage = |
607f2c27 | 3588 | le16_to_cpu(lut->usVoltageValue); |
779187f2 | 3589 | return 0; |
ae5b0abb AD |
3590 | } |
3591 | } | |
3592 | break; | |
3593 | default: | |
3594 | DRM_ERROR("unknown voltage object table\n"); | |
3595 | return -EINVAL; | |
3596 | } | |
3597 | ||
3598 | } | |
3599 | return -EINVAL; | |
3600 | } | |
3601 | ||
3602 | int radeon_atom_get_min_voltage(struct radeon_device *rdev, | |
3603 | u8 voltage_type, u16 *min_voltage) | |
3604 | { | |
3605 | int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); | |
3606 | u8 frev, crev; | |
3607 | u16 data_offset, size; | |
ae5b0abb | 3608 | union voltage_object_info *voltage_info; |
779187f2 | 3609 | union voltage_object *voltage_object = NULL; |
ae5b0abb AD |
3610 | |
3611 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, | |
3612 | &frev, &crev, &data_offset)) { | |
3613 | voltage_info = (union voltage_object_info *) | |
3614 | (rdev->mode_info.atom_context->bios + data_offset); | |
3615 | ||
3616 | switch (crev) { | |
3617 | case 1: | |
779187f2 AD |
3618 | voltage_object = (union voltage_object *) |
3619 | atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); | |
3620 | if (voltage_object) { | |
3621 | ATOM_VOLTAGE_FORMULA *formula = | |
3622 | &voltage_object->v1.asFormula; | |
3623 | *min_voltage = | |
3624 | le16_to_cpu(formula->usVoltageBaseLevel); | |
3625 | return 0; | |
ae5b0abb AD |
3626 | } |
3627 | break; | |
3628 | case 2: | |
779187f2 AD |
3629 | voltage_object = (union voltage_object *) |
3630 | atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); | |
3631 | if (voltage_object) { | |
3632 | ATOM_VOLTAGE_FORMULA_V2 *formula = | |
3633 | &voltage_object->v2.asFormula; | |
3634 | if (formula->ucNumOfVoltageEntries) { | |
3635 | *min_voltage = | |
3636 | le16_to_cpu(formula->asVIDAdjustEntries[ | |
3637 | 0 | |
3638 | ].usVoltageValue); | |
3639 | return 0; | |
ae5b0abb AD |
3640 | } |
3641 | } | |
3642 | break; | |
3643 | default: | |
3644 | DRM_ERROR("unknown voltage object table\n"); | |
3645 | return -EINVAL; | |
3646 | } | |
3647 | ||
3648 | } | |
3649 | return -EINVAL; | |
3650 | } | |
3651 | ||
3652 | int radeon_atom_get_voltage_step(struct radeon_device *rdev, | |
3653 | u8 voltage_type, u16 *voltage_step) | |
3654 | { | |
3655 | int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); | |
3656 | u8 frev, crev; | |
3657 | u16 data_offset, size; | |
ae5b0abb | 3658 | union voltage_object_info *voltage_info; |
779187f2 | 3659 | union voltage_object *voltage_object = NULL; |
ae5b0abb AD |
3660 | |
3661 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, | |
3662 | &frev, &crev, &data_offset)) { | |
3663 | voltage_info = (union voltage_object_info *) | |
3664 | (rdev->mode_info.atom_context->bios + data_offset); | |
3665 | ||
3666 | switch (crev) { | |
3667 | case 1: | |
779187f2 AD |
3668 | voltage_object = (union voltage_object *) |
3669 | atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); | |
3670 | if (voltage_object) { | |
3671 | ATOM_VOLTAGE_FORMULA *formula = | |
3672 | &voltage_object->v1.asFormula; | |
3673 | if (formula->ucFlag & 1) | |
3674 | *voltage_step = | |
3675 | (le16_to_cpu(formula->usVoltageStep) + 1) / 2; | |
3676 | else | |
3677 | *voltage_step = | |
3678 | le16_to_cpu(formula->usVoltageStep); | |
3679 | return 0; | |
ae5b0abb AD |
3680 | } |
3681 | break; | |
3682 | case 2: | |
3683 | return -EINVAL; | |
3684 | default: | |
3685 | DRM_ERROR("unknown voltage object table\n"); | |
3686 | return -EINVAL; | |
3687 | } | |
3688 | ||
3689 | } | |
3690 | return -EINVAL; | |
3691 | } | |
3692 | ||
3693 | int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, | |
3694 | u8 voltage_type, | |
3695 | u16 nominal_voltage, | |
3696 | u16 *true_voltage) | |
3697 | { | |
3698 | u16 min_voltage, max_voltage, voltage_step; | |
3699 | ||
3700 | if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage)) | |
3701 | return -EINVAL; | |
3702 | if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage)) | |
3703 | return -EINVAL; | |
3704 | if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step)) | |
3705 | return -EINVAL; | |
3706 | ||
3707 | if (nominal_voltage <= min_voltage) | |
3708 | *true_voltage = min_voltage; | |
3709 | else if (nominal_voltage >= max_voltage) | |
3710 | *true_voltage = max_voltage; | |
3711 | else | |
3712 | *true_voltage = min_voltage + | |
3713 | ((nominal_voltage - min_voltage) / voltage_step) * | |
3714 | voltage_step; | |
3715 | ||
3716 | return 0; | |
3717 | } | |
3718 | ||
3719 | int radeon_atom_get_voltage_table(struct radeon_device *rdev, | |
65171944 | 3720 | u8 voltage_type, u8 voltage_mode, |
ae5b0abb AD |
3721 | struct atom_voltage_table *voltage_table) |
3722 | { | |
3723 | int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); | |
3724 | u8 frev, crev; | |
3725 | u16 data_offset, size; | |
779187f2 | 3726 | int i, ret; |
ae5b0abb | 3727 | union voltage_object_info *voltage_info; |
779187f2 | 3728 | union voltage_object *voltage_object = NULL; |
ae5b0abb AD |
3729 | |
3730 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, | |
3731 | &frev, &crev, &data_offset)) { | |
3732 | voltage_info = (union voltage_object_info *) | |
3733 | (rdev->mode_info.atom_context->bios + data_offset); | |
3734 | ||
65171944 | 3735 | switch (frev) { |
ae5b0abb | 3736 | case 1: |
ae5b0abb | 3737 | case 2: |
65171944 AD |
3738 | switch (crev) { |
3739 | case 1: | |
3740 | DRM_ERROR("old table version %d, %d\n", frev, crev); | |
3741 | return -EINVAL; | |
3742 | case 2: | |
779187f2 AD |
3743 | voltage_object = (union voltage_object *) |
3744 | atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); | |
3745 | if (voltage_object) { | |
3746 | ATOM_VOLTAGE_FORMULA_V2 *formula = | |
3747 | &voltage_object->v2.asFormula; | |
607f2c27 | 3748 | VOLTAGE_LUT_ENTRY *lut; |
779187f2 AD |
3749 | if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES) |
3750 | return -EINVAL; | |
607f2c27 | 3751 | lut = &formula->asVIDAdjustEntries[0]; |
779187f2 AD |
3752 | for (i = 0; i < formula->ucNumOfVoltageEntries; i++) { |
3753 | voltage_table->entries[i].value = | |
607f2c27 | 3754 | le16_to_cpu(lut->usVoltageValue); |
779187f2 AD |
3755 | ret = radeon_atom_get_voltage_gpio_settings(rdev, |
3756 | voltage_table->entries[i].value, | |
3757 | voltage_type, | |
3758 | &voltage_table->entries[i].smio_low, | |
3759 | &voltage_table->mask_low); | |
3760 | if (ret) | |
3761 | return ret; | |
607f2c27 AD |
3762 | lut = (VOLTAGE_LUT_ENTRY *) |
3763 | ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY)); | |
ae5b0abb | 3764 | } |
779187f2 AD |
3765 | voltage_table->count = formula->ucNumOfVoltageEntries; |
3766 | return 0; | |
ae5b0abb | 3767 | } |
65171944 AD |
3768 | break; |
3769 | default: | |
3770 | DRM_ERROR("unknown voltage object table\n"); | |
3771 | return -EINVAL; | |
3772 | } | |
3773 | break; | |
3774 | case 3: | |
3775 | switch (crev) { | |
3776 | case 1: | |
779187f2 AD |
3777 | voltage_object = (union voltage_object *) |
3778 | atom_lookup_voltage_object_v3(&voltage_info->v3, | |
3779 | voltage_type, voltage_mode); | |
3780 | if (voltage_object) { | |
3781 | ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = | |
3782 | &voltage_object->v3.asGpioVoltageObj; | |
607f2c27 | 3783 | VOLTAGE_LUT_ENTRY_V2 *lut; |
779187f2 AD |
3784 | if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) |
3785 | return -EINVAL; | |
607f2c27 | 3786 | lut = &gpio->asVolGpioLut[0]; |
779187f2 AD |
3787 | for (i = 0; i < gpio->ucGpioEntryNum; i++) { |
3788 | voltage_table->entries[i].value = | |
607f2c27 | 3789 | le16_to_cpu(lut->usVoltageValue); |
779187f2 | 3790 | voltage_table->entries[i].smio_low = |
607f2c27 AD |
3791 | le32_to_cpu(lut->ulVoltageId); |
3792 | lut = (VOLTAGE_LUT_ENTRY_V2 *) | |
3793 | ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2)); | |
65171944 | 3794 | } |
779187f2 AD |
3795 | voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); |
3796 | voltage_table->count = gpio->ucGpioEntryNum; | |
3797 | voltage_table->phase_delay = gpio->ucPhaseDelay; | |
3798 | return 0; | |
65171944 AD |
3799 | } |
3800 | break; | |
3801 | default: | |
3802 | DRM_ERROR("unknown voltage object table\n"); | |
3803 | return -EINVAL; | |
ae5b0abb AD |
3804 | } |
3805 | break; | |
3806 | default: | |
3807 | DRM_ERROR("unknown voltage object table\n"); | |
3808 | return -EINVAL; | |
3809 | } | |
ae5b0abb AD |
3810 | } |
3811 | return -EINVAL; | |
3812 | } | |
3813 | ||
3814 | union vram_info { | |
3815 | struct _ATOM_VRAM_INFO_V3 v1_3; | |
3816 | struct _ATOM_VRAM_INFO_V4 v1_4; | |
3817 | struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; | |
3818 | }; | |
3819 | ||
3820 | int radeon_atom_get_memory_info(struct radeon_device *rdev, | |
3821 | u8 module_index, struct atom_memory_info *mem_info) | |
3822 | { | |
3823 | int index = GetIndexIntoMasterTable(DATA, VRAM_Info); | |
3824 | u8 frev, crev, i; | |
3825 | u16 data_offset, size; | |
3826 | union vram_info *vram_info; | |
ae5b0abb AD |
3827 | |
3828 | memset(mem_info, 0, sizeof(struct atom_memory_info)); | |
3829 | ||
3830 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, | |
3831 | &frev, &crev, &data_offset)) { | |
3832 | vram_info = (union vram_info *) | |
3833 | (rdev->mode_info.atom_context->bios + data_offset); | |
3834 | switch (frev) { | |
3835 | case 1: | |
3836 | switch (crev) { | |
3837 | case 3: | |
3838 | /* r6xx */ | |
3839 | if (module_index < vram_info->v1_3.ucNumOfVRAMModule) { | |
3840 | ATOM_VRAM_MODULE_V3 *vram_module = | |
3841 | (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo; | |
ae5b0abb AD |
3842 | |
3843 | for (i = 0; i < module_index; i++) { | |
ae5b0abb AD |
3844 | if (le16_to_cpu(vram_module->usSize) == 0) |
3845 | return -EINVAL; | |
77c7d50a AD |
3846 | vram_module = (ATOM_VRAM_MODULE_V3 *) |
3847 | ((u8 *)vram_module + le16_to_cpu(vram_module->usSize)); | |
ae5b0abb AD |
3848 | } |
3849 | mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf; | |
3850 | mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0; | |
3851 | } else | |
3852 | return -EINVAL; | |
3853 | break; | |
3854 | case 4: | |
3855 | /* r7xx, evergreen */ | |
3856 | if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { | |
3857 | ATOM_VRAM_MODULE_V4 *vram_module = | |
3858 | (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; | |
ae5b0abb AD |
3859 | |
3860 | for (i = 0; i < module_index; i++) { | |
ae5b0abb AD |
3861 | if (le16_to_cpu(vram_module->usModuleSize) == 0) |
3862 | return -EINVAL; | |
77c7d50a AD |
3863 | vram_module = (ATOM_VRAM_MODULE_V4 *) |
3864 | ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); | |
ae5b0abb AD |
3865 | } |
3866 | mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; | |
3867 | mem_info->mem_type = vram_module->ucMemoryType & 0xf0; | |
3868 | } else | |
3869 | return -EINVAL; | |
3870 | break; | |
3871 | default: | |
3872 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
3873 | return -EINVAL; | |
3874 | } | |
3875 | break; | |
3876 | case 2: | |
3877 | switch (crev) { | |
3878 | case 1: | |
3879 | /* ni */ | |
3880 | if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { | |
3881 | ATOM_VRAM_MODULE_V7 *vram_module = | |
3882 | (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo; | |
ae5b0abb AD |
3883 | |
3884 | for (i = 0; i < module_index; i++) { | |
ae5b0abb AD |
3885 | if (le16_to_cpu(vram_module->usModuleSize) == 0) |
3886 | return -EINVAL; | |
77c7d50a AD |
3887 | vram_module = (ATOM_VRAM_MODULE_V7 *) |
3888 | ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); | |
ae5b0abb AD |
3889 | } |
3890 | mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; | |
3891 | mem_info->mem_type = vram_module->ucMemoryType & 0xf0; | |
3892 | } else | |
3893 | return -EINVAL; | |
3894 | break; | |
3895 | default: | |
3896 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
3897 | return -EINVAL; | |
3898 | } | |
3899 | break; | |
3900 | default: | |
3901 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
3902 | return -EINVAL; | |
3903 | } | |
3904 | return 0; | |
3905 | } | |
3906 | return -EINVAL; | |
3907 | } | |
3908 | ||
3909 | int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, | |
3910 | bool gddr5, u8 module_index, | |
3911 | struct atom_memory_clock_range_table *mclk_range_table) | |
3912 | { | |
3913 | int index = GetIndexIntoMasterTable(DATA, VRAM_Info); | |
3914 | u8 frev, crev, i; | |
3915 | u16 data_offset, size; | |
3916 | union vram_info *vram_info; | |
3917 | u32 mem_timing_size = gddr5 ? | |
3918 | sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT); | |
ae5b0abb AD |
3919 | |
3920 | memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table)); | |
3921 | ||
3922 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, | |
3923 | &frev, &crev, &data_offset)) { | |
3924 | vram_info = (union vram_info *) | |
3925 | (rdev->mode_info.atom_context->bios + data_offset); | |
3926 | switch (frev) { | |
3927 | case 1: | |
3928 | switch (crev) { | |
3929 | case 3: | |
3930 | DRM_ERROR("old table version %d, %d\n", frev, crev); | |
3931 | return -EINVAL; | |
3932 | case 4: | |
3933 | /* r7xx, evergreen */ | |
3934 | if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { | |
3935 | ATOM_VRAM_MODULE_V4 *vram_module = | |
3936 | (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; | |
607f2c27 | 3937 | ATOM_MEMORY_TIMING_FORMAT *format; |
ae5b0abb AD |
3938 | |
3939 | for (i = 0; i < module_index; i++) { | |
ae5b0abb AD |
3940 | if (le16_to_cpu(vram_module->usModuleSize) == 0) |
3941 | return -EINVAL; | |
77c7d50a AD |
3942 | vram_module = (ATOM_VRAM_MODULE_V4 *) |
3943 | ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); | |
ae5b0abb AD |
3944 | } |
3945 | mclk_range_table->num_entries = (u8) | |
1fa4252a | 3946 | ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) / |
ae5b0abb | 3947 | mem_timing_size); |
607f2c27 | 3948 | format = &vram_module->asMemTiming[0]; |
ae5b0abb | 3949 | for (i = 0; i < mclk_range_table->num_entries; i++) { |
e631227f | 3950 | mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange); |
607f2c27 AD |
3951 | format = (ATOM_MEMORY_TIMING_FORMAT *) |
3952 | ((u8 *)format + mem_timing_size); | |
ae5b0abb AD |
3953 | } |
3954 | } else | |
3955 | return -EINVAL; | |
3956 | break; | |
3957 | default: | |
3958 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
3959 | return -EINVAL; | |
3960 | } | |
3961 | break; | |
3962 | case 2: | |
3963 | DRM_ERROR("new table version %d, %d\n", frev, crev); | |
3964 | return -EINVAL; | |
3965 | default: | |
3966 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
3967 | return -EINVAL; | |
3968 | } | |
3969 | return 0; | |
3970 | } | |
3971 | return -EINVAL; | |
3972 | } | |
3973 | ||
3974 | #define MEM_ID_MASK 0xff000000 | |
3975 | #define MEM_ID_SHIFT 24 | |
3976 | #define CLOCK_RANGE_MASK 0x00ffffff | |
3977 | #define CLOCK_RANGE_SHIFT 0 | |
3978 | #define LOW_NIBBLE_MASK 0xf | |
3979 | #define DATA_EQU_PREV 0 | |
3980 | #define DATA_FROM_TABLE 4 | |
3981 | ||
3982 | int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, | |
3983 | u8 module_index, | |
3984 | struct atom_mc_reg_table *reg_table) | |
3985 | { | |
3986 | int index = GetIndexIntoMasterTable(DATA, VRAM_Info); | |
3987 | u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; | |
3988 | u32 i = 0, j; | |
3989 | u16 data_offset, size; | |
3990 | union vram_info *vram_info; | |
3991 | ||
3992 | memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); | |
3993 | ||
3994 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, | |
3995 | &frev, &crev, &data_offset)) { | |
3996 | vram_info = (union vram_info *) | |
3997 | (rdev->mode_info.atom_context->bios + data_offset); | |
3998 | switch (frev) { | |
3999 | case 1: | |
4000 | DRM_ERROR("old table version %d, %d\n", frev, crev); | |
4001 | return -EINVAL; | |
4002 | case 2: | |
4003 | switch (crev) { | |
4004 | case 1: | |
4005 | if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { | |
4006 | ATOM_INIT_REG_BLOCK *reg_block = | |
4007 | (ATOM_INIT_REG_BLOCK *) | |
4008 | ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); | |
4009 | ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = | |
4010 | (ATOM_MEMORY_SETTING_DATA_BLOCK *) | |
4011 | ((u8 *)reg_block + (2 * sizeof(u16)) + | |
4012 | le16_to_cpu(reg_block->usRegIndexTblSize)); | |
f90555cb | 4013 | ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; |
ae5b0abb AD |
4014 | num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / |
4015 | sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; | |
4016 | if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) | |
4017 | return -EINVAL; | |
48fa04c3 | 4018 | while (i < num_entries) { |
f90555cb | 4019 | if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) |
48fa04c3 | 4020 | break; |
ae5b0abb | 4021 | reg_table->mc_reg_address[i].s1 = |
f90555cb | 4022 | (u16)(le16_to_cpu(format->usRegIndex)); |
ae5b0abb | 4023 | reg_table->mc_reg_address[i].pre_reg_data = |
f90555cb | 4024 | (u8)(format->ucPreRegDataLength); |
ae5b0abb | 4025 | i++; |
f90555cb AD |
4026 | format = (ATOM_INIT_REG_INDEX_FORMAT *) |
4027 | ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); | |
ae5b0abb AD |
4028 | } |
4029 | reg_table->last = i; | |
d526fbdd | 4030 | while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && |
ae5b0abb | 4031 | (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { |
d526fbdd AD |
4032 | t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) |
4033 | >> MEM_ID_SHIFT); | |
ae5b0abb AD |
4034 | if (module_index == t_mem_id) { |
4035 | reg_table->mc_reg_table_entry[num_ranges].mclk_max = | |
d526fbdd AD |
4036 | (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) |
4037 | >> CLOCK_RANGE_SHIFT); | |
ae5b0abb AD |
4038 | for (i = 0, j = 1; i < reg_table->last; i++) { |
4039 | if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { | |
4040 | reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = | |
d526fbdd | 4041 | (u32)le32_to_cpu(*((u32 *)reg_data + j)); |
ae5b0abb AD |
4042 | j++; |
4043 | } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { | |
4044 | reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = | |
4045 | reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; | |
4046 | } | |
4047 | } | |
4048 | num_ranges++; | |
4049 | } | |
4da18e26 AD |
4050 | reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) |
4051 | ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); | |
ae5b0abb | 4052 | } |
d526fbdd | 4053 | if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) |
ae5b0abb AD |
4054 | return -EINVAL; |
4055 | reg_table->num_entries = num_ranges; | |
4056 | } else | |
4057 | return -EINVAL; | |
4058 | break; | |
4059 | default: | |
4060 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
4061 | return -EINVAL; | |
4062 | } | |
4063 | break; | |
4064 | default: | |
4065 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
4066 | return -EINVAL; | |
4067 | } | |
4068 | return 0; | |
4069 | } | |
4070 | return -EINVAL; | |
4071 | } | |
4072 | ||
771fe6b9 JG |
4073 | void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) |
4074 | { | |
4075 | struct radeon_device *rdev = dev->dev_private; | |
4076 | uint32_t bios_2_scratch, bios_6_scratch; | |
4077 | ||
4078 | if (rdev->family >= CHIP_R600) { | |
4ce001ab | 4079 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); |
771fe6b9 JG |
4080 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
4081 | } else { | |
4ce001ab | 4082 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); |
771fe6b9 JG |
4083 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
4084 | } | |
4085 | ||
4086 | /* let the bios control the backlight */ | |
4087 | bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; | |
4088 | ||
4089 | /* tell the bios not to handle mode switching */ | |
87364760 | 4090 | bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; |
771fe6b9 | 4091 | |
6802d4ba AD |
4092 | /* clear the vbios dpms state */ |
4093 | if (ASIC_IS_DCE4(rdev)) | |
4094 | bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; | |
4095 | ||
771fe6b9 JG |
4096 | if (rdev->family >= CHIP_R600) { |
4097 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); | |
4098 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); | |
4099 | } else { | |
4100 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); | |
4101 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); | |
4102 | } | |
4103 | ||
4104 | } | |
4105 | ||
f657c2a7 YZ |
4106 | void radeon_save_bios_scratch_regs(struct radeon_device *rdev) |
4107 | { | |
4108 | uint32_t scratch_reg; | |
4109 | int i; | |
4110 | ||
4111 | if (rdev->family >= CHIP_R600) | |
4112 | scratch_reg = R600_BIOS_0_SCRATCH; | |
4113 | else | |
4114 | scratch_reg = RADEON_BIOS_0_SCRATCH; | |
4115 | ||
4116 | for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) | |
4117 | rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); | |
4118 | } | |
4119 | ||
4120 | void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) | |
4121 | { | |
4122 | uint32_t scratch_reg; | |
4123 | int i; | |
4124 | ||
4125 | if (rdev->family >= CHIP_R600) | |
4126 | scratch_reg = R600_BIOS_0_SCRATCH; | |
4127 | else | |
4128 | scratch_reg = RADEON_BIOS_0_SCRATCH; | |
4129 | ||
4130 | for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) | |
4131 | WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); | |
4132 | } | |
4133 | ||
771fe6b9 JG |
4134 | void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) |
4135 | { | |
4136 | struct drm_device *dev = encoder->dev; | |
4137 | struct radeon_device *rdev = dev->dev_private; | |
4138 | uint32_t bios_6_scratch; | |
4139 | ||
4140 | if (rdev->family >= CHIP_R600) | |
4141 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); | |
4142 | else | |
4143 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); | |
4144 | ||
87364760 | 4145 | if (lock) { |
771fe6b9 | 4146 | bios_6_scratch |= ATOM_S6_CRITICAL_STATE; |
87364760 AD |
4147 | bios_6_scratch &= ~ATOM_S6_ACC_MODE; |
4148 | } else { | |
771fe6b9 | 4149 | bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; |
87364760 AD |
4150 | bios_6_scratch |= ATOM_S6_ACC_MODE; |
4151 | } | |
771fe6b9 JG |
4152 | |
4153 | if (rdev->family >= CHIP_R600) | |
4154 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); | |
4155 | else | |
4156 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); | |
4157 | } | |
4158 | ||
4159 | /* at some point we may want to break this out into individual functions */ | |
4160 | void | |
4161 | radeon_atombios_connected_scratch_regs(struct drm_connector *connector, | |
4162 | struct drm_encoder *encoder, | |
4163 | bool connected) | |
4164 | { | |
4165 | struct drm_device *dev = connector->dev; | |
4166 | struct radeon_device *rdev = dev->dev_private; | |
4167 | struct radeon_connector *radeon_connector = | |
4168 | to_radeon_connector(connector); | |
4169 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
4170 | uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; | |
4171 | ||
4172 | if (rdev->family >= CHIP_R600) { | |
4173 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); | |
4174 | bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); | |
4175 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); | |
4176 | } else { | |
4177 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); | |
4178 | bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); | |
4179 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); | |
4180 | } | |
4181 | ||
4182 | if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && | |
4183 | (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { | |
4184 | if (connected) { | |
d9fdaafb | 4185 | DRM_DEBUG_KMS("TV1 connected\n"); |
771fe6b9 JG |
4186 | bios_3_scratch |= ATOM_S3_TV1_ACTIVE; |
4187 | bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; | |
4188 | } else { | |
d9fdaafb | 4189 | DRM_DEBUG_KMS("TV1 disconnected\n"); |
771fe6b9 JG |
4190 | bios_0_scratch &= ~ATOM_S0_TV1_MASK; |
4191 | bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; | |
4192 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; | |
4193 | } | |
4194 | } | |
4195 | if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && | |
4196 | (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { | |
4197 | if (connected) { | |
d9fdaafb | 4198 | DRM_DEBUG_KMS("CV connected\n"); |
771fe6b9 JG |
4199 | bios_3_scratch |= ATOM_S3_CV_ACTIVE; |
4200 | bios_6_scratch |= ATOM_S6_ACC_REQ_CV; | |
4201 | } else { | |
d9fdaafb | 4202 | DRM_DEBUG_KMS("CV disconnected\n"); |
771fe6b9 JG |
4203 | bios_0_scratch &= ~ATOM_S0_CV_MASK; |
4204 | bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; | |
4205 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; | |
4206 | } | |
4207 | } | |
4208 | if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && | |
4209 | (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { | |
4210 | if (connected) { | |
d9fdaafb | 4211 | DRM_DEBUG_KMS("LCD1 connected\n"); |
771fe6b9 JG |
4212 | bios_0_scratch |= ATOM_S0_LCD1; |
4213 | bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; | |
4214 | bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; | |
4215 | } else { | |
d9fdaafb | 4216 | DRM_DEBUG_KMS("LCD1 disconnected\n"); |
771fe6b9 JG |
4217 | bios_0_scratch &= ~ATOM_S0_LCD1; |
4218 | bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; | |
4219 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; | |
4220 | } | |
4221 | } | |
4222 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && | |
4223 | (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { | |
4224 | if (connected) { | |
d9fdaafb | 4225 | DRM_DEBUG_KMS("CRT1 connected\n"); |
771fe6b9 JG |
4226 | bios_0_scratch |= ATOM_S0_CRT1_COLOR; |
4227 | bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; | |
4228 | bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; | |
4229 | } else { | |
d9fdaafb | 4230 | DRM_DEBUG_KMS("CRT1 disconnected\n"); |
771fe6b9 JG |
4231 | bios_0_scratch &= ~ATOM_S0_CRT1_MASK; |
4232 | bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; | |
4233 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; | |
4234 | } | |
4235 | } | |
4236 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && | |
4237 | (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { | |
4238 | if (connected) { | |
d9fdaafb | 4239 | DRM_DEBUG_KMS("CRT2 connected\n"); |
771fe6b9 JG |
4240 | bios_0_scratch |= ATOM_S0_CRT2_COLOR; |
4241 | bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; | |
4242 | bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; | |
4243 | } else { | |
d9fdaafb | 4244 | DRM_DEBUG_KMS("CRT2 disconnected\n"); |
771fe6b9 JG |
4245 | bios_0_scratch &= ~ATOM_S0_CRT2_MASK; |
4246 | bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; | |
4247 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; | |
4248 | } | |
4249 | } | |
4250 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && | |
4251 | (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { | |
4252 | if (connected) { | |
d9fdaafb | 4253 | DRM_DEBUG_KMS("DFP1 connected\n"); |
771fe6b9 JG |
4254 | bios_0_scratch |= ATOM_S0_DFP1; |
4255 | bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; | |
4256 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; | |
4257 | } else { | |
d9fdaafb | 4258 | DRM_DEBUG_KMS("DFP1 disconnected\n"); |
771fe6b9 JG |
4259 | bios_0_scratch &= ~ATOM_S0_DFP1; |
4260 | bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; | |
4261 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; | |
4262 | } | |
4263 | } | |
4264 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && | |
4265 | (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { | |
4266 | if (connected) { | |
d9fdaafb | 4267 | DRM_DEBUG_KMS("DFP2 connected\n"); |
771fe6b9 JG |
4268 | bios_0_scratch |= ATOM_S0_DFP2; |
4269 | bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; | |
4270 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; | |
4271 | } else { | |
d9fdaafb | 4272 | DRM_DEBUG_KMS("DFP2 disconnected\n"); |
771fe6b9 JG |
4273 | bios_0_scratch &= ~ATOM_S0_DFP2; |
4274 | bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; | |
4275 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; | |
4276 | } | |
4277 | } | |
4278 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && | |
4279 | (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { | |
4280 | if (connected) { | |
d9fdaafb | 4281 | DRM_DEBUG_KMS("DFP3 connected\n"); |
771fe6b9 JG |
4282 | bios_0_scratch |= ATOM_S0_DFP3; |
4283 | bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; | |
4284 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; | |
4285 | } else { | |
d9fdaafb | 4286 | DRM_DEBUG_KMS("DFP3 disconnected\n"); |
771fe6b9 JG |
4287 | bios_0_scratch &= ~ATOM_S0_DFP3; |
4288 | bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; | |
4289 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; | |
4290 | } | |
4291 | } | |
4292 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && | |
4293 | (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { | |
4294 | if (connected) { | |
d9fdaafb | 4295 | DRM_DEBUG_KMS("DFP4 connected\n"); |
771fe6b9 JG |
4296 | bios_0_scratch |= ATOM_S0_DFP4; |
4297 | bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; | |
4298 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; | |
4299 | } else { | |
d9fdaafb | 4300 | DRM_DEBUG_KMS("DFP4 disconnected\n"); |
771fe6b9 JG |
4301 | bios_0_scratch &= ~ATOM_S0_DFP4; |
4302 | bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; | |
4303 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; | |
4304 | } | |
4305 | } | |
4306 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && | |
4307 | (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { | |
4308 | if (connected) { | |
d9fdaafb | 4309 | DRM_DEBUG_KMS("DFP5 connected\n"); |
771fe6b9 JG |
4310 | bios_0_scratch |= ATOM_S0_DFP5; |
4311 | bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; | |
4312 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; | |
4313 | } else { | |
d9fdaafb | 4314 | DRM_DEBUG_KMS("DFP5 disconnected\n"); |
771fe6b9 JG |
4315 | bios_0_scratch &= ~ATOM_S0_DFP5; |
4316 | bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; | |
4317 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; | |
4318 | } | |
4319 | } | |
6f9f8a61 AD |
4320 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) && |
4321 | (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) { | |
4322 | if (connected) { | |
4323 | DRM_DEBUG_KMS("DFP6 connected\n"); | |
4324 | bios_0_scratch |= ATOM_S0_DFP6; | |
4325 | bios_3_scratch |= ATOM_S3_DFP6_ACTIVE; | |
4326 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6; | |
4327 | } else { | |
4328 | DRM_DEBUG_KMS("DFP6 disconnected\n"); | |
4329 | bios_0_scratch &= ~ATOM_S0_DFP6; | |
4330 | bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE; | |
4331 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6; | |
4332 | } | |
4333 | } | |
771fe6b9 JG |
4334 | |
4335 | if (rdev->family >= CHIP_R600) { | |
4336 | WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); | |
4337 | WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); | |
4338 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); | |
4339 | } else { | |
4340 | WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); | |
4341 | WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); | |
4342 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); | |
4343 | } | |
4344 | } | |
4345 | ||
4346 | void | |
4347 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) | |
4348 | { | |
4349 | struct drm_device *dev = encoder->dev; | |
4350 | struct radeon_device *rdev = dev->dev_private; | |
4351 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
4352 | uint32_t bios_3_scratch; | |
4353 | ||
6f9f8a61 AD |
4354 | if (ASIC_IS_DCE4(rdev)) |
4355 | return; | |
4356 | ||
771fe6b9 JG |
4357 | if (rdev->family >= CHIP_R600) |
4358 | bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); | |
4359 | else | |
4360 | bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); | |
4361 | ||
4362 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { | |
4363 | bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; | |
4364 | bios_3_scratch |= (crtc << 18); | |
4365 | } | |
4366 | if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { | |
4367 | bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; | |
4368 | bios_3_scratch |= (crtc << 24); | |
4369 | } | |
4370 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { | |
4371 | bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; | |
4372 | bios_3_scratch |= (crtc << 16); | |
4373 | } | |
4374 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { | |
4375 | bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; | |
4376 | bios_3_scratch |= (crtc << 20); | |
4377 | } | |
4378 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { | |
4379 | bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; | |
4380 | bios_3_scratch |= (crtc << 17); | |
4381 | } | |
4382 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { | |
4383 | bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; | |
4384 | bios_3_scratch |= (crtc << 19); | |
4385 | } | |
4386 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { | |
4387 | bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; | |
4388 | bios_3_scratch |= (crtc << 23); | |
4389 | } | |
4390 | if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { | |
4391 | bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; | |
4392 | bios_3_scratch |= (crtc << 25); | |
4393 | } | |
4394 | ||
4395 | if (rdev->family >= CHIP_R600) | |
4396 | WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); | |
4397 | else | |
4398 | WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); | |
4399 | } | |
4400 | ||
4401 | void | |
4402 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) | |
4403 | { | |
4404 | struct drm_device *dev = encoder->dev; | |
4405 | struct radeon_device *rdev = dev->dev_private; | |
4406 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
4407 | uint32_t bios_2_scratch; | |
4408 | ||
3ac0eb6d AD |
4409 | if (ASIC_IS_DCE4(rdev)) |
4410 | return; | |
4411 | ||
771fe6b9 JG |
4412 | if (rdev->family >= CHIP_R600) |
4413 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); | |
4414 | else | |
4415 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); | |
4416 | ||
4417 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { | |
4418 | if (on) | |
4419 | bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; | |
4420 | else | |
4421 | bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; | |
4422 | } | |
4423 | if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { | |
4424 | if (on) | |
4425 | bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; | |
4426 | else | |
4427 | bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; | |
4428 | } | |
4429 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { | |
4430 | if (on) | |
4431 | bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; | |
4432 | else | |
4433 | bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; | |
4434 | } | |
4435 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { | |
4436 | if (on) | |
4437 | bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; | |
4438 | else | |
4439 | bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; | |
4440 | } | |
4441 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { | |
4442 | if (on) | |
4443 | bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; | |
4444 | else | |
4445 | bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; | |
4446 | } | |
4447 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { | |
4448 | if (on) | |
4449 | bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; | |
4450 | else | |
4451 | bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; | |
4452 | } | |
4453 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { | |
4454 | if (on) | |
4455 | bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; | |
4456 | else | |
4457 | bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; | |
4458 | } | |
4459 | if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { | |
4460 | if (on) | |
4461 | bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; | |
4462 | else | |
4463 | bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; | |
4464 | } | |
4465 | if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { | |
4466 | if (on) | |
4467 | bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; | |
4468 | else | |
4469 | bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; | |
4470 | } | |
4471 | if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { | |
4472 | if (on) | |
4473 | bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; | |
4474 | else | |
4475 | bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; | |
4476 | } | |
4477 | ||
4478 | if (rdev->family >= CHIP_R600) | |
4479 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); | |
4480 | else | |
4481 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); | |
4482 | } |