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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include "drmP.h" | |
29 | #include "radeon_reg.h" | |
30 | #include "radeon.h" | |
31 | #include "atom.h" | |
32 | ||
33 | /* | |
34 | * BIOS. | |
35 | */ | |
36 | static bool radeon_read_bios(struct radeon_device *rdev) | |
37 | { | |
38 | uint8_t __iomem *bios; | |
39 | size_t size; | |
40 | ||
41 | rdev->bios = NULL; | |
42 | bios = pci_map_rom(rdev->pdev, &size); | |
43 | if (!bios) { | |
44 | return false; | |
45 | } | |
46 | ||
47 | if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { | |
48 | pci_unmap_rom(rdev->pdev, bios); | |
49 | return false; | |
50 | } | |
51 | rdev->bios = kmalloc(size, GFP_KERNEL); | |
52 | if (rdev->bios == NULL) { | |
53 | pci_unmap_rom(rdev->pdev, bios); | |
54 | return false; | |
55 | } | |
56 | memcpy(rdev->bios, bios, size); | |
57 | pci_unmap_rom(rdev->pdev, bios); | |
58 | return true; | |
59 | } | |
60 | ||
61 | static bool r700_read_disabled_bios(struct radeon_device *rdev) | |
62 | { | |
63 | uint32_t viph_control; | |
64 | uint32_t bus_cntl; | |
65 | uint32_t d1vga_control; | |
66 | uint32_t d2vga_control; | |
67 | uint32_t vga_render_control; | |
68 | uint32_t rom_cntl; | |
69 | uint32_t cg_spll_func_cntl = 0; | |
70 | uint32_t cg_spll_status; | |
71 | bool r; | |
72 | ||
73 | viph_control = RREG32(RADEON_VIPH_CONTROL); | |
74 | bus_cntl = RREG32(RADEON_BUS_CNTL); | |
75 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); | |
76 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); | |
77 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); | |
78 | rom_cntl = RREG32(R600_ROM_CNTL); | |
79 | ||
80 | /* disable VIP */ | |
81 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); | |
82 | /* enable the rom */ | |
83 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); | |
84 | /* Disable VGA mode */ | |
85 | WREG32(AVIVO_D1VGA_CONTROL, | |
86 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
87 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
88 | WREG32(AVIVO_D2VGA_CONTROL, | |
89 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
90 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
91 | WREG32(AVIVO_VGA_RENDER_CONTROL, | |
92 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); | |
93 | ||
94 | if (rdev->family == CHIP_RV730) { | |
95 | cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); | |
96 | ||
97 | /* enable bypass mode */ | |
98 | WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | | |
99 | R600_SPLL_BYPASS_EN)); | |
100 | ||
101 | /* wait for SPLL_CHG_STATUS to change to 1 */ | |
102 | cg_spll_status = 0; | |
103 | while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) | |
104 | cg_spll_status = RREG32(R600_CG_SPLL_STATUS); | |
105 | ||
106 | WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); | |
107 | } else | |
108 | WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); | |
109 | ||
110 | r = radeon_read_bios(rdev); | |
111 | ||
112 | /* restore regs */ | |
113 | if (rdev->family == CHIP_RV730) { | |
114 | WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); | |
115 | ||
116 | /* wait for SPLL_CHG_STATUS to change to 1 */ | |
117 | cg_spll_status = 0; | |
118 | while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) | |
119 | cg_spll_status = RREG32(R600_CG_SPLL_STATUS); | |
120 | } | |
121 | WREG32(RADEON_VIPH_CONTROL, viph_control); | |
122 | WREG32(RADEON_BUS_CNTL, bus_cntl); | |
123 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); | |
124 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); | |
125 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | |
126 | WREG32(R600_ROM_CNTL, rom_cntl); | |
127 | return r; | |
128 | } | |
129 | ||
130 | static bool r600_read_disabled_bios(struct radeon_device *rdev) | |
131 | { | |
132 | uint32_t viph_control; | |
133 | uint32_t bus_cntl; | |
134 | uint32_t d1vga_control; | |
135 | uint32_t d2vga_control; | |
136 | uint32_t vga_render_control; | |
137 | uint32_t rom_cntl; | |
138 | uint32_t general_pwrmgt; | |
139 | uint32_t low_vid_lower_gpio_cntl; | |
140 | uint32_t medium_vid_lower_gpio_cntl; | |
141 | uint32_t high_vid_lower_gpio_cntl; | |
142 | uint32_t ctxsw_vid_lower_gpio_cntl; | |
143 | uint32_t lower_gpio_enable; | |
144 | bool r; | |
145 | ||
146 | viph_control = RREG32(RADEON_VIPH_CONTROL); | |
147 | bus_cntl = RREG32(RADEON_BUS_CNTL); | |
148 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); | |
149 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); | |
150 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); | |
151 | rom_cntl = RREG32(R600_ROM_CNTL); | |
152 | general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); | |
153 | low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); | |
154 | medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); | |
155 | high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); | |
156 | ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); | |
157 | lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); | |
158 | ||
159 | /* disable VIP */ | |
160 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); | |
161 | /* enable the rom */ | |
162 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); | |
163 | /* Disable VGA mode */ | |
164 | WREG32(AVIVO_D1VGA_CONTROL, | |
165 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
166 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
167 | WREG32(AVIVO_D2VGA_CONTROL, | |
168 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
169 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
170 | WREG32(AVIVO_VGA_RENDER_CONTROL, | |
171 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); | |
172 | ||
173 | WREG32(R600_ROM_CNTL, | |
174 | ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | | |
175 | (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | | |
176 | R600_SCK_OVERWRITE)); | |
177 | ||
178 | WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); | |
179 | WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, | |
180 | (low_vid_lower_gpio_cntl & ~0x400)); | |
181 | WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, | |
182 | (medium_vid_lower_gpio_cntl & ~0x400)); | |
183 | WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, | |
184 | (high_vid_lower_gpio_cntl & ~0x400)); | |
185 | WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, | |
186 | (ctxsw_vid_lower_gpio_cntl & ~0x400)); | |
187 | WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); | |
188 | ||
189 | r = radeon_read_bios(rdev); | |
190 | ||
191 | /* restore regs */ | |
192 | WREG32(RADEON_VIPH_CONTROL, viph_control); | |
193 | WREG32(RADEON_BUS_CNTL, bus_cntl); | |
194 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); | |
195 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); | |
196 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | |
197 | WREG32(R600_ROM_CNTL, rom_cntl); | |
198 | WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); | |
199 | WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); | |
200 | WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); | |
201 | WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); | |
202 | WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); | |
203 | WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); | |
204 | return r; | |
205 | } | |
206 | ||
207 | static bool avivo_read_disabled_bios(struct radeon_device *rdev) | |
208 | { | |
209 | uint32_t seprom_cntl1; | |
210 | uint32_t viph_control; | |
211 | uint32_t bus_cntl; | |
212 | uint32_t d1vga_control; | |
213 | uint32_t d2vga_control; | |
214 | uint32_t vga_render_control; | |
215 | uint32_t gpiopad_a; | |
216 | uint32_t gpiopad_en; | |
217 | uint32_t gpiopad_mask; | |
218 | bool r; | |
219 | ||
220 | seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); | |
221 | viph_control = RREG32(RADEON_VIPH_CONTROL); | |
222 | bus_cntl = RREG32(RADEON_BUS_CNTL); | |
223 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); | |
224 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); | |
225 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); | |
226 | gpiopad_a = RREG32(RADEON_GPIOPAD_A); | |
227 | gpiopad_en = RREG32(RADEON_GPIOPAD_EN); | |
228 | gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); | |
229 | ||
230 | WREG32(RADEON_SEPROM_CNTL1, | |
231 | ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | | |
232 | (0xc << RADEON_SCK_PRESCALE_SHIFT))); | |
233 | WREG32(RADEON_GPIOPAD_A, 0); | |
234 | WREG32(RADEON_GPIOPAD_EN, 0); | |
235 | WREG32(RADEON_GPIOPAD_MASK, 0); | |
236 | ||
237 | /* disable VIP */ | |
238 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); | |
239 | ||
240 | /* enable the rom */ | |
241 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); | |
242 | ||
243 | /* Disable VGA mode */ | |
244 | WREG32(AVIVO_D1VGA_CONTROL, | |
245 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
246 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
247 | WREG32(AVIVO_D2VGA_CONTROL, | |
248 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
249 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
250 | WREG32(AVIVO_VGA_RENDER_CONTROL, | |
251 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); | |
252 | ||
253 | r = radeon_read_bios(rdev); | |
254 | ||
255 | /* restore regs */ | |
256 | WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); | |
257 | WREG32(RADEON_VIPH_CONTROL, viph_control); | |
258 | WREG32(RADEON_BUS_CNTL, bus_cntl); | |
259 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); | |
260 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); | |
261 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | |
262 | WREG32(RADEON_GPIOPAD_A, gpiopad_a); | |
263 | WREG32(RADEON_GPIOPAD_EN, gpiopad_en); | |
264 | WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); | |
265 | return r; | |
266 | } | |
267 | ||
268 | static bool legacy_read_disabled_bios(struct radeon_device *rdev) | |
269 | { | |
270 | uint32_t seprom_cntl1; | |
271 | uint32_t viph_control; | |
272 | uint32_t bus_cntl; | |
273 | uint32_t crtc_gen_cntl; | |
274 | uint32_t crtc2_gen_cntl; | |
275 | uint32_t crtc_ext_cntl; | |
276 | uint32_t fp2_gen_cntl; | |
277 | bool r; | |
278 | ||
279 | seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); | |
280 | viph_control = RREG32(RADEON_VIPH_CONTROL); | |
281 | bus_cntl = RREG32(RADEON_BUS_CNTL); | |
282 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); | |
283 | crtc2_gen_cntl = 0; | |
284 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); | |
285 | fp2_gen_cntl = 0; | |
286 | ||
287 | if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { | |
288 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); | |
289 | } | |
290 | ||
291 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
292 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); | |
293 | } | |
294 | ||
295 | WREG32(RADEON_SEPROM_CNTL1, | |
296 | ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | | |
297 | (0xc << RADEON_SCK_PRESCALE_SHIFT))); | |
298 | ||
299 | /* disable VIP */ | |
300 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); | |
301 | ||
302 | /* enable the rom */ | |
303 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); | |
304 | ||
305 | /* Turn off mem requests and CRTC for both controllers */ | |
306 | WREG32(RADEON_CRTC_GEN_CNTL, | |
307 | ((crtc_gen_cntl & ~RADEON_CRTC_EN) | | |
308 | (RADEON_CRTC_DISP_REQ_EN_B | | |
309 | RADEON_CRTC_EXT_DISP_EN))); | |
310 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
311 | WREG32(RADEON_CRTC2_GEN_CNTL, | |
312 | ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | | |
313 | RADEON_CRTC2_DISP_REQ_EN_B)); | |
314 | } | |
315 | /* Turn off CRTC */ | |
316 | WREG32(RADEON_CRTC_EXT_CNTL, | |
317 | ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | | |
318 | (RADEON_CRTC_SYNC_TRISTAT | | |
319 | RADEON_CRTC_DISPLAY_DIS))); | |
320 | ||
321 | if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { | |
322 | WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); | |
323 | } | |
324 | ||
325 | r = radeon_read_bios(rdev); | |
326 | ||
327 | /* restore regs */ | |
328 | WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); | |
329 | WREG32(RADEON_VIPH_CONTROL, viph_control); | |
330 | WREG32(RADEON_BUS_CNTL, bus_cntl); | |
331 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); | |
332 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
333 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); | |
334 | } | |
335 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); | |
336 | if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { | |
337 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); | |
338 | } | |
339 | return r; | |
340 | } | |
341 | ||
342 | static bool radeon_read_disabled_bios(struct radeon_device *rdev) | |
343 | { | |
344 | if (rdev->family >= CHIP_RV770) | |
345 | return r700_read_disabled_bios(rdev); | |
346 | else if (rdev->family >= CHIP_R600) | |
347 | return r600_read_disabled_bios(rdev); | |
348 | else if (rdev->family >= CHIP_RS600) | |
349 | return avivo_read_disabled_bios(rdev); | |
350 | else | |
351 | return legacy_read_disabled_bios(rdev); | |
352 | } | |
353 | ||
354 | bool radeon_get_bios(struct radeon_device *rdev) | |
355 | { | |
356 | bool r; | |
357 | uint16_t tmp; | |
358 | ||
359 | r = radeon_read_bios(rdev); | |
360 | if (r == false) { | |
361 | r = radeon_read_disabled_bios(rdev); | |
362 | } | |
363 | if (r == false || rdev->bios == NULL) { | |
364 | DRM_ERROR("Unable to locate a BIOS ROM\n"); | |
365 | rdev->bios = NULL; | |
366 | return false; | |
367 | } | |
368 | if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { | |
369 | goto free_bios; | |
370 | } | |
371 | ||
372 | rdev->bios_header_start = RBIOS16(0x48); | |
373 | if (!rdev->bios_header_start) { | |
374 | goto free_bios; | |
375 | } | |
376 | tmp = rdev->bios_header_start + 4; | |
377 | if (!memcmp(rdev->bios + tmp, "ATOM", 4) || | |
378 | !memcmp(rdev->bios + tmp, "MOTA", 4)) { | |
379 | rdev->is_atom_bios = true; | |
380 | } else { | |
381 | rdev->is_atom_bios = false; | |
382 | } | |
383 | ||
384 | DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); | |
385 | return true; | |
386 | free_bios: | |
387 | kfree(rdev->bios); | |
388 | rdev->bios = NULL; | |
389 | return false; | |
390 | } |