]>
Commit | Line | Data |
---|---|---|
771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include "drmP.h" | |
29 | #include "radeon_reg.h" | |
30 | #include "radeon.h" | |
31 | #include "atom.h" | |
32 | ||
6a9ee8af | 33 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
771fe6b9 JG |
35 | /* |
36 | * BIOS. | |
37 | */ | |
b442962a AD |
38 | |
39 | /* If you boot an IGP board with a discrete card as the primary, | |
40 | * the IGP rom is not accessible via the rom bar as the IGP rom is | |
41 | * part of the system bios. On boot, the system bios puts a | |
42 | * copy of the igp rom at the start of vram if a discrete card is | |
43 | * present. | |
44 | */ | |
45 | static bool igp_read_bios_from_vram(struct radeon_device *rdev) | |
46 | { | |
47 | uint8_t __iomem *bios; | |
48 | resource_size_t vram_base; | |
49 | resource_size_t size = 256 * 1024; /* ??? */ | |
50 | ||
8b5d8dec DA |
51 | if (!(rdev->flags & RADEON_IS_IGP)) |
52 | if (!radeon_card_posted(rdev)) | |
53 | return false; | |
54 | ||
b442962a | 55 | rdev->bios = NULL; |
01d73a69 | 56 | vram_base = pci_resource_start(rdev->pdev, 0); |
b442962a AD |
57 | bios = ioremap(vram_base, size); |
58 | if (!bios) { | |
b442962a AD |
59 | return false; |
60 | } | |
61 | ||
62 | if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { | |
63 | iounmap(bios); | |
b442962a AD |
64 | return false; |
65 | } | |
66 | rdev->bios = kmalloc(size, GFP_KERNEL); | |
67 | if (rdev->bios == NULL) { | |
68 | iounmap(bios); | |
b442962a AD |
69 | return false; |
70 | } | |
6a9ee8af | 71 | memcpy_fromio(rdev->bios, bios, size); |
b442962a AD |
72 | iounmap(bios); |
73 | return true; | |
74 | } | |
75 | ||
771fe6b9 JG |
76 | static bool radeon_read_bios(struct radeon_device *rdev) |
77 | { | |
78 | uint8_t __iomem *bios; | |
79 | size_t size; | |
80 | ||
81 | rdev->bios = NULL; | |
b442962a | 82 | /* XXX: some cards may return 0 for rom size? ddx has a workaround */ |
771fe6b9 JG |
83 | bios = pci_map_rom(rdev->pdev, &size); |
84 | if (!bios) { | |
85 | return false; | |
86 | } | |
87 | ||
88 | if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { | |
89 | pci_unmap_rom(rdev->pdev, bios); | |
90 | return false; | |
91 | } | |
f405a1ab | 92 | rdev->bios = kmemdup(bios, size, GFP_KERNEL); |
771fe6b9 JG |
93 | if (rdev->bios == NULL) { |
94 | pci_unmap_rom(rdev->pdev, bios); | |
95 | return false; | |
96 | } | |
771fe6b9 JG |
97 | pci_unmap_rom(rdev->pdev, bios); |
98 | return true; | |
99 | } | |
100 | ||
6a9ee8af DA |
101 | /* ATRM is used to get the BIOS on the discrete cards in |
102 | * dual-gpu systems. | |
103 | */ | |
104 | static bool radeon_atrm_get_bios(struct radeon_device *rdev) | |
105 | { | |
106 | int ret; | |
b271a988 | 107 | int size = 256 * 1024; |
6a9ee8af DA |
108 | int i; |
109 | ||
110 | if (!radeon_atrm_supported(rdev->pdev)) | |
111 | return false; | |
112 | ||
113 | rdev->bios = kmalloc(size, GFP_KERNEL); | |
114 | if (!rdev->bios) { | |
115 | DRM_ERROR("Unable to allocate bios\n"); | |
116 | return false; | |
117 | } | |
118 | ||
119 | for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { | |
120 | ret = radeon_atrm_get_bios_chunk(rdev->bios, | |
121 | (i * ATRM_BIOS_PAGE), | |
122 | ATRM_BIOS_PAGE); | |
123 | if (ret <= 0) | |
124 | break; | |
125 | } | |
126 | ||
127 | if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { | |
128 | kfree(rdev->bios); | |
129 | return false; | |
130 | } | |
131 | return true; | |
132 | } | |
0ec80d64 | 133 | |
c901bcdd AD |
134 | static bool ni_read_disabled_bios(struct radeon_device *rdev) |
135 | { | |
136 | u32 bus_cntl; | |
137 | u32 d1vga_control; | |
138 | u32 d2vga_control; | |
139 | u32 vga_render_control; | |
140 | u32 rom_cntl; | |
141 | bool r; | |
142 | ||
143 | bus_cntl = RREG32(R600_BUS_CNTL); | |
144 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); | |
145 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); | |
146 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); | |
147 | rom_cntl = RREG32(R600_ROM_CNTL); | |
148 | ||
149 | /* enable the rom */ | |
150 | WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); | |
151 | /* Disable VGA mode */ | |
152 | WREG32(AVIVO_D1VGA_CONTROL, | |
153 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
154 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
155 | WREG32(AVIVO_D2VGA_CONTROL, | |
156 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
157 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
158 | WREG32(AVIVO_VGA_RENDER_CONTROL, | |
159 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); | |
160 | WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); | |
161 | ||
162 | r = radeon_read_bios(rdev); | |
163 | ||
164 | /* restore regs */ | |
165 | WREG32(R600_BUS_CNTL, bus_cntl); | |
166 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); | |
167 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); | |
168 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | |
169 | WREG32(R600_ROM_CNTL, rom_cntl); | |
170 | return r; | |
171 | } | |
172 | ||
771fe6b9 JG |
173 | static bool r700_read_disabled_bios(struct radeon_device *rdev) |
174 | { | |
175 | uint32_t viph_control; | |
176 | uint32_t bus_cntl; | |
177 | uint32_t d1vga_control; | |
178 | uint32_t d2vga_control; | |
179 | uint32_t vga_render_control; | |
180 | uint32_t rom_cntl; | |
181 | uint32_t cg_spll_func_cntl = 0; | |
182 | uint32_t cg_spll_status; | |
183 | bool r; | |
184 | ||
185 | viph_control = RREG32(RADEON_VIPH_CONTROL); | |
0ec80d64 | 186 | bus_cntl = RREG32(R600_BUS_CNTL); |
771fe6b9 JG |
187 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
188 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); | |
189 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); | |
190 | rom_cntl = RREG32(R600_ROM_CNTL); | |
191 | ||
192 | /* disable VIP */ | |
193 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); | |
194 | /* enable the rom */ | |
0ec80d64 | 195 | WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); |
771fe6b9 JG |
196 | /* Disable VGA mode */ |
197 | WREG32(AVIVO_D1VGA_CONTROL, | |
198 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
199 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
200 | WREG32(AVIVO_D2VGA_CONTROL, | |
201 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
202 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
203 | WREG32(AVIVO_VGA_RENDER_CONTROL, | |
204 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); | |
205 | ||
206 | if (rdev->family == CHIP_RV730) { | |
207 | cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); | |
208 | ||
209 | /* enable bypass mode */ | |
210 | WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | | |
211 | R600_SPLL_BYPASS_EN)); | |
212 | ||
213 | /* wait for SPLL_CHG_STATUS to change to 1 */ | |
214 | cg_spll_status = 0; | |
215 | while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) | |
216 | cg_spll_status = RREG32(R600_CG_SPLL_STATUS); | |
217 | ||
218 | WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); | |
219 | } else | |
220 | WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); | |
221 | ||
222 | r = radeon_read_bios(rdev); | |
223 | ||
224 | /* restore regs */ | |
225 | if (rdev->family == CHIP_RV730) { | |
226 | WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); | |
227 | ||
228 | /* wait for SPLL_CHG_STATUS to change to 1 */ | |
229 | cg_spll_status = 0; | |
230 | while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) | |
231 | cg_spll_status = RREG32(R600_CG_SPLL_STATUS); | |
232 | } | |
233 | WREG32(RADEON_VIPH_CONTROL, viph_control); | |
0ec80d64 | 234 | WREG32(R600_BUS_CNTL, bus_cntl); |
771fe6b9 JG |
235 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
236 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); | |
237 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | |
238 | WREG32(R600_ROM_CNTL, rom_cntl); | |
239 | return r; | |
240 | } | |
241 | ||
242 | static bool r600_read_disabled_bios(struct radeon_device *rdev) | |
243 | { | |
244 | uint32_t viph_control; | |
245 | uint32_t bus_cntl; | |
246 | uint32_t d1vga_control; | |
247 | uint32_t d2vga_control; | |
248 | uint32_t vga_render_control; | |
249 | uint32_t rom_cntl; | |
250 | uint32_t general_pwrmgt; | |
251 | uint32_t low_vid_lower_gpio_cntl; | |
252 | uint32_t medium_vid_lower_gpio_cntl; | |
253 | uint32_t high_vid_lower_gpio_cntl; | |
254 | uint32_t ctxsw_vid_lower_gpio_cntl; | |
255 | uint32_t lower_gpio_enable; | |
256 | bool r; | |
257 | ||
258 | viph_control = RREG32(RADEON_VIPH_CONTROL); | |
0ec80d64 | 259 | bus_cntl = RREG32(R600_BUS_CNTL); |
771fe6b9 JG |
260 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
261 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); | |
262 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); | |
263 | rom_cntl = RREG32(R600_ROM_CNTL); | |
264 | general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); | |
265 | low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); | |
266 | medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); | |
267 | high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); | |
268 | ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); | |
269 | lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); | |
270 | ||
271 | /* disable VIP */ | |
272 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); | |
273 | /* enable the rom */ | |
0ec80d64 | 274 | WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); |
771fe6b9 JG |
275 | /* Disable VGA mode */ |
276 | WREG32(AVIVO_D1VGA_CONTROL, | |
277 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
278 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
279 | WREG32(AVIVO_D2VGA_CONTROL, | |
280 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
281 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
282 | WREG32(AVIVO_VGA_RENDER_CONTROL, | |
283 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); | |
284 | ||
285 | WREG32(R600_ROM_CNTL, | |
286 | ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | | |
287 | (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | | |
288 | R600_SCK_OVERWRITE)); | |
289 | ||
290 | WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); | |
291 | WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, | |
292 | (low_vid_lower_gpio_cntl & ~0x400)); | |
293 | WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, | |
294 | (medium_vid_lower_gpio_cntl & ~0x400)); | |
295 | WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, | |
296 | (high_vid_lower_gpio_cntl & ~0x400)); | |
297 | WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, | |
298 | (ctxsw_vid_lower_gpio_cntl & ~0x400)); | |
299 | WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); | |
300 | ||
301 | r = radeon_read_bios(rdev); | |
302 | ||
303 | /* restore regs */ | |
304 | WREG32(RADEON_VIPH_CONTROL, viph_control); | |
0ec80d64 | 305 | WREG32(R600_BUS_CNTL, bus_cntl); |
771fe6b9 JG |
306 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
307 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); | |
308 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | |
309 | WREG32(R600_ROM_CNTL, rom_cntl); | |
310 | WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); | |
311 | WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); | |
312 | WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); | |
313 | WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); | |
314 | WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); | |
315 | WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); | |
316 | return r; | |
317 | } | |
318 | ||
319 | static bool avivo_read_disabled_bios(struct radeon_device *rdev) | |
320 | { | |
321 | uint32_t seprom_cntl1; | |
322 | uint32_t viph_control; | |
323 | uint32_t bus_cntl; | |
324 | uint32_t d1vga_control; | |
325 | uint32_t d2vga_control; | |
326 | uint32_t vga_render_control; | |
327 | uint32_t gpiopad_a; | |
328 | uint32_t gpiopad_en; | |
329 | uint32_t gpiopad_mask; | |
330 | bool r; | |
331 | ||
332 | seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); | |
333 | viph_control = RREG32(RADEON_VIPH_CONTROL); | |
334 | bus_cntl = RREG32(RADEON_BUS_CNTL); | |
335 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); | |
336 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); | |
337 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); | |
338 | gpiopad_a = RREG32(RADEON_GPIOPAD_A); | |
339 | gpiopad_en = RREG32(RADEON_GPIOPAD_EN); | |
340 | gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); | |
341 | ||
342 | WREG32(RADEON_SEPROM_CNTL1, | |
343 | ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | | |
344 | (0xc << RADEON_SCK_PRESCALE_SHIFT))); | |
345 | WREG32(RADEON_GPIOPAD_A, 0); | |
346 | WREG32(RADEON_GPIOPAD_EN, 0); | |
347 | WREG32(RADEON_GPIOPAD_MASK, 0); | |
348 | ||
349 | /* disable VIP */ | |
350 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); | |
351 | ||
352 | /* enable the rom */ | |
353 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); | |
354 | ||
355 | /* Disable VGA mode */ | |
356 | WREG32(AVIVO_D1VGA_CONTROL, | |
357 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
358 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
359 | WREG32(AVIVO_D2VGA_CONTROL, | |
360 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
361 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
362 | WREG32(AVIVO_VGA_RENDER_CONTROL, | |
363 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); | |
364 | ||
365 | r = radeon_read_bios(rdev); | |
366 | ||
367 | /* restore regs */ | |
368 | WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); | |
369 | WREG32(RADEON_VIPH_CONTROL, viph_control); | |
370 | WREG32(RADEON_BUS_CNTL, bus_cntl); | |
371 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); | |
372 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); | |
373 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | |
374 | WREG32(RADEON_GPIOPAD_A, gpiopad_a); | |
375 | WREG32(RADEON_GPIOPAD_EN, gpiopad_en); | |
376 | WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); | |
377 | return r; | |
378 | } | |
379 | ||
380 | static bool legacy_read_disabled_bios(struct radeon_device *rdev) | |
381 | { | |
382 | uint32_t seprom_cntl1; | |
383 | uint32_t viph_control; | |
384 | uint32_t bus_cntl; | |
385 | uint32_t crtc_gen_cntl; | |
386 | uint32_t crtc2_gen_cntl; | |
387 | uint32_t crtc_ext_cntl; | |
388 | uint32_t fp2_gen_cntl; | |
389 | bool r; | |
390 | ||
391 | seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); | |
392 | viph_control = RREG32(RADEON_VIPH_CONTROL); | |
393 | bus_cntl = RREG32(RADEON_BUS_CNTL); | |
394 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); | |
395 | crtc2_gen_cntl = 0; | |
396 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); | |
397 | fp2_gen_cntl = 0; | |
398 | ||
399 | if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { | |
400 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); | |
401 | } | |
402 | ||
403 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
404 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); | |
405 | } | |
406 | ||
407 | WREG32(RADEON_SEPROM_CNTL1, | |
408 | ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | | |
409 | (0xc << RADEON_SCK_PRESCALE_SHIFT))); | |
410 | ||
411 | /* disable VIP */ | |
412 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); | |
413 | ||
414 | /* enable the rom */ | |
415 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); | |
416 | ||
417 | /* Turn off mem requests and CRTC for both controllers */ | |
418 | WREG32(RADEON_CRTC_GEN_CNTL, | |
419 | ((crtc_gen_cntl & ~RADEON_CRTC_EN) | | |
420 | (RADEON_CRTC_DISP_REQ_EN_B | | |
421 | RADEON_CRTC_EXT_DISP_EN))); | |
422 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
423 | WREG32(RADEON_CRTC2_GEN_CNTL, | |
424 | ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | | |
425 | RADEON_CRTC2_DISP_REQ_EN_B)); | |
426 | } | |
427 | /* Turn off CRTC */ | |
428 | WREG32(RADEON_CRTC_EXT_CNTL, | |
429 | ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | | |
430 | (RADEON_CRTC_SYNC_TRISTAT | | |
431 | RADEON_CRTC_DISPLAY_DIS))); | |
432 | ||
433 | if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { | |
434 | WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); | |
435 | } | |
436 | ||
437 | r = radeon_read_bios(rdev); | |
438 | ||
439 | /* restore regs */ | |
440 | WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); | |
441 | WREG32(RADEON_VIPH_CONTROL, viph_control); | |
442 | WREG32(RADEON_BUS_CNTL, bus_cntl); | |
443 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); | |
444 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
445 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); | |
446 | } | |
447 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); | |
448 | if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { | |
449 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); | |
450 | } | |
451 | return r; | |
452 | } | |
453 | ||
454 | static bool radeon_read_disabled_bios(struct radeon_device *rdev) | |
455 | { | |
b442962a AD |
456 | if (rdev->flags & RADEON_IS_IGP) |
457 | return igp_read_bios_from_vram(rdev); | |
c901bcdd AD |
458 | else if (rdev->family >= CHIP_BARTS) |
459 | return ni_read_disabled_bios(rdev); | |
b442962a | 460 | else if (rdev->family >= CHIP_RV770) |
771fe6b9 JG |
461 | return r700_read_disabled_bios(rdev); |
462 | else if (rdev->family >= CHIP_R600) | |
463 | return r600_read_disabled_bios(rdev); | |
464 | else if (rdev->family >= CHIP_RS600) | |
465 | return avivo_read_disabled_bios(rdev); | |
466 | else | |
467 | return legacy_read_disabled_bios(rdev); | |
468 | } | |
469 | ||
6a9ee8af | 470 | |
771fe6b9 JG |
471 | bool radeon_get_bios(struct radeon_device *rdev) |
472 | { | |
473 | bool r; | |
474 | uint16_t tmp; | |
475 | ||
6a9ee8af DA |
476 | r = radeon_atrm_get_bios(rdev); |
477 | if (r == false) | |
b442962a | 478 | r = igp_read_bios_from_vram(rdev); |
6a9ee8af | 479 | if (r == false) |
b442962a | 480 | r = radeon_read_bios(rdev); |
771fe6b9 JG |
481 | if (r == false) { |
482 | r = radeon_read_disabled_bios(rdev); | |
483 | } | |
484 | if (r == false || rdev->bios == NULL) { | |
485 | DRM_ERROR("Unable to locate a BIOS ROM\n"); | |
486 | rdev->bios = NULL; | |
487 | return false; | |
488 | } | |
489 | if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { | |
6a9ee8af | 490 | printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); |
771fe6b9 JG |
491 | goto free_bios; |
492 | } | |
493 | ||
e3439895 DA |
494 | tmp = RBIOS16(0x18); |
495 | if (RBIOS8(tmp + 0x14) != 0x0) { | |
496 | DRM_INFO("Not an x86 BIOS ROM, not using.\n"); | |
497 | goto free_bios; | |
498 | } | |
499 | ||
771fe6b9 JG |
500 | rdev->bios_header_start = RBIOS16(0x48); |
501 | if (!rdev->bios_header_start) { | |
502 | goto free_bios; | |
503 | } | |
504 | tmp = rdev->bios_header_start + 4; | |
505 | if (!memcmp(rdev->bios + tmp, "ATOM", 4) || | |
506 | !memcmp(rdev->bios + tmp, "MOTA", 4)) { | |
507 | rdev->is_atom_bios = true; | |
508 | } else { | |
509 | rdev->is_atom_bios = false; | |
510 | } | |
511 | ||
512 | DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); | |
513 | return true; | |
514 | free_bios: | |
515 | kfree(rdev->bios); | |
516 | rdev->bios = NULL; | |
517 | return false; | |
518 | } |