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Merge branch 'topic/lx6464es' into for-linus
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / radeon_cp.c
CommitLineData
f26c473c
DA		 1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2/*
1da177e4
LT		 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
45e51905 5 * Copyright 2007 Advanced Micro Devices, Inc.
1da177e4
LT		 6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32#include "drmP.h"
33#include "drm.h"
7c1c2871 34#include "drm_sarea.h"
1da177e4
LT		 35#include "radeon_drm.h"
36#include "radeon_drv.h"
414ed537 37#include "r300_reg.h"
1da177e4 38
9f18409e
AD		 39#include "radeon_microcode.h"
40
1da177e4
LT		 41#define RADEON_FIFO_DEBUG 0
42
84b1fd10 43static int radeon_do_cleanup_cp(struct drm_device * dev);
54f961a6 44static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
1da177e4 45
c05ce083 46u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
b07fa022
DM		 47{
48 u32 val;
49
50 if (dev_priv->flags & RADEON_IS_AGP) {
51 val = DRM_READ32(dev_priv->ring_rptr, off);
52 } else {
53 val = *(((volatile u32 *)
54 dev_priv->ring_rptr->handle) +
55 (off / sizeof(u32)));
56 val = le32_to_cpu(val);
57 }
58 return val;
59}
60
61u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
62{
63 if (dev_priv->writeback_works)
64 return radeon_read_ring_rptr(dev_priv, 0);
c05ce083
AD		 65 else {
66 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
67 return RADEON_READ(R600_CP_RB_RPTR);
68 else
69 return RADEON_READ(RADEON_CP_RB_RPTR);
70 }
b07fa022
DM		 71}
72
c05ce083 73void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
b07fa022
DM		 74{
75 if (dev_priv->flags & RADEON_IS_AGP)
76 DRM_WRITE32(dev_priv->ring_rptr, off, val);
77 else
78 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
79 (off / sizeof(u32))) = cpu_to_le32(val);
80}
81
82void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
83{
84 radeon_write_ring_rptr(dev_priv, 0, val);
85}
86
87u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
88{
c05ce083
AD		 89 if (dev_priv->writeback_works) {
90 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
91 return radeon_read_ring_rptr(dev_priv,
92 R600_SCRATCHOFF(index));
93 else
94 return radeon_read_ring_rptr(dev_priv,
95 RADEON_SCRATCHOFF(index));
96 } else {
97 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
98 return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
99 else
100 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
101 }
b07fa022
DM		 102}
103
befb73c2
AD		 104u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
105{
106 u32 ret;
107
108 if (addr < 0x10000)
109 ret = DRM_READ32(dev_priv->mmio, addr);
110 else {
111 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
112 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
113 }
114
115 return ret;
116}
117
45e51905 118static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
3d5e2c13
DA		 119{
120 u32 ret;
121 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
122 ret = RADEON_READ(R520_MC_IND_DATA);
123 RADEON_WRITE(R520_MC_IND_INDEX, 0);
124 return ret;
125}
126
45e51905
AD		 127static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
128{
129 u32 ret;
130 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
131 ret = RADEON_READ(RS480_NB_MC_DATA);
132 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
133 return ret;
134}
135
60f92683
MC		 136static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
137{
45e51905 138 u32 ret;
60f92683 139 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
45e51905
AD		 140 ret = RADEON_READ(RS690_MC_DATA);
141 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
142 return ret;
143}
144
c1556f71
AD		 145static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
146{
147 u32 ret;
148 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
149 RS600_MC_IND_CITF_ARB0));
150 ret = RADEON_READ(RS600_MC_DATA);
151 return ret;
152}
153
45e51905
AD		 154static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
155{
f0738e92
AD		 156 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
157 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
45e51905 158 return RS690_READ_MCIND(dev_priv, addr);
c1556f71
AD		 159 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
160 return RS600_READ_MCIND(dev_priv, addr);
45e51905
AD		 161 else
162 return RS480_READ_MCIND(dev_priv, addr);
60f92683
MC		 163}
164
3d5e2c13
DA		 165u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
166{
167
c05ce083
AD		 168 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
169 return RADEON_READ(R700_MC_VM_FB_LOCATION);
170 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
171 return RADEON_READ(R600_MC_VM_FB_LOCATION);
172 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
45e51905 173 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
f0738e92
AD		 174 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
175 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
60f92683 176 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
c1556f71
AD		 177 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
178 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
3d5e2c13 179 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
45e51905 180 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
3d5e2c13
DA		 181 else
182 return RADEON_READ(RADEON_MC_FB_LOCATION);
183}
184
185static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
186{
c05ce083
AD		 187 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
188 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
189 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
190 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
191 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
45e51905 192 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
f0738e92
AD		 193 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
194 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
60f92683 195 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
c1556f71
AD		 196 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
197 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
3d5e2c13 198 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
45e51905 199 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
3d5e2c13
DA		 200 else
201 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
202}
203
c05ce083 204void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
3d5e2c13 205{
c05ce083
AD		 206 /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
207 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
208 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
209 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
210 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
211 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
212 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
213 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
45e51905 214 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
f0738e92
AD		 215 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
216 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
60f92683 217 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
c1556f71
AD		 218 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
219 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
3d5e2c13 220 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
45e51905 221 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
3d5e2c13
DA		 222 else
223 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
224}
225
c05ce083 226void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
70b13d51
DA		 227{
228 u32 agp_base_hi = upper_32_bits(agp_base);
229 u32 agp_base_lo = agp_base & 0xffffffff;
c05ce083
AD		 230 u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
231
232 /* R6xx/R7xx must be aligned to a 4MB boundry */
233 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
234 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
235 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
236 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
237 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
70b13d51
DA		 238 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
239 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
f0738e92
AD		 240 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
241 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
70b13d51
DA		 242 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
243 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
c1556f71
AD		 244 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
245 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
246 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
70b13d51
DA		 247 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
248 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
249 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
b2ceddfa
AD		 250 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
251 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
5cfb6956 252 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
b2ceddfa 253 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
70b13d51
DA		 254 } else {
255 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
256 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
257 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
258 }
259}
260
c05ce083 261void radeon_enable_bm(struct drm_radeon_private *dev_priv)
dd8d7cb4
DA		 262{
263 u32 tmp;
264 /* Turn on bus mastering */
265 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
266 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
267 /* rs600/rs690/rs740 */
268 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
269 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
270 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
271 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
272 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
273 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
274 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
275 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
276 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
277 } /* PCIE cards appears to not need this */
278}
279
84b1fd10 280static int RADEON_READ_PLL(struct drm_device * dev, int addr)
1da177e4
LT		 281{
282 drm_radeon_private_t *dev_priv = dev->dev_private;
283
284 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
285 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
286}
287
3d5e2c13 288static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
ea98a92f
DA		 289{
290 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
291 return RADEON_READ(RADEON_PCIE_DATA);
292}
293
1da177e4 294#if RADEON_FIFO_DEBUG
b5e89ed5 295static void radeon_status(drm_radeon_private_t * dev_priv)
1da177e4 296{
bf9d8929 297 printk("%s:\n", __func__);
b5e89ed5
DA		 298 printk("RBBM_STATUS = 0x%08x\n",
299 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
300 printk("CP_RB_RTPR = 0x%08x\n",
301 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
302 printk("CP_RB_WTPR = 0x%08x\n",
303 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
304 printk("AIC_CNTL = 0x%08x\n",
305 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
306 printk("AIC_STAT = 0x%08x\n",
307 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
308 printk("AIC_PT_BASE = 0x%08x\n",
309 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
310 printk("TLB_ADDR = 0x%08x\n",
311 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
312 printk("TLB_DATA = 0x%08x\n",
313 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
1da177e4
LT		 314}
315#endif
316
1da177e4
LT		 317/* ================================================================
318 * Engine, FIFO control
319 */
320
b5e89ed5 321static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
1da177e4
LT		 322{
323 u32 tmp;
324 int i;
325
326 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
327
259434ac
AD		 328 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
329 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
330 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
331 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
332
333 for (i = 0; i < dev_priv->usec_timeout; i++) {
334 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
335 & RADEON_RB3D_DC_BUSY)) {
336 return 0;
337 }
338 DRM_UDELAY(1);
339 }
340 } else {
54f961a6
JG		 341 /* don't flush or purge cache here or lockup */
342 return 0;
1da177e4
LT		 343 }
344
345#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 346 DRM_ERROR("failed!\n");
347 radeon_status(dev_priv);
1da177e4 348#endif
20caafa6 349 return -EBUSY;
1da177e4
LT		 350}
351
b5e89ed5 352static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
1da177e4
LT		 353{
354 int i;
355
356 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
357
b5e89ed5
DA		 358 for (i = 0; i < dev_priv->usec_timeout; i++) {
359 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
360 & RADEON_RBBM_FIFOCNT_MASK);
361 if (slots >= entries)
362 return 0;
363 DRM_UDELAY(1);
1da177e4 364 }
6c7be298 365 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
54f961a6
JG		 366 RADEON_READ(RADEON_RBBM_STATUS),
367 RADEON_READ(R300_VAP_CNTL_STATUS));
1da177e4
LT		 368
369#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 370 DRM_ERROR("failed!\n");
371 radeon_status(dev_priv);
1da177e4 372#endif
20caafa6 373 return -EBUSY;
1da177e4
LT		 374}
375
b5e89ed5 376static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
1da177e4
LT		 377{
378 int i, ret;
379
380 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
381
b5e89ed5
DA		 382 ret = radeon_do_wait_for_fifo(dev_priv, 64);
383 if (ret)
384 return ret;
1da177e4 385
b5e89ed5
DA		 386 for (i = 0; i < dev_priv->usec_timeout; i++) {
387 if (!(RADEON_READ(RADEON_RBBM_STATUS)
388 & RADEON_RBBM_ACTIVE)) {
389 radeon_do_pixcache_flush(dev_priv);
1da177e4
LT		 390 return 0;
391 }
b5e89ed5 392 DRM_UDELAY(1);
1da177e4 393 }
6c7be298 394 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
54f961a6
JG		 395 RADEON_READ(RADEON_RBBM_STATUS),
396 RADEON_READ(R300_VAP_CNTL_STATUS));
1da177e4
LT		 397
398#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 399 DRM_ERROR("failed!\n");
400 radeon_status(dev_priv);
1da177e4 401#endif
20caafa6 402 return -EBUSY;
1da177e4
LT		 403}
404
5b92c404
AD		 405static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
406{
407 uint32_t gb_tile_config, gb_pipe_sel = 0;
408
409 /* RS4xx/RS6xx/R4xx/R5xx */
410 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
411 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
412 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
413 } else {
414 /* R3xx */
415 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
416 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
417 dev_priv->num_gb_pipes = 2;
418 } else {
419 /* R3Vxx */
420 dev_priv->num_gb_pipes = 1;
421 }
422 }
423 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
424
425 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
426
427 switch (dev_priv->num_gb_pipes) {
428 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
429 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
430 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
431 default:
432 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
433 }
434
435 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
436 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
af7ae351 437 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
5b92c404
AD		 438 }
439 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
440 radeon_do_wait_for_idle(dev_priv);
441 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
442 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
443 R300_DC_AUTOFLUSH_ENABLE |
444 R300_DC_DC_DISABLE_IGNORE_PE));
445
446
447}
448
1da177e4
LT		 449/* ================================================================
450 * CP control, initialization
451 */
452
453/* Load the microcode for the CP */
b5e89ed5 454static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
1da177e4
LT		 455{
456 int i;
b5e89ed5 457 DRM_DEBUG("\n");
1da177e4 458
b5e89ed5 459 radeon_do_wait_for_idle(dev_priv);
1da177e4 460
b5e89ed5 461 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
9f18409e
AD		 462 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
463 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
464 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
465 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
466 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
467 DRM_INFO("Loading R100 Microcode\n");
468 for (i = 0; i < 256; i++) {
469 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
470 R100_cp_microcode[i][1]);
471 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
472 R100_cp_microcode[i][0]);
473 }
474 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
475 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
476 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
477 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
1da177e4 478 DRM_INFO("Loading R200 Microcode\n");
b5e89ed5
DA		 479 for (i = 0; i < 256; i++) {
480 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
481 R200_cp_microcode[i][1]);
482 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
483 R200_cp_microcode[i][0]);
1da177e4 484 }
9f18409e
AD		 485 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
486 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
487 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
488 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
b2ceddfa 489 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
45e51905 490 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
1da177e4 491 DRM_INFO("Loading R300 Microcode\n");
b5e89ed5
DA		 492 for (i = 0; i < 256; i++) {
493 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
494 R300_cp_microcode[i][1]);
495 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
496 R300_cp_microcode[i][0]);
1da177e4 497 }
9f18409e 498 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
edc6f389 499 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
9f18409e
AD		 500 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
501 DRM_INFO("Loading R400 Microcode\n");
502 for (i = 0; i < 256; i++) {
503 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
504 R420_cp_microcode[i][1]);
505 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
506 R420_cp_microcode[i][0]);
507 }
f0738e92
AD		 508 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
509 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
510 DRM_INFO("Loading RS690/RS740 Microcode\n");
9f18409e
AD		 511 for (i = 0; i < 256; i++) {
512 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
513 RS690_cp_microcode[i][1]);
514 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
515 RS690_cp_microcode[i][0]);
516 }
c1556f71
AD		 517 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
518 DRM_INFO("Loading RS600 Microcode\n");
519 for (i = 0; i < 256; i++) {
520 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
521 RS600_cp_microcode[i][1]);
522 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
523 RS600_cp_microcode[i][0]);
524 }
9f18409e
AD		 525 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
526 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
527 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
528 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
529 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
530 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
531 DRM_INFO("Loading R500 Microcode\n");
b5e89ed5
DA		 532 for (i = 0; i < 256; i++) {
533 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
9f18409e 534 R520_cp_microcode[i][1]);
b5e89ed5 535 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
9f18409e 536 R520_cp_microcode[i][0]);
1da177e4
LT		 537 }
538 }
539}
540
541/* Flush any pending commands to the CP. This should only be used just
542 * prior to a wait for idle, as it informs the engine that the command
543 * stream is ending.
544 */
b5e89ed5 545static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
1da177e4 546{
b5e89ed5 547 DRM_DEBUG("\n");
1da177e4
LT		 548#if 0
549 u32 tmp;
550
b5e89ed5
DA		 551 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
552 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
1da177e4
LT		 553#endif
554}
555
556/* Wait for the CP to go idle.
557 */
b5e89ed5 558int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
1da177e4
LT		 559{
560 RING_LOCALS;
b5e89ed5 561 DRM_DEBUG("\n");
1da177e4 562
b5e89ed5 563 BEGIN_RING(6);
1da177e4
LT		 564
565 RADEON_PURGE_CACHE();
566 RADEON_PURGE_ZCACHE();
567 RADEON_WAIT_UNTIL_IDLE();
568
569 ADVANCE_RING();
570 COMMIT_RING();
571
b5e89ed5 572 return radeon_do_wait_for_idle(dev_priv);
1da177e4
LT		 573}
574
575/* Start the Command Processor.
576 */
b5e89ed5 577static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1da177e4
LT		 578{
579 RING_LOCALS;
b5e89ed5 580 DRM_DEBUG("\n");
1da177e4 581
b5e89ed5 582 radeon_do_wait_for_idle(dev_priv);
1da177e4 583
b5e89ed5 584 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1da177e4
LT		 585
586 dev_priv->cp_running = 1;
587
54f961a6
JG		 588 BEGIN_RING(8);
589 /* isync can only be written through cp on r5xx write it here */
590 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
591 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
592 RADEON_ISYNC_ANY3D_IDLE2D |
593 RADEON_ISYNC_WAIT_IDLEGUI |
594 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
1da177e4
LT		 595 RADEON_PURGE_CACHE();
596 RADEON_PURGE_ZCACHE();
597 RADEON_WAIT_UNTIL_IDLE();
1da177e4
LT		 598 ADVANCE_RING();
599 COMMIT_RING();
54f961a6
JG		 600
601 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
1da177e4
LT		 602}
603
604/* Reset the Command Processor. This will not flush any pending
605 * commands, so you must wait for the CP command stream to complete
606 * before calling this routine.
607 */
b5e89ed5 608static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1da177e4
LT		 609{
610 u32 cur_read_ptr;
b5e89ed5 611 DRM_DEBUG("\n");
1da177e4 612
b5e89ed5
DA		 613 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
614 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
615 SET_RING_HEAD(dev_priv, cur_read_ptr);
1da177e4
LT		 616 dev_priv->ring.tail = cur_read_ptr;
617}
618
619/* Stop the Command Processor. This will not flush any pending
620 * commands, so you must flush the command stream and wait for the CP
621 * to go idle before calling this routine.
622 */
b5e89ed5 623static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1da177e4 624{
b5e89ed5 625 DRM_DEBUG("\n");
1da177e4 626
b5e89ed5 627 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1da177e4
LT		 628
629 dev_priv->cp_running = 0;
630}
631
632/* Reset the engine. This will stop the CP if it is running.
633 */
84b1fd10 634static int radeon_do_engine_reset(struct drm_device * dev)
1da177e4
LT		 635{
636 drm_radeon_private_t *dev_priv = dev->dev_private;
d396db32 637 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
b5e89ed5 638 DRM_DEBUG("\n");
1da177e4 639
b5e89ed5
DA		 640 radeon_do_pixcache_flush(dev_priv);
641
d396db32
AD		 642 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
643 /* may need something similar for newer chips */
3d5e2c13
DA		 644 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
645 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
646
647 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
648 RADEON_FORCEON_MCLKA |
649 RADEON_FORCEON_MCLKB |
650 RADEON_FORCEON_YCLKA |
651 RADEON_FORCEON_YCLKB |
652 RADEON_FORCEON_MC |
653 RADEON_FORCEON_AIC));
d396db32 654 }
3d5e2c13 655
d396db32
AD		 656 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
657
658 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
659 RADEON_SOFT_RESET_CP |
660 RADEON_SOFT_RESET_HI |
661 RADEON_SOFT_RESET_SE |
662 RADEON_SOFT_RESET_RE |
663 RADEON_SOFT_RESET_PP |
664 RADEON_SOFT_RESET_E2 |
665 RADEON_SOFT_RESET_RB));
666 RADEON_READ(RADEON_RBBM_SOFT_RESET);
667 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
668 ~(RADEON_SOFT_RESET_CP |
669 RADEON_SOFT_RESET_HI |
670 RADEON_SOFT_RESET_SE |
671 RADEON_SOFT_RESET_RE |
672 RADEON_SOFT_RESET_PP |
673 RADEON_SOFT_RESET_E2 |
674 RADEON_SOFT_RESET_RB)));
675 RADEON_READ(RADEON_RBBM_SOFT_RESET);
676
677 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
3d5e2c13
DA		 678 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
679 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
680 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
681 }
1da177e4 682
5b92c404
AD		 683 /* setup the raster pipes */
684 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
685 radeon_init_pipes(dev_priv);
686
1da177e4 687 /* Reset the CP ring */
b5e89ed5 688 radeon_do_cp_reset(dev_priv);
1da177e4
LT		 689
690 /* The CP is no longer running after an engine reset */
691 dev_priv->cp_running = 0;
692
693 /* Reset any pending vertex, indirect buffers */
b5e89ed5 694 radeon_freelist_reset(dev);
1da177e4
LT		 695
696 return 0;
697}
698
84b1fd10 699static void radeon_cp_init_ring_buffer(struct drm_device * dev,
3d16118d 700 drm_radeon_private_t *dev_priv,
701 struct drm_file *file_priv)
1da177e4 702{
3d16118d 703 struct drm_radeon_master_private *master_priv;
1da177e4 704 u32 ring_start, cur_read_ptr;
bc5f4523 705
d5ea702f
DA		 706 /* Initialize the memory controller. With new memory map, the fb location
707 * is not changed, it should have been properly initialized already. Part
708 * of the problem is that the code below is bogus, assuming the GART is
709 * always appended to the fb which is not necessarily the case
710 */
711 if (!dev_priv->new_memmap)
3d5e2c13 712 radeon_write_fb_location(dev_priv,
d5ea702f
DA		 713 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
714 | (dev_priv->fb_location >> 16));
1da177e4
LT		 715
716#if __OS_HAS_AGP
54a56ac5 717 if (dev_priv->flags & RADEON_IS_AGP) {
70b13d51
DA		 718 radeon_write_agp_base(dev_priv, dev->agp->base);
719
3d5e2c13 720 radeon_write_agp_location(dev_priv,
b5e89ed5
DA		 721 (((dev_priv->gart_vm_start - 1 +
722 dev_priv->gart_size) & 0xffff0000) |
723 (dev_priv->gart_vm_start >> 16)));
1da177e4
LT		 724
725 ring_start = (dev_priv->cp_ring->offset
726 - dev->agp->base
727 + dev_priv->gart_vm_start);
b0917bd9 728 } else
1da177e4
LT		 729#endif
730 ring_start = (dev_priv->cp_ring->offset
b0917bd9 731 - (unsigned long)dev->sg->virtual
1da177e4
LT		 732 + dev_priv->gart_vm_start);
733
b5e89ed5 734 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1da177e4
LT		 735
736 /* Set the write pointer delay */
b5e89ed5 737 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1da177e4
LT		 738
739 /* Initialize the ring buffer's read and write pointers */
b5e89ed5
DA		 740 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
741 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
742 SET_RING_HEAD(dev_priv, cur_read_ptr);
1da177e4
LT		 743 dev_priv->ring.tail = cur_read_ptr;
744
745#if __OS_HAS_AGP
54a56ac5 746 if (dev_priv->flags & RADEON_IS_AGP) {
b5e89ed5
DA		 747 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
748 dev_priv->ring_rptr->offset
749 - dev->agp->base + dev_priv->gart_vm_start);
1da177e4
LT		 750 } else
751#endif
752 {
e8a89437
DM		 753 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
754 dev_priv->ring_rptr->offset
755 - ((unsigned long) dev->sg->virtual)
756 + dev_priv->gart_vm_start);
1da177e4
LT		 757 }
758
d5ea702f
DA		 759 /* Set ring buffer size */
760#ifdef __BIG_ENDIAN
761 RADEON_WRITE(RADEON_CP_RB_CNTL,
576cc458
RS		 762 RADEON_BUF_SWAP_32BIT |
763 (dev_priv->ring.fetch_size_l2ow << 18) |
764 (dev_priv->ring.rptr_update_l2qw << 8) |
765 dev_priv->ring.size_l2qw);
d5ea702f 766#else
576cc458
RS		 767 RADEON_WRITE(RADEON_CP_RB_CNTL,
768 (dev_priv->ring.fetch_size_l2ow << 18) |
769 (dev_priv->ring.rptr_update_l2qw << 8) |
770 dev_priv->ring.size_l2qw);
d5ea702f
DA		 771#endif
772
d5ea702f 773
1da177e4
LT		 774 /* Initialize the scratch register pointer. This will cause
775 * the scratch register values to be written out to memory
776 * whenever they are updated.
777 *
778 * We simply put this behind the ring read pointer, this works
779 * with PCI GART as well as (whatever kind of) AGP GART
780 */
b5e89ed5
DA		 781 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
782 + RADEON_SCRATCH_REG_OFFSET);
1da177e4 783
b5e89ed5 784 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1da177e4 785
dd8d7cb4 786 radeon_enable_bm(dev_priv);
1da177e4 787
b07fa022 788 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
7c1c2871 789 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
1da177e4 790
b07fa022 791 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
7c1c2871 792 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
1da177e4 793
b07fa022 794 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
7c1c2871 795 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
1da177e4 796
3d16118d 797 /* reset sarea copies of these */
798 master_priv = file_priv->master->driver_priv;
799 if (master_priv->sarea_priv) {
800 master_priv->sarea_priv->last_frame = 0;
801 master_priv->sarea_priv->last_dispatch = 0;
802 master_priv->sarea_priv->last_clear = 0;
803 }
804
b5e89ed5 805 radeon_do_wait_for_idle(dev_priv);
1da177e4 806
1da177e4 807 /* Sync everything up */
b5e89ed5
DA		 808 RADEON_WRITE(RADEON_ISYNC_CNTL,
809 (RADEON_ISYNC_ANY2D_IDLE3D |
810 RADEON_ISYNC_ANY3D_IDLE2D |
811 RADEON_ISYNC_WAIT_IDLEGUI |
812 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
d5ea702f
DA		 813
814}
815
816static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
817{
818 u32 tmp;
819
6b79d521
DA		 820 /* Start with assuming that writeback doesn't work */
821 dev_priv->writeback_works = 0;
822
d5ea702f
DA		 823 /* Writeback doesn't seem to work everywhere, test it here and possibly
824 * enable it if it appears to work
825 */
b07fa022
DM		 826 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
827
d5ea702f
DA		 828 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
829
830 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
b07fa022
DM		 831 u32 val;
832
833 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
834 if (val == 0xdeadbeef)
d5ea702f
DA		 835 break;
836 DRM_UDELAY(1);
837 }
838
839 if (tmp < dev_priv->usec_timeout) {
840 dev_priv->writeback_works = 1;
841 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
842 } else {
843 dev_priv->writeback_works = 0;
844 DRM_INFO("writeback test failed\n");
845 }
846 if (radeon_no_wb == 1) {
847 dev_priv->writeback_works = 0;
848 DRM_INFO("writeback forced off\n");
849 }
ae1b1a48
MD		 850
851 if (!dev_priv->writeback_works) {
852 /* Disable writeback to avoid unnecessary bus master transfer */
853 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
854 RADEON_RB_NO_UPDATE);
855 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
856 }
1da177e4
LT		 857}
858
f2b04cd2
DA		 859/* Enable or disable IGP GART on the chip */
860static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
60f92683
MC		 861{
862 u32 temp;
863
864 if (on) {
45e51905 865 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
60f92683
MC		 866 dev_priv->gart_vm_start,
867 (long)dev_priv->gart_info.bus_addr,
868 dev_priv->gart_size);
869
45e51905 870 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
f0738e92
AD		 871 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
872 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
45e51905
AD		 873 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
874 RS690_BLOCK_GFX_D3_EN));
875 else
876 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
60f92683 877
45e51905
AD		 878 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
879 RS480_VA_SIZE_32MB));
60f92683 880
45e51905
AD		 881 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
882 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
883 RS480_TLB_ENABLE |
884 RS480_GTW_LAC_EN |
885 RS480_1LEVEL_GART));
60f92683 886
fa0d71b9
DA		 887 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
888 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
45e51905
AD		 889 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
890
891 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
892 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
893 RS480_REQ_TYPE_SNOOP_DIS));
894
5cfb6956 895 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
3722bfc6 896
60f92683
MC		 897 dev_priv->gart_size = 32*1024*1024;
898 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
899 0xffff0000) | (dev_priv->gart_vm_start >> 16));
900
45e51905 901 radeon_write_agp_location(dev_priv, temp);
60f92683 902
45e51905
AD		 903 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
904 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
905 RS480_VA_SIZE_32MB));
60f92683
MC		 906
907 do {
45e51905
AD		 908 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
909 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
60f92683
MC		 910 break;
911 DRM_UDELAY(1);
912 } while (1);
913
45e51905
AD		 914 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
915 RS480_GART_CACHE_INVALIDATE);
2735977b 916
60f92683 917 do {
45e51905
AD		 918 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
919 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
60f92683
MC		 920 break;
921 DRM_UDELAY(1);
922 } while (1);
923
45e51905 924 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
60f92683 925 } else {
45e51905 926 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
60f92683
MC		 927 }
928}
929
c1556f71
AD		 930/* Enable or disable IGP GART on the chip */
931static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
932{
933 u32 temp;
934 int i;
935
936 if (on) {
937 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
938 dev_priv->gart_vm_start,
939 (long)dev_priv->gart_info.bus_addr,
940 dev_priv->gart_size);
941
942 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
943 RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
944
945 for (i = 0; i < 19; i++)
946 IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
947 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
948 RS600_SYSTEM_ACCESS_MODE_IN_SYS |
949 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
950 RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
951 RS600_ENABLE_FRAGMENT_PROCESSING |
952 RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
953
954 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
955 RS600_PAGE_TABLE_TYPE_FLAT));
956
957 /* disable all other contexts */
958 for (i = 1; i < 8; i++)
959 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
960
961 /* setup the page table aperture */
962 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
963 dev_priv->gart_info.bus_addr);
964 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
965 dev_priv->gart_vm_start);
966 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
967 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
968 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
969
970 /* setup the system aperture */
971 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
972 dev_priv->gart_vm_start);
973 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
974 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
975
976 /* enable page tables */
977 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
978 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
979
980 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
981 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
982
983 /* invalidate the cache */
984 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
985
986 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
987 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
988 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
989
990 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
991 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
992 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
993
994 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
995 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
996 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
997
998 } else {
999 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
1000 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1001 temp &= ~RS600_ENABLE_PAGE_TABLES;
1002 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
1003 }
1004}
1005
ea98a92f
DA		 1006static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1007{
1008 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1009 if (on) {
1010
1011 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
b5e89ed5
DA		 1012 dev_priv->gart_vm_start,
1013 (long)dev_priv->gart_info.bus_addr,
ea98a92f 1014 dev_priv->gart_size);
b5e89ed5
DA		 1015 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1016 dev_priv->gart_vm_start);
1017 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1018 dev_priv->gart_info.bus_addr);
1019 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1020 dev_priv->gart_vm_start);
1021 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1022 dev_priv->gart_vm_start +
1023 dev_priv->gart_size - 1);
1024
3d5e2c13 1025 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
b5e89ed5
DA		 1026
1027 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1028 RADEON_PCIE_TX_GART_EN);
ea98a92f 1029 } else {
b5e89ed5
DA		 1030 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1031 tmp & ~RADEON_PCIE_TX_GART_EN);
ea98a92f 1032 }
1da177e4
LT		 1033}
1034
1035/* Enable or disable PCI GART on the chip */
b5e89ed5 1036static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1da177e4 1037{
d985c108 1038 u32 tmp;
1da177e4 1039
45e51905 1040 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
f0738e92 1041 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
45e51905 1042 (dev_priv->flags & RADEON_IS_IGPGART)) {
f2b04cd2
DA		 1043 radeon_set_igpgart(dev_priv, on);
1044 return;
1045 }
1046
c1556f71
AD		 1047 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1048 rs600_set_igpgart(dev_priv, on);
1049 return;
1050 }
1051
54a56ac5 1052 if (dev_priv->flags & RADEON_IS_PCIE) {
ea98a92f
DA		 1053 radeon_set_pciegart(dev_priv, on);
1054 return;
1055 }
1da177e4 1056
bc5f4523 1057 tmp = RADEON_READ(RADEON_AIC_CNTL);
d985c108 1058
b5e89ed5
DA		 1059 if (on) {
1060 RADEON_WRITE(RADEON_AIC_CNTL,
1061 tmp | RADEON_PCIGART_TRANSLATE_EN);
1da177e4
LT		 1062
1063 /* set PCI GART page-table base address
1064 */
ea98a92f 1065 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1da177e4
LT		 1066
1067 /* set address range for PCI address translate
1068 */
b5e89ed5
DA		 1069 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1070 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1071 + dev_priv->gart_size - 1);
1da177e4
LT		 1072
1073 /* Turn off AGP aperture -- is this required for PCI GART?
1074 */
3d5e2c13 1075 radeon_write_agp_location(dev_priv, 0xffffffc0);
b5e89ed5 1076 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1da177e4 1077 } else {
b5e89ed5
DA		 1078 RADEON_WRITE(RADEON_AIC_CNTL,
1079 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1da177e4
LT		 1080 }
1081}
1082
6abf6bb0
DM		 1083static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1084{
1085 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1086 struct radeon_virt_surface *vp;
1087 int i;
1088
1089 for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1090 if (!dev_priv->virt_surfaces[i].file_priv ||
1091 dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1092 break;
1093 }
1094 if (i >= 2 * RADEON_MAX_SURFACES)
1095 return -ENOMEM;
1096 vp = &dev_priv->virt_surfaces[i];
1097
1098 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1099 struct radeon_surface *sp = &dev_priv->surfaces[i];
1100 if (sp->refcount)
1101 continue;
1102
1103 vp->surface_index = i;
1104 vp->lower = gart_info->bus_addr;
1105 vp->upper = vp->lower + gart_info->table_size;
1106 vp->flags = 0;
1107 vp->file_priv = PCIGART_FILE_PRIV;
1108
1109 sp->refcount = 1;
1110 sp->lower = vp->lower;
1111 sp->upper = vp->upper;
1112 sp->flags = 0;
1113
1114 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1115 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1116 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1117 return 0;
1118 }
1119
1120 return -ENOMEM;
1121}
1122
7c1c2871
DA		 1123static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1124 struct drm_file *file_priv)
1da177e4 1125{
d985c108 1126 drm_radeon_private_t *dev_priv = dev->dev_private;
7c1c2871 1127 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
d985c108 1128
b5e89ed5 1129 DRM_DEBUG("\n");
1da177e4 1130
f3dd5c37 1131 /* if we require new memory map but we don't have it fail */
54a56ac5 1132 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
b15ec368 1133 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
f3dd5c37 1134 radeon_do_cleanup_cp(dev);
20caafa6 1135 return -EINVAL;
f3dd5c37
DA		 1136 }
1137
54a56ac5 1138 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
d985c108 1139 DRM_DEBUG("Forcing AGP card to PCI mode\n");
54a56ac5
DA		 1140 dev_priv->flags &= ~RADEON_IS_AGP;
1141 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
b15ec368
DA		 1142 && !init->is_pci) {
1143 DRM_DEBUG("Restoring AGP flag\n");
54a56ac5 1144 dev_priv->flags |= RADEON_IS_AGP;
d985c108 1145 }
1da177e4 1146
54a56ac5 1147 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
b5e89ed5 1148 DRM_ERROR("PCI GART memory not allocated!\n");
1da177e4 1149 radeon_do_cleanup_cp(dev);
20caafa6 1150 return -EINVAL;
1da177e4
LT		 1151 }
1152
1153 dev_priv->usec_timeout = init->usec_timeout;
b5e89ed5
DA		 1154 if (dev_priv->usec_timeout < 1 ||
1155 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1156 DRM_DEBUG("TIMEOUT problem!\n");
1da177e4 1157 radeon_do_cleanup_cp(dev);
20caafa6 1158 return -EINVAL;
1da177e4
LT		 1159 }
1160
ddbee333
DA		 1161 /* Enable vblank on CRTC1 for older X servers
1162 */
1163 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1164
d985c108 1165 switch(init->func) {
1da177e4 1166 case RADEON_INIT_R200_CP:
b5e89ed5 1167 dev_priv->microcode_version = UCODE_R200;
1da177e4
LT		 1168 break;
1169 case RADEON_INIT_R300_CP:
b5e89ed5 1170 dev_priv->microcode_version = UCODE_R300;
1da177e4
LT		 1171 break;
1172 default:
b5e89ed5 1173 dev_priv->microcode_version = UCODE_R100;
1da177e4 1174 }
b5e89ed5 1175
1da177e4
LT		 1176 dev_priv->do_boxes = 0;
1177 dev_priv->cp_mode = init->cp_mode;
1178
1179 /* We don't support anything other than bus-mastering ring mode,
1180 * but the ring can be in either AGP or PCI space for the ring
1181 * read pointer.
1182 */
b5e89ed5
DA		 1183 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1184 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1185 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1da177e4 1186 radeon_do_cleanup_cp(dev);
20caafa6 1187 return -EINVAL;
1da177e4
LT		 1188 }
1189
b5e89ed5 1190 switch (init->fb_bpp) {
1da177e4
LT		 1191 case 16:
1192 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1193 break;
1194 case 32:
1195 default:
1196 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1197 break;
1198 }
b5e89ed5
DA		 1199 dev_priv->front_offset = init->front_offset;
1200 dev_priv->front_pitch = init->front_pitch;
1201 dev_priv->back_offset = init->back_offset;
1202 dev_priv->back_pitch = init->back_pitch;
1da177e4 1203
b5e89ed5 1204 switch (init->depth_bpp) {
1da177e4
LT		 1205 case 16:
1206 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1207 break;
1208 case 32:
1209 default:
1210 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1211 break;
1212 }
b5e89ed5
DA		 1213 dev_priv->depth_offset = init->depth_offset;
1214 dev_priv->depth_pitch = init->depth_pitch;
1da177e4
LT		 1215
1216 /* Hardware state for depth clears. Remove this if/when we no
1217 * longer clear the depth buffer with a 3D rectangle. Hard-code
1218 * all values to prevent unwanted 3D state from slipping through
1219 * and screwing with the clear operation.
1220 */
1221 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1222 (dev_priv->color_fmt << 10) |
b5e89ed5
DA		 1223 (dev_priv->microcode_version ==
1224 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1da177e4 1225
b5e89ed5
DA		 1226 dev_priv->depth_clear.rb3d_zstencilcntl =
1227 (dev_priv->depth_fmt |
1228 RADEON_Z_TEST_ALWAYS |
1229 RADEON_STENCIL_TEST_ALWAYS |
1230 RADEON_STENCIL_S_FAIL_REPLACE |
1231 RADEON_STENCIL_ZPASS_REPLACE |
1232 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1da177e4
LT		 1233
1234 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1235 RADEON_BFACE_SOLID |
1236 RADEON_FFACE_SOLID |
1237 RADEON_FLAT_SHADE_VTX_LAST |
1238 RADEON_DIFFUSE_SHADE_FLAT |
1239 RADEON_ALPHA_SHADE_FLAT |
1240 RADEON_SPECULAR_SHADE_FLAT |
1241 RADEON_FOG_SHADE_FLAT |
1242 RADEON_VTX_PIX_CENTER_OGL |
1243 RADEON_ROUND_MODE_TRUNC |
1244 RADEON_ROUND_PREC_8TH_PIX);
1245
1da177e4 1246
1da177e4
LT		 1247 dev_priv->ring_offset = init->ring_offset;
1248 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1249 dev_priv->buffers_offset = init->buffers_offset;
1250 dev_priv->gart_textures_offset = init->gart_textures_offset;
b5e89ed5 1251
7c1c2871
DA		 1252 master_priv->sarea = drm_getsarea(dev);
1253 if (!master_priv->sarea) {
1da177e4 1254 DRM_ERROR("could not find sarea!\n");
1da177e4 1255 radeon_do_cleanup_cp(dev);
20caafa6 1256 return -EINVAL;
1da177e4
LT		 1257 }
1258
1da177e4 1259 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
b5e89ed5 1260 if (!dev_priv->cp_ring) {
1da177e4 1261 DRM_ERROR("could not find cp ring region!\n");
1da177e4 1262 radeon_do_cleanup_cp(dev);
20caafa6 1263 return -EINVAL;
1da177e4
LT		 1264 }
1265 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
b5e89ed5 1266 if (!dev_priv->ring_rptr) {
1da177e4 1267 DRM_ERROR("could not find ring read pointer!\n");
1da177e4 1268 radeon_do_cleanup_cp(dev);
20caafa6 1269 return -EINVAL;
1da177e4 1270 }
d1f2b55a 1271 dev->agp_buffer_token = init->buffers_offset;
1da177e4 1272 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
b5e89ed5 1273 if (!dev->agp_buffer_map) {
1da177e4 1274 DRM_ERROR("could not find dma buffer region!\n");
1da177e4 1275 radeon_do_cleanup_cp(dev);
20caafa6 1276 return -EINVAL;
1da177e4
LT		 1277 }
1278
b5e89ed5
DA		 1279 if (init->gart_textures_offset) {
1280 dev_priv->gart_textures =
1281 drm_core_findmap(dev, init->gart_textures_offset);
1282 if (!dev_priv->gart_textures) {
1da177e4 1283 DRM_ERROR("could not find GART texture region!\n");
1da177e4 1284 radeon_do_cleanup_cp(dev);
20caafa6 1285 return -EINVAL;
1da177e4
LT		 1286 }
1287 }
1288
1da177e4 1289#if __OS_HAS_AGP
54a56ac5 1290 if (dev_priv->flags & RADEON_IS_AGP) {
9b8d5a12
DA		 1291 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1292 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1293 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
b5e89ed5
DA		 1294 if (!dev_priv->cp_ring->handle ||
1295 !dev_priv->ring_rptr->handle ||
1296 !dev->agp_buffer_map->handle) {
1da177e4 1297 DRM_ERROR("could not find ioremap agp regions!\n");
1da177e4 1298 radeon_do_cleanup_cp(dev);
20caafa6 1299 return -EINVAL;
1da177e4
LT		 1300 }
1301 } else
1302#endif
1303 {
41c2e75e
BH		 1304 dev_priv->cp_ring->handle =
1305 (void *)(unsigned long)dev_priv->cp_ring->offset;
1da177e4 1306 dev_priv->ring_rptr->handle =
41c2e75e 1307 (void *)(unsigned long)dev_priv->ring_rptr->offset;
b5e89ed5 1308 dev->agp_buffer_map->handle =
41c2e75e 1309 (void *)(unsigned long)dev->agp_buffer_map->offset;
b5e89ed5
DA		 1310
1311 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1312 dev_priv->cp_ring->handle);
1313 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1314 dev_priv->ring_rptr->handle);
1315 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1316 dev->agp_buffer_map->handle);
1da177e4
LT		 1317 }
1318
3d5e2c13 1319 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
bc5f4523 1320 dev_priv->fb_size =
3d5e2c13 1321 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
d5ea702f 1322 - dev_priv->fb_location;
1da177e4 1323
b5e89ed5
DA		 1324 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1325 ((dev_priv->front_offset
1326 + dev_priv->fb_location) >> 10));
1da177e4 1327
b5e89ed5
DA		 1328 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1329 ((dev_priv->back_offset
1330 + dev_priv->fb_location) >> 10));
1da177e4 1331
b5e89ed5
DA		 1332 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1333 ((dev_priv->depth_offset
1334 + dev_priv->fb_location) >> 10));
1da177e4
LT		 1335
1336 dev_priv->gart_size = init->gart_size;
d5ea702f
DA		 1337
1338 /* New let's set the memory map ... */
1339 if (dev_priv->new_memmap) {
1340 u32 base = 0;
1341
1342 DRM_INFO("Setting GART location based on new memory map\n");
1343
1344 /* If using AGP, try to locate the AGP aperture at the same
1345 * location in the card and on the bus, though we have to
1346 * align it down.
1347 */
1348#if __OS_HAS_AGP
54a56ac5 1349 if (dev_priv->flags & RADEON_IS_AGP) {
d5ea702f
DA		 1350 base = dev->agp->base;
1351 /* Check if valid */
80b2c386
MD		 1352 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1353 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
d5ea702f
DA		 1354 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1355 dev->agp->base);
1356 base = 0;
1357 }
1358 }
1359#endif
1360 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1361 if (base == 0) {
1362 base = dev_priv->fb_location + dev_priv->fb_size;
80b2c386
MD		 1363 if (base < dev_priv->fb_location ||
1364 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
d5ea702f
DA		 1365 base = dev_priv->fb_location
1366 - dev_priv->gart_size;
bc5f4523 1367 }
d5ea702f
DA		 1368 dev_priv->gart_vm_start = base & 0xffc00000u;
1369 if (dev_priv->gart_vm_start != base)
1370 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1371 base, dev_priv->gart_vm_start);
1372 } else {
1373 DRM_INFO("Setting GART location based on old memory map\n");
1374 dev_priv->gart_vm_start = dev_priv->fb_location +
1375 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1376 }
1da177e4
LT		 1377
1378#if __OS_HAS_AGP
54a56ac5 1379 if (dev_priv->flags & RADEON_IS_AGP)
1da177e4 1380 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
b5e89ed5
DA		 1381 - dev->agp->base
1382 + dev_priv->gart_vm_start);
1da177e4
LT		 1383 else
1384#endif
1385 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
b0917bd9
IK		 1386 - (unsigned long)dev->sg->virtual
1387 + dev_priv->gart_vm_start);
1da177e4 1388
b5e89ed5
DA		 1389 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1390 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1391 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1392 dev_priv->gart_buffers_offset);
1da177e4 1393
b5e89ed5
DA		 1394 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1395 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1da177e4
LT		 1396 + init->ring_size / sizeof(u32));
1397 dev_priv->ring.size = init->ring_size;
b5e89ed5 1398 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1da177e4 1399
576cc458
RS		 1400 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1401 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1402
1403 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1404 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
b5e89ed5 1405 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1da177e4
LT		 1406
1407 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1408
1409#if __OS_HAS_AGP
54a56ac5 1410 if (dev_priv->flags & RADEON_IS_AGP) {
1da177e4 1411 /* Turn off PCI GART */
b5e89ed5 1412 radeon_set_pcigart(dev_priv, 0);
1da177e4
LT		 1413 } else
1414#endif
1415 {
6abf6bb0
DM		 1416 u32 sctrl;
1417 int ret;
1418
b05c2385 1419 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
ea98a92f 1420 /* if we have an offset set from userspace */
f2b04cd2 1421 if (dev_priv->pcigart_offset_set) {
b5e89ed5 1422 dev_priv->gart_info.bus_addr =
41c2e75e 1423 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
f26c473c 1424 dev_priv->gart_info.mapping.offset =
7fc86860 1425 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
f26c473c 1426 dev_priv->gart_info.mapping.size =
f2b04cd2 1427 dev_priv->gart_info.table_size;
f26c473c 1428
242e3df8 1429 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
b5e89ed5 1430 dev_priv->gart_info.addr =
f26c473c 1431 dev_priv->gart_info.mapping.handle;
b5e89ed5 1432
f2b04cd2
DA		 1433 if (dev_priv->flags & RADEON_IS_PCIE)
1434 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1435 else
1436 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
b5e89ed5
DA		 1437 dev_priv->gart_info.gart_table_location =
1438 DRM_ATI_GART_FB;
1439
f26c473c 1440 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
b5e89ed5
DA		 1441 dev_priv->gart_info.addr,
1442 dev_priv->pcigart_offset);
1443 } else {
f2b04cd2
DA		 1444 if (dev_priv->flags & RADEON_IS_IGPGART)
1445 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1446 else
1447 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
b5e89ed5
DA		 1448 dev_priv->gart_info.gart_table_location =
1449 DRM_ATI_GART_MAIN;
f26c473c
DA		 1450 dev_priv->gart_info.addr = NULL;
1451 dev_priv->gart_info.bus_addr = 0;
54a56ac5 1452 if (dev_priv->flags & RADEON_IS_PCIE) {
b5e89ed5
DA		 1453 DRM_ERROR
1454 ("Cannot use PCI Express without GART in FB memory\n");
ea98a92f 1455 radeon_do_cleanup_cp(dev);
20caafa6 1456 return -EINVAL;
ea98a92f
DA		 1457 }
1458 }
1459
6abf6bb0
DM		 1460 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1461 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
c1556f71
AD		 1462 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1463 ret = r600_page_table_init(dev);
1464 else
1465 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
6abf6bb0
DM		 1466 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1467
1468 if (!ret) {
b5e89ed5 1469 DRM_ERROR("failed to init PCI GART!\n");
1da177e4 1470 radeon_do_cleanup_cp(dev);
20caafa6 1471 return -ENOMEM;
1da177e4
LT		 1472 }
1473
6abf6bb0
DM		 1474 ret = radeon_setup_pcigart_surface(dev_priv);
1475 if (ret) {
1476 DRM_ERROR("failed to setup GART surface!\n");
c1556f71
AD		 1477 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1478 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1479 else
1480 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
6abf6bb0
DM		 1481 radeon_do_cleanup_cp(dev);
1482 return ret;
1483 }
1484
1da177e4 1485 /* Turn on PCI GART */
b5e89ed5 1486 radeon_set_pcigart(dev_priv, 1);
1da177e4
LT		 1487 }
1488
b5e89ed5 1489 radeon_cp_load_microcode(dev_priv);
3d16118d 1490 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1da177e4
LT		 1491
1492 dev_priv->last_buf = 0;
1493
b5e89ed5 1494 radeon_do_engine_reset(dev);
d5ea702f 1495 radeon_test_writeback(dev_priv);
1da177e4
LT		 1496
1497 return 0;
1498}
1499
84b1fd10 1500static int radeon_do_cleanup_cp(struct drm_device * dev)
1da177e4
LT		 1501{
1502 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1503 DRM_DEBUG("\n");
1da177e4
LT		 1504
1505 /* Make sure interrupts are disabled here because the uninstall ioctl
1506 * may not have been called from userspace and after dev_private
1507 * is freed, it's too late.
1508 */
b5e89ed5
DA		 1509 if (dev->irq_enabled)
1510 drm_irq_uninstall(dev);
1da177e4
LT		 1511
1512#if __OS_HAS_AGP
54a56ac5 1513 if (dev_priv->flags & RADEON_IS_AGP) {
d985c108 1514 if (dev_priv->cp_ring != NULL) {
b5e89ed5 1515 drm_core_ioremapfree(dev_priv->cp_ring, dev);
d985c108
DA		 1516 dev_priv->cp_ring = NULL;
1517 }
1518 if (dev_priv->ring_rptr != NULL) {
b5e89ed5 1519 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
d985c108
DA		 1520 dev_priv->ring_rptr = NULL;
1521 }
b5e89ed5
DA		 1522 if (dev->agp_buffer_map != NULL) {
1523 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1da177e4
LT		 1524 dev->agp_buffer_map = NULL;
1525 }
1526 } else
1527#endif
1528 {
d985c108
DA		 1529
1530 if (dev_priv->gart_info.bus_addr) {
1531 /* Turn off PCI GART */
1532 radeon_set_pcigart(dev_priv, 0);
c1556f71
AD		 1533 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1534 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1535 else {
1536 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1537 DRM_ERROR("failed to cleanup PCI GART!\n");
1538 }
d985c108 1539 }
b5e89ed5 1540
d985c108
DA		 1541 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1542 {
f26c473c 1543 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
8f497aad 1544 dev_priv->gart_info.addr = NULL;
ea98a92f 1545 }
1da177e4 1546 }
1da177e4
LT		 1547 /* only clear to the start of flags */
1548 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1549
1550 return 0;
1551}
1552
b5e89ed5
DA		 1553/* This code will reinit the Radeon CP hardware after a resume from disc.
1554 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1da177e4
LT		 1555 * here we make sure that all Radeon hardware initialisation is re-done without
1556 * affecting running applications.
1557 *
1558 * Charl P. Botha <http://cpbotha.net>
1559 */
3d16118d 1560static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1da177e4
LT		 1561{
1562 drm_radeon_private_t *dev_priv = dev->dev_private;
1563
b5e89ed5
DA		 1564 if (!dev_priv) {
1565 DRM_ERROR("Called with no initialization\n");
20caafa6 1566 return -EINVAL;
1da177e4
LT		 1567 }
1568
1569 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1570
1571#if __OS_HAS_AGP
54a56ac5 1572 if (dev_priv->flags & RADEON_IS_AGP) {
1da177e4 1573 /* Turn off PCI GART */
b5e89ed5 1574 radeon_set_pcigart(dev_priv, 0);
1da177e4
LT		 1575 } else
1576#endif
1577 {
1578 /* Turn on PCI GART */
b5e89ed5 1579 radeon_set_pcigart(dev_priv, 1);
1da177e4
LT		 1580 }
1581
b5e89ed5 1582 radeon_cp_load_microcode(dev_priv);
3d16118d 1583 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1da177e4 1584
b5e89ed5 1585 radeon_do_engine_reset(dev);
0a3e67a4 1586 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1da177e4
LT		 1587
1588 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1589
1590 return 0;
1591}
1592
c153f45f 1593int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1594{
c05ce083 1595 drm_radeon_private_t *dev_priv = dev->dev_private;
c153f45f 1596 drm_radeon_init_t *init = data;
1da177e4 1597
6c340eac 1598 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1599
c153f45f 1600 if (init->func == RADEON_INIT_R300_CP)
3d5e2c13 1601 r300_init_reg_flags(dev);
414ed537 1602
c153f45f 1603 switch (init->func) {
1da177e4
LT		 1604 case RADEON_INIT_CP:
1605 case RADEON_INIT_R200_CP:
1606 case RADEON_INIT_R300_CP:
7c1c2871 1607 return radeon_do_init_cp(dev, init, file_priv);
c05ce083
AD		 1608 case RADEON_INIT_R600_CP:
1609 return r600_do_init_cp(dev, init, file_priv);
1da177e4 1610 case RADEON_CLEANUP_CP:
c05ce083
AD		 1611 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1612 return r600_do_cleanup_cp(dev);
1613 else
1614 return radeon_do_cleanup_cp(dev);
1da177e4
LT		 1615 }
1616
20caafa6 1617 return -EINVAL;
1da177e4
LT		 1618}
1619
c153f45f 1620int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1621{
1da177e4 1622 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1623 DRM_DEBUG("\n");
1da177e4 1624
6c340eac 1625 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1626
b5e89ed5 1627 if (dev_priv->cp_running) {
3e684eae 1628 DRM_DEBUG("while CP running\n");
1da177e4
LT		 1629 return 0;
1630 }
b5e89ed5 1631 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
3e684eae
MN		 1632 DRM_DEBUG("called with bogus CP mode (%d)\n",
1633 dev_priv->cp_mode);
1da177e4
LT		 1634 return 0;
1635 }
1636
c05ce083
AD		 1637 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1638 r600_do_cp_start(dev_priv);
1639 else
1640 radeon_do_cp_start(dev_priv);
1da177e4
LT		 1641
1642 return 0;
1643}
1644
1645/* Stop the CP. The engine must have been idled before calling this
1646 * routine.
1647 */
c153f45f 1648int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1649{
1da177e4 1650 drm_radeon_private_t *dev_priv = dev->dev_private;
c153f45f 1651 drm_radeon_cp_stop_t *stop = data;
1da177e4 1652 int ret;
b5e89ed5 1653 DRM_DEBUG("\n");
1da177e4 1654
6c340eac 1655 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1656
1da177e4
LT		 1657 if (!dev_priv->cp_running)
1658 return 0;
1659
1660 /* Flush any pending CP commands. This ensures any outstanding
1661 * commands are exectuted by the engine before we turn it off.
1662 */
c153f45f 1663 if (stop->flush) {
b5e89ed5 1664 radeon_do_cp_flush(dev_priv);
1da177e4
LT		 1665 }
1666
1667 /* If we fail to make the engine go idle, we return an error
1668 * code so that the DRM ioctl wrapper can try again.
1669 */
c153f45f 1670 if (stop->idle) {
c05ce083
AD		 1671 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1672 ret = r600_do_cp_idle(dev_priv);
1673 else
1674 ret = radeon_do_cp_idle(dev_priv);
b5e89ed5
DA		 1675 if (ret)
1676 return ret;
1da177e4
LT		 1677 }
1678
1679 /* Finally, we can turn off the CP. If the engine isn't idle,
1680 * we will get some dropped triangles as they won't be fully
1681 * rendered before the CP is shut down.
1682 */
c05ce083
AD		 1683 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1684 r600_do_cp_stop(dev_priv);
1685 else
1686 radeon_do_cp_stop(dev_priv);
1da177e4
LT		 1687
1688 /* Reset the engine */
c05ce083
AD		 1689 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1690 r600_do_engine_reset(dev);
1691 else
1692 radeon_do_engine_reset(dev);
1da177e4
LT		 1693
1694 return 0;
1695}
1696
84b1fd10 1697void radeon_do_release(struct drm_device * dev)
1da177e4
LT		 1698{
1699 drm_radeon_private_t *dev_priv = dev->dev_private;
1700 int i, ret;
1701
1702 if (dev_priv) {
1703 if (dev_priv->cp_running) {
1704 /* Stop the cp */
53c379e9 1705 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
c05ce083
AD		 1706 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1707 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1da177e4 1708#ifdef __linux__
c05ce083 1709 schedule();
1da177e4 1710#else
c05ce083 1711 tsleep(&ret, PZERO, "rdnrel", 1);
1da177e4 1712#endif
c05ce083
AD		 1713 }
1714 } else {
1715 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1716 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1717#ifdef __linux__
1718 schedule();
1719#else
1720 tsleep(&ret, PZERO, "rdnrel", 1);
1721#endif
1722 }
1723 }
1724 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1725 r600_do_cp_stop(dev_priv);
1726 r600_do_engine_reset(dev);
1727 } else {
1728 radeon_do_cp_stop(dev_priv);
1729 radeon_do_engine_reset(dev);
1da177e4 1730 }
1da177e4
LT		 1731 }
1732
c05ce083
AD		 1733 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1734 /* Disable *all* interrupts */
1735 if (dev_priv->mmio) /* remove this after permanent addmaps */
1736 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1737
1738 if (dev_priv->mmio) { /* remove all surfaces */
1739 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1740 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1741 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1742 16 * i, 0);
1743 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1744 16 * i, 0);
1745 }
1da177e4
LT		 1746 }
1747 }
1748
1749 /* Free memory heap structures */
b5e89ed5
DA		 1750 radeon_mem_takedown(&(dev_priv->gart_heap));
1751 radeon_mem_takedown(&(dev_priv->fb_heap));
1da177e4
LT		 1752
1753 /* deallocate kernel resources */
c05ce083
AD		 1754 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1755 r600_do_cleanup_cp(dev);
1756 else
1757 radeon_do_cleanup_cp(dev);
1da177e4
LT		 1758 }
1759}
1760
1761/* Just reset the CP ring. Called as part of an X Server engine reset.
1762 */
c153f45f 1763int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1764{
1da177e4 1765 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1766 DRM_DEBUG("\n");
1da177e4 1767
6c340eac 1768 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1769
b5e89ed5 1770 if (!dev_priv) {
3e684eae 1771 DRM_DEBUG("called before init done\n");
20caafa6 1772 return -EINVAL;
1da177e4
LT		 1773 }
1774
c05ce083
AD		 1775 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1776 r600_do_cp_reset(dev_priv);
1777 else
1778 radeon_do_cp_reset(dev_priv);
1da177e4
LT		 1779
1780 /* The CP is no longer running after an engine reset */
1781 dev_priv->cp_running = 0;
1782
1783 return 0;
1784}
1785
c153f45f 1786int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1787{
1da177e4 1788 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1789 DRM_DEBUG("\n");
1da177e4 1790
6c340eac 1791 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1792
c05ce083
AD		 1793 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1794 return r600_do_cp_idle(dev_priv);
1795 else
1796 return radeon_do_cp_idle(dev_priv);
1da177e4
LT		 1797}
1798
1799/* Added by Charl P. Botha to call radeon_do_resume_cp().
1800 */
c153f45f 1801int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1802{
c05ce083
AD		 1803 drm_radeon_private_t *dev_priv = dev->dev_private;
1804 DRM_DEBUG("\n");
1805
1806 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1807 return r600_do_resume_cp(dev, file_priv);
1808 else
1809 return radeon_do_resume_cp(dev, file_priv);
1da177e4
LT		 1810}
1811
c153f45f 1812int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1813{
c05ce083 1814 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1815 DRM_DEBUG("\n");
1da177e4 1816
6c340eac 1817 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1818
c05ce083
AD		 1819 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1820 return r600_do_engine_reset(dev);
1821 else
1822 return radeon_do_engine_reset(dev);
1da177e4
LT		 1823}
1824
1da177e4
LT		 1825/* ================================================================
1826 * Fullscreen mode
1827 */
1828
1829/* KW: Deprecated to say the least:
1830 */
c153f45f 1831int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4
LT		 1832{
1833 return 0;
1834}
1835
1da177e4
LT		 1836/* ================================================================
1837 * Freelist management
1838 */
1839
1840/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1841 * bufs until freelist code is used. Note this hides a problem with
1842 * the scratch register * (used to keep track of last buffer
1843 * completed) being written to before * the last buffer has actually
b5e89ed5 1844 * completed rendering.
1da177e4
LT		 1845 *
1846 * KW: It's also a good way to find free buffers quickly.
1847 *
1848 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1849 * sleep. However, bugs in older versions of radeon_accel.c mean that
1850 * we essentially have to do this, else old clients will break.
b5e89ed5 1851 *
1da177e4
LT		 1852 * However, it does leave open a potential deadlock where all the
1853 * buffers are held by other clients, which can't release them because
b5e89ed5 1854 * they can't get the lock.
1da177e4
LT		 1855 */
1856
056219e2 1857struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1da177e4 1858{
cdd55a29 1859 struct drm_device_dma *dma = dev->dma;
1da177e4
LT		 1860 drm_radeon_private_t *dev_priv = dev->dev_private;
1861 drm_radeon_buf_priv_t *buf_priv;
056219e2 1862 struct drm_buf *buf;
1da177e4
LT		 1863 int i, t;
1864 int start;
1865
b5e89ed5 1866 if (++dev_priv->last_buf >= dma->buf_count)
1da177e4
LT		 1867 dev_priv->last_buf = 0;
1868
1869 start = dev_priv->last_buf;
1870
b5e89ed5 1871 for (t = 0; t < dev_priv->usec_timeout; t++) {
b07fa022 1872 u32 done_age = GET_SCRATCH(dev_priv, 1);
b5e89ed5
DA		 1873 DRM_DEBUG("done_age = %d\n", done_age);
1874 for (i = start; i < dma->buf_count; i++) {
1da177e4
LT		 1875 buf = dma->buflist[i];
1876 buf_priv = buf->dev_private;
6c340eac
EA		 1877 if (buf->file_priv == NULL || (buf->pending &&
1878 buf_priv->age <=
1879 done_age)) {
1da177e4
LT		 1880 dev_priv->stats.requested_bufs++;
1881 buf->pending = 0;
1882 return buf;
1883 }
1884 start = 0;
1885 }
1886
1887 if (t) {
b5e89ed5 1888 DRM_UDELAY(1);
1da177e4
LT		 1889 dev_priv->stats.freelist_loops++;
1890 }
1891 }
1892
b5e89ed5 1893 DRM_DEBUG("returning NULL!\n");
1da177e4
LT		 1894 return NULL;
1895}
b5e89ed5 1896
1da177e4 1897#if 0
056219e2 1898struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1da177e4 1899{
cdd55a29 1900 struct drm_device_dma *dma = dev->dma;
1da177e4
LT		 1901 drm_radeon_private_t *dev_priv = dev->dev_private;
1902 drm_radeon_buf_priv_t *buf_priv;
056219e2 1903 struct drm_buf *buf;
1da177e4
LT		 1904 int i, t;
1905 int start;
b07fa022 1906 u32 done_age;
1da177e4 1907
b07fa022 1908 done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
b5e89ed5 1909 if (++dev_priv->last_buf >= dma->buf_count)
1da177e4
LT		 1910 dev_priv->last_buf = 0;
1911
1912 start = dev_priv->last_buf;
1913 dev_priv->stats.freelist_loops++;
b5e89ed5
DA		 1914
1915 for (t = 0; t < 2; t++) {
1916 for (i = start; i < dma->buf_count; i++) {
1da177e4
LT		 1917 buf = dma->buflist[i];
1918 buf_priv = buf->dev_private;
6c340eac
EA		 1919 if (buf->file_priv == 0 || (buf->pending &&
1920 buf_priv->age <=
1921 done_age)) {
1da177e4
LT		 1922 dev_priv->stats.requested_bufs++;
1923 buf->pending = 0;
1924 return buf;
1925 }
1926 }
1927 start = 0;
1928 }
1929
1930 return NULL;
1931}
1932#endif
1933
84b1fd10 1934void radeon_freelist_reset(struct drm_device * dev)
1da177e4 1935{
cdd55a29 1936 struct drm_device_dma *dma = dev->dma;
1da177e4
LT		 1937 drm_radeon_private_t *dev_priv = dev->dev_private;
1938 int i;
1939
1940 dev_priv->last_buf = 0;
b5e89ed5 1941 for (i = 0; i < dma->buf_count; i++) {
056219e2 1942 struct drm_buf *buf = dma->buflist[i];
1da177e4
LT		 1943 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1944 buf_priv->age = 0;
1945 }
1946}
1947
1da177e4
LT		 1948/* ================================================================
1949 * CP command submission
1950 */
1951
b5e89ed5 1952int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1da177e4
LT		 1953{
1954 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1955 int i;
b5e89ed5 1956 u32 last_head = GET_RING_HEAD(dev_priv);
1da177e4 1957
b5e89ed5
DA		 1958 for (i = 0; i < dev_priv->usec_timeout; i++) {
1959 u32 head = GET_RING_HEAD(dev_priv);
1da177e4
LT		 1960
1961 ring->space = (head - ring->tail) * sizeof(u32);
b5e89ed5 1962 if (ring->space <= 0)
1da177e4 1963 ring->space += ring->size;
b5e89ed5 1964 if (ring->space > n)
1da177e4 1965 return 0;
b5e89ed5 1966
1da177e4
LT		 1967 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1968
1969 if (head != last_head)
1970 i = 0;
1971 last_head = head;
1972
b5e89ed5 1973 DRM_UDELAY(1);
1da177e4
LT		 1974 }
1975
1976 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1977#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 1978 radeon_status(dev_priv);
1979 DRM_ERROR("failed!\n");
1da177e4 1980#endif
20caafa6 1981 return -EBUSY;
1da177e4
LT		 1982}
1983
6c340eac
EA		 1984static int radeon_cp_get_buffers(struct drm_device *dev,
1985 struct drm_file *file_priv,
c60ce623 1986 struct drm_dma * d)
1da177e4
LT		 1987{
1988 int i;
056219e2 1989 struct drm_buf *buf;
1da177e4 1990
b5e89ed5
DA		 1991 for (i = d->granted_count; i < d->request_count; i++) {
1992 buf = radeon_freelist_get(dev);
1993 if (!buf)
20caafa6 1994 return -EBUSY; /* NOTE: broken client */
1da177e4 1995
6c340eac 1996 buf->file_priv = file_priv;
1da177e4 1997
b5e89ed5
DA		 1998 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1999 sizeof(buf->idx)))
20caafa6 2000 return -EFAULT;
b5e89ed5
DA		 2001 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2002 sizeof(buf->total)))
20caafa6 2003 return -EFAULT;
1da177e4
LT		 2004
2005 d->granted_count++;
2006 }
2007 return 0;
2008}
2009
c153f45f 2010int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 2011{
cdd55a29 2012 struct drm_device_dma *dma = dev->dma;
1da177e4 2013 int ret = 0;
c153f45f 2014 struct drm_dma *d = data;
1da177e4 2015
6c340eac 2016 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 2017
1da177e4
LT		 2018 /* Please don't send us buffers.
2019 */
c153f45f 2020 if (d->send_count != 0) {
b5e89ed5 2021 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
c153f45f 2022 DRM_CURRENTPID, d->send_count);
20caafa6 2023 return -EINVAL;
1da177e4
LT		 2024 }
2025
2026 /* We'll send you buffers.
2027 */
c153f45f 2028 if (d->request_count < 0 || d->request_count > dma->buf_count) {
b5e89ed5 2029 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
c153f45f 2030 DRM_CURRENTPID, d->request_count, dma->buf_count);
20caafa6 2031 return -EINVAL;
1da177e4
LT		 2032 }
2033
c153f45f 2034 d->granted_count = 0;
1da177e4 2035
c153f45f
EA		 2036 if (d->request_count) {
2037 ret = radeon_cp_get_buffers(dev, file_priv, d);
1da177e4
LT		 2038 }
2039
1da177e4
LT		 2040 return ret;
2041}
2042
22eae947 2043int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1da177e4
LT		 2044{
2045 drm_radeon_private_t *dev_priv;
2046 int ret = 0;
2047
2048 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2049 if (dev_priv == NULL)
20caafa6 2050 return -ENOMEM;
1da177e4
LT		 2051
2052 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2053 dev->dev_private = (void *)dev_priv;
2054 dev_priv->flags = flags;
2055
54a56ac5 2056 switch (flags & RADEON_FAMILY_MASK) {
1da177e4
LT		 2057 case CHIP_R100:
2058 case CHIP_RV200:
2059 case CHIP_R200:
2060 case CHIP_R300:
b15ec368 2061 case CHIP_R350:
414ed537 2062 case CHIP_R420:
edc6f389 2063 case CHIP_R423:
b15ec368 2064 case CHIP_RV410:
3d5e2c13
DA		 2065 case CHIP_RV515:
2066 case CHIP_R520:
2067 case CHIP_RV570:
2068 case CHIP_R580:
54a56ac5 2069 dev_priv->flags |= RADEON_HAS_HIERZ;
1da177e4
LT		 2070 break;
2071 default:
b5e89ed5 2072 /* all other chips have no hierarchical z buffer */
1da177e4
LT		 2073 break;
2074 }
414ed537
DA		 2075
2076 if (drm_device_is_agp(dev))
54a56ac5 2077 dev_priv->flags |= RADEON_IS_AGP;
b15ec368 2078 else if (drm_device_is_pcie(dev))
54a56ac5 2079 dev_priv->flags |= RADEON_IS_PCIE;
b15ec368 2080 else
54a56ac5 2081 dev_priv->flags |= RADEON_IS_PCI;
ea98a92f 2082
78538bf1
DA		 2083 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2084 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2085 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2086 if (ret != 0)
2087 return ret;
2088
52440211
KP		 2089 ret = drm_vblank_init(dev, 2);
2090 if (ret) {
2091 radeon_driver_unload(dev);
2092 return ret;
2093 }
2094
414ed537 2095 DRM_DEBUG("%s card detected\n",
54a56ac5 2096 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1da177e4
LT		 2097 return ret;
2098}
2099
7c1c2871
DA		 2100int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2101{
2102 struct drm_radeon_master_private *master_priv;
2103 unsigned long sareapage;
2104 int ret;
2105
2106 master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
2107 if (!master_priv)
2108 return -ENOMEM;
2109
2110 /* prebuild the SAREA */
bdf539ad 2111 sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
7c1c2871
DA		 2112 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
2113 &master_priv->sarea);
2114 if (ret) {
2115 DRM_ERROR("SAREA setup failed\n");
2116 return ret;
2117 }
2118 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
2119 master_priv->sarea_priv->pfCurrentPage = 0;
2120
2121 master->driver_priv = master_priv;
2122 return 0;
2123}
2124
2125void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2126{
2127 struct drm_radeon_master_private *master_priv = master->driver_priv;
2128
2129 if (!master_priv)
2130 return;
2131
2132 if (master_priv->sarea_priv &&
2133 master_priv->sarea_priv->pfCurrentPage != 0)
2134 radeon_cp_dispatch_flip(dev, master);
2135
2136 master_priv->sarea_priv = NULL;
2137 if (master_priv->sarea)
4e74f36d 2138 drm_rmmap_locked(dev, master_priv->sarea);
7c1c2871
DA		 2139
2140 drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
2141
2142 master->driver_priv = NULL;
2143}
2144
22eae947
DA		 2145/* Create mappings for registers and framebuffer so userland doesn't necessarily
2146 * have to find them.
2147 */
2148int radeon_driver_firstopen(struct drm_device *dev)
836cf046
DA		 2149{
2150 int ret;
2151 drm_local_map_t *map;
2152 drm_radeon_private_t *dev_priv = dev->dev_private;
2153
f2b04cd2
DA		 2154 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2155
7fc86860
DA		 2156 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2157 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
836cf046
DA		 2158 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2159 _DRM_WRITE_COMBINING, &map);
2160 if (ret != 0)
2161 return ret;
2162
2163 return 0;
2164}
2165
22eae947 2166int radeon_driver_unload(struct drm_device *dev)
1da177e4
LT		 2167{
2168 drm_radeon_private_t *dev_priv = dev->dev_private;
2169
2170 DRM_DEBUG("\n");
78538bf1
DA		 2171
2172 drm_rmmap(dev, dev_priv->mmio);
2173
1da177e4
LT		 2174 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2175
2176 dev->dev_private = NULL;
2177 return 0;
2178}
4247ca94
DA		 2179
2180void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2181{
2182 int i;
2183 u32 *ring;
2184 int tail_aligned;
2185
2186 /* check if the ring is padded out to 16-dword alignment */
2187
9863871b 2188 tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1);
4247ca94 2189 if (tail_aligned) {
9863871b 2190 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
4247ca94
DA		 2191
2192 ring = dev_priv->ring.start;
2193 /* pad with some CP_PACKET2 */
2194 for (i = 0; i < num_p2; i++)
2195 ring[dev_priv->ring.tail + i] = CP_PACKET2();
2196
2197 dev_priv->ring.tail += i;
2198
2199 dev_priv->ring.space -= num_p2 * sizeof(u32);
2200 }
2201
2202 dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2203
2204 DRM_MEMORYBARRIER();
2205 GET_RING_HEAD( dev_priv );
2206
c05ce083
AD		 2207 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2208 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2209 /* read from PCI bus to ensure correct posting */
2210 RADEON_READ(R600_CP_RB_RPTR);
2211 } else {
2212 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2213 /* read from PCI bus to ensure correct posting */
2214 RADEON_READ(RADEON_CP_RB_RPTR);
2215 }
4247ca94 2216}
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