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f26c473c DA |
1 | /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */ |
2 | /* | |
1da177e4 LT |
3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | |
45e51905 | 5 | * Copyright 2007 Advanced Micro Devices, Inc. |
1da177e4 LT |
6 | * All Rights Reserved. |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the next | |
16 | * paragraph) shall be included in all copies or substantial portions of the | |
17 | * Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
23 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
25 | * DEALINGS IN THE SOFTWARE. | |
26 | * | |
27 | * Authors: | |
28 | * Kevin E. Martin <martin@valinux.com> | |
29 | * Gareth Hughes <gareth@valinux.com> | |
30 | */ | |
31 | ||
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "radeon_drm.h" | |
35 | #include "radeon_drv.h" | |
414ed537 | 36 | #include "r300_reg.h" |
1da177e4 | 37 | |
9f18409e AD |
38 | #include "radeon_microcode.h" |
39 | ||
1da177e4 LT |
40 | #define RADEON_FIFO_DEBUG 0 |
41 | ||
84b1fd10 | 42 | static int radeon_do_cleanup_cp(struct drm_device * dev); |
1da177e4 | 43 | |
45e51905 | 44 | static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
3d5e2c13 DA |
45 | { |
46 | u32 ret; | |
47 | RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); | |
48 | ret = RADEON_READ(R520_MC_IND_DATA); | |
49 | RADEON_WRITE(R520_MC_IND_INDEX, 0); | |
50 | return ret; | |
51 | } | |
52 | ||
45e51905 AD |
53 | static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
54 | { | |
55 | u32 ret; | |
56 | RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff); | |
57 | ret = RADEON_READ(RS480_NB_MC_DATA); | |
58 | RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); | |
59 | return ret; | |
60 | } | |
61 | ||
60f92683 MC |
62 | static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
63 | { | |
45e51905 | 64 | u32 ret; |
60f92683 | 65 | RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); |
45e51905 AD |
66 | ret = RADEON_READ(RS690_MC_DATA); |
67 | RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK); | |
68 | return ret; | |
69 | } | |
70 | ||
71 | static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) | |
72 | { | |
73 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) | |
74 | return RS690_READ_MCIND(dev_priv, addr); | |
75 | else | |
76 | return RS480_READ_MCIND(dev_priv, addr); | |
60f92683 MC |
77 | } |
78 | ||
3d5e2c13 DA |
79 | u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) |
80 | { | |
81 | ||
82 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) | |
45e51905 | 83 | return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); |
60f92683 MC |
84 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) |
85 | return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); | |
3d5e2c13 | 86 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
45e51905 | 87 | return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); |
3d5e2c13 DA |
88 | else |
89 | return RADEON_READ(RADEON_MC_FB_LOCATION); | |
90 | } | |
91 | ||
92 | static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) | |
93 | { | |
94 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) | |
45e51905 | 95 | R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); |
60f92683 MC |
96 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) |
97 | RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); | |
3d5e2c13 | 98 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
45e51905 | 99 | R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); |
3d5e2c13 DA |
100 | else |
101 | RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); | |
102 | } | |
103 | ||
104 | static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) | |
105 | { | |
106 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) | |
45e51905 | 107 | R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); |
60f92683 MC |
108 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) |
109 | RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); | |
3d5e2c13 | 110 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
45e51905 | 111 | R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); |
3d5e2c13 DA |
112 | else |
113 | RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); | |
114 | } | |
115 | ||
70b13d51 DA |
116 | static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base) |
117 | { | |
118 | u32 agp_base_hi = upper_32_bits(agp_base); | |
119 | u32 agp_base_lo = agp_base & 0xffffffff; | |
120 | ||
121 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) { | |
122 | R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo); | |
123 | R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi); | |
124 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { | |
125 | RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo); | |
126 | RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi); | |
127 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { | |
128 | R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo); | |
129 | R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi); | |
5cfb6956 AD |
130 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) { |
131 | RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); | |
132 | RADEON_WRITE(RS480_AGP_BASE_2, 0); | |
70b13d51 DA |
133 | } else { |
134 | RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); | |
135 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) | |
136 | RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi); | |
137 | } | |
138 | } | |
139 | ||
84b1fd10 | 140 | static int RADEON_READ_PLL(struct drm_device * dev, int addr) |
1da177e4 LT |
141 | { |
142 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
143 | ||
144 | RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); | |
145 | return RADEON_READ(RADEON_CLOCK_CNTL_DATA); | |
146 | } | |
147 | ||
3d5e2c13 | 148 | static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) |
ea98a92f DA |
149 | { |
150 | RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); | |
151 | return RADEON_READ(RADEON_PCIE_DATA); | |
152 | } | |
153 | ||
1da177e4 | 154 | #if RADEON_FIFO_DEBUG |
b5e89ed5 | 155 | static void radeon_status(drm_radeon_private_t * dev_priv) |
1da177e4 | 156 | { |
bf9d8929 | 157 | printk("%s:\n", __func__); |
b5e89ed5 DA |
158 | printk("RBBM_STATUS = 0x%08x\n", |
159 | (unsigned int)RADEON_READ(RADEON_RBBM_STATUS)); | |
160 | printk("CP_RB_RTPR = 0x%08x\n", | |
161 | (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR)); | |
162 | printk("CP_RB_WTPR = 0x%08x\n", | |
163 | (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR)); | |
164 | printk("AIC_CNTL = 0x%08x\n", | |
165 | (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); | |
166 | printk("AIC_STAT = 0x%08x\n", | |
167 | (unsigned int)RADEON_READ(RADEON_AIC_STAT)); | |
168 | printk("AIC_PT_BASE = 0x%08x\n", | |
169 | (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE)); | |
170 | printk("TLB_ADDR = 0x%08x\n", | |
171 | (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR)); | |
172 | printk("TLB_DATA = 0x%08x\n", | |
173 | (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA)); | |
1da177e4 LT |
174 | } |
175 | #endif | |
176 | ||
1da177e4 LT |
177 | /* ================================================================ |
178 | * Engine, FIFO control | |
179 | */ | |
180 | ||
b5e89ed5 | 181 | static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
182 | { |
183 | u32 tmp; | |
184 | int i; | |
185 | ||
186 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
187 | ||
259434ac AD |
188 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { |
189 | tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); | |
190 | tmp |= RADEON_RB3D_DC_FLUSH_ALL; | |
191 | RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); | |
192 | ||
193 | for (i = 0; i < dev_priv->usec_timeout; i++) { | |
194 | if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) | |
195 | & RADEON_RB3D_DC_BUSY)) { | |
196 | return 0; | |
197 | } | |
198 | DRM_UDELAY(1); | |
199 | } | |
200 | } else { | |
201 | /* 3D */ | |
202 | tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT); | |
203 | tmp |= RADEON_RB3D_DC_FLUSH_ALL; | |
204 | RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp); | |
205 | ||
206 | /* 2D */ | |
5e35eff1 | 207 | tmp = RADEON_READ(R300_DSTCACHE_CTLSTAT); |
259434ac | 208 | tmp |= RADEON_RB3D_DC_FLUSH_ALL; |
5e35eff1 | 209 | RADEON_WRITE(R300_DSTCACHE_CTLSTAT, tmp); |
259434ac AD |
210 | |
211 | for (i = 0; i < dev_priv->usec_timeout; i++) { | |
5e35eff1 | 212 | if (!(RADEON_READ(R300_DSTCACHE_CTLSTAT) |
259434ac AD |
213 | & RADEON_RB3D_DC_BUSY)) { |
214 | return 0; | |
215 | } | |
216 | DRM_UDELAY(1); | |
1da177e4 | 217 | } |
1da177e4 LT |
218 | } |
219 | ||
220 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
221 | DRM_ERROR("failed!\n"); |
222 | radeon_status(dev_priv); | |
1da177e4 | 223 | #endif |
20caafa6 | 224 | return -EBUSY; |
1da177e4 LT |
225 | } |
226 | ||
b5e89ed5 | 227 | static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) |
1da177e4 LT |
228 | { |
229 | int i; | |
230 | ||
231 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
232 | ||
b5e89ed5 DA |
233 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
234 | int slots = (RADEON_READ(RADEON_RBBM_STATUS) | |
235 | & RADEON_RBBM_FIFOCNT_MASK); | |
236 | if (slots >= entries) | |
237 | return 0; | |
238 | DRM_UDELAY(1); | |
1da177e4 LT |
239 | } |
240 | ||
241 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
242 | DRM_ERROR("failed!\n"); |
243 | radeon_status(dev_priv); | |
1da177e4 | 244 | #endif |
20caafa6 | 245 | return -EBUSY; |
1da177e4 LT |
246 | } |
247 | ||
b5e89ed5 | 248 | static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
249 | { |
250 | int i, ret; | |
251 | ||
252 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
253 | ||
b5e89ed5 DA |
254 | ret = radeon_do_wait_for_fifo(dev_priv, 64); |
255 | if (ret) | |
256 | return ret; | |
1da177e4 | 257 | |
b5e89ed5 DA |
258 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
259 | if (!(RADEON_READ(RADEON_RBBM_STATUS) | |
260 | & RADEON_RBBM_ACTIVE)) { | |
261 | radeon_do_pixcache_flush(dev_priv); | |
1da177e4 LT |
262 | return 0; |
263 | } | |
b5e89ed5 | 264 | DRM_UDELAY(1); |
1da177e4 LT |
265 | } |
266 | ||
267 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
268 | DRM_ERROR("failed!\n"); |
269 | radeon_status(dev_priv); | |
1da177e4 | 270 | #endif |
20caafa6 | 271 | return -EBUSY; |
1da177e4 LT |
272 | } |
273 | ||
5b92c404 AD |
274 | static void radeon_init_pipes(drm_radeon_private_t *dev_priv) |
275 | { | |
276 | uint32_t gb_tile_config, gb_pipe_sel = 0; | |
277 | ||
278 | /* RS4xx/RS6xx/R4xx/R5xx */ | |
279 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { | |
280 | gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT); | |
281 | dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; | |
282 | } else { | |
283 | /* R3xx */ | |
284 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || | |
285 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) { | |
286 | dev_priv->num_gb_pipes = 2; | |
287 | } else { | |
288 | /* R3Vxx */ | |
289 | dev_priv->num_gb_pipes = 1; | |
290 | } | |
291 | } | |
292 | DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes); | |
293 | ||
294 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/); | |
295 | ||
296 | switch (dev_priv->num_gb_pipes) { | |
297 | case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; | |
298 | case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; | |
299 | case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; | |
300 | default: | |
301 | case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; | |
302 | } | |
303 | ||
304 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { | |
305 | RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); | |
306 | RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1)); | |
307 | } | |
308 | RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config); | |
309 | radeon_do_wait_for_idle(dev_priv); | |
310 | RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); | |
311 | RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) | | |
312 | R300_DC_AUTOFLUSH_ENABLE | | |
313 | R300_DC_DC_DISABLE_IGNORE_PE)); | |
314 | ||
315 | ||
316 | } | |
317 | ||
1da177e4 LT |
318 | /* ================================================================ |
319 | * CP control, initialization | |
320 | */ | |
321 | ||
322 | /* Load the microcode for the CP */ | |
b5e89ed5 | 323 | static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
324 | { |
325 | int i; | |
b5e89ed5 | 326 | DRM_DEBUG("\n"); |
1da177e4 | 327 | |
b5e89ed5 | 328 | radeon_do_wait_for_idle(dev_priv); |
1da177e4 | 329 | |
b5e89ed5 | 330 | RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); |
9f18409e AD |
331 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) || |
332 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) || | |
333 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) || | |
334 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) || | |
335 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) { | |
336 | DRM_INFO("Loading R100 Microcode\n"); | |
337 | for (i = 0; i < 256; i++) { | |
338 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
339 | R100_cp_microcode[i][1]); | |
340 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
341 | R100_cp_microcode[i][0]); | |
342 | } | |
343 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) || | |
344 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) || | |
345 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) || | |
346 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) { | |
1da177e4 | 347 | DRM_INFO("Loading R200 Microcode\n"); |
b5e89ed5 DA |
348 | for (i = 0; i < 256; i++) { |
349 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
350 | R200_cp_microcode[i][1]); | |
351 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
352 | R200_cp_microcode[i][0]); | |
1da177e4 | 353 | } |
9f18409e AD |
354 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || |
355 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || | |
356 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || | |
357 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || | |
45e51905 | 358 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { |
1da177e4 | 359 | DRM_INFO("Loading R300 Microcode\n"); |
b5e89ed5 DA |
360 | for (i = 0; i < 256; i++) { |
361 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
362 | R300_cp_microcode[i][1]); | |
363 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
364 | R300_cp_microcode[i][0]); | |
1da177e4 | 365 | } |
9f18409e AD |
366 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || |
367 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) { | |
368 | DRM_INFO("Loading R400 Microcode\n"); | |
369 | for (i = 0; i < 256; i++) { | |
370 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
371 | R420_cp_microcode[i][1]); | |
372 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
373 | R420_cp_microcode[i][0]); | |
374 | } | |
375 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { | |
376 | DRM_INFO("Loading RS690 Microcode\n"); | |
377 | for (i = 0; i < 256; i++) { | |
378 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
379 | RS690_cp_microcode[i][1]); | |
380 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
381 | RS690_cp_microcode[i][0]); | |
382 | } | |
383 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) || | |
384 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) || | |
385 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) || | |
386 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) || | |
387 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) || | |
388 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) { | |
389 | DRM_INFO("Loading R500 Microcode\n"); | |
b5e89ed5 DA |
390 | for (i = 0; i < 256; i++) { |
391 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
9f18409e | 392 | R520_cp_microcode[i][1]); |
b5e89ed5 | 393 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, |
9f18409e | 394 | R520_cp_microcode[i][0]); |
1da177e4 LT |
395 | } |
396 | } | |
397 | } | |
398 | ||
399 | /* Flush any pending commands to the CP. This should only be used just | |
400 | * prior to a wait for idle, as it informs the engine that the command | |
401 | * stream is ending. | |
402 | */ | |
b5e89ed5 | 403 | static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) |
1da177e4 | 404 | { |
b5e89ed5 | 405 | DRM_DEBUG("\n"); |
1da177e4 LT |
406 | #if 0 |
407 | u32 tmp; | |
408 | ||
b5e89ed5 DA |
409 | tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); |
410 | RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); | |
1da177e4 LT |
411 | #endif |
412 | } | |
413 | ||
414 | /* Wait for the CP to go idle. | |
415 | */ | |
b5e89ed5 | 416 | int radeon_do_cp_idle(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
417 | { |
418 | RING_LOCALS; | |
b5e89ed5 | 419 | DRM_DEBUG("\n"); |
1da177e4 | 420 | |
b5e89ed5 | 421 | BEGIN_RING(6); |
1da177e4 LT |
422 | |
423 | RADEON_PURGE_CACHE(); | |
424 | RADEON_PURGE_ZCACHE(); | |
425 | RADEON_WAIT_UNTIL_IDLE(); | |
426 | ||
427 | ADVANCE_RING(); | |
428 | COMMIT_RING(); | |
429 | ||
b5e89ed5 | 430 | return radeon_do_wait_for_idle(dev_priv); |
1da177e4 LT |
431 | } |
432 | ||
433 | /* Start the Command Processor. | |
434 | */ | |
b5e89ed5 | 435 | static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
436 | { |
437 | RING_LOCALS; | |
b5e89ed5 | 438 | DRM_DEBUG("\n"); |
1da177e4 | 439 | |
b5e89ed5 | 440 | radeon_do_wait_for_idle(dev_priv); |
1da177e4 | 441 | |
b5e89ed5 | 442 | RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); |
1da177e4 LT |
443 | |
444 | dev_priv->cp_running = 1; | |
445 | ||
b5e89ed5 | 446 | BEGIN_RING(6); |
1da177e4 LT |
447 | |
448 | RADEON_PURGE_CACHE(); | |
449 | RADEON_PURGE_ZCACHE(); | |
450 | RADEON_WAIT_UNTIL_IDLE(); | |
451 | ||
452 | ADVANCE_RING(); | |
453 | COMMIT_RING(); | |
454 | } | |
455 | ||
456 | /* Reset the Command Processor. This will not flush any pending | |
457 | * commands, so you must wait for the CP command stream to complete | |
458 | * before calling this routine. | |
459 | */ | |
b5e89ed5 | 460 | static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
461 | { |
462 | u32 cur_read_ptr; | |
b5e89ed5 | 463 | DRM_DEBUG("\n"); |
1da177e4 | 464 | |
b5e89ed5 DA |
465 | cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); |
466 | RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); | |
467 | SET_RING_HEAD(dev_priv, cur_read_ptr); | |
1da177e4 LT |
468 | dev_priv->ring.tail = cur_read_ptr; |
469 | } | |
470 | ||
471 | /* Stop the Command Processor. This will not flush any pending | |
472 | * commands, so you must flush the command stream and wait for the CP | |
473 | * to go idle before calling this routine. | |
474 | */ | |
b5e89ed5 | 475 | static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) |
1da177e4 | 476 | { |
b5e89ed5 | 477 | DRM_DEBUG("\n"); |
1da177e4 | 478 | |
b5e89ed5 | 479 | RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); |
1da177e4 LT |
480 | |
481 | dev_priv->cp_running = 0; | |
482 | } | |
483 | ||
484 | /* Reset the engine. This will stop the CP if it is running. | |
485 | */ | |
84b1fd10 | 486 | static int radeon_do_engine_reset(struct drm_device * dev) |
1da177e4 LT |
487 | { |
488 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
d396db32 | 489 | u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset; |
b5e89ed5 | 490 | DRM_DEBUG("\n"); |
1da177e4 | 491 | |
b5e89ed5 DA |
492 | radeon_do_pixcache_flush(dev_priv); |
493 | ||
d396db32 AD |
494 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { |
495 | /* may need something similar for newer chips */ | |
3d5e2c13 DA |
496 | clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); |
497 | mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); | |
498 | ||
499 | RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | | |
500 | RADEON_FORCEON_MCLKA | | |
501 | RADEON_FORCEON_MCLKB | | |
502 | RADEON_FORCEON_YCLKA | | |
503 | RADEON_FORCEON_YCLKB | | |
504 | RADEON_FORCEON_MC | | |
505 | RADEON_FORCEON_AIC)); | |
d396db32 | 506 | } |
3d5e2c13 | 507 | |
d396db32 AD |
508 | rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); |
509 | ||
510 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | | |
511 | RADEON_SOFT_RESET_CP | | |
512 | RADEON_SOFT_RESET_HI | | |
513 | RADEON_SOFT_RESET_SE | | |
514 | RADEON_SOFT_RESET_RE | | |
515 | RADEON_SOFT_RESET_PP | | |
516 | RADEON_SOFT_RESET_E2 | | |
517 | RADEON_SOFT_RESET_RB)); | |
518 | RADEON_READ(RADEON_RBBM_SOFT_RESET); | |
519 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & | |
520 | ~(RADEON_SOFT_RESET_CP | | |
521 | RADEON_SOFT_RESET_HI | | |
522 | RADEON_SOFT_RESET_SE | | |
523 | RADEON_SOFT_RESET_RE | | |
524 | RADEON_SOFT_RESET_PP | | |
525 | RADEON_SOFT_RESET_E2 | | |
526 | RADEON_SOFT_RESET_RB))); | |
527 | RADEON_READ(RADEON_RBBM_SOFT_RESET); | |
528 | ||
529 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { | |
3d5e2c13 DA |
530 | RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); |
531 | RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); | |
532 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); | |
533 | } | |
1da177e4 | 534 | |
5b92c404 AD |
535 | /* setup the raster pipes */ |
536 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300) | |
537 | radeon_init_pipes(dev_priv); | |
538 | ||
1da177e4 | 539 | /* Reset the CP ring */ |
b5e89ed5 | 540 | radeon_do_cp_reset(dev_priv); |
1da177e4 LT |
541 | |
542 | /* The CP is no longer running after an engine reset */ | |
543 | dev_priv->cp_running = 0; | |
544 | ||
545 | /* Reset any pending vertex, indirect buffers */ | |
b5e89ed5 | 546 | radeon_freelist_reset(dev); |
1da177e4 LT |
547 | |
548 | return 0; | |
549 | } | |
550 | ||
84b1fd10 | 551 | static void radeon_cp_init_ring_buffer(struct drm_device * dev, |
b5e89ed5 | 552 | drm_radeon_private_t * dev_priv) |
1da177e4 LT |
553 | { |
554 | u32 ring_start, cur_read_ptr; | |
555 | u32 tmp; | |
bc5f4523 | 556 | |
d5ea702f DA |
557 | /* Initialize the memory controller. With new memory map, the fb location |
558 | * is not changed, it should have been properly initialized already. Part | |
559 | * of the problem is that the code below is bogus, assuming the GART is | |
560 | * always appended to the fb which is not necessarily the case | |
561 | */ | |
562 | if (!dev_priv->new_memmap) | |
3d5e2c13 | 563 | radeon_write_fb_location(dev_priv, |
d5ea702f DA |
564 | ((dev_priv->gart_vm_start - 1) & 0xffff0000) |
565 | | (dev_priv->fb_location >> 16)); | |
1da177e4 LT |
566 | |
567 | #if __OS_HAS_AGP | |
54a56ac5 | 568 | if (dev_priv->flags & RADEON_IS_AGP) { |
70b13d51 DA |
569 | radeon_write_agp_base(dev_priv, dev->agp->base); |
570 | ||
3d5e2c13 | 571 | radeon_write_agp_location(dev_priv, |
b5e89ed5 DA |
572 | (((dev_priv->gart_vm_start - 1 + |
573 | dev_priv->gart_size) & 0xffff0000) | | |
574 | (dev_priv->gart_vm_start >> 16))); | |
1da177e4 LT |
575 | |
576 | ring_start = (dev_priv->cp_ring->offset | |
577 | - dev->agp->base | |
578 | + dev_priv->gart_vm_start); | |
b0917bd9 | 579 | } else |
1da177e4 LT |
580 | #endif |
581 | ring_start = (dev_priv->cp_ring->offset | |
b0917bd9 | 582 | - (unsigned long)dev->sg->virtual |
1da177e4 LT |
583 | + dev_priv->gart_vm_start); |
584 | ||
b5e89ed5 | 585 | RADEON_WRITE(RADEON_CP_RB_BASE, ring_start); |
1da177e4 LT |
586 | |
587 | /* Set the write pointer delay */ | |
b5e89ed5 | 588 | RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0); |
1da177e4 LT |
589 | |
590 | /* Initialize the ring buffer's read and write pointers */ | |
b5e89ed5 DA |
591 | cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); |
592 | RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); | |
593 | SET_RING_HEAD(dev_priv, cur_read_ptr); | |
1da177e4 LT |
594 | dev_priv->ring.tail = cur_read_ptr; |
595 | ||
596 | #if __OS_HAS_AGP | |
54a56ac5 | 597 | if (dev_priv->flags & RADEON_IS_AGP) { |
b5e89ed5 DA |
598 | RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, |
599 | dev_priv->ring_rptr->offset | |
600 | - dev->agp->base + dev_priv->gart_vm_start); | |
1da177e4 LT |
601 | } else |
602 | #endif | |
603 | { | |
55910517 | 604 | struct drm_sg_mem *entry = dev->sg; |
1da177e4 LT |
605 | unsigned long tmp_ofs, page_ofs; |
606 | ||
b0917bd9 IK |
607 | tmp_ofs = dev_priv->ring_rptr->offset - |
608 | (unsigned long)dev->sg->virtual; | |
1da177e4 LT |
609 | page_ofs = tmp_ofs >> PAGE_SHIFT; |
610 | ||
b5e89ed5 DA |
611 | RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]); |
612 | DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n", | |
613 | (unsigned long)entry->busaddr[page_ofs], | |
614 | entry->handle + tmp_ofs); | |
1da177e4 LT |
615 | } |
616 | ||
d5ea702f DA |
617 | /* Set ring buffer size */ |
618 | #ifdef __BIG_ENDIAN | |
619 | RADEON_WRITE(RADEON_CP_RB_CNTL, | |
576cc458 RS |
620 | RADEON_BUF_SWAP_32BIT | |
621 | (dev_priv->ring.fetch_size_l2ow << 18) | | |
622 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
623 | dev_priv->ring.size_l2qw); | |
d5ea702f | 624 | #else |
576cc458 RS |
625 | RADEON_WRITE(RADEON_CP_RB_CNTL, |
626 | (dev_priv->ring.fetch_size_l2ow << 18) | | |
627 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
628 | dev_priv->ring.size_l2qw); | |
d5ea702f DA |
629 | #endif |
630 | ||
631 | /* Start with assuming that writeback doesn't work */ | |
632 | dev_priv->writeback_works = 0; | |
633 | ||
1da177e4 LT |
634 | /* Initialize the scratch register pointer. This will cause |
635 | * the scratch register values to be written out to memory | |
636 | * whenever they are updated. | |
637 | * | |
638 | * We simply put this behind the ring read pointer, this works | |
639 | * with PCI GART as well as (whatever kind of) AGP GART | |
640 | */ | |
b5e89ed5 DA |
641 | RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR) |
642 | + RADEON_SCRATCH_REG_OFFSET); | |
1da177e4 LT |
643 | |
644 | dev_priv->scratch = ((__volatile__ u32 *) | |
645 | dev_priv->ring_rptr->handle + | |
646 | (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); | |
647 | ||
b5e89ed5 | 648 | RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); |
1da177e4 | 649 | |
d5ea702f DA |
650 | /* Turn on bus mastering */ |
651 | tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; | |
652 | RADEON_WRITE(RADEON_BUS_CNTL, tmp); | |
1da177e4 LT |
653 | |
654 | dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; | |
b5e89ed5 | 655 | RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); |
1da177e4 LT |
656 | |
657 | dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; | |
b5e89ed5 DA |
658 | RADEON_WRITE(RADEON_LAST_DISPATCH_REG, |
659 | dev_priv->sarea_priv->last_dispatch); | |
1da177e4 LT |
660 | |
661 | dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; | |
b5e89ed5 | 662 | RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear); |
1da177e4 | 663 | |
b5e89ed5 | 664 | radeon_do_wait_for_idle(dev_priv); |
1da177e4 | 665 | |
1da177e4 | 666 | /* Sync everything up */ |
b5e89ed5 DA |
667 | RADEON_WRITE(RADEON_ISYNC_CNTL, |
668 | (RADEON_ISYNC_ANY2D_IDLE3D | | |
669 | RADEON_ISYNC_ANY3D_IDLE2D | | |
670 | RADEON_ISYNC_WAIT_IDLEGUI | | |
671 | RADEON_ISYNC_CPSCRATCH_IDLEGUI)); | |
d5ea702f DA |
672 | |
673 | } | |
674 | ||
675 | static void radeon_test_writeback(drm_radeon_private_t * dev_priv) | |
676 | { | |
677 | u32 tmp; | |
678 | ||
679 | /* Writeback doesn't seem to work everywhere, test it here and possibly | |
680 | * enable it if it appears to work | |
681 | */ | |
682 | DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0); | |
683 | RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef); | |
684 | ||
685 | for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { | |
686 | if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) == | |
687 | 0xdeadbeef) | |
688 | break; | |
689 | DRM_UDELAY(1); | |
690 | } | |
691 | ||
692 | if (tmp < dev_priv->usec_timeout) { | |
693 | dev_priv->writeback_works = 1; | |
694 | DRM_INFO("writeback test succeeded in %d usecs\n", tmp); | |
695 | } else { | |
696 | dev_priv->writeback_works = 0; | |
697 | DRM_INFO("writeback test failed\n"); | |
698 | } | |
699 | if (radeon_no_wb == 1) { | |
700 | dev_priv->writeback_works = 0; | |
701 | DRM_INFO("writeback forced off\n"); | |
702 | } | |
ae1b1a48 MD |
703 | |
704 | if (!dev_priv->writeback_works) { | |
705 | /* Disable writeback to avoid unnecessary bus master transfer */ | |
706 | RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | | |
707 | RADEON_RB_NO_UPDATE); | |
708 | RADEON_WRITE(RADEON_SCRATCH_UMSK, 0); | |
709 | } | |
1da177e4 LT |
710 | } |
711 | ||
f2b04cd2 DA |
712 | /* Enable or disable IGP GART on the chip */ |
713 | static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) | |
60f92683 MC |
714 | { |
715 | u32 temp; | |
716 | ||
717 | if (on) { | |
45e51905 | 718 | DRM_DEBUG("programming igp gart %08X %08lX %08X\n", |
60f92683 MC |
719 | dev_priv->gart_vm_start, |
720 | (long)dev_priv->gart_info.bus_addr, | |
721 | dev_priv->gart_size); | |
722 | ||
45e51905 AD |
723 | temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL); |
724 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) | |
725 | IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN | | |
726 | RS690_BLOCK_GFX_D3_EN)); | |
727 | else | |
728 | IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); | |
60f92683 | 729 | |
45e51905 AD |
730 | IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | |
731 | RS480_VA_SIZE_32MB)); | |
60f92683 | 732 | |
45e51905 AD |
733 | temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID); |
734 | IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN | | |
735 | RS480_TLB_ENABLE | | |
736 | RS480_GTW_LAC_EN | | |
737 | RS480_1LEVEL_GART)); | |
60f92683 | 738 | |
fa0d71b9 DA |
739 | temp = dev_priv->gart_info.bus_addr & 0xfffff000; |
740 | temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; | |
45e51905 AD |
741 | IGP_WRITE_MCIND(RS480_GART_BASE, temp); |
742 | ||
743 | temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL); | |
744 | IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) | | |
745 | RS480_REQ_TYPE_SNOOP_DIS)); | |
746 | ||
5cfb6956 | 747 | radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start); |
3722bfc6 | 748 | |
60f92683 MC |
749 | dev_priv->gart_size = 32*1024*1024; |
750 | temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & | |
751 | 0xffff0000) | (dev_priv->gart_vm_start >> 16)); | |
752 | ||
45e51905 | 753 | radeon_write_agp_location(dev_priv, temp); |
60f92683 | 754 | |
45e51905 AD |
755 | temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE); |
756 | IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | | |
757 | RS480_VA_SIZE_32MB)); | |
60f92683 MC |
758 | |
759 | do { | |
45e51905 AD |
760 | temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); |
761 | if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) | |
60f92683 MC |
762 | break; |
763 | DRM_UDELAY(1); | |
764 | } while (1); | |
765 | ||
45e51905 AD |
766 | IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, |
767 | RS480_GART_CACHE_INVALIDATE); | |
2735977b | 768 | |
60f92683 | 769 | do { |
45e51905 AD |
770 | temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); |
771 | if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) | |
60f92683 MC |
772 | break; |
773 | DRM_UDELAY(1); | |
774 | } while (1); | |
775 | ||
45e51905 | 776 | IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0); |
60f92683 | 777 | } else { |
45e51905 | 778 | IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0); |
60f92683 MC |
779 | } |
780 | } | |
781 | ||
ea98a92f DA |
782 | static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) |
783 | { | |
784 | u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); | |
785 | if (on) { | |
786 | ||
787 | DRM_DEBUG("programming pcie %08X %08lX %08X\n", | |
b5e89ed5 DA |
788 | dev_priv->gart_vm_start, |
789 | (long)dev_priv->gart_info.bus_addr, | |
ea98a92f | 790 | dev_priv->gart_size); |
b5e89ed5 DA |
791 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, |
792 | dev_priv->gart_vm_start); | |
793 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, | |
794 | dev_priv->gart_info.bus_addr); | |
795 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, | |
796 | dev_priv->gart_vm_start); | |
797 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, | |
798 | dev_priv->gart_vm_start + | |
799 | dev_priv->gart_size - 1); | |
800 | ||
3d5e2c13 | 801 | radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */ |
b5e89ed5 DA |
802 | |
803 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, | |
804 | RADEON_PCIE_TX_GART_EN); | |
ea98a92f | 805 | } else { |
b5e89ed5 DA |
806 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, |
807 | tmp & ~RADEON_PCIE_TX_GART_EN); | |
ea98a92f | 808 | } |
1da177e4 LT |
809 | } |
810 | ||
811 | /* Enable or disable PCI GART on the chip */ | |
b5e89ed5 | 812 | static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) |
1da177e4 | 813 | { |
d985c108 | 814 | u32 tmp; |
1da177e4 | 815 | |
45e51905 AD |
816 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
817 | (dev_priv->flags & RADEON_IS_IGPGART)) { | |
f2b04cd2 DA |
818 | radeon_set_igpgart(dev_priv, on); |
819 | return; | |
820 | } | |
821 | ||
54a56ac5 | 822 | if (dev_priv->flags & RADEON_IS_PCIE) { |
ea98a92f DA |
823 | radeon_set_pciegart(dev_priv, on); |
824 | return; | |
825 | } | |
1da177e4 | 826 | |
bc5f4523 | 827 | tmp = RADEON_READ(RADEON_AIC_CNTL); |
d985c108 | 828 | |
b5e89ed5 DA |
829 | if (on) { |
830 | RADEON_WRITE(RADEON_AIC_CNTL, | |
831 | tmp | RADEON_PCIGART_TRANSLATE_EN); | |
1da177e4 LT |
832 | |
833 | /* set PCI GART page-table base address | |
834 | */ | |
ea98a92f | 835 | RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr); |
1da177e4 LT |
836 | |
837 | /* set address range for PCI address translate | |
838 | */ | |
b5e89ed5 DA |
839 | RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); |
840 | RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start | |
841 | + dev_priv->gart_size - 1); | |
1da177e4 LT |
842 | |
843 | /* Turn off AGP aperture -- is this required for PCI GART? | |
844 | */ | |
3d5e2c13 | 845 | radeon_write_agp_location(dev_priv, 0xffffffc0); |
b5e89ed5 | 846 | RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ |
1da177e4 | 847 | } else { |
b5e89ed5 DA |
848 | RADEON_WRITE(RADEON_AIC_CNTL, |
849 | tmp & ~RADEON_PCIGART_TRANSLATE_EN); | |
1da177e4 LT |
850 | } |
851 | } | |
852 | ||
84b1fd10 | 853 | static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) |
1da177e4 | 854 | { |
d985c108 DA |
855 | drm_radeon_private_t *dev_priv = dev->dev_private; |
856 | ||
b5e89ed5 | 857 | DRM_DEBUG("\n"); |
1da177e4 | 858 | |
f3dd5c37 | 859 | /* if we require new memory map but we don't have it fail */ |
54a56ac5 | 860 | if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { |
b15ec368 | 861 | DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); |
f3dd5c37 | 862 | radeon_do_cleanup_cp(dev); |
20caafa6 | 863 | return -EINVAL; |
f3dd5c37 DA |
864 | } |
865 | ||
54a56ac5 | 866 | if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { |
d985c108 | 867 | DRM_DEBUG("Forcing AGP card to PCI mode\n"); |
54a56ac5 DA |
868 | dev_priv->flags &= ~RADEON_IS_AGP; |
869 | } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) | |
b15ec368 DA |
870 | && !init->is_pci) { |
871 | DRM_DEBUG("Restoring AGP flag\n"); | |
54a56ac5 | 872 | dev_priv->flags |= RADEON_IS_AGP; |
d985c108 | 873 | } |
1da177e4 | 874 | |
54a56ac5 | 875 | if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) { |
b5e89ed5 | 876 | DRM_ERROR("PCI GART memory not allocated!\n"); |
1da177e4 | 877 | radeon_do_cleanup_cp(dev); |
20caafa6 | 878 | return -EINVAL; |
1da177e4 LT |
879 | } |
880 | ||
881 | dev_priv->usec_timeout = init->usec_timeout; | |
b5e89ed5 DA |
882 | if (dev_priv->usec_timeout < 1 || |
883 | dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { | |
884 | DRM_DEBUG("TIMEOUT problem!\n"); | |
1da177e4 | 885 | radeon_do_cleanup_cp(dev); |
20caafa6 | 886 | return -EINVAL; |
1da177e4 LT |
887 | } |
888 | ||
ddbee333 DA |
889 | /* Enable vblank on CRTC1 for older X servers |
890 | */ | |
891 | dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; | |
892 | ||
d985c108 | 893 | switch(init->func) { |
1da177e4 | 894 | case RADEON_INIT_R200_CP: |
b5e89ed5 | 895 | dev_priv->microcode_version = UCODE_R200; |
1da177e4 LT |
896 | break; |
897 | case RADEON_INIT_R300_CP: | |
b5e89ed5 | 898 | dev_priv->microcode_version = UCODE_R300; |
1da177e4 LT |
899 | break; |
900 | default: | |
b5e89ed5 | 901 | dev_priv->microcode_version = UCODE_R100; |
1da177e4 | 902 | } |
b5e89ed5 | 903 | |
1da177e4 LT |
904 | dev_priv->do_boxes = 0; |
905 | dev_priv->cp_mode = init->cp_mode; | |
906 | ||
907 | /* We don't support anything other than bus-mastering ring mode, | |
908 | * but the ring can be in either AGP or PCI space for the ring | |
909 | * read pointer. | |
910 | */ | |
b5e89ed5 DA |
911 | if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && |
912 | (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { | |
913 | DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); | |
1da177e4 | 914 | radeon_do_cleanup_cp(dev); |
20caafa6 | 915 | return -EINVAL; |
1da177e4 LT |
916 | } |
917 | ||
b5e89ed5 | 918 | switch (init->fb_bpp) { |
1da177e4 LT |
919 | case 16: |
920 | dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; | |
921 | break; | |
922 | case 32: | |
923 | default: | |
924 | dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; | |
925 | break; | |
926 | } | |
b5e89ed5 DA |
927 | dev_priv->front_offset = init->front_offset; |
928 | dev_priv->front_pitch = init->front_pitch; | |
929 | dev_priv->back_offset = init->back_offset; | |
930 | dev_priv->back_pitch = init->back_pitch; | |
1da177e4 | 931 | |
b5e89ed5 | 932 | switch (init->depth_bpp) { |
1da177e4 LT |
933 | case 16: |
934 | dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; | |
935 | break; | |
936 | case 32: | |
937 | default: | |
938 | dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; | |
939 | break; | |
940 | } | |
b5e89ed5 DA |
941 | dev_priv->depth_offset = init->depth_offset; |
942 | dev_priv->depth_pitch = init->depth_pitch; | |
1da177e4 LT |
943 | |
944 | /* Hardware state for depth clears. Remove this if/when we no | |
945 | * longer clear the depth buffer with a 3D rectangle. Hard-code | |
946 | * all values to prevent unwanted 3D state from slipping through | |
947 | * and screwing with the clear operation. | |
948 | */ | |
949 | dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | | |
950 | (dev_priv->color_fmt << 10) | | |
b5e89ed5 DA |
951 | (dev_priv->microcode_version == |
952 | UCODE_R100 ? RADEON_ZBLOCK16 : 0)); | |
1da177e4 | 953 | |
b5e89ed5 DA |
954 | dev_priv->depth_clear.rb3d_zstencilcntl = |
955 | (dev_priv->depth_fmt | | |
956 | RADEON_Z_TEST_ALWAYS | | |
957 | RADEON_STENCIL_TEST_ALWAYS | | |
958 | RADEON_STENCIL_S_FAIL_REPLACE | | |
959 | RADEON_STENCIL_ZPASS_REPLACE | | |
960 | RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE); | |
1da177e4 LT |
961 | |
962 | dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | | |
963 | RADEON_BFACE_SOLID | | |
964 | RADEON_FFACE_SOLID | | |
965 | RADEON_FLAT_SHADE_VTX_LAST | | |
966 | RADEON_DIFFUSE_SHADE_FLAT | | |
967 | RADEON_ALPHA_SHADE_FLAT | | |
968 | RADEON_SPECULAR_SHADE_FLAT | | |
969 | RADEON_FOG_SHADE_FLAT | | |
970 | RADEON_VTX_PIX_CENTER_OGL | | |
971 | RADEON_ROUND_MODE_TRUNC | | |
972 | RADEON_ROUND_PREC_8TH_PIX); | |
973 | ||
1da177e4 | 974 | |
1da177e4 LT |
975 | dev_priv->ring_offset = init->ring_offset; |
976 | dev_priv->ring_rptr_offset = init->ring_rptr_offset; | |
977 | dev_priv->buffers_offset = init->buffers_offset; | |
978 | dev_priv->gart_textures_offset = init->gart_textures_offset; | |
b5e89ed5 | 979 | |
da509d7a | 980 | dev_priv->sarea = drm_getsarea(dev); |
b5e89ed5 | 981 | if (!dev_priv->sarea) { |
1da177e4 | 982 | DRM_ERROR("could not find sarea!\n"); |
1da177e4 | 983 | radeon_do_cleanup_cp(dev); |
20caafa6 | 984 | return -EINVAL; |
1da177e4 LT |
985 | } |
986 | ||
1da177e4 | 987 | dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); |
b5e89ed5 | 988 | if (!dev_priv->cp_ring) { |
1da177e4 | 989 | DRM_ERROR("could not find cp ring region!\n"); |
1da177e4 | 990 | radeon_do_cleanup_cp(dev); |
20caafa6 | 991 | return -EINVAL; |
1da177e4 LT |
992 | } |
993 | dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); | |
b5e89ed5 | 994 | if (!dev_priv->ring_rptr) { |
1da177e4 | 995 | DRM_ERROR("could not find ring read pointer!\n"); |
1da177e4 | 996 | radeon_do_cleanup_cp(dev); |
20caafa6 | 997 | return -EINVAL; |
1da177e4 | 998 | } |
d1f2b55a | 999 | dev->agp_buffer_token = init->buffers_offset; |
1da177e4 | 1000 | dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); |
b5e89ed5 | 1001 | if (!dev->agp_buffer_map) { |
1da177e4 | 1002 | DRM_ERROR("could not find dma buffer region!\n"); |
1da177e4 | 1003 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1004 | return -EINVAL; |
1da177e4 LT |
1005 | } |
1006 | ||
b5e89ed5 DA |
1007 | if (init->gart_textures_offset) { |
1008 | dev_priv->gart_textures = | |
1009 | drm_core_findmap(dev, init->gart_textures_offset); | |
1010 | if (!dev_priv->gart_textures) { | |
1da177e4 | 1011 | DRM_ERROR("could not find GART texture region!\n"); |
1da177e4 | 1012 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1013 | return -EINVAL; |
1da177e4 LT |
1014 | } |
1015 | } | |
1016 | ||
1017 | dev_priv->sarea_priv = | |
b5e89ed5 DA |
1018 | (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle + |
1019 | init->sarea_priv_offset); | |
1da177e4 LT |
1020 | |
1021 | #if __OS_HAS_AGP | |
54a56ac5 | 1022 | if (dev_priv->flags & RADEON_IS_AGP) { |
b5e89ed5 DA |
1023 | drm_core_ioremap(dev_priv->cp_ring, dev); |
1024 | drm_core_ioremap(dev_priv->ring_rptr, dev); | |
1025 | drm_core_ioremap(dev->agp_buffer_map, dev); | |
1026 | if (!dev_priv->cp_ring->handle || | |
1027 | !dev_priv->ring_rptr->handle || | |
1028 | !dev->agp_buffer_map->handle) { | |
1da177e4 | 1029 | DRM_ERROR("could not find ioremap agp regions!\n"); |
1da177e4 | 1030 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1031 | return -EINVAL; |
1da177e4 LT |
1032 | } |
1033 | } else | |
1034 | #endif | |
1035 | { | |
b5e89ed5 | 1036 | dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; |
1da177e4 | 1037 | dev_priv->ring_rptr->handle = |
b5e89ed5 DA |
1038 | (void *)dev_priv->ring_rptr->offset; |
1039 | dev->agp_buffer_map->handle = | |
1040 | (void *)dev->agp_buffer_map->offset; | |
1041 | ||
1042 | DRM_DEBUG("dev_priv->cp_ring->handle %p\n", | |
1043 | dev_priv->cp_ring->handle); | |
1044 | DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", | |
1045 | dev_priv->ring_rptr->handle); | |
1046 | DRM_DEBUG("dev->agp_buffer_map->handle %p\n", | |
1047 | dev->agp_buffer_map->handle); | |
1da177e4 LT |
1048 | } |
1049 | ||
3d5e2c13 | 1050 | dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16; |
bc5f4523 | 1051 | dev_priv->fb_size = |
3d5e2c13 | 1052 | ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000) |
d5ea702f | 1053 | - dev_priv->fb_location; |
1da177e4 | 1054 | |
b5e89ed5 DA |
1055 | dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | |
1056 | ((dev_priv->front_offset | |
1057 | + dev_priv->fb_location) >> 10)); | |
1da177e4 | 1058 | |
b5e89ed5 DA |
1059 | dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | |
1060 | ((dev_priv->back_offset | |
1061 | + dev_priv->fb_location) >> 10)); | |
1da177e4 | 1062 | |
b5e89ed5 DA |
1063 | dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | |
1064 | ((dev_priv->depth_offset | |
1065 | + dev_priv->fb_location) >> 10)); | |
1da177e4 LT |
1066 | |
1067 | dev_priv->gart_size = init->gart_size; | |
d5ea702f DA |
1068 | |
1069 | /* New let's set the memory map ... */ | |
1070 | if (dev_priv->new_memmap) { | |
1071 | u32 base = 0; | |
1072 | ||
1073 | DRM_INFO("Setting GART location based on new memory map\n"); | |
1074 | ||
1075 | /* If using AGP, try to locate the AGP aperture at the same | |
1076 | * location in the card and on the bus, though we have to | |
1077 | * align it down. | |
1078 | */ | |
1079 | #if __OS_HAS_AGP | |
54a56ac5 | 1080 | if (dev_priv->flags & RADEON_IS_AGP) { |
d5ea702f DA |
1081 | base = dev->agp->base; |
1082 | /* Check if valid */ | |
80b2c386 MD |
1083 | if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && |
1084 | base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { | |
d5ea702f DA |
1085 | DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", |
1086 | dev->agp->base); | |
1087 | base = 0; | |
1088 | } | |
1089 | } | |
1090 | #endif | |
1091 | /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ | |
1092 | if (base == 0) { | |
1093 | base = dev_priv->fb_location + dev_priv->fb_size; | |
80b2c386 MD |
1094 | if (base < dev_priv->fb_location || |
1095 | ((base + dev_priv->gart_size) & 0xfffffffful) < base) | |
d5ea702f DA |
1096 | base = dev_priv->fb_location |
1097 | - dev_priv->gart_size; | |
bc5f4523 | 1098 | } |
d5ea702f DA |
1099 | dev_priv->gart_vm_start = base & 0xffc00000u; |
1100 | if (dev_priv->gart_vm_start != base) | |
1101 | DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", | |
1102 | base, dev_priv->gart_vm_start); | |
1103 | } else { | |
1104 | DRM_INFO("Setting GART location based on old memory map\n"); | |
1105 | dev_priv->gart_vm_start = dev_priv->fb_location + | |
1106 | RADEON_READ(RADEON_CONFIG_APER_SIZE); | |
1107 | } | |
1da177e4 LT |
1108 | |
1109 | #if __OS_HAS_AGP | |
54a56ac5 | 1110 | if (dev_priv->flags & RADEON_IS_AGP) |
1da177e4 | 1111 | dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset |
b5e89ed5 DA |
1112 | - dev->agp->base |
1113 | + dev_priv->gart_vm_start); | |
1da177e4 LT |
1114 | else |
1115 | #endif | |
1116 | dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset | |
b0917bd9 IK |
1117 | - (unsigned long)dev->sg->virtual |
1118 | + dev_priv->gart_vm_start); | |
1da177e4 | 1119 | |
b5e89ed5 DA |
1120 | DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); |
1121 | DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start); | |
1122 | DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n", | |
1123 | dev_priv->gart_buffers_offset); | |
1da177e4 | 1124 | |
b5e89ed5 DA |
1125 | dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; |
1126 | dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle | |
1da177e4 LT |
1127 | + init->ring_size / sizeof(u32)); |
1128 | dev_priv->ring.size = init->ring_size; | |
b5e89ed5 | 1129 | dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); |
1da177e4 | 1130 | |
576cc458 RS |
1131 | dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; |
1132 | dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8); | |
1133 | ||
1134 | dev_priv->ring.fetch_size = /* init->fetch_size */ 32; | |
1135 | dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16); | |
b5e89ed5 | 1136 | dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; |
1da177e4 LT |
1137 | |
1138 | dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; | |
1139 | ||
1140 | #if __OS_HAS_AGP | |
54a56ac5 | 1141 | if (dev_priv->flags & RADEON_IS_AGP) { |
1da177e4 | 1142 | /* Turn off PCI GART */ |
b5e89ed5 | 1143 | radeon_set_pcigart(dev_priv, 0); |
1da177e4 LT |
1144 | } else |
1145 | #endif | |
1146 | { | |
b05c2385 | 1147 | dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); |
ea98a92f | 1148 | /* if we have an offset set from userspace */ |
f2b04cd2 | 1149 | if (dev_priv->pcigart_offset_set) { |
b5e89ed5 DA |
1150 | dev_priv->gart_info.bus_addr = |
1151 | dev_priv->pcigart_offset + dev_priv->fb_location; | |
f26c473c | 1152 | dev_priv->gart_info.mapping.offset = |
7fc86860 | 1153 | dev_priv->pcigart_offset + dev_priv->fb_aper_offset; |
f26c473c | 1154 | dev_priv->gart_info.mapping.size = |
f2b04cd2 | 1155 | dev_priv->gart_info.table_size; |
f26c473c | 1156 | |
242e3df8 | 1157 | drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); |
b5e89ed5 | 1158 | dev_priv->gart_info.addr = |
f26c473c | 1159 | dev_priv->gart_info.mapping.handle; |
b5e89ed5 | 1160 | |
f2b04cd2 DA |
1161 | if (dev_priv->flags & RADEON_IS_PCIE) |
1162 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE; | |
1163 | else | |
1164 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; | |
b5e89ed5 DA |
1165 | dev_priv->gart_info.gart_table_location = |
1166 | DRM_ATI_GART_FB; | |
1167 | ||
f26c473c | 1168 | DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", |
b5e89ed5 DA |
1169 | dev_priv->gart_info.addr, |
1170 | dev_priv->pcigart_offset); | |
1171 | } else { | |
f2b04cd2 DA |
1172 | if (dev_priv->flags & RADEON_IS_IGPGART) |
1173 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP; | |
1174 | else | |
1175 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; | |
b5e89ed5 DA |
1176 | dev_priv->gart_info.gart_table_location = |
1177 | DRM_ATI_GART_MAIN; | |
f26c473c DA |
1178 | dev_priv->gart_info.addr = NULL; |
1179 | dev_priv->gart_info.bus_addr = 0; | |
54a56ac5 | 1180 | if (dev_priv->flags & RADEON_IS_PCIE) { |
b5e89ed5 DA |
1181 | DRM_ERROR |
1182 | ("Cannot use PCI Express without GART in FB memory\n"); | |
ea98a92f | 1183 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1184 | return -EINVAL; |
ea98a92f DA |
1185 | } |
1186 | } | |
1187 | ||
1188 | if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { | |
b5e89ed5 | 1189 | DRM_ERROR("failed to init PCI GART!\n"); |
1da177e4 | 1190 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1191 | return -ENOMEM; |
1da177e4 LT |
1192 | } |
1193 | ||
1194 | /* Turn on PCI GART */ | |
b5e89ed5 | 1195 | radeon_set_pcigart(dev_priv, 1); |
1da177e4 LT |
1196 | } |
1197 | ||
b5e89ed5 DA |
1198 | radeon_cp_load_microcode(dev_priv); |
1199 | radeon_cp_init_ring_buffer(dev, dev_priv); | |
1da177e4 LT |
1200 | |
1201 | dev_priv->last_buf = 0; | |
1202 | ||
b5e89ed5 | 1203 | radeon_do_engine_reset(dev); |
d5ea702f | 1204 | radeon_test_writeback(dev_priv); |
1da177e4 LT |
1205 | |
1206 | return 0; | |
1207 | } | |
1208 | ||
84b1fd10 | 1209 | static int radeon_do_cleanup_cp(struct drm_device * dev) |
1da177e4 LT |
1210 | { |
1211 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
b5e89ed5 | 1212 | DRM_DEBUG("\n"); |
1da177e4 LT |
1213 | |
1214 | /* Make sure interrupts are disabled here because the uninstall ioctl | |
1215 | * may not have been called from userspace and after dev_private | |
1216 | * is freed, it's too late. | |
1217 | */ | |
b5e89ed5 DA |
1218 | if (dev->irq_enabled) |
1219 | drm_irq_uninstall(dev); | |
1da177e4 LT |
1220 | |
1221 | #if __OS_HAS_AGP | |
54a56ac5 | 1222 | if (dev_priv->flags & RADEON_IS_AGP) { |
d985c108 | 1223 | if (dev_priv->cp_ring != NULL) { |
b5e89ed5 | 1224 | drm_core_ioremapfree(dev_priv->cp_ring, dev); |
d985c108 DA |
1225 | dev_priv->cp_ring = NULL; |
1226 | } | |
1227 | if (dev_priv->ring_rptr != NULL) { | |
b5e89ed5 | 1228 | drm_core_ioremapfree(dev_priv->ring_rptr, dev); |
d985c108 DA |
1229 | dev_priv->ring_rptr = NULL; |
1230 | } | |
b5e89ed5 DA |
1231 | if (dev->agp_buffer_map != NULL) { |
1232 | drm_core_ioremapfree(dev->agp_buffer_map, dev); | |
1da177e4 LT |
1233 | dev->agp_buffer_map = NULL; |
1234 | } | |
1235 | } else | |
1236 | #endif | |
1237 | { | |
d985c108 DA |
1238 | |
1239 | if (dev_priv->gart_info.bus_addr) { | |
1240 | /* Turn off PCI GART */ | |
1241 | radeon_set_pcigart(dev_priv, 0); | |
ea98a92f DA |
1242 | if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) |
1243 | DRM_ERROR("failed to cleanup PCI GART!\n"); | |
d985c108 | 1244 | } |
b5e89ed5 | 1245 | |
d985c108 DA |
1246 | if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) |
1247 | { | |
f26c473c | 1248 | drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); |
f2b04cd2 | 1249 | dev_priv->gart_info.addr = 0; |
ea98a92f | 1250 | } |
1da177e4 | 1251 | } |
1da177e4 LT |
1252 | /* only clear to the start of flags */ |
1253 | memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); | |
1254 | ||
1255 | return 0; | |
1256 | } | |
1257 | ||
b5e89ed5 DA |
1258 | /* This code will reinit the Radeon CP hardware after a resume from disc. |
1259 | * AFAIK, it would be very difficult to pickle the state at suspend time, so | |
1da177e4 LT |
1260 | * here we make sure that all Radeon hardware initialisation is re-done without |
1261 | * affecting running applications. | |
1262 | * | |
1263 | * Charl P. Botha <http://cpbotha.net> | |
1264 | */ | |
84b1fd10 | 1265 | static int radeon_do_resume_cp(struct drm_device * dev) |
1da177e4 LT |
1266 | { |
1267 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1268 | ||
b5e89ed5 DA |
1269 | if (!dev_priv) { |
1270 | DRM_ERROR("Called with no initialization\n"); | |
20caafa6 | 1271 | return -EINVAL; |
1da177e4 LT |
1272 | } |
1273 | ||
1274 | DRM_DEBUG("Starting radeon_do_resume_cp()\n"); | |
1275 | ||
1276 | #if __OS_HAS_AGP | |
54a56ac5 | 1277 | if (dev_priv->flags & RADEON_IS_AGP) { |
1da177e4 | 1278 | /* Turn off PCI GART */ |
b5e89ed5 | 1279 | radeon_set_pcigart(dev_priv, 0); |
1da177e4 LT |
1280 | } else |
1281 | #endif | |
1282 | { | |
1283 | /* Turn on PCI GART */ | |
b5e89ed5 | 1284 | radeon_set_pcigart(dev_priv, 1); |
1da177e4 LT |
1285 | } |
1286 | ||
b5e89ed5 DA |
1287 | radeon_cp_load_microcode(dev_priv); |
1288 | radeon_cp_init_ring_buffer(dev, dev_priv); | |
1da177e4 | 1289 | |
b5e89ed5 | 1290 | radeon_do_engine_reset(dev); |
7ecabc53 | 1291 | radeon_enable_interrupt(dev); |
1da177e4 LT |
1292 | |
1293 | DRM_DEBUG("radeon_do_resume_cp() complete\n"); | |
1294 | ||
1295 | return 0; | |
1296 | } | |
1297 | ||
c153f45f | 1298 | int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1299 | { |
c153f45f | 1300 | drm_radeon_init_t *init = data; |
1da177e4 | 1301 | |
6c340eac | 1302 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1303 | |
c153f45f | 1304 | if (init->func == RADEON_INIT_R300_CP) |
3d5e2c13 | 1305 | r300_init_reg_flags(dev); |
414ed537 | 1306 | |
c153f45f | 1307 | switch (init->func) { |
1da177e4 LT |
1308 | case RADEON_INIT_CP: |
1309 | case RADEON_INIT_R200_CP: | |
1310 | case RADEON_INIT_R300_CP: | |
c153f45f | 1311 | return radeon_do_init_cp(dev, init); |
1da177e4 | 1312 | case RADEON_CLEANUP_CP: |
b5e89ed5 | 1313 | return radeon_do_cleanup_cp(dev); |
1da177e4 LT |
1314 | } |
1315 | ||
20caafa6 | 1316 | return -EINVAL; |
1da177e4 LT |
1317 | } |
1318 | ||
c153f45f | 1319 | int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1320 | { |
1da177e4 | 1321 | drm_radeon_private_t *dev_priv = dev->dev_private; |
b5e89ed5 | 1322 | DRM_DEBUG("\n"); |
1da177e4 | 1323 | |
6c340eac | 1324 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1325 | |
b5e89ed5 | 1326 | if (dev_priv->cp_running) { |
3e684eae | 1327 | DRM_DEBUG("while CP running\n"); |
1da177e4 LT |
1328 | return 0; |
1329 | } | |
b5e89ed5 | 1330 | if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { |
3e684eae MN |
1331 | DRM_DEBUG("called with bogus CP mode (%d)\n", |
1332 | dev_priv->cp_mode); | |
1da177e4 LT |
1333 | return 0; |
1334 | } | |
1335 | ||
b5e89ed5 | 1336 | radeon_do_cp_start(dev_priv); |
1da177e4 LT |
1337 | |
1338 | return 0; | |
1339 | } | |
1340 | ||
1341 | /* Stop the CP. The engine must have been idled before calling this | |
1342 | * routine. | |
1343 | */ | |
c153f45f | 1344 | int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1345 | { |
1da177e4 | 1346 | drm_radeon_private_t *dev_priv = dev->dev_private; |
c153f45f | 1347 | drm_radeon_cp_stop_t *stop = data; |
1da177e4 | 1348 | int ret; |
b5e89ed5 | 1349 | DRM_DEBUG("\n"); |
1da177e4 | 1350 | |
6c340eac | 1351 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1352 | |
1da177e4 LT |
1353 | if (!dev_priv->cp_running) |
1354 | return 0; | |
1355 | ||
1356 | /* Flush any pending CP commands. This ensures any outstanding | |
1357 | * commands are exectuted by the engine before we turn it off. | |
1358 | */ | |
c153f45f | 1359 | if (stop->flush) { |
b5e89ed5 | 1360 | radeon_do_cp_flush(dev_priv); |
1da177e4 LT |
1361 | } |
1362 | ||
1363 | /* If we fail to make the engine go idle, we return an error | |
1364 | * code so that the DRM ioctl wrapper can try again. | |
1365 | */ | |
c153f45f | 1366 | if (stop->idle) { |
b5e89ed5 DA |
1367 | ret = radeon_do_cp_idle(dev_priv); |
1368 | if (ret) | |
1369 | return ret; | |
1da177e4 LT |
1370 | } |
1371 | ||
1372 | /* Finally, we can turn off the CP. If the engine isn't idle, | |
1373 | * we will get some dropped triangles as they won't be fully | |
1374 | * rendered before the CP is shut down. | |
1375 | */ | |
b5e89ed5 | 1376 | radeon_do_cp_stop(dev_priv); |
1da177e4 LT |
1377 | |
1378 | /* Reset the engine */ | |
b5e89ed5 | 1379 | radeon_do_engine_reset(dev); |
1da177e4 LT |
1380 | |
1381 | return 0; | |
1382 | } | |
1383 | ||
84b1fd10 | 1384 | void radeon_do_release(struct drm_device * dev) |
1da177e4 LT |
1385 | { |
1386 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1387 | int i, ret; | |
1388 | ||
1389 | if (dev_priv) { | |
1390 | if (dev_priv->cp_running) { | |
1391 | /* Stop the cp */ | |
b5e89ed5 | 1392 | while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { |
1da177e4 LT |
1393 | DRM_DEBUG("radeon_do_cp_idle %d\n", ret); |
1394 | #ifdef __linux__ | |
1395 | schedule(); | |
1396 | #else | |
1397 | tsleep(&ret, PZERO, "rdnrel", 1); | |
1398 | #endif | |
1399 | } | |
b5e89ed5 DA |
1400 | radeon_do_cp_stop(dev_priv); |
1401 | radeon_do_engine_reset(dev); | |
1da177e4 LT |
1402 | } |
1403 | ||
1404 | /* Disable *all* interrupts */ | |
1405 | if (dev_priv->mmio) /* remove this after permanent addmaps */ | |
b5e89ed5 | 1406 | RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); |
1da177e4 | 1407 | |
b5e89ed5 | 1408 | if (dev_priv->mmio) { /* remove all surfaces */ |
1da177e4 | 1409 | for (i = 0; i < RADEON_MAX_SURFACES; i++) { |
b5e89ed5 DA |
1410 | RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0); |
1411 | RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + | |
1412 | 16 * i, 0); | |
1413 | RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + | |
1414 | 16 * i, 0); | |
1da177e4 LT |
1415 | } |
1416 | } | |
1417 | ||
1418 | /* Free memory heap structures */ | |
b5e89ed5 DA |
1419 | radeon_mem_takedown(&(dev_priv->gart_heap)); |
1420 | radeon_mem_takedown(&(dev_priv->fb_heap)); | |
1da177e4 LT |
1421 | |
1422 | /* deallocate kernel resources */ | |
b5e89ed5 | 1423 | radeon_do_cleanup_cp(dev); |
1da177e4 LT |
1424 | } |
1425 | } | |
1426 | ||
1427 | /* Just reset the CP ring. Called as part of an X Server engine reset. | |
1428 | */ | |
c153f45f | 1429 | int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1430 | { |
1da177e4 | 1431 | drm_radeon_private_t *dev_priv = dev->dev_private; |
b5e89ed5 | 1432 | DRM_DEBUG("\n"); |
1da177e4 | 1433 | |
6c340eac | 1434 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1435 | |
b5e89ed5 | 1436 | if (!dev_priv) { |
3e684eae | 1437 | DRM_DEBUG("called before init done\n"); |
20caafa6 | 1438 | return -EINVAL; |
1da177e4 LT |
1439 | } |
1440 | ||
b5e89ed5 | 1441 | radeon_do_cp_reset(dev_priv); |
1da177e4 LT |
1442 | |
1443 | /* The CP is no longer running after an engine reset */ | |
1444 | dev_priv->cp_running = 0; | |
1445 | ||
1446 | return 0; | |
1447 | } | |
1448 | ||
c153f45f | 1449 | int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1450 | { |
1da177e4 | 1451 | drm_radeon_private_t *dev_priv = dev->dev_private; |
b5e89ed5 | 1452 | DRM_DEBUG("\n"); |
1da177e4 | 1453 | |
6c340eac | 1454 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1455 | |
b5e89ed5 | 1456 | return radeon_do_cp_idle(dev_priv); |
1da177e4 LT |
1457 | } |
1458 | ||
1459 | /* Added by Charl P. Botha to call radeon_do_resume_cp(). | |
1460 | */ | |
c153f45f | 1461 | int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1462 | { |
1da177e4 LT |
1463 | |
1464 | return radeon_do_resume_cp(dev); | |
1465 | } | |
1466 | ||
c153f45f | 1467 | int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1468 | { |
b5e89ed5 | 1469 | DRM_DEBUG("\n"); |
1da177e4 | 1470 | |
6c340eac | 1471 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1472 | |
b5e89ed5 | 1473 | return radeon_do_engine_reset(dev); |
1da177e4 LT |
1474 | } |
1475 | ||
1da177e4 LT |
1476 | /* ================================================================ |
1477 | * Fullscreen mode | |
1478 | */ | |
1479 | ||
1480 | /* KW: Deprecated to say the least: | |
1481 | */ | |
c153f45f | 1482 | int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 LT |
1483 | { |
1484 | return 0; | |
1485 | } | |
1486 | ||
1da177e4 LT |
1487 | /* ================================================================ |
1488 | * Freelist management | |
1489 | */ | |
1490 | ||
1491 | /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through | |
1492 | * bufs until freelist code is used. Note this hides a problem with | |
1493 | * the scratch register * (used to keep track of last buffer | |
1494 | * completed) being written to before * the last buffer has actually | |
b5e89ed5 | 1495 | * completed rendering. |
1da177e4 LT |
1496 | * |
1497 | * KW: It's also a good way to find free buffers quickly. | |
1498 | * | |
1499 | * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't | |
1500 | * sleep. However, bugs in older versions of radeon_accel.c mean that | |
1501 | * we essentially have to do this, else old clients will break. | |
b5e89ed5 | 1502 | * |
1da177e4 LT |
1503 | * However, it does leave open a potential deadlock where all the |
1504 | * buffers are held by other clients, which can't release them because | |
b5e89ed5 | 1505 | * they can't get the lock. |
1da177e4 LT |
1506 | */ |
1507 | ||
056219e2 | 1508 | struct drm_buf *radeon_freelist_get(struct drm_device * dev) |
1da177e4 | 1509 | { |
cdd55a29 | 1510 | struct drm_device_dma *dma = dev->dma; |
1da177e4 LT |
1511 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1512 | drm_radeon_buf_priv_t *buf_priv; | |
056219e2 | 1513 | struct drm_buf *buf; |
1da177e4 LT |
1514 | int i, t; |
1515 | int start; | |
1516 | ||
b5e89ed5 | 1517 | if (++dev_priv->last_buf >= dma->buf_count) |
1da177e4 LT |
1518 | dev_priv->last_buf = 0; |
1519 | ||
1520 | start = dev_priv->last_buf; | |
1521 | ||
b5e89ed5 DA |
1522 | for (t = 0; t < dev_priv->usec_timeout; t++) { |
1523 | u32 done_age = GET_SCRATCH(1); | |
1524 | DRM_DEBUG("done_age = %d\n", done_age); | |
1525 | for (i = start; i < dma->buf_count; i++) { | |
1da177e4 LT |
1526 | buf = dma->buflist[i]; |
1527 | buf_priv = buf->dev_private; | |
6c340eac EA |
1528 | if (buf->file_priv == NULL || (buf->pending && |
1529 | buf_priv->age <= | |
1530 | done_age)) { | |
1da177e4 LT |
1531 | dev_priv->stats.requested_bufs++; |
1532 | buf->pending = 0; | |
1533 | return buf; | |
1534 | } | |
1535 | start = 0; | |
1536 | } | |
1537 | ||
1538 | if (t) { | |
b5e89ed5 | 1539 | DRM_UDELAY(1); |
1da177e4 LT |
1540 | dev_priv->stats.freelist_loops++; |
1541 | } | |
1542 | } | |
1543 | ||
b5e89ed5 | 1544 | DRM_DEBUG("returning NULL!\n"); |
1da177e4 LT |
1545 | return NULL; |
1546 | } | |
b5e89ed5 | 1547 | |
1da177e4 | 1548 | #if 0 |
056219e2 | 1549 | struct drm_buf *radeon_freelist_get(struct drm_device * dev) |
1da177e4 | 1550 | { |
cdd55a29 | 1551 | struct drm_device_dma *dma = dev->dma; |
1da177e4 LT |
1552 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1553 | drm_radeon_buf_priv_t *buf_priv; | |
056219e2 | 1554 | struct drm_buf *buf; |
1da177e4 LT |
1555 | int i, t; |
1556 | int start; | |
1557 | u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); | |
1558 | ||
b5e89ed5 | 1559 | if (++dev_priv->last_buf >= dma->buf_count) |
1da177e4 LT |
1560 | dev_priv->last_buf = 0; |
1561 | ||
1562 | start = dev_priv->last_buf; | |
1563 | dev_priv->stats.freelist_loops++; | |
b5e89ed5 DA |
1564 | |
1565 | for (t = 0; t < 2; t++) { | |
1566 | for (i = start; i < dma->buf_count; i++) { | |
1da177e4 LT |
1567 | buf = dma->buflist[i]; |
1568 | buf_priv = buf->dev_private; | |
6c340eac EA |
1569 | if (buf->file_priv == 0 || (buf->pending && |
1570 | buf_priv->age <= | |
1571 | done_age)) { | |
1da177e4 LT |
1572 | dev_priv->stats.requested_bufs++; |
1573 | buf->pending = 0; | |
1574 | return buf; | |
1575 | } | |
1576 | } | |
1577 | start = 0; | |
1578 | } | |
1579 | ||
1580 | return NULL; | |
1581 | } | |
1582 | #endif | |
1583 | ||
84b1fd10 | 1584 | void radeon_freelist_reset(struct drm_device * dev) |
1da177e4 | 1585 | { |
cdd55a29 | 1586 | struct drm_device_dma *dma = dev->dma; |
1da177e4 LT |
1587 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1588 | int i; | |
1589 | ||
1590 | dev_priv->last_buf = 0; | |
b5e89ed5 | 1591 | for (i = 0; i < dma->buf_count; i++) { |
056219e2 | 1592 | struct drm_buf *buf = dma->buflist[i]; |
1da177e4 LT |
1593 | drm_radeon_buf_priv_t *buf_priv = buf->dev_private; |
1594 | buf_priv->age = 0; | |
1595 | } | |
1596 | } | |
1597 | ||
1da177e4 LT |
1598 | /* ================================================================ |
1599 | * CP command submission | |
1600 | */ | |
1601 | ||
b5e89ed5 | 1602 | int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) |
1da177e4 LT |
1603 | { |
1604 | drm_radeon_ring_buffer_t *ring = &dev_priv->ring; | |
1605 | int i; | |
b5e89ed5 | 1606 | u32 last_head = GET_RING_HEAD(dev_priv); |
1da177e4 | 1607 | |
b5e89ed5 DA |
1608 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
1609 | u32 head = GET_RING_HEAD(dev_priv); | |
1da177e4 LT |
1610 | |
1611 | ring->space = (head - ring->tail) * sizeof(u32); | |
b5e89ed5 | 1612 | if (ring->space <= 0) |
1da177e4 | 1613 | ring->space += ring->size; |
b5e89ed5 | 1614 | if (ring->space > n) |
1da177e4 | 1615 | return 0; |
b5e89ed5 | 1616 | |
1da177e4 LT |
1617 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; |
1618 | ||
1619 | if (head != last_head) | |
1620 | i = 0; | |
1621 | last_head = head; | |
1622 | ||
b5e89ed5 | 1623 | DRM_UDELAY(1); |
1da177e4 LT |
1624 | } |
1625 | ||
1626 | /* FIXME: This return value is ignored in the BEGIN_RING macro! */ | |
1627 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
1628 | radeon_status(dev_priv); |
1629 | DRM_ERROR("failed!\n"); | |
1da177e4 | 1630 | #endif |
20caafa6 | 1631 | return -EBUSY; |
1da177e4 LT |
1632 | } |
1633 | ||
6c340eac EA |
1634 | static int radeon_cp_get_buffers(struct drm_device *dev, |
1635 | struct drm_file *file_priv, | |
c60ce623 | 1636 | struct drm_dma * d) |
1da177e4 LT |
1637 | { |
1638 | int i; | |
056219e2 | 1639 | struct drm_buf *buf; |
1da177e4 | 1640 | |
b5e89ed5 DA |
1641 | for (i = d->granted_count; i < d->request_count; i++) { |
1642 | buf = radeon_freelist_get(dev); | |
1643 | if (!buf) | |
20caafa6 | 1644 | return -EBUSY; /* NOTE: broken client */ |
1da177e4 | 1645 | |
6c340eac | 1646 | buf->file_priv = file_priv; |
1da177e4 | 1647 | |
b5e89ed5 DA |
1648 | if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, |
1649 | sizeof(buf->idx))) | |
20caafa6 | 1650 | return -EFAULT; |
b5e89ed5 DA |
1651 | if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, |
1652 | sizeof(buf->total))) | |
20caafa6 | 1653 | return -EFAULT; |
1da177e4 LT |
1654 | |
1655 | d->granted_count++; | |
1656 | } | |
1657 | return 0; | |
1658 | } | |
1659 | ||
c153f45f | 1660 | int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1661 | { |
cdd55a29 | 1662 | struct drm_device_dma *dma = dev->dma; |
1da177e4 | 1663 | int ret = 0; |
c153f45f | 1664 | struct drm_dma *d = data; |
1da177e4 | 1665 | |
6c340eac | 1666 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1667 | |
1da177e4 LT |
1668 | /* Please don't send us buffers. |
1669 | */ | |
c153f45f | 1670 | if (d->send_count != 0) { |
b5e89ed5 | 1671 | DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", |
c153f45f | 1672 | DRM_CURRENTPID, d->send_count); |
20caafa6 | 1673 | return -EINVAL; |
1da177e4 LT |
1674 | } |
1675 | ||
1676 | /* We'll send you buffers. | |
1677 | */ | |
c153f45f | 1678 | if (d->request_count < 0 || d->request_count > dma->buf_count) { |
b5e89ed5 | 1679 | DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", |
c153f45f | 1680 | DRM_CURRENTPID, d->request_count, dma->buf_count); |
20caafa6 | 1681 | return -EINVAL; |
1da177e4 LT |
1682 | } |
1683 | ||
c153f45f | 1684 | d->granted_count = 0; |
1da177e4 | 1685 | |
c153f45f EA |
1686 | if (d->request_count) { |
1687 | ret = radeon_cp_get_buffers(dev, file_priv, d); | |
1da177e4 LT |
1688 | } |
1689 | ||
1da177e4 LT |
1690 | return ret; |
1691 | } | |
1692 | ||
22eae947 | 1693 | int radeon_driver_load(struct drm_device *dev, unsigned long flags) |
1da177e4 LT |
1694 | { |
1695 | drm_radeon_private_t *dev_priv; | |
1696 | int ret = 0; | |
1697 | ||
1698 | dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER); | |
1699 | if (dev_priv == NULL) | |
20caafa6 | 1700 | return -ENOMEM; |
1da177e4 LT |
1701 | |
1702 | memset(dev_priv, 0, sizeof(drm_radeon_private_t)); | |
1703 | dev->dev_private = (void *)dev_priv; | |
1704 | dev_priv->flags = flags; | |
1705 | ||
54a56ac5 | 1706 | switch (flags & RADEON_FAMILY_MASK) { |
1da177e4 LT |
1707 | case CHIP_R100: |
1708 | case CHIP_RV200: | |
1709 | case CHIP_R200: | |
1710 | case CHIP_R300: | |
b15ec368 | 1711 | case CHIP_R350: |
414ed537 | 1712 | case CHIP_R420: |
b15ec368 | 1713 | case CHIP_RV410: |
3d5e2c13 DA |
1714 | case CHIP_RV515: |
1715 | case CHIP_R520: | |
1716 | case CHIP_RV570: | |
1717 | case CHIP_R580: | |
54a56ac5 | 1718 | dev_priv->flags |= RADEON_HAS_HIERZ; |
1da177e4 LT |
1719 | break; |
1720 | default: | |
b5e89ed5 | 1721 | /* all other chips have no hierarchical z buffer */ |
1da177e4 LT |
1722 | break; |
1723 | } | |
414ed537 DA |
1724 | |
1725 | if (drm_device_is_agp(dev)) | |
54a56ac5 | 1726 | dev_priv->flags |= RADEON_IS_AGP; |
b15ec368 | 1727 | else if (drm_device_is_pcie(dev)) |
54a56ac5 | 1728 | dev_priv->flags |= RADEON_IS_PCIE; |
b15ec368 | 1729 | else |
54a56ac5 | 1730 | dev_priv->flags |= RADEON_IS_PCI; |
ea98a92f | 1731 | |
414ed537 | 1732 | DRM_DEBUG("%s card detected\n", |
54a56ac5 | 1733 | ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); |
1da177e4 LT |
1734 | return ret; |
1735 | } | |
1736 | ||
22eae947 DA |
1737 | /* Create mappings for registers and framebuffer so userland doesn't necessarily |
1738 | * have to find them. | |
1739 | */ | |
1740 | int radeon_driver_firstopen(struct drm_device *dev) | |
836cf046 DA |
1741 | { |
1742 | int ret; | |
1743 | drm_local_map_t *map; | |
1744 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1745 | ||
f2b04cd2 DA |
1746 | dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; |
1747 | ||
836cf046 DA |
1748 | ret = drm_addmap(dev, drm_get_resource_start(dev, 2), |
1749 | drm_get_resource_len(dev, 2), _DRM_REGISTERS, | |
1750 | _DRM_READ_ONLY, &dev_priv->mmio); | |
1751 | if (ret != 0) | |
1752 | return ret; | |
1753 | ||
7fc86860 DA |
1754 | dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0); |
1755 | ret = drm_addmap(dev, dev_priv->fb_aper_offset, | |
836cf046 DA |
1756 | drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER, |
1757 | _DRM_WRITE_COMBINING, &map); | |
1758 | if (ret != 0) | |
1759 | return ret; | |
1760 | ||
1761 | return 0; | |
1762 | } | |
1763 | ||
22eae947 | 1764 | int radeon_driver_unload(struct drm_device *dev) |
1da177e4 LT |
1765 | { |
1766 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1767 | ||
1768 | DRM_DEBUG("\n"); | |
1da177e4 LT |
1769 | drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); |
1770 | ||
1771 | dev->dev_private = NULL; | |
1772 | return 0; | |
1773 | } |