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f26c473c DA |
1 | /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */ |
2 | /* | |
1da177e4 LT |
3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | |
45e51905 | 5 | * Copyright 2007 Advanced Micro Devices, Inc. |
1da177e4 LT |
6 | * All Rights Reserved. |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the next | |
16 | * paragraph) shall be included in all copies or substantial portions of the | |
17 | * Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
23 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
25 | * DEALINGS IN THE SOFTWARE. | |
26 | * | |
27 | * Authors: | |
28 | * Kevin E. Martin <martin@valinux.com> | |
29 | * Gareth Hughes <gareth@valinux.com> | |
30 | */ | |
31 | ||
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "radeon_drm.h" | |
35 | #include "radeon_drv.h" | |
414ed537 | 36 | #include "r300_reg.h" |
1da177e4 | 37 | |
9f18409e AD |
38 | #include "radeon_microcode.h" |
39 | ||
1da177e4 LT |
40 | #define RADEON_FIFO_DEBUG 0 |
41 | ||
84b1fd10 | 42 | static int radeon_do_cleanup_cp(struct drm_device * dev); |
54f961a6 | 43 | static void radeon_do_cp_start(drm_radeon_private_t * dev_priv); |
1da177e4 | 44 | |
45e51905 | 45 | static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
3d5e2c13 DA |
46 | { |
47 | u32 ret; | |
48 | RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); | |
49 | ret = RADEON_READ(R520_MC_IND_DATA); | |
50 | RADEON_WRITE(R520_MC_IND_INDEX, 0); | |
51 | return ret; | |
52 | } | |
53 | ||
45e51905 AD |
54 | static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
55 | { | |
56 | u32 ret; | |
57 | RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff); | |
58 | ret = RADEON_READ(RS480_NB_MC_DATA); | |
59 | RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); | |
60 | return ret; | |
61 | } | |
62 | ||
60f92683 MC |
63 | static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
64 | { | |
45e51905 | 65 | u32 ret; |
60f92683 | 66 | RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); |
45e51905 AD |
67 | ret = RADEON_READ(RS690_MC_DATA); |
68 | RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK); | |
69 | return ret; | |
70 | } | |
71 | ||
72 | static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) | |
73 | { | |
f0738e92 AD |
74 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
75 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) | |
45e51905 AD |
76 | return RS690_READ_MCIND(dev_priv, addr); |
77 | else | |
78 | return RS480_READ_MCIND(dev_priv, addr); | |
60f92683 MC |
79 | } |
80 | ||
3d5e2c13 DA |
81 | u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) |
82 | { | |
83 | ||
84 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) | |
45e51905 | 85 | return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); |
f0738e92 AD |
86 | else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
87 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) | |
60f92683 | 88 | return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); |
3d5e2c13 | 89 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
45e51905 | 90 | return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); |
3d5e2c13 DA |
91 | else |
92 | return RADEON_READ(RADEON_MC_FB_LOCATION); | |
93 | } | |
94 | ||
95 | static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) | |
96 | { | |
97 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) | |
45e51905 | 98 | R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); |
f0738e92 AD |
99 | else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
100 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) | |
60f92683 | 101 | RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); |
3d5e2c13 | 102 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
45e51905 | 103 | R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); |
3d5e2c13 DA |
104 | else |
105 | RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); | |
106 | } | |
107 | ||
108 | static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) | |
109 | { | |
110 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) | |
45e51905 | 111 | R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); |
f0738e92 AD |
112 | else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
113 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) | |
60f92683 | 114 | RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); |
3d5e2c13 | 115 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
45e51905 | 116 | R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); |
3d5e2c13 DA |
117 | else |
118 | RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); | |
119 | } | |
120 | ||
70b13d51 DA |
121 | static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base) |
122 | { | |
123 | u32 agp_base_hi = upper_32_bits(agp_base); | |
124 | u32 agp_base_lo = agp_base & 0xffffffff; | |
125 | ||
126 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) { | |
127 | R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo); | |
128 | R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi); | |
f0738e92 AD |
129 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
130 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { | |
70b13d51 DA |
131 | RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo); |
132 | RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi); | |
133 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { | |
134 | R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo); | |
135 | R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi); | |
b2ceddfa AD |
136 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || |
137 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { | |
5cfb6956 | 138 | RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); |
b2ceddfa | 139 | RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi); |
70b13d51 DA |
140 | } else { |
141 | RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); | |
142 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) | |
143 | RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi); | |
144 | } | |
145 | } | |
146 | ||
84b1fd10 | 147 | static int RADEON_READ_PLL(struct drm_device * dev, int addr) |
1da177e4 LT |
148 | { |
149 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
150 | ||
151 | RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); | |
152 | return RADEON_READ(RADEON_CLOCK_CNTL_DATA); | |
153 | } | |
154 | ||
3d5e2c13 | 155 | static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) |
ea98a92f DA |
156 | { |
157 | RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); | |
158 | return RADEON_READ(RADEON_PCIE_DATA); | |
159 | } | |
160 | ||
1da177e4 | 161 | #if RADEON_FIFO_DEBUG |
b5e89ed5 | 162 | static void radeon_status(drm_radeon_private_t * dev_priv) |
1da177e4 | 163 | { |
bf9d8929 | 164 | printk("%s:\n", __func__); |
b5e89ed5 DA |
165 | printk("RBBM_STATUS = 0x%08x\n", |
166 | (unsigned int)RADEON_READ(RADEON_RBBM_STATUS)); | |
167 | printk("CP_RB_RTPR = 0x%08x\n", | |
168 | (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR)); | |
169 | printk("CP_RB_WTPR = 0x%08x\n", | |
170 | (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR)); | |
171 | printk("AIC_CNTL = 0x%08x\n", | |
172 | (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); | |
173 | printk("AIC_STAT = 0x%08x\n", | |
174 | (unsigned int)RADEON_READ(RADEON_AIC_STAT)); | |
175 | printk("AIC_PT_BASE = 0x%08x\n", | |
176 | (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE)); | |
177 | printk("TLB_ADDR = 0x%08x\n", | |
178 | (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR)); | |
179 | printk("TLB_DATA = 0x%08x\n", | |
180 | (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA)); | |
1da177e4 LT |
181 | } |
182 | #endif | |
183 | ||
1da177e4 LT |
184 | /* ================================================================ |
185 | * Engine, FIFO control | |
186 | */ | |
187 | ||
b5e89ed5 | 188 | static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
189 | { |
190 | u32 tmp; | |
191 | int i; | |
192 | ||
193 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
194 | ||
259434ac AD |
195 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { |
196 | tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); | |
197 | tmp |= RADEON_RB3D_DC_FLUSH_ALL; | |
198 | RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); | |
199 | ||
200 | for (i = 0; i < dev_priv->usec_timeout; i++) { | |
201 | if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) | |
202 | & RADEON_RB3D_DC_BUSY)) { | |
203 | return 0; | |
204 | } | |
205 | DRM_UDELAY(1); | |
206 | } | |
207 | } else { | |
54f961a6 JG |
208 | /* don't flush or purge cache here or lockup */ |
209 | return 0; | |
1da177e4 LT |
210 | } |
211 | ||
212 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
213 | DRM_ERROR("failed!\n"); |
214 | radeon_status(dev_priv); | |
1da177e4 | 215 | #endif |
20caafa6 | 216 | return -EBUSY; |
1da177e4 LT |
217 | } |
218 | ||
b5e89ed5 | 219 | static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) |
1da177e4 LT |
220 | { |
221 | int i; | |
222 | ||
223 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
224 | ||
b5e89ed5 DA |
225 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
226 | int slots = (RADEON_READ(RADEON_RBBM_STATUS) | |
227 | & RADEON_RBBM_FIFOCNT_MASK); | |
228 | if (slots >= entries) | |
229 | return 0; | |
230 | DRM_UDELAY(1); | |
1da177e4 | 231 | } |
6c7be298 | 232 | DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n", |
54f961a6 JG |
233 | RADEON_READ(RADEON_RBBM_STATUS), |
234 | RADEON_READ(R300_VAP_CNTL_STATUS)); | |
1da177e4 LT |
235 | |
236 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
237 | DRM_ERROR("failed!\n"); |
238 | radeon_status(dev_priv); | |
1da177e4 | 239 | #endif |
20caafa6 | 240 | return -EBUSY; |
1da177e4 LT |
241 | } |
242 | ||
b5e89ed5 | 243 | static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
244 | { |
245 | int i, ret; | |
246 | ||
247 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
248 | ||
b5e89ed5 DA |
249 | ret = radeon_do_wait_for_fifo(dev_priv, 64); |
250 | if (ret) | |
251 | return ret; | |
1da177e4 | 252 | |
b5e89ed5 DA |
253 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
254 | if (!(RADEON_READ(RADEON_RBBM_STATUS) | |
255 | & RADEON_RBBM_ACTIVE)) { | |
256 | radeon_do_pixcache_flush(dev_priv); | |
1da177e4 LT |
257 | return 0; |
258 | } | |
b5e89ed5 | 259 | DRM_UDELAY(1); |
1da177e4 | 260 | } |
6c7be298 | 261 | DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n", |
54f961a6 JG |
262 | RADEON_READ(RADEON_RBBM_STATUS), |
263 | RADEON_READ(R300_VAP_CNTL_STATUS)); | |
1da177e4 LT |
264 | |
265 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
266 | DRM_ERROR("failed!\n"); |
267 | radeon_status(dev_priv); | |
1da177e4 | 268 | #endif |
20caafa6 | 269 | return -EBUSY; |
1da177e4 LT |
270 | } |
271 | ||
5b92c404 AD |
272 | static void radeon_init_pipes(drm_radeon_private_t *dev_priv) |
273 | { | |
274 | uint32_t gb_tile_config, gb_pipe_sel = 0; | |
275 | ||
276 | /* RS4xx/RS6xx/R4xx/R5xx */ | |
277 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { | |
278 | gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT); | |
279 | dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; | |
280 | } else { | |
281 | /* R3xx */ | |
282 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || | |
283 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) { | |
284 | dev_priv->num_gb_pipes = 2; | |
285 | } else { | |
286 | /* R3Vxx */ | |
287 | dev_priv->num_gb_pipes = 1; | |
288 | } | |
289 | } | |
290 | DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes); | |
291 | ||
292 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/); | |
293 | ||
294 | switch (dev_priv->num_gb_pipes) { | |
295 | case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; | |
296 | case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; | |
297 | case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; | |
298 | default: | |
299 | case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; | |
300 | } | |
301 | ||
302 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { | |
303 | RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); | |
304 | RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1)); | |
305 | } | |
306 | RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config); | |
307 | radeon_do_wait_for_idle(dev_priv); | |
308 | RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); | |
309 | RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) | | |
310 | R300_DC_AUTOFLUSH_ENABLE | | |
311 | R300_DC_DC_DISABLE_IGNORE_PE)); | |
312 | ||
313 | ||
314 | } | |
315 | ||
1da177e4 LT |
316 | /* ================================================================ |
317 | * CP control, initialization | |
318 | */ | |
319 | ||
320 | /* Load the microcode for the CP */ | |
b5e89ed5 | 321 | static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
322 | { |
323 | int i; | |
b5e89ed5 | 324 | DRM_DEBUG("\n"); |
1da177e4 | 325 | |
b5e89ed5 | 326 | radeon_do_wait_for_idle(dev_priv); |
1da177e4 | 327 | |
b5e89ed5 | 328 | RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); |
9f18409e AD |
329 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) || |
330 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) || | |
331 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) || | |
332 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) || | |
333 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) { | |
334 | DRM_INFO("Loading R100 Microcode\n"); | |
335 | for (i = 0; i < 256; i++) { | |
336 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
337 | R100_cp_microcode[i][1]); | |
338 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
339 | R100_cp_microcode[i][0]); | |
340 | } | |
341 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) || | |
342 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) || | |
343 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) || | |
344 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) { | |
1da177e4 | 345 | DRM_INFO("Loading R200 Microcode\n"); |
b5e89ed5 DA |
346 | for (i = 0; i < 256; i++) { |
347 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
348 | R200_cp_microcode[i][1]); | |
349 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
350 | R200_cp_microcode[i][0]); | |
1da177e4 | 351 | } |
9f18409e AD |
352 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || |
353 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || | |
354 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || | |
355 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || | |
b2ceddfa | 356 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || |
45e51905 | 357 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { |
1da177e4 | 358 | DRM_INFO("Loading R300 Microcode\n"); |
b5e89ed5 DA |
359 | for (i = 0; i < 256; i++) { |
360 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
361 | R300_cp_microcode[i][1]); | |
362 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
363 | R300_cp_microcode[i][0]); | |
1da177e4 | 364 | } |
9f18409e | 365 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || |
edc6f389 | 366 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) || |
9f18409e AD |
367 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) { |
368 | DRM_INFO("Loading R400 Microcode\n"); | |
369 | for (i = 0; i < 256; i++) { | |
370 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
371 | R420_cp_microcode[i][1]); | |
372 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
373 | R420_cp_microcode[i][0]); | |
374 | } | |
f0738e92 AD |
375 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
376 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { | |
377 | DRM_INFO("Loading RS690/RS740 Microcode\n"); | |
9f18409e AD |
378 | for (i = 0; i < 256; i++) { |
379 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
380 | RS690_cp_microcode[i][1]); | |
381 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
382 | RS690_cp_microcode[i][0]); | |
383 | } | |
384 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) || | |
385 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) || | |
386 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) || | |
387 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) || | |
388 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) || | |
389 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) { | |
390 | DRM_INFO("Loading R500 Microcode\n"); | |
b5e89ed5 DA |
391 | for (i = 0; i < 256; i++) { |
392 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
9f18409e | 393 | R520_cp_microcode[i][1]); |
b5e89ed5 | 394 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, |
9f18409e | 395 | R520_cp_microcode[i][0]); |
1da177e4 LT |
396 | } |
397 | } | |
398 | } | |
399 | ||
400 | /* Flush any pending commands to the CP. This should only be used just | |
401 | * prior to a wait for idle, as it informs the engine that the command | |
402 | * stream is ending. | |
403 | */ | |
b5e89ed5 | 404 | static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) |
1da177e4 | 405 | { |
b5e89ed5 | 406 | DRM_DEBUG("\n"); |
1da177e4 LT |
407 | #if 0 |
408 | u32 tmp; | |
409 | ||
b5e89ed5 DA |
410 | tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); |
411 | RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); | |
1da177e4 LT |
412 | #endif |
413 | } | |
414 | ||
415 | /* Wait for the CP to go idle. | |
416 | */ | |
b5e89ed5 | 417 | int radeon_do_cp_idle(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
418 | { |
419 | RING_LOCALS; | |
b5e89ed5 | 420 | DRM_DEBUG("\n"); |
1da177e4 | 421 | |
b5e89ed5 | 422 | BEGIN_RING(6); |
1da177e4 LT |
423 | |
424 | RADEON_PURGE_CACHE(); | |
425 | RADEON_PURGE_ZCACHE(); | |
426 | RADEON_WAIT_UNTIL_IDLE(); | |
427 | ||
428 | ADVANCE_RING(); | |
429 | COMMIT_RING(); | |
430 | ||
b5e89ed5 | 431 | return radeon_do_wait_for_idle(dev_priv); |
1da177e4 LT |
432 | } |
433 | ||
434 | /* Start the Command Processor. | |
435 | */ | |
b5e89ed5 | 436 | static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
437 | { |
438 | RING_LOCALS; | |
b5e89ed5 | 439 | DRM_DEBUG("\n"); |
1da177e4 | 440 | |
b5e89ed5 | 441 | radeon_do_wait_for_idle(dev_priv); |
1da177e4 | 442 | |
b5e89ed5 | 443 | RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); |
1da177e4 LT |
444 | |
445 | dev_priv->cp_running = 1; | |
446 | ||
54f961a6 JG |
447 | BEGIN_RING(8); |
448 | /* isync can only be written through cp on r5xx write it here */ | |
449 | OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); | |
450 | OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D | | |
451 | RADEON_ISYNC_ANY3D_IDLE2D | | |
452 | RADEON_ISYNC_WAIT_IDLEGUI | | |
453 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); | |
1da177e4 LT |
454 | RADEON_PURGE_CACHE(); |
455 | RADEON_PURGE_ZCACHE(); | |
456 | RADEON_WAIT_UNTIL_IDLE(); | |
1da177e4 LT |
457 | ADVANCE_RING(); |
458 | COMMIT_RING(); | |
54f961a6 JG |
459 | |
460 | dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED; | |
1da177e4 LT |
461 | } |
462 | ||
463 | /* Reset the Command Processor. This will not flush any pending | |
464 | * commands, so you must wait for the CP command stream to complete | |
465 | * before calling this routine. | |
466 | */ | |
b5e89ed5 | 467 | static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
468 | { |
469 | u32 cur_read_ptr; | |
b5e89ed5 | 470 | DRM_DEBUG("\n"); |
1da177e4 | 471 | |
b5e89ed5 DA |
472 | cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); |
473 | RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); | |
474 | SET_RING_HEAD(dev_priv, cur_read_ptr); | |
1da177e4 LT |
475 | dev_priv->ring.tail = cur_read_ptr; |
476 | } | |
477 | ||
478 | /* Stop the Command Processor. This will not flush any pending | |
479 | * commands, so you must flush the command stream and wait for the CP | |
480 | * to go idle before calling this routine. | |
481 | */ | |
b5e89ed5 | 482 | static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) |
1da177e4 | 483 | { |
b5e89ed5 | 484 | DRM_DEBUG("\n"); |
1da177e4 | 485 | |
b5e89ed5 | 486 | RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); |
1da177e4 LT |
487 | |
488 | dev_priv->cp_running = 0; | |
489 | } | |
490 | ||
491 | /* Reset the engine. This will stop the CP if it is running. | |
492 | */ | |
84b1fd10 | 493 | static int radeon_do_engine_reset(struct drm_device * dev) |
1da177e4 LT |
494 | { |
495 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
d396db32 | 496 | u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset; |
b5e89ed5 | 497 | DRM_DEBUG("\n"); |
1da177e4 | 498 | |
b5e89ed5 DA |
499 | radeon_do_pixcache_flush(dev_priv); |
500 | ||
d396db32 AD |
501 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { |
502 | /* may need something similar for newer chips */ | |
3d5e2c13 DA |
503 | clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); |
504 | mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); | |
505 | ||
506 | RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | | |
507 | RADEON_FORCEON_MCLKA | | |
508 | RADEON_FORCEON_MCLKB | | |
509 | RADEON_FORCEON_YCLKA | | |
510 | RADEON_FORCEON_YCLKB | | |
511 | RADEON_FORCEON_MC | | |
512 | RADEON_FORCEON_AIC)); | |
d396db32 | 513 | } |
3d5e2c13 | 514 | |
d396db32 AD |
515 | rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); |
516 | ||
517 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | | |
518 | RADEON_SOFT_RESET_CP | | |
519 | RADEON_SOFT_RESET_HI | | |
520 | RADEON_SOFT_RESET_SE | | |
521 | RADEON_SOFT_RESET_RE | | |
522 | RADEON_SOFT_RESET_PP | | |
523 | RADEON_SOFT_RESET_E2 | | |
524 | RADEON_SOFT_RESET_RB)); | |
525 | RADEON_READ(RADEON_RBBM_SOFT_RESET); | |
526 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & | |
527 | ~(RADEON_SOFT_RESET_CP | | |
528 | RADEON_SOFT_RESET_HI | | |
529 | RADEON_SOFT_RESET_SE | | |
530 | RADEON_SOFT_RESET_RE | | |
531 | RADEON_SOFT_RESET_PP | | |
532 | RADEON_SOFT_RESET_E2 | | |
533 | RADEON_SOFT_RESET_RB))); | |
534 | RADEON_READ(RADEON_RBBM_SOFT_RESET); | |
535 | ||
536 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { | |
3d5e2c13 DA |
537 | RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); |
538 | RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); | |
539 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); | |
540 | } | |
1da177e4 | 541 | |
5b92c404 AD |
542 | /* setup the raster pipes */ |
543 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300) | |
544 | radeon_init_pipes(dev_priv); | |
545 | ||
1da177e4 | 546 | /* Reset the CP ring */ |
b5e89ed5 | 547 | radeon_do_cp_reset(dev_priv); |
1da177e4 LT |
548 | |
549 | /* The CP is no longer running after an engine reset */ | |
550 | dev_priv->cp_running = 0; | |
551 | ||
552 | /* Reset any pending vertex, indirect buffers */ | |
b5e89ed5 | 553 | radeon_freelist_reset(dev); |
1da177e4 LT |
554 | |
555 | return 0; | |
556 | } | |
557 | ||
84b1fd10 | 558 | static void radeon_cp_init_ring_buffer(struct drm_device * dev, |
b5e89ed5 | 559 | drm_radeon_private_t * dev_priv) |
1da177e4 LT |
560 | { |
561 | u32 ring_start, cur_read_ptr; | |
562 | u32 tmp; | |
bc5f4523 | 563 | |
d5ea702f DA |
564 | /* Initialize the memory controller. With new memory map, the fb location |
565 | * is not changed, it should have been properly initialized already. Part | |
566 | * of the problem is that the code below is bogus, assuming the GART is | |
567 | * always appended to the fb which is not necessarily the case | |
568 | */ | |
569 | if (!dev_priv->new_memmap) | |
3d5e2c13 | 570 | radeon_write_fb_location(dev_priv, |
d5ea702f DA |
571 | ((dev_priv->gart_vm_start - 1) & 0xffff0000) |
572 | | (dev_priv->fb_location >> 16)); | |
1da177e4 LT |
573 | |
574 | #if __OS_HAS_AGP | |
54a56ac5 | 575 | if (dev_priv->flags & RADEON_IS_AGP) { |
70b13d51 DA |
576 | radeon_write_agp_base(dev_priv, dev->agp->base); |
577 | ||
3d5e2c13 | 578 | radeon_write_agp_location(dev_priv, |
b5e89ed5 DA |
579 | (((dev_priv->gart_vm_start - 1 + |
580 | dev_priv->gart_size) & 0xffff0000) | | |
581 | (dev_priv->gart_vm_start >> 16))); | |
1da177e4 LT |
582 | |
583 | ring_start = (dev_priv->cp_ring->offset | |
584 | - dev->agp->base | |
585 | + dev_priv->gart_vm_start); | |
b0917bd9 | 586 | } else |
1da177e4 LT |
587 | #endif |
588 | ring_start = (dev_priv->cp_ring->offset | |
b0917bd9 | 589 | - (unsigned long)dev->sg->virtual |
1da177e4 LT |
590 | + dev_priv->gart_vm_start); |
591 | ||
b5e89ed5 | 592 | RADEON_WRITE(RADEON_CP_RB_BASE, ring_start); |
1da177e4 LT |
593 | |
594 | /* Set the write pointer delay */ | |
b5e89ed5 | 595 | RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0); |
1da177e4 LT |
596 | |
597 | /* Initialize the ring buffer's read and write pointers */ | |
b5e89ed5 DA |
598 | cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); |
599 | RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); | |
600 | SET_RING_HEAD(dev_priv, cur_read_ptr); | |
1da177e4 LT |
601 | dev_priv->ring.tail = cur_read_ptr; |
602 | ||
603 | #if __OS_HAS_AGP | |
54a56ac5 | 604 | if (dev_priv->flags & RADEON_IS_AGP) { |
b5e89ed5 DA |
605 | RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, |
606 | dev_priv->ring_rptr->offset | |
607 | - dev->agp->base + dev_priv->gart_vm_start); | |
1da177e4 LT |
608 | } else |
609 | #endif | |
610 | { | |
55910517 | 611 | struct drm_sg_mem *entry = dev->sg; |
1da177e4 LT |
612 | unsigned long tmp_ofs, page_ofs; |
613 | ||
b0917bd9 IK |
614 | tmp_ofs = dev_priv->ring_rptr->offset - |
615 | (unsigned long)dev->sg->virtual; | |
1da177e4 LT |
616 | page_ofs = tmp_ofs >> PAGE_SHIFT; |
617 | ||
b5e89ed5 DA |
618 | RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]); |
619 | DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n", | |
620 | (unsigned long)entry->busaddr[page_ofs], | |
621 | entry->handle + tmp_ofs); | |
1da177e4 LT |
622 | } |
623 | ||
d5ea702f DA |
624 | /* Set ring buffer size */ |
625 | #ifdef __BIG_ENDIAN | |
626 | RADEON_WRITE(RADEON_CP_RB_CNTL, | |
576cc458 RS |
627 | RADEON_BUF_SWAP_32BIT | |
628 | (dev_priv->ring.fetch_size_l2ow << 18) | | |
629 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
630 | dev_priv->ring.size_l2qw); | |
d5ea702f | 631 | #else |
576cc458 RS |
632 | RADEON_WRITE(RADEON_CP_RB_CNTL, |
633 | (dev_priv->ring.fetch_size_l2ow << 18) | | |
634 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
635 | dev_priv->ring.size_l2qw); | |
d5ea702f DA |
636 | #endif |
637 | ||
d5ea702f | 638 | |
1da177e4 LT |
639 | /* Initialize the scratch register pointer. This will cause |
640 | * the scratch register values to be written out to memory | |
641 | * whenever they are updated. | |
642 | * | |
643 | * We simply put this behind the ring read pointer, this works | |
644 | * with PCI GART as well as (whatever kind of) AGP GART | |
645 | */ | |
b5e89ed5 DA |
646 | RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR) |
647 | + RADEON_SCRATCH_REG_OFFSET); | |
1da177e4 LT |
648 | |
649 | dev_priv->scratch = ((__volatile__ u32 *) | |
650 | dev_priv->ring_rptr->handle + | |
651 | (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); | |
652 | ||
b5e89ed5 | 653 | RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); |
1da177e4 | 654 | |
d5ea702f | 655 | /* Turn on bus mastering */ |
4e270e9b | 656 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
edc6f389 | 657 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { |
4e270e9b AD |
658 | /* rs600/rs690/rs740 */ |
659 | tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; | |
edc6f389 | 660 | RADEON_WRITE(RADEON_BUS_CNTL, tmp); |
4e270e9b AD |
661 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) || |
662 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || | |
663 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || | |
664 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { | |
665 | /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ | |
edc6f389 AD |
666 | tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
667 | RADEON_WRITE(RADEON_BUS_CNTL, tmp); | |
668 | } /* PCIE cards appears to not need this */ | |
1da177e4 LT |
669 | |
670 | dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; | |
b5e89ed5 | 671 | RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); |
1da177e4 LT |
672 | |
673 | dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; | |
b5e89ed5 DA |
674 | RADEON_WRITE(RADEON_LAST_DISPATCH_REG, |
675 | dev_priv->sarea_priv->last_dispatch); | |
1da177e4 LT |
676 | |
677 | dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; | |
b5e89ed5 | 678 | RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear); |
1da177e4 | 679 | |
b5e89ed5 | 680 | radeon_do_wait_for_idle(dev_priv); |
1da177e4 | 681 | |
1da177e4 | 682 | /* Sync everything up */ |
b5e89ed5 DA |
683 | RADEON_WRITE(RADEON_ISYNC_CNTL, |
684 | (RADEON_ISYNC_ANY2D_IDLE3D | | |
685 | RADEON_ISYNC_ANY3D_IDLE2D | | |
686 | RADEON_ISYNC_WAIT_IDLEGUI | | |
687 | RADEON_ISYNC_CPSCRATCH_IDLEGUI)); | |
d5ea702f DA |
688 | |
689 | } | |
690 | ||
691 | static void radeon_test_writeback(drm_radeon_private_t * dev_priv) | |
692 | { | |
693 | u32 tmp; | |
694 | ||
6b79d521 DA |
695 | /* Start with assuming that writeback doesn't work */ |
696 | dev_priv->writeback_works = 0; | |
697 | ||
d5ea702f DA |
698 | /* Writeback doesn't seem to work everywhere, test it here and possibly |
699 | * enable it if it appears to work | |
700 | */ | |
701 | DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0); | |
702 | RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef); | |
703 | ||
704 | for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { | |
705 | if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) == | |
706 | 0xdeadbeef) | |
707 | break; | |
708 | DRM_UDELAY(1); | |
709 | } | |
710 | ||
711 | if (tmp < dev_priv->usec_timeout) { | |
712 | dev_priv->writeback_works = 1; | |
713 | DRM_INFO("writeback test succeeded in %d usecs\n", tmp); | |
714 | } else { | |
715 | dev_priv->writeback_works = 0; | |
716 | DRM_INFO("writeback test failed\n"); | |
717 | } | |
718 | if (radeon_no_wb == 1) { | |
719 | dev_priv->writeback_works = 0; | |
720 | DRM_INFO("writeback forced off\n"); | |
721 | } | |
ae1b1a48 MD |
722 | |
723 | if (!dev_priv->writeback_works) { | |
724 | /* Disable writeback to avoid unnecessary bus master transfer */ | |
725 | RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | | |
726 | RADEON_RB_NO_UPDATE); | |
727 | RADEON_WRITE(RADEON_SCRATCH_UMSK, 0); | |
728 | } | |
1da177e4 LT |
729 | } |
730 | ||
f2b04cd2 DA |
731 | /* Enable or disable IGP GART on the chip */ |
732 | static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) | |
60f92683 MC |
733 | { |
734 | u32 temp; | |
735 | ||
736 | if (on) { | |
45e51905 | 737 | DRM_DEBUG("programming igp gart %08X %08lX %08X\n", |
60f92683 MC |
738 | dev_priv->gart_vm_start, |
739 | (long)dev_priv->gart_info.bus_addr, | |
740 | dev_priv->gart_size); | |
741 | ||
45e51905 | 742 | temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL); |
f0738e92 AD |
743 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
744 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) | |
45e51905 AD |
745 | IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN | |
746 | RS690_BLOCK_GFX_D3_EN)); | |
747 | else | |
748 | IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); | |
60f92683 | 749 | |
45e51905 AD |
750 | IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | |
751 | RS480_VA_SIZE_32MB)); | |
60f92683 | 752 | |
45e51905 AD |
753 | temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID); |
754 | IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN | | |
755 | RS480_TLB_ENABLE | | |
756 | RS480_GTW_LAC_EN | | |
757 | RS480_1LEVEL_GART)); | |
60f92683 | 758 | |
fa0d71b9 DA |
759 | temp = dev_priv->gart_info.bus_addr & 0xfffff000; |
760 | temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; | |
45e51905 AD |
761 | IGP_WRITE_MCIND(RS480_GART_BASE, temp); |
762 | ||
763 | temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL); | |
764 | IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) | | |
765 | RS480_REQ_TYPE_SNOOP_DIS)); | |
766 | ||
5cfb6956 | 767 | radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start); |
3722bfc6 | 768 | |
60f92683 MC |
769 | dev_priv->gart_size = 32*1024*1024; |
770 | temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & | |
771 | 0xffff0000) | (dev_priv->gart_vm_start >> 16)); | |
772 | ||
45e51905 | 773 | radeon_write_agp_location(dev_priv, temp); |
60f92683 | 774 | |
45e51905 AD |
775 | temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE); |
776 | IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | | |
777 | RS480_VA_SIZE_32MB)); | |
60f92683 MC |
778 | |
779 | do { | |
45e51905 AD |
780 | temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); |
781 | if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) | |
60f92683 MC |
782 | break; |
783 | DRM_UDELAY(1); | |
784 | } while (1); | |
785 | ||
45e51905 AD |
786 | IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, |
787 | RS480_GART_CACHE_INVALIDATE); | |
2735977b | 788 | |
60f92683 | 789 | do { |
45e51905 AD |
790 | temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); |
791 | if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) | |
60f92683 MC |
792 | break; |
793 | DRM_UDELAY(1); | |
794 | } while (1); | |
795 | ||
45e51905 | 796 | IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0); |
60f92683 | 797 | } else { |
45e51905 | 798 | IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0); |
60f92683 MC |
799 | } |
800 | } | |
801 | ||
ea98a92f DA |
802 | static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) |
803 | { | |
804 | u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); | |
805 | if (on) { | |
806 | ||
807 | DRM_DEBUG("programming pcie %08X %08lX %08X\n", | |
b5e89ed5 DA |
808 | dev_priv->gart_vm_start, |
809 | (long)dev_priv->gart_info.bus_addr, | |
ea98a92f | 810 | dev_priv->gart_size); |
b5e89ed5 DA |
811 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, |
812 | dev_priv->gart_vm_start); | |
813 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, | |
814 | dev_priv->gart_info.bus_addr); | |
815 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, | |
816 | dev_priv->gart_vm_start); | |
817 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, | |
818 | dev_priv->gart_vm_start + | |
819 | dev_priv->gart_size - 1); | |
820 | ||
3d5e2c13 | 821 | radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */ |
b5e89ed5 DA |
822 | |
823 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, | |
824 | RADEON_PCIE_TX_GART_EN); | |
ea98a92f | 825 | } else { |
b5e89ed5 DA |
826 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, |
827 | tmp & ~RADEON_PCIE_TX_GART_EN); | |
ea98a92f | 828 | } |
1da177e4 LT |
829 | } |
830 | ||
831 | /* Enable or disable PCI GART on the chip */ | |
b5e89ed5 | 832 | static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) |
1da177e4 | 833 | { |
d985c108 | 834 | u32 tmp; |
1da177e4 | 835 | |
45e51905 | 836 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
f0738e92 | 837 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) || |
45e51905 | 838 | (dev_priv->flags & RADEON_IS_IGPGART)) { |
f2b04cd2 DA |
839 | radeon_set_igpgart(dev_priv, on); |
840 | return; | |
841 | } | |
842 | ||
54a56ac5 | 843 | if (dev_priv->flags & RADEON_IS_PCIE) { |
ea98a92f DA |
844 | radeon_set_pciegart(dev_priv, on); |
845 | return; | |
846 | } | |
1da177e4 | 847 | |
bc5f4523 | 848 | tmp = RADEON_READ(RADEON_AIC_CNTL); |
d985c108 | 849 | |
b5e89ed5 DA |
850 | if (on) { |
851 | RADEON_WRITE(RADEON_AIC_CNTL, | |
852 | tmp | RADEON_PCIGART_TRANSLATE_EN); | |
1da177e4 LT |
853 | |
854 | /* set PCI GART page-table base address | |
855 | */ | |
ea98a92f | 856 | RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr); |
1da177e4 LT |
857 | |
858 | /* set address range for PCI address translate | |
859 | */ | |
b5e89ed5 DA |
860 | RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); |
861 | RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start | |
862 | + dev_priv->gart_size - 1); | |
1da177e4 LT |
863 | |
864 | /* Turn off AGP aperture -- is this required for PCI GART? | |
865 | */ | |
3d5e2c13 | 866 | radeon_write_agp_location(dev_priv, 0xffffffc0); |
b5e89ed5 | 867 | RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ |
1da177e4 | 868 | } else { |
b5e89ed5 DA |
869 | RADEON_WRITE(RADEON_AIC_CNTL, |
870 | tmp & ~RADEON_PCIGART_TRANSLATE_EN); | |
1da177e4 LT |
871 | } |
872 | } | |
873 | ||
84b1fd10 | 874 | static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) |
1da177e4 | 875 | { |
d985c108 DA |
876 | drm_radeon_private_t *dev_priv = dev->dev_private; |
877 | ||
b5e89ed5 | 878 | DRM_DEBUG("\n"); |
1da177e4 | 879 | |
f3dd5c37 | 880 | /* if we require new memory map but we don't have it fail */ |
54a56ac5 | 881 | if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { |
b15ec368 | 882 | DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); |
f3dd5c37 | 883 | radeon_do_cleanup_cp(dev); |
20caafa6 | 884 | return -EINVAL; |
f3dd5c37 DA |
885 | } |
886 | ||
54a56ac5 | 887 | if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { |
d985c108 | 888 | DRM_DEBUG("Forcing AGP card to PCI mode\n"); |
54a56ac5 DA |
889 | dev_priv->flags &= ~RADEON_IS_AGP; |
890 | } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) | |
b15ec368 DA |
891 | && !init->is_pci) { |
892 | DRM_DEBUG("Restoring AGP flag\n"); | |
54a56ac5 | 893 | dev_priv->flags |= RADEON_IS_AGP; |
d985c108 | 894 | } |
1da177e4 | 895 | |
54a56ac5 | 896 | if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) { |
b5e89ed5 | 897 | DRM_ERROR("PCI GART memory not allocated!\n"); |
1da177e4 | 898 | radeon_do_cleanup_cp(dev); |
20caafa6 | 899 | return -EINVAL; |
1da177e4 LT |
900 | } |
901 | ||
902 | dev_priv->usec_timeout = init->usec_timeout; | |
b5e89ed5 DA |
903 | if (dev_priv->usec_timeout < 1 || |
904 | dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { | |
905 | DRM_DEBUG("TIMEOUT problem!\n"); | |
1da177e4 | 906 | radeon_do_cleanup_cp(dev); |
20caafa6 | 907 | return -EINVAL; |
1da177e4 LT |
908 | } |
909 | ||
ddbee333 DA |
910 | /* Enable vblank on CRTC1 for older X servers |
911 | */ | |
912 | dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; | |
913 | ||
d985c108 | 914 | switch(init->func) { |
1da177e4 | 915 | case RADEON_INIT_R200_CP: |
b5e89ed5 | 916 | dev_priv->microcode_version = UCODE_R200; |
1da177e4 LT |
917 | break; |
918 | case RADEON_INIT_R300_CP: | |
b5e89ed5 | 919 | dev_priv->microcode_version = UCODE_R300; |
1da177e4 LT |
920 | break; |
921 | default: | |
b5e89ed5 | 922 | dev_priv->microcode_version = UCODE_R100; |
1da177e4 | 923 | } |
b5e89ed5 | 924 | |
1da177e4 LT |
925 | dev_priv->do_boxes = 0; |
926 | dev_priv->cp_mode = init->cp_mode; | |
927 | ||
928 | /* We don't support anything other than bus-mastering ring mode, | |
929 | * but the ring can be in either AGP or PCI space for the ring | |
930 | * read pointer. | |
931 | */ | |
b5e89ed5 DA |
932 | if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && |
933 | (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { | |
934 | DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); | |
1da177e4 | 935 | radeon_do_cleanup_cp(dev); |
20caafa6 | 936 | return -EINVAL; |
1da177e4 LT |
937 | } |
938 | ||
b5e89ed5 | 939 | switch (init->fb_bpp) { |
1da177e4 LT |
940 | case 16: |
941 | dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; | |
942 | break; | |
943 | case 32: | |
944 | default: | |
945 | dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; | |
946 | break; | |
947 | } | |
b5e89ed5 DA |
948 | dev_priv->front_offset = init->front_offset; |
949 | dev_priv->front_pitch = init->front_pitch; | |
950 | dev_priv->back_offset = init->back_offset; | |
951 | dev_priv->back_pitch = init->back_pitch; | |
1da177e4 | 952 | |
b5e89ed5 | 953 | switch (init->depth_bpp) { |
1da177e4 LT |
954 | case 16: |
955 | dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; | |
956 | break; | |
957 | case 32: | |
958 | default: | |
959 | dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; | |
960 | break; | |
961 | } | |
b5e89ed5 DA |
962 | dev_priv->depth_offset = init->depth_offset; |
963 | dev_priv->depth_pitch = init->depth_pitch; | |
1da177e4 LT |
964 | |
965 | /* Hardware state for depth clears. Remove this if/when we no | |
966 | * longer clear the depth buffer with a 3D rectangle. Hard-code | |
967 | * all values to prevent unwanted 3D state from slipping through | |
968 | * and screwing with the clear operation. | |
969 | */ | |
970 | dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | | |
971 | (dev_priv->color_fmt << 10) | | |
b5e89ed5 DA |
972 | (dev_priv->microcode_version == |
973 | UCODE_R100 ? RADEON_ZBLOCK16 : 0)); | |
1da177e4 | 974 | |
b5e89ed5 DA |
975 | dev_priv->depth_clear.rb3d_zstencilcntl = |
976 | (dev_priv->depth_fmt | | |
977 | RADEON_Z_TEST_ALWAYS | | |
978 | RADEON_STENCIL_TEST_ALWAYS | | |
979 | RADEON_STENCIL_S_FAIL_REPLACE | | |
980 | RADEON_STENCIL_ZPASS_REPLACE | | |
981 | RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE); | |
1da177e4 LT |
982 | |
983 | dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | | |
984 | RADEON_BFACE_SOLID | | |
985 | RADEON_FFACE_SOLID | | |
986 | RADEON_FLAT_SHADE_VTX_LAST | | |
987 | RADEON_DIFFUSE_SHADE_FLAT | | |
988 | RADEON_ALPHA_SHADE_FLAT | | |
989 | RADEON_SPECULAR_SHADE_FLAT | | |
990 | RADEON_FOG_SHADE_FLAT | | |
991 | RADEON_VTX_PIX_CENTER_OGL | | |
992 | RADEON_ROUND_MODE_TRUNC | | |
993 | RADEON_ROUND_PREC_8TH_PIX); | |
994 | ||
1da177e4 | 995 | |
1da177e4 LT |
996 | dev_priv->ring_offset = init->ring_offset; |
997 | dev_priv->ring_rptr_offset = init->ring_rptr_offset; | |
998 | dev_priv->buffers_offset = init->buffers_offset; | |
999 | dev_priv->gart_textures_offset = init->gart_textures_offset; | |
b5e89ed5 | 1000 | |
da509d7a | 1001 | dev_priv->sarea = drm_getsarea(dev); |
b5e89ed5 | 1002 | if (!dev_priv->sarea) { |
1da177e4 | 1003 | DRM_ERROR("could not find sarea!\n"); |
1da177e4 | 1004 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1005 | return -EINVAL; |
1da177e4 LT |
1006 | } |
1007 | ||
1da177e4 | 1008 | dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); |
b5e89ed5 | 1009 | if (!dev_priv->cp_ring) { |
1da177e4 | 1010 | DRM_ERROR("could not find cp ring region!\n"); |
1da177e4 | 1011 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1012 | return -EINVAL; |
1da177e4 LT |
1013 | } |
1014 | dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); | |
b5e89ed5 | 1015 | if (!dev_priv->ring_rptr) { |
1da177e4 | 1016 | DRM_ERROR("could not find ring read pointer!\n"); |
1da177e4 | 1017 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1018 | return -EINVAL; |
1da177e4 | 1019 | } |
d1f2b55a | 1020 | dev->agp_buffer_token = init->buffers_offset; |
1da177e4 | 1021 | dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); |
b5e89ed5 | 1022 | if (!dev->agp_buffer_map) { |
1da177e4 | 1023 | DRM_ERROR("could not find dma buffer region!\n"); |
1da177e4 | 1024 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1025 | return -EINVAL; |
1da177e4 LT |
1026 | } |
1027 | ||
b5e89ed5 DA |
1028 | if (init->gart_textures_offset) { |
1029 | dev_priv->gart_textures = | |
1030 | drm_core_findmap(dev, init->gart_textures_offset); | |
1031 | if (!dev_priv->gart_textures) { | |
1da177e4 | 1032 | DRM_ERROR("could not find GART texture region!\n"); |
1da177e4 | 1033 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1034 | return -EINVAL; |
1da177e4 LT |
1035 | } |
1036 | } | |
1037 | ||
1038 | dev_priv->sarea_priv = | |
b5e89ed5 DA |
1039 | (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle + |
1040 | init->sarea_priv_offset); | |
1da177e4 LT |
1041 | |
1042 | #if __OS_HAS_AGP | |
54a56ac5 | 1043 | if (dev_priv->flags & RADEON_IS_AGP) { |
b5e89ed5 DA |
1044 | drm_core_ioremap(dev_priv->cp_ring, dev); |
1045 | drm_core_ioremap(dev_priv->ring_rptr, dev); | |
1046 | drm_core_ioremap(dev->agp_buffer_map, dev); | |
1047 | if (!dev_priv->cp_ring->handle || | |
1048 | !dev_priv->ring_rptr->handle || | |
1049 | !dev->agp_buffer_map->handle) { | |
1da177e4 | 1050 | DRM_ERROR("could not find ioremap agp regions!\n"); |
1da177e4 | 1051 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1052 | return -EINVAL; |
1da177e4 LT |
1053 | } |
1054 | } else | |
1055 | #endif | |
1056 | { | |
b5e89ed5 | 1057 | dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; |
1da177e4 | 1058 | dev_priv->ring_rptr->handle = |
b5e89ed5 DA |
1059 | (void *)dev_priv->ring_rptr->offset; |
1060 | dev->agp_buffer_map->handle = | |
1061 | (void *)dev->agp_buffer_map->offset; | |
1062 | ||
1063 | DRM_DEBUG("dev_priv->cp_ring->handle %p\n", | |
1064 | dev_priv->cp_ring->handle); | |
1065 | DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", | |
1066 | dev_priv->ring_rptr->handle); | |
1067 | DRM_DEBUG("dev->agp_buffer_map->handle %p\n", | |
1068 | dev->agp_buffer_map->handle); | |
1da177e4 LT |
1069 | } |
1070 | ||
3d5e2c13 | 1071 | dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16; |
bc5f4523 | 1072 | dev_priv->fb_size = |
3d5e2c13 | 1073 | ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000) |
d5ea702f | 1074 | - dev_priv->fb_location; |
1da177e4 | 1075 | |
b5e89ed5 DA |
1076 | dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | |
1077 | ((dev_priv->front_offset | |
1078 | + dev_priv->fb_location) >> 10)); | |
1da177e4 | 1079 | |
b5e89ed5 DA |
1080 | dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | |
1081 | ((dev_priv->back_offset | |
1082 | + dev_priv->fb_location) >> 10)); | |
1da177e4 | 1083 | |
b5e89ed5 DA |
1084 | dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | |
1085 | ((dev_priv->depth_offset | |
1086 | + dev_priv->fb_location) >> 10)); | |
1da177e4 LT |
1087 | |
1088 | dev_priv->gart_size = init->gart_size; | |
d5ea702f DA |
1089 | |
1090 | /* New let's set the memory map ... */ | |
1091 | if (dev_priv->new_memmap) { | |
1092 | u32 base = 0; | |
1093 | ||
1094 | DRM_INFO("Setting GART location based on new memory map\n"); | |
1095 | ||
1096 | /* If using AGP, try to locate the AGP aperture at the same | |
1097 | * location in the card and on the bus, though we have to | |
1098 | * align it down. | |
1099 | */ | |
1100 | #if __OS_HAS_AGP | |
54a56ac5 | 1101 | if (dev_priv->flags & RADEON_IS_AGP) { |
d5ea702f DA |
1102 | base = dev->agp->base; |
1103 | /* Check if valid */ | |
80b2c386 MD |
1104 | if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && |
1105 | base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { | |
d5ea702f DA |
1106 | DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", |
1107 | dev->agp->base); | |
1108 | base = 0; | |
1109 | } | |
1110 | } | |
1111 | #endif | |
1112 | /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ | |
1113 | if (base == 0) { | |
1114 | base = dev_priv->fb_location + dev_priv->fb_size; | |
80b2c386 MD |
1115 | if (base < dev_priv->fb_location || |
1116 | ((base + dev_priv->gart_size) & 0xfffffffful) < base) | |
d5ea702f DA |
1117 | base = dev_priv->fb_location |
1118 | - dev_priv->gart_size; | |
bc5f4523 | 1119 | } |
d5ea702f DA |
1120 | dev_priv->gart_vm_start = base & 0xffc00000u; |
1121 | if (dev_priv->gart_vm_start != base) | |
1122 | DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", | |
1123 | base, dev_priv->gart_vm_start); | |
1124 | } else { | |
1125 | DRM_INFO("Setting GART location based on old memory map\n"); | |
1126 | dev_priv->gart_vm_start = dev_priv->fb_location + | |
1127 | RADEON_READ(RADEON_CONFIG_APER_SIZE); | |
1128 | } | |
1da177e4 LT |
1129 | |
1130 | #if __OS_HAS_AGP | |
54a56ac5 | 1131 | if (dev_priv->flags & RADEON_IS_AGP) |
1da177e4 | 1132 | dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset |
b5e89ed5 DA |
1133 | - dev->agp->base |
1134 | + dev_priv->gart_vm_start); | |
1da177e4 LT |
1135 | else |
1136 | #endif | |
1137 | dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset | |
b0917bd9 IK |
1138 | - (unsigned long)dev->sg->virtual |
1139 | + dev_priv->gart_vm_start); | |
1da177e4 | 1140 | |
b5e89ed5 DA |
1141 | DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); |
1142 | DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start); | |
1143 | DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n", | |
1144 | dev_priv->gart_buffers_offset); | |
1da177e4 | 1145 | |
b5e89ed5 DA |
1146 | dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; |
1147 | dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle | |
1da177e4 LT |
1148 | + init->ring_size / sizeof(u32)); |
1149 | dev_priv->ring.size = init->ring_size; | |
b5e89ed5 | 1150 | dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); |
1da177e4 | 1151 | |
576cc458 RS |
1152 | dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; |
1153 | dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8); | |
1154 | ||
1155 | dev_priv->ring.fetch_size = /* init->fetch_size */ 32; | |
1156 | dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16); | |
b5e89ed5 | 1157 | dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; |
1da177e4 LT |
1158 | |
1159 | dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; | |
1160 | ||
1161 | #if __OS_HAS_AGP | |
54a56ac5 | 1162 | if (dev_priv->flags & RADEON_IS_AGP) { |
1da177e4 | 1163 | /* Turn off PCI GART */ |
b5e89ed5 | 1164 | radeon_set_pcigart(dev_priv, 0); |
1da177e4 LT |
1165 | } else |
1166 | #endif | |
1167 | { | |
b05c2385 | 1168 | dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); |
ea98a92f | 1169 | /* if we have an offset set from userspace */ |
f2b04cd2 | 1170 | if (dev_priv->pcigart_offset_set) { |
b5e89ed5 DA |
1171 | dev_priv->gart_info.bus_addr = |
1172 | dev_priv->pcigart_offset + dev_priv->fb_location; | |
f26c473c | 1173 | dev_priv->gart_info.mapping.offset = |
7fc86860 | 1174 | dev_priv->pcigart_offset + dev_priv->fb_aper_offset; |
f26c473c | 1175 | dev_priv->gart_info.mapping.size = |
f2b04cd2 | 1176 | dev_priv->gart_info.table_size; |
f26c473c | 1177 | |
242e3df8 | 1178 | drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); |
b5e89ed5 | 1179 | dev_priv->gart_info.addr = |
f26c473c | 1180 | dev_priv->gart_info.mapping.handle; |
b5e89ed5 | 1181 | |
f2b04cd2 DA |
1182 | if (dev_priv->flags & RADEON_IS_PCIE) |
1183 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE; | |
1184 | else | |
1185 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; | |
b5e89ed5 DA |
1186 | dev_priv->gart_info.gart_table_location = |
1187 | DRM_ATI_GART_FB; | |
1188 | ||
f26c473c | 1189 | DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", |
b5e89ed5 DA |
1190 | dev_priv->gart_info.addr, |
1191 | dev_priv->pcigart_offset); | |
1192 | } else { | |
f2b04cd2 DA |
1193 | if (dev_priv->flags & RADEON_IS_IGPGART) |
1194 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP; | |
1195 | else | |
1196 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; | |
b5e89ed5 DA |
1197 | dev_priv->gart_info.gart_table_location = |
1198 | DRM_ATI_GART_MAIN; | |
f26c473c DA |
1199 | dev_priv->gart_info.addr = NULL; |
1200 | dev_priv->gart_info.bus_addr = 0; | |
54a56ac5 | 1201 | if (dev_priv->flags & RADEON_IS_PCIE) { |
b5e89ed5 DA |
1202 | DRM_ERROR |
1203 | ("Cannot use PCI Express without GART in FB memory\n"); | |
ea98a92f | 1204 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1205 | return -EINVAL; |
ea98a92f DA |
1206 | } |
1207 | } | |
1208 | ||
1209 | if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { | |
b5e89ed5 | 1210 | DRM_ERROR("failed to init PCI GART!\n"); |
1da177e4 | 1211 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1212 | return -ENOMEM; |
1da177e4 LT |
1213 | } |
1214 | ||
1215 | /* Turn on PCI GART */ | |
b5e89ed5 | 1216 | radeon_set_pcigart(dev_priv, 1); |
1da177e4 LT |
1217 | } |
1218 | ||
b5e89ed5 DA |
1219 | radeon_cp_load_microcode(dev_priv); |
1220 | radeon_cp_init_ring_buffer(dev, dev_priv); | |
1da177e4 LT |
1221 | |
1222 | dev_priv->last_buf = 0; | |
1223 | ||
b5e89ed5 | 1224 | radeon_do_engine_reset(dev); |
d5ea702f | 1225 | radeon_test_writeback(dev_priv); |
1da177e4 LT |
1226 | |
1227 | return 0; | |
1228 | } | |
1229 | ||
84b1fd10 | 1230 | static int radeon_do_cleanup_cp(struct drm_device * dev) |
1da177e4 LT |
1231 | { |
1232 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
b5e89ed5 | 1233 | DRM_DEBUG("\n"); |
1da177e4 LT |
1234 | |
1235 | /* Make sure interrupts are disabled here because the uninstall ioctl | |
1236 | * may not have been called from userspace and after dev_private | |
1237 | * is freed, it's too late. | |
1238 | */ | |
b5e89ed5 DA |
1239 | if (dev->irq_enabled) |
1240 | drm_irq_uninstall(dev); | |
1da177e4 LT |
1241 | |
1242 | #if __OS_HAS_AGP | |
54a56ac5 | 1243 | if (dev_priv->flags & RADEON_IS_AGP) { |
d985c108 | 1244 | if (dev_priv->cp_ring != NULL) { |
b5e89ed5 | 1245 | drm_core_ioremapfree(dev_priv->cp_ring, dev); |
d985c108 DA |
1246 | dev_priv->cp_ring = NULL; |
1247 | } | |
1248 | if (dev_priv->ring_rptr != NULL) { | |
b5e89ed5 | 1249 | drm_core_ioremapfree(dev_priv->ring_rptr, dev); |
d985c108 DA |
1250 | dev_priv->ring_rptr = NULL; |
1251 | } | |
b5e89ed5 DA |
1252 | if (dev->agp_buffer_map != NULL) { |
1253 | drm_core_ioremapfree(dev->agp_buffer_map, dev); | |
1da177e4 LT |
1254 | dev->agp_buffer_map = NULL; |
1255 | } | |
1256 | } else | |
1257 | #endif | |
1258 | { | |
d985c108 DA |
1259 | |
1260 | if (dev_priv->gart_info.bus_addr) { | |
1261 | /* Turn off PCI GART */ | |
1262 | radeon_set_pcigart(dev_priv, 0); | |
ea98a92f DA |
1263 | if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) |
1264 | DRM_ERROR("failed to cleanup PCI GART!\n"); | |
d985c108 | 1265 | } |
b5e89ed5 | 1266 | |
d985c108 DA |
1267 | if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) |
1268 | { | |
f26c473c | 1269 | drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); |
f2b04cd2 | 1270 | dev_priv->gart_info.addr = 0; |
ea98a92f | 1271 | } |
1da177e4 | 1272 | } |
1da177e4 LT |
1273 | /* only clear to the start of flags */ |
1274 | memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); | |
1275 | ||
1276 | return 0; | |
1277 | } | |
1278 | ||
b5e89ed5 DA |
1279 | /* This code will reinit the Radeon CP hardware after a resume from disc. |
1280 | * AFAIK, it would be very difficult to pickle the state at suspend time, so | |
1da177e4 LT |
1281 | * here we make sure that all Radeon hardware initialisation is re-done without |
1282 | * affecting running applications. | |
1283 | * | |
1284 | * Charl P. Botha <http://cpbotha.net> | |
1285 | */ | |
84b1fd10 | 1286 | static int radeon_do_resume_cp(struct drm_device * dev) |
1da177e4 LT |
1287 | { |
1288 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1289 | ||
b5e89ed5 DA |
1290 | if (!dev_priv) { |
1291 | DRM_ERROR("Called with no initialization\n"); | |
20caafa6 | 1292 | return -EINVAL; |
1da177e4 LT |
1293 | } |
1294 | ||
1295 | DRM_DEBUG("Starting radeon_do_resume_cp()\n"); | |
1296 | ||
1297 | #if __OS_HAS_AGP | |
54a56ac5 | 1298 | if (dev_priv->flags & RADEON_IS_AGP) { |
1da177e4 | 1299 | /* Turn off PCI GART */ |
b5e89ed5 | 1300 | radeon_set_pcigart(dev_priv, 0); |
1da177e4 LT |
1301 | } else |
1302 | #endif | |
1303 | { | |
1304 | /* Turn on PCI GART */ | |
b5e89ed5 | 1305 | radeon_set_pcigart(dev_priv, 1); |
1da177e4 LT |
1306 | } |
1307 | ||
b5e89ed5 DA |
1308 | radeon_cp_load_microcode(dev_priv); |
1309 | radeon_cp_init_ring_buffer(dev, dev_priv); | |
1da177e4 | 1310 | |
b5e89ed5 | 1311 | radeon_do_engine_reset(dev); |
0a3e67a4 | 1312 | radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); |
1da177e4 LT |
1313 | |
1314 | DRM_DEBUG("radeon_do_resume_cp() complete\n"); | |
1315 | ||
1316 | return 0; | |
1317 | } | |
1318 | ||
c153f45f | 1319 | int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1320 | { |
c153f45f | 1321 | drm_radeon_init_t *init = data; |
1da177e4 | 1322 | |
6c340eac | 1323 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1324 | |
c153f45f | 1325 | if (init->func == RADEON_INIT_R300_CP) |
3d5e2c13 | 1326 | r300_init_reg_flags(dev); |
414ed537 | 1327 | |
c153f45f | 1328 | switch (init->func) { |
1da177e4 LT |
1329 | case RADEON_INIT_CP: |
1330 | case RADEON_INIT_R200_CP: | |
1331 | case RADEON_INIT_R300_CP: | |
c153f45f | 1332 | return radeon_do_init_cp(dev, init); |
1da177e4 | 1333 | case RADEON_CLEANUP_CP: |
b5e89ed5 | 1334 | return radeon_do_cleanup_cp(dev); |
1da177e4 LT |
1335 | } |
1336 | ||
20caafa6 | 1337 | return -EINVAL; |
1da177e4 LT |
1338 | } |
1339 | ||
c153f45f | 1340 | int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1341 | { |
1da177e4 | 1342 | drm_radeon_private_t *dev_priv = dev->dev_private; |
b5e89ed5 | 1343 | DRM_DEBUG("\n"); |
1da177e4 | 1344 | |
6c340eac | 1345 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1346 | |
b5e89ed5 | 1347 | if (dev_priv->cp_running) { |
3e684eae | 1348 | DRM_DEBUG("while CP running\n"); |
1da177e4 LT |
1349 | return 0; |
1350 | } | |
b5e89ed5 | 1351 | if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { |
3e684eae MN |
1352 | DRM_DEBUG("called with bogus CP mode (%d)\n", |
1353 | dev_priv->cp_mode); | |
1da177e4 LT |
1354 | return 0; |
1355 | } | |
1356 | ||
b5e89ed5 | 1357 | radeon_do_cp_start(dev_priv); |
1da177e4 LT |
1358 | |
1359 | return 0; | |
1360 | } | |
1361 | ||
1362 | /* Stop the CP. The engine must have been idled before calling this | |
1363 | * routine. | |
1364 | */ | |
c153f45f | 1365 | int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1366 | { |
1da177e4 | 1367 | drm_radeon_private_t *dev_priv = dev->dev_private; |
c153f45f | 1368 | drm_radeon_cp_stop_t *stop = data; |
1da177e4 | 1369 | int ret; |
b5e89ed5 | 1370 | DRM_DEBUG("\n"); |
1da177e4 | 1371 | |
6c340eac | 1372 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1373 | |
1da177e4 LT |
1374 | if (!dev_priv->cp_running) |
1375 | return 0; | |
1376 | ||
1377 | /* Flush any pending CP commands. This ensures any outstanding | |
1378 | * commands are exectuted by the engine before we turn it off. | |
1379 | */ | |
c153f45f | 1380 | if (stop->flush) { |
b5e89ed5 | 1381 | radeon_do_cp_flush(dev_priv); |
1da177e4 LT |
1382 | } |
1383 | ||
1384 | /* If we fail to make the engine go idle, we return an error | |
1385 | * code so that the DRM ioctl wrapper can try again. | |
1386 | */ | |
c153f45f | 1387 | if (stop->idle) { |
b5e89ed5 DA |
1388 | ret = radeon_do_cp_idle(dev_priv); |
1389 | if (ret) | |
1390 | return ret; | |
1da177e4 LT |
1391 | } |
1392 | ||
1393 | /* Finally, we can turn off the CP. If the engine isn't idle, | |
1394 | * we will get some dropped triangles as they won't be fully | |
1395 | * rendered before the CP is shut down. | |
1396 | */ | |
b5e89ed5 | 1397 | radeon_do_cp_stop(dev_priv); |
1da177e4 LT |
1398 | |
1399 | /* Reset the engine */ | |
b5e89ed5 | 1400 | radeon_do_engine_reset(dev); |
1da177e4 LT |
1401 | |
1402 | return 0; | |
1403 | } | |
1404 | ||
84b1fd10 | 1405 | void radeon_do_release(struct drm_device * dev) |
1da177e4 LT |
1406 | { |
1407 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1408 | int i, ret; | |
1409 | ||
1410 | if (dev_priv) { | |
1411 | if (dev_priv->cp_running) { | |
1412 | /* Stop the cp */ | |
b5e89ed5 | 1413 | while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { |
1da177e4 LT |
1414 | DRM_DEBUG("radeon_do_cp_idle %d\n", ret); |
1415 | #ifdef __linux__ | |
1416 | schedule(); | |
1417 | #else | |
1418 | tsleep(&ret, PZERO, "rdnrel", 1); | |
1419 | #endif | |
1420 | } | |
b5e89ed5 DA |
1421 | radeon_do_cp_stop(dev_priv); |
1422 | radeon_do_engine_reset(dev); | |
1da177e4 LT |
1423 | } |
1424 | ||
1425 | /* Disable *all* interrupts */ | |
1426 | if (dev_priv->mmio) /* remove this after permanent addmaps */ | |
b5e89ed5 | 1427 | RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); |
1da177e4 | 1428 | |
b5e89ed5 | 1429 | if (dev_priv->mmio) { /* remove all surfaces */ |
1da177e4 | 1430 | for (i = 0; i < RADEON_MAX_SURFACES; i++) { |
b5e89ed5 DA |
1431 | RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0); |
1432 | RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + | |
1433 | 16 * i, 0); | |
1434 | RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + | |
1435 | 16 * i, 0); | |
1da177e4 LT |
1436 | } |
1437 | } | |
1438 | ||
1439 | /* Free memory heap structures */ | |
b5e89ed5 DA |
1440 | radeon_mem_takedown(&(dev_priv->gart_heap)); |
1441 | radeon_mem_takedown(&(dev_priv->fb_heap)); | |
1da177e4 LT |
1442 | |
1443 | /* deallocate kernel resources */ | |
b5e89ed5 | 1444 | radeon_do_cleanup_cp(dev); |
1da177e4 LT |
1445 | } |
1446 | } | |
1447 | ||
1448 | /* Just reset the CP ring. Called as part of an X Server engine reset. | |
1449 | */ | |
c153f45f | 1450 | int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1451 | { |
1da177e4 | 1452 | drm_radeon_private_t *dev_priv = dev->dev_private; |
b5e89ed5 | 1453 | DRM_DEBUG("\n"); |
1da177e4 | 1454 | |
6c340eac | 1455 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1456 | |
b5e89ed5 | 1457 | if (!dev_priv) { |
3e684eae | 1458 | DRM_DEBUG("called before init done\n"); |
20caafa6 | 1459 | return -EINVAL; |
1da177e4 LT |
1460 | } |
1461 | ||
b5e89ed5 | 1462 | radeon_do_cp_reset(dev_priv); |
1da177e4 LT |
1463 | |
1464 | /* The CP is no longer running after an engine reset */ | |
1465 | dev_priv->cp_running = 0; | |
1466 | ||
1467 | return 0; | |
1468 | } | |
1469 | ||
c153f45f | 1470 | int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1471 | { |
1da177e4 | 1472 | drm_radeon_private_t *dev_priv = dev->dev_private; |
b5e89ed5 | 1473 | DRM_DEBUG("\n"); |
1da177e4 | 1474 | |
6c340eac | 1475 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1476 | |
b5e89ed5 | 1477 | return radeon_do_cp_idle(dev_priv); |
1da177e4 LT |
1478 | } |
1479 | ||
1480 | /* Added by Charl P. Botha to call radeon_do_resume_cp(). | |
1481 | */ | |
c153f45f | 1482 | int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1483 | { |
1da177e4 LT |
1484 | |
1485 | return radeon_do_resume_cp(dev); | |
1486 | } | |
1487 | ||
c153f45f | 1488 | int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1489 | { |
b5e89ed5 | 1490 | DRM_DEBUG("\n"); |
1da177e4 | 1491 | |
6c340eac | 1492 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1493 | |
b5e89ed5 | 1494 | return radeon_do_engine_reset(dev); |
1da177e4 LT |
1495 | } |
1496 | ||
1da177e4 LT |
1497 | /* ================================================================ |
1498 | * Fullscreen mode | |
1499 | */ | |
1500 | ||
1501 | /* KW: Deprecated to say the least: | |
1502 | */ | |
c153f45f | 1503 | int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 LT |
1504 | { |
1505 | return 0; | |
1506 | } | |
1507 | ||
1da177e4 LT |
1508 | /* ================================================================ |
1509 | * Freelist management | |
1510 | */ | |
1511 | ||
1512 | /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through | |
1513 | * bufs until freelist code is used. Note this hides a problem with | |
1514 | * the scratch register * (used to keep track of last buffer | |
1515 | * completed) being written to before * the last buffer has actually | |
b5e89ed5 | 1516 | * completed rendering. |
1da177e4 LT |
1517 | * |
1518 | * KW: It's also a good way to find free buffers quickly. | |
1519 | * | |
1520 | * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't | |
1521 | * sleep. However, bugs in older versions of radeon_accel.c mean that | |
1522 | * we essentially have to do this, else old clients will break. | |
b5e89ed5 | 1523 | * |
1da177e4 LT |
1524 | * However, it does leave open a potential deadlock where all the |
1525 | * buffers are held by other clients, which can't release them because | |
b5e89ed5 | 1526 | * they can't get the lock. |
1da177e4 LT |
1527 | */ |
1528 | ||
056219e2 | 1529 | struct drm_buf *radeon_freelist_get(struct drm_device * dev) |
1da177e4 | 1530 | { |
cdd55a29 | 1531 | struct drm_device_dma *dma = dev->dma; |
1da177e4 LT |
1532 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1533 | drm_radeon_buf_priv_t *buf_priv; | |
056219e2 | 1534 | struct drm_buf *buf; |
1da177e4 LT |
1535 | int i, t; |
1536 | int start; | |
1537 | ||
b5e89ed5 | 1538 | if (++dev_priv->last_buf >= dma->buf_count) |
1da177e4 LT |
1539 | dev_priv->last_buf = 0; |
1540 | ||
1541 | start = dev_priv->last_buf; | |
1542 | ||
b5e89ed5 DA |
1543 | for (t = 0; t < dev_priv->usec_timeout; t++) { |
1544 | u32 done_age = GET_SCRATCH(1); | |
1545 | DRM_DEBUG("done_age = %d\n", done_age); | |
1546 | for (i = start; i < dma->buf_count; i++) { | |
1da177e4 LT |
1547 | buf = dma->buflist[i]; |
1548 | buf_priv = buf->dev_private; | |
6c340eac EA |
1549 | if (buf->file_priv == NULL || (buf->pending && |
1550 | buf_priv->age <= | |
1551 | done_age)) { | |
1da177e4 LT |
1552 | dev_priv->stats.requested_bufs++; |
1553 | buf->pending = 0; | |
1554 | return buf; | |
1555 | } | |
1556 | start = 0; | |
1557 | } | |
1558 | ||
1559 | if (t) { | |
b5e89ed5 | 1560 | DRM_UDELAY(1); |
1da177e4 LT |
1561 | dev_priv->stats.freelist_loops++; |
1562 | } | |
1563 | } | |
1564 | ||
b5e89ed5 | 1565 | DRM_DEBUG("returning NULL!\n"); |
1da177e4 LT |
1566 | return NULL; |
1567 | } | |
b5e89ed5 | 1568 | |
1da177e4 | 1569 | #if 0 |
056219e2 | 1570 | struct drm_buf *radeon_freelist_get(struct drm_device * dev) |
1da177e4 | 1571 | { |
cdd55a29 | 1572 | struct drm_device_dma *dma = dev->dma; |
1da177e4 LT |
1573 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1574 | drm_radeon_buf_priv_t *buf_priv; | |
056219e2 | 1575 | struct drm_buf *buf; |
1da177e4 LT |
1576 | int i, t; |
1577 | int start; | |
1578 | u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); | |
1579 | ||
b5e89ed5 | 1580 | if (++dev_priv->last_buf >= dma->buf_count) |
1da177e4 LT |
1581 | dev_priv->last_buf = 0; |
1582 | ||
1583 | start = dev_priv->last_buf; | |
1584 | dev_priv->stats.freelist_loops++; | |
b5e89ed5 DA |
1585 | |
1586 | for (t = 0; t < 2; t++) { | |
1587 | for (i = start; i < dma->buf_count; i++) { | |
1da177e4 LT |
1588 | buf = dma->buflist[i]; |
1589 | buf_priv = buf->dev_private; | |
6c340eac EA |
1590 | if (buf->file_priv == 0 || (buf->pending && |
1591 | buf_priv->age <= | |
1592 | done_age)) { | |
1da177e4 LT |
1593 | dev_priv->stats.requested_bufs++; |
1594 | buf->pending = 0; | |
1595 | return buf; | |
1596 | } | |
1597 | } | |
1598 | start = 0; | |
1599 | } | |
1600 | ||
1601 | return NULL; | |
1602 | } | |
1603 | #endif | |
1604 | ||
84b1fd10 | 1605 | void radeon_freelist_reset(struct drm_device * dev) |
1da177e4 | 1606 | { |
cdd55a29 | 1607 | struct drm_device_dma *dma = dev->dma; |
1da177e4 LT |
1608 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1609 | int i; | |
1610 | ||
1611 | dev_priv->last_buf = 0; | |
b5e89ed5 | 1612 | for (i = 0; i < dma->buf_count; i++) { |
056219e2 | 1613 | struct drm_buf *buf = dma->buflist[i]; |
1da177e4 LT |
1614 | drm_radeon_buf_priv_t *buf_priv = buf->dev_private; |
1615 | buf_priv->age = 0; | |
1616 | } | |
1617 | } | |
1618 | ||
1da177e4 LT |
1619 | /* ================================================================ |
1620 | * CP command submission | |
1621 | */ | |
1622 | ||
b5e89ed5 | 1623 | int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) |
1da177e4 LT |
1624 | { |
1625 | drm_radeon_ring_buffer_t *ring = &dev_priv->ring; | |
1626 | int i; | |
b5e89ed5 | 1627 | u32 last_head = GET_RING_HEAD(dev_priv); |
1da177e4 | 1628 | |
b5e89ed5 DA |
1629 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
1630 | u32 head = GET_RING_HEAD(dev_priv); | |
1da177e4 LT |
1631 | |
1632 | ring->space = (head - ring->tail) * sizeof(u32); | |
b5e89ed5 | 1633 | if (ring->space <= 0) |
1da177e4 | 1634 | ring->space += ring->size; |
b5e89ed5 | 1635 | if (ring->space > n) |
1da177e4 | 1636 | return 0; |
b5e89ed5 | 1637 | |
1da177e4 LT |
1638 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; |
1639 | ||
1640 | if (head != last_head) | |
1641 | i = 0; | |
1642 | last_head = head; | |
1643 | ||
b5e89ed5 | 1644 | DRM_UDELAY(1); |
1da177e4 LT |
1645 | } |
1646 | ||
1647 | /* FIXME: This return value is ignored in the BEGIN_RING macro! */ | |
1648 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
1649 | radeon_status(dev_priv); |
1650 | DRM_ERROR("failed!\n"); | |
1da177e4 | 1651 | #endif |
20caafa6 | 1652 | return -EBUSY; |
1da177e4 LT |
1653 | } |
1654 | ||
6c340eac EA |
1655 | static int radeon_cp_get_buffers(struct drm_device *dev, |
1656 | struct drm_file *file_priv, | |
c60ce623 | 1657 | struct drm_dma * d) |
1da177e4 LT |
1658 | { |
1659 | int i; | |
056219e2 | 1660 | struct drm_buf *buf; |
1da177e4 | 1661 | |
b5e89ed5 DA |
1662 | for (i = d->granted_count; i < d->request_count; i++) { |
1663 | buf = radeon_freelist_get(dev); | |
1664 | if (!buf) | |
20caafa6 | 1665 | return -EBUSY; /* NOTE: broken client */ |
1da177e4 | 1666 | |
6c340eac | 1667 | buf->file_priv = file_priv; |
1da177e4 | 1668 | |
b5e89ed5 DA |
1669 | if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, |
1670 | sizeof(buf->idx))) | |
20caafa6 | 1671 | return -EFAULT; |
b5e89ed5 DA |
1672 | if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, |
1673 | sizeof(buf->total))) | |
20caafa6 | 1674 | return -EFAULT; |
1da177e4 LT |
1675 | |
1676 | d->granted_count++; | |
1677 | } | |
1678 | return 0; | |
1679 | } | |
1680 | ||
c153f45f | 1681 | int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1682 | { |
cdd55a29 | 1683 | struct drm_device_dma *dma = dev->dma; |
1da177e4 | 1684 | int ret = 0; |
c153f45f | 1685 | struct drm_dma *d = data; |
1da177e4 | 1686 | |
6c340eac | 1687 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1688 | |
1da177e4 LT |
1689 | /* Please don't send us buffers. |
1690 | */ | |
c153f45f | 1691 | if (d->send_count != 0) { |
b5e89ed5 | 1692 | DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", |
c153f45f | 1693 | DRM_CURRENTPID, d->send_count); |
20caafa6 | 1694 | return -EINVAL; |
1da177e4 LT |
1695 | } |
1696 | ||
1697 | /* We'll send you buffers. | |
1698 | */ | |
c153f45f | 1699 | if (d->request_count < 0 || d->request_count > dma->buf_count) { |
b5e89ed5 | 1700 | DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", |
c153f45f | 1701 | DRM_CURRENTPID, d->request_count, dma->buf_count); |
20caafa6 | 1702 | return -EINVAL; |
1da177e4 LT |
1703 | } |
1704 | ||
c153f45f | 1705 | d->granted_count = 0; |
1da177e4 | 1706 | |
c153f45f EA |
1707 | if (d->request_count) { |
1708 | ret = radeon_cp_get_buffers(dev, file_priv, d); | |
1da177e4 LT |
1709 | } |
1710 | ||
1da177e4 LT |
1711 | return ret; |
1712 | } | |
1713 | ||
22eae947 | 1714 | int radeon_driver_load(struct drm_device *dev, unsigned long flags) |
1da177e4 LT |
1715 | { |
1716 | drm_radeon_private_t *dev_priv; | |
1717 | int ret = 0; | |
1718 | ||
1719 | dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER); | |
1720 | if (dev_priv == NULL) | |
20caafa6 | 1721 | return -ENOMEM; |
1da177e4 LT |
1722 | |
1723 | memset(dev_priv, 0, sizeof(drm_radeon_private_t)); | |
1724 | dev->dev_private = (void *)dev_priv; | |
1725 | dev_priv->flags = flags; | |
1726 | ||
54a56ac5 | 1727 | switch (flags & RADEON_FAMILY_MASK) { |
1da177e4 LT |
1728 | case CHIP_R100: |
1729 | case CHIP_RV200: | |
1730 | case CHIP_R200: | |
1731 | case CHIP_R300: | |
b15ec368 | 1732 | case CHIP_R350: |
414ed537 | 1733 | case CHIP_R420: |
edc6f389 | 1734 | case CHIP_R423: |
b15ec368 | 1735 | case CHIP_RV410: |
3d5e2c13 DA |
1736 | case CHIP_RV515: |
1737 | case CHIP_R520: | |
1738 | case CHIP_RV570: | |
1739 | case CHIP_R580: | |
54a56ac5 | 1740 | dev_priv->flags |= RADEON_HAS_HIERZ; |
1da177e4 LT |
1741 | break; |
1742 | default: | |
b5e89ed5 | 1743 | /* all other chips have no hierarchical z buffer */ |
1da177e4 LT |
1744 | break; |
1745 | } | |
414ed537 DA |
1746 | |
1747 | if (drm_device_is_agp(dev)) | |
54a56ac5 | 1748 | dev_priv->flags |= RADEON_IS_AGP; |
b15ec368 | 1749 | else if (drm_device_is_pcie(dev)) |
54a56ac5 | 1750 | dev_priv->flags |= RADEON_IS_PCIE; |
b15ec368 | 1751 | else |
54a56ac5 | 1752 | dev_priv->flags |= RADEON_IS_PCI; |
ea98a92f | 1753 | |
78538bf1 DA |
1754 | ret = drm_addmap(dev, drm_get_resource_start(dev, 2), |
1755 | drm_get_resource_len(dev, 2), _DRM_REGISTERS, | |
1756 | _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio); | |
1757 | if (ret != 0) | |
1758 | return ret; | |
1759 | ||
414ed537 | 1760 | DRM_DEBUG("%s card detected\n", |
54a56ac5 | 1761 | ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); |
1da177e4 LT |
1762 | return ret; |
1763 | } | |
1764 | ||
22eae947 DA |
1765 | /* Create mappings for registers and framebuffer so userland doesn't necessarily |
1766 | * have to find them. | |
1767 | */ | |
1768 | int radeon_driver_firstopen(struct drm_device *dev) | |
836cf046 DA |
1769 | { |
1770 | int ret; | |
1771 | drm_local_map_t *map; | |
1772 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1773 | ||
f2b04cd2 DA |
1774 | dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; |
1775 | ||
7fc86860 DA |
1776 | dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0); |
1777 | ret = drm_addmap(dev, dev_priv->fb_aper_offset, | |
836cf046 DA |
1778 | drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER, |
1779 | _DRM_WRITE_COMBINING, &map); | |
1780 | if (ret != 0) | |
1781 | return ret; | |
1782 | ||
1783 | return 0; | |
1784 | } | |
1785 | ||
22eae947 | 1786 | int radeon_driver_unload(struct drm_device *dev) |
1da177e4 LT |
1787 | { |
1788 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1789 | ||
1790 | DRM_DEBUG("\n"); | |
78538bf1 DA |
1791 | |
1792 | drm_rmmap(dev, dev_priv->mmio); | |
1793 | ||
1da177e4 LT |
1794 | drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); |
1795 | ||
1796 | dev->dev_private = NULL; | |
1797 | return 0; | |
1798 | } |