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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/console.h> | |
29 | #include <drm/drmP.h> | |
30 | #include <drm/drm_crtc_helper.h> | |
31 | #include <drm/radeon_drm.h> | |
32 | #include "radeon_reg.h" | |
33 | #include "radeon.h" | |
34 | #include "radeon_asic.h" | |
35 | #include "atom.h" | |
36 | ||
b1e3a6d1 MD |
37 | /* |
38 | * Clear GPU surface registers. | |
39 | */ | |
3ce0a23d | 40 | void radeon_surface_init(struct radeon_device *rdev) |
b1e3a6d1 MD |
41 | { |
42 | /* FIXME: check this out */ | |
43 | if (rdev->family < CHIP_R600) { | |
44 | int i; | |
45 | ||
46 | for (i = 0; i < 8; i++) { | |
47 | WREG32(RADEON_SURFACE0_INFO + | |
48 | i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO), | |
49 | 0); | |
50 | } | |
e024e110 DA |
51 | /* enable surfaces */ |
52 | WREG32(RADEON_SURFACE_CNTL, 0); | |
b1e3a6d1 MD |
53 | } |
54 | } | |
55 | ||
771fe6b9 JG |
56 | /* |
57 | * GPU scratch registers helpers function. | |
58 | */ | |
3ce0a23d | 59 | void radeon_scratch_init(struct radeon_device *rdev) |
771fe6b9 JG |
60 | { |
61 | int i; | |
62 | ||
63 | /* FIXME: check this out */ | |
64 | if (rdev->family < CHIP_R300) { | |
65 | rdev->scratch.num_reg = 5; | |
66 | } else { | |
67 | rdev->scratch.num_reg = 7; | |
68 | } | |
69 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
70 | rdev->scratch.free[i] = true; | |
71 | rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); | |
72 | } | |
73 | } | |
74 | ||
75 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) | |
76 | { | |
77 | int i; | |
78 | ||
79 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
80 | if (rdev->scratch.free[i]) { | |
81 | rdev->scratch.free[i] = false; | |
82 | *reg = rdev->scratch.reg[i]; | |
83 | return 0; | |
84 | } | |
85 | } | |
86 | return -EINVAL; | |
87 | } | |
88 | ||
89 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) | |
90 | { | |
91 | int i; | |
92 | ||
93 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
94 | if (rdev->scratch.reg[i] == reg) { | |
95 | rdev->scratch.free[i] = true; | |
96 | return; | |
97 | } | |
98 | } | |
99 | } | |
100 | ||
101 | /* | |
102 | * MC common functions | |
103 | */ | |
104 | int radeon_mc_setup(struct radeon_device *rdev) | |
105 | { | |
106 | uint32_t tmp; | |
107 | ||
108 | /* Some chips have an "issue" with the memory controller, the | |
109 | * location must be aligned to the size. We just align it down, | |
110 | * too bad if we walk over the top of system memory, we don't | |
111 | * use DMA without a remapped anyway. | |
112 | * Affected chips are rv280, all r3xx, and all r4xx, but not IGP | |
113 | */ | |
114 | /* FGLRX seems to setup like this, VRAM a 0, then GART. | |
115 | */ | |
116 | /* | |
117 | * Note: from R6xx the address space is 40bits but here we only | |
118 | * use 32bits (still have to see a card which would exhaust 4G | |
119 | * address space). | |
120 | */ | |
121 | if (rdev->mc.vram_location != 0xFFFFFFFFUL) { | |
122 | /* vram location was already setup try to put gtt after | |
123 | * if it fits */ | |
7a50f01a | 124 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; |
771fe6b9 JG |
125 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); |
126 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { | |
127 | rdev->mc.gtt_location = tmp; | |
128 | } else { | |
129 | if (rdev->mc.gtt_size >= rdev->mc.vram_location) { | |
130 | printk(KERN_ERR "[drm] GTT too big to fit " | |
131 | "before or after vram location.\n"); | |
132 | return -EINVAL; | |
133 | } | |
134 | rdev->mc.gtt_location = 0; | |
135 | } | |
136 | } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { | |
137 | /* gtt location was already setup try to put vram before | |
138 | * if it fits */ | |
7a50f01a | 139 | if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) { |
771fe6b9 JG |
140 | rdev->mc.vram_location = 0; |
141 | } else { | |
142 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; | |
7a50f01a DA |
143 | tmp += (rdev->mc.mc_vram_size - 1); |
144 | tmp &= ~(rdev->mc.mc_vram_size - 1); | |
145 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) { | |
771fe6b9 JG |
146 | rdev->mc.vram_location = tmp; |
147 | } else { | |
148 | printk(KERN_ERR "[drm] vram too big to fit " | |
149 | "before or after GTT location.\n"); | |
150 | return -EINVAL; | |
151 | } | |
152 | } | |
153 | } else { | |
154 | rdev->mc.vram_location = 0; | |
17332925 DA |
155 | tmp = rdev->mc.mc_vram_size; |
156 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); | |
157 | rdev->mc.gtt_location = tmp; | |
771fe6b9 | 158 | } |
9f022ddf JG |
159 | rdev->mc.vram_start = rdev->mc.vram_location; |
160 | rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; | |
161 | rdev->mc.gtt_start = rdev->mc.gtt_location; | |
162 | rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; | |
3ce0a23d | 163 | DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20)); |
771fe6b9 | 164 | DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", |
3ce0a23d JG |
165 | (unsigned)rdev->mc.vram_location, |
166 | (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1)); | |
167 | DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20)); | |
771fe6b9 | 168 | DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", |
3ce0a23d JG |
169 | (unsigned)rdev->mc.gtt_location, |
170 | (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1)); | |
771fe6b9 JG |
171 | return 0; |
172 | } | |
173 | ||
174 | ||
175 | /* | |
176 | * GPU helpers function. | |
177 | */ | |
9f022ddf | 178 | bool radeon_card_posted(struct radeon_device *rdev) |
771fe6b9 JG |
179 | { |
180 | uint32_t reg; | |
181 | ||
182 | /* first check CRTCs */ | |
183 | if (ASIC_IS_AVIVO(rdev)) { | |
184 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | | |
185 | RREG32(AVIVO_D2CRTC_CONTROL); | |
186 | if (reg & AVIVO_CRTC_EN) { | |
187 | return true; | |
188 | } | |
189 | } else { | |
190 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | | |
191 | RREG32(RADEON_CRTC2_GEN_CNTL); | |
192 | if (reg & RADEON_CRTC_EN) { | |
193 | return true; | |
194 | } | |
195 | } | |
196 | ||
197 | /* then check MEM_SIZE, in case the crtcs are off */ | |
198 | if (rdev->family >= CHIP_R600) | |
199 | reg = RREG32(R600_CONFIG_MEMSIZE); | |
200 | else | |
201 | reg = RREG32(RADEON_CONFIG_MEMSIZE); | |
202 | ||
203 | if (reg) | |
204 | return true; | |
205 | ||
206 | return false; | |
207 | ||
208 | } | |
209 | ||
3ce0a23d JG |
210 | int radeon_dummy_page_init(struct radeon_device *rdev) |
211 | { | |
212 | rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); | |
213 | if (rdev->dummy_page.page == NULL) | |
214 | return -ENOMEM; | |
215 | rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, | |
216 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
217 | if (!rdev->dummy_page.addr) { | |
218 | __free_page(rdev->dummy_page.page); | |
219 | rdev->dummy_page.page = NULL; | |
220 | return -ENOMEM; | |
221 | } | |
222 | return 0; | |
223 | } | |
224 | ||
225 | void radeon_dummy_page_fini(struct radeon_device *rdev) | |
226 | { | |
227 | if (rdev->dummy_page.page == NULL) | |
228 | return; | |
229 | pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, | |
230 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
231 | __free_page(rdev->dummy_page.page); | |
232 | rdev->dummy_page.page = NULL; | |
233 | } | |
234 | ||
771fe6b9 JG |
235 | |
236 | /* | |
237 | * Registers accessors functions. | |
238 | */ | |
239 | uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) | |
240 | { | |
241 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
242 | BUG_ON(1); | |
243 | return 0; | |
244 | } | |
245 | ||
246 | void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
247 | { | |
248 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
249 | reg, v); | |
250 | BUG_ON(1); | |
251 | } | |
252 | ||
253 | void radeon_register_accessor_init(struct radeon_device *rdev) | |
254 | { | |
771fe6b9 JG |
255 | rdev->mc_rreg = &radeon_invalid_rreg; |
256 | rdev->mc_wreg = &radeon_invalid_wreg; | |
257 | rdev->pll_rreg = &radeon_invalid_rreg; | |
258 | rdev->pll_wreg = &radeon_invalid_wreg; | |
771fe6b9 JG |
259 | rdev->pciep_rreg = &radeon_invalid_rreg; |
260 | rdev->pciep_wreg = &radeon_invalid_wreg; | |
261 | ||
262 | /* Don't change order as we are overridding accessor. */ | |
263 | if (rdev->family < CHIP_RV515) { | |
de1b2898 DA |
264 | rdev->pcie_reg_mask = 0xff; |
265 | } else { | |
266 | rdev->pcie_reg_mask = 0x7ff; | |
771fe6b9 JG |
267 | } |
268 | /* FIXME: not sure here */ | |
269 | if (rdev->family <= CHIP_R580) { | |
270 | rdev->pll_rreg = &r100_pll_rreg; | |
271 | rdev->pll_wreg = &r100_pll_wreg; | |
272 | } | |
905b6822 JG |
273 | if (rdev->family >= CHIP_R420) { |
274 | rdev->mc_rreg = &r420_mc_rreg; | |
275 | rdev->mc_wreg = &r420_mc_wreg; | |
276 | } | |
771fe6b9 JG |
277 | if (rdev->family >= CHIP_RV515) { |
278 | rdev->mc_rreg = &rv515_mc_rreg; | |
279 | rdev->mc_wreg = &rv515_mc_wreg; | |
280 | } | |
281 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { | |
282 | rdev->mc_rreg = &rs400_mc_rreg; | |
283 | rdev->mc_wreg = &rs400_mc_wreg; | |
284 | } | |
285 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { | |
286 | rdev->mc_rreg = &rs690_mc_rreg; | |
287 | rdev->mc_wreg = &rs690_mc_wreg; | |
288 | } | |
289 | if (rdev->family == CHIP_RS600) { | |
290 | rdev->mc_rreg = &rs600_mc_rreg; | |
291 | rdev->mc_wreg = &rs600_mc_wreg; | |
292 | } | |
293 | if (rdev->family >= CHIP_R600) { | |
294 | rdev->pciep_rreg = &r600_pciep_rreg; | |
295 | rdev->pciep_wreg = &r600_pciep_wreg; | |
296 | } | |
297 | } | |
298 | ||
299 | ||
300 | /* | |
301 | * ASIC | |
302 | */ | |
303 | int radeon_asic_init(struct radeon_device *rdev) | |
304 | { | |
305 | radeon_register_accessor_init(rdev); | |
306 | switch (rdev->family) { | |
307 | case CHIP_R100: | |
308 | case CHIP_RV100: | |
309 | case CHIP_RS100: | |
310 | case CHIP_RV200: | |
311 | case CHIP_RS200: | |
312 | case CHIP_R200: | |
313 | case CHIP_RV250: | |
314 | case CHIP_RS300: | |
315 | case CHIP_RV280: | |
316 | rdev->asic = &r100_asic; | |
317 | break; | |
318 | case CHIP_R300: | |
319 | case CHIP_R350: | |
320 | case CHIP_RV350: | |
321 | case CHIP_RV380: | |
322 | rdev->asic = &r300_asic; | |
323 | break; | |
324 | case CHIP_R420: | |
325 | case CHIP_R423: | |
326 | case CHIP_RV410: | |
327 | rdev->asic = &r420_asic; | |
328 | break; | |
329 | case CHIP_RS400: | |
330 | case CHIP_RS480: | |
331 | rdev->asic = &rs400_asic; | |
332 | break; | |
333 | case CHIP_RS600: | |
334 | rdev->asic = &rs600_asic; | |
335 | break; | |
336 | case CHIP_RS690: | |
337 | case CHIP_RS740: | |
338 | rdev->asic = &rs690_asic; | |
339 | break; | |
340 | case CHIP_RV515: | |
341 | rdev->asic = &rv515_asic; | |
342 | break; | |
343 | case CHIP_R520: | |
344 | case CHIP_RV530: | |
345 | case CHIP_RV560: | |
346 | case CHIP_RV570: | |
347 | case CHIP_R580: | |
348 | rdev->asic = &r520_asic; | |
349 | break; | |
350 | case CHIP_R600: | |
351 | case CHIP_RV610: | |
352 | case CHIP_RV630: | |
353 | case CHIP_RV620: | |
354 | case CHIP_RV635: | |
355 | case CHIP_RV670: | |
356 | case CHIP_RS780: | |
3ce0a23d JG |
357 | case CHIP_RS880: |
358 | rdev->asic = &r600_asic; | |
359 | break; | |
771fe6b9 JG |
360 | case CHIP_RV770: |
361 | case CHIP_RV730: | |
362 | case CHIP_RV710: | |
3ce0a23d JG |
363 | case CHIP_RV740: |
364 | rdev->asic = &rv770_asic; | |
365 | break; | |
771fe6b9 JG |
366 | default: |
367 | /* FIXME: not supported yet */ | |
368 | return -EINVAL; | |
369 | } | |
370 | return 0; | |
371 | } | |
372 | ||
373 | ||
374 | /* | |
375 | * Wrapper around modesetting bits. | |
376 | */ | |
377 | int radeon_clocks_init(struct radeon_device *rdev) | |
378 | { | |
379 | int r; | |
380 | ||
381 | radeon_get_clock_info(rdev->ddev); | |
382 | r = radeon_static_clocks_init(rdev->ddev); | |
383 | if (r) { | |
384 | return r; | |
385 | } | |
386 | DRM_INFO("Clocks initialized !\n"); | |
387 | return 0; | |
388 | } | |
389 | ||
390 | void radeon_clocks_fini(struct radeon_device *rdev) | |
391 | { | |
392 | } | |
393 | ||
394 | /* ATOM accessor methods */ | |
395 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
396 | { | |
397 | struct radeon_device *rdev = info->dev->dev_private; | |
398 | uint32_t r; | |
399 | ||
400 | r = rdev->pll_rreg(rdev, reg); | |
401 | return r; | |
402 | } | |
403 | ||
404 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
405 | { | |
406 | struct radeon_device *rdev = info->dev->dev_private; | |
407 | ||
408 | rdev->pll_wreg(rdev, reg, val); | |
409 | } | |
410 | ||
411 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
412 | { | |
413 | struct radeon_device *rdev = info->dev->dev_private; | |
414 | uint32_t r; | |
415 | ||
416 | r = rdev->mc_rreg(rdev, reg); | |
417 | return r; | |
418 | } | |
419 | ||
420 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
421 | { | |
422 | struct radeon_device *rdev = info->dev->dev_private; | |
423 | ||
424 | rdev->mc_wreg(rdev, reg, val); | |
425 | } | |
426 | ||
427 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
428 | { | |
429 | struct radeon_device *rdev = info->dev->dev_private; | |
430 | ||
431 | WREG32(reg*4, val); | |
432 | } | |
433 | ||
434 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
435 | { | |
436 | struct radeon_device *rdev = info->dev->dev_private; | |
437 | uint32_t r; | |
438 | ||
439 | r = RREG32(reg*4); | |
440 | return r; | |
441 | } | |
442 | ||
443 | static struct card_info atom_card_info = { | |
444 | .dev = NULL, | |
445 | .reg_read = cail_reg_read, | |
446 | .reg_write = cail_reg_write, | |
447 | .mc_read = cail_mc_read, | |
448 | .mc_write = cail_mc_write, | |
449 | .pll_read = cail_pll_read, | |
450 | .pll_write = cail_pll_write, | |
451 | }; | |
452 | ||
453 | int radeon_atombios_init(struct radeon_device *rdev) | |
454 | { | |
455 | atom_card_info.dev = rdev->ddev; | |
456 | rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios); | |
457 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); | |
458 | return 0; | |
459 | } | |
460 | ||
461 | void radeon_atombios_fini(struct radeon_device *rdev) | |
462 | { | |
463 | kfree(rdev->mode_info.atom_context); | |
464 | } | |
465 | ||
466 | int radeon_combios_init(struct radeon_device *rdev) | |
467 | { | |
468 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); | |
469 | return 0; | |
470 | } | |
471 | ||
472 | void radeon_combios_fini(struct radeon_device *rdev) | |
473 | { | |
474 | } | |
475 | ||
771fe6b9 JG |
476 | |
477 | /* | |
478 | * Radeon device. | |
479 | */ | |
480 | int radeon_device_init(struct radeon_device *rdev, | |
481 | struct drm_device *ddev, | |
482 | struct pci_dev *pdev, | |
483 | uint32_t flags) | |
484 | { | |
6cf8a3f5 | 485 | int r; |
ad49f501 | 486 | int dma_bits; |
771fe6b9 JG |
487 | |
488 | DRM_INFO("radeon: Initializing kernel modesetting.\n"); | |
489 | rdev->shutdown = false; | |
9f022ddf | 490 | rdev->dev = &pdev->dev; |
771fe6b9 JG |
491 | rdev->ddev = ddev; |
492 | rdev->pdev = pdev; | |
493 | rdev->flags = flags; | |
494 | rdev->family = flags & RADEON_FAMILY_MASK; | |
495 | rdev->is_atom_bios = false; | |
496 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; | |
497 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
498 | rdev->gpu_lockup = false; | |
499 | /* mutex initialization are all done here so we | |
500 | * can recall function without having locking issues */ | |
501 | mutex_init(&rdev->cs_mutex); | |
502 | mutex_init(&rdev->ib_pool.mutex); | |
503 | mutex_init(&rdev->cp.mutex); | |
504 | rwlock_init(&rdev->fence_drv.lock); | |
9f022ddf | 505 | INIT_LIST_HEAD(&rdev->gem.objects); |
771fe6b9 JG |
506 | |
507 | if (radeon_agpmode == -1) { | |
508 | rdev->flags &= ~RADEON_IS_AGP; | |
c000273e | 509 | if (rdev->family >= CHIP_RV515 || |
771fe6b9 JG |
510 | rdev->family == CHIP_RV380 || |
511 | rdev->family == CHIP_RV410 || | |
512 | rdev->family == CHIP_R423) { | |
513 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
514 | rdev->flags |= RADEON_IS_PCIE; | |
515 | } else { | |
516 | DRM_INFO("Forcing AGP to PCI mode\n"); | |
517 | rdev->flags |= RADEON_IS_PCI; | |
518 | } | |
519 | } | |
520 | ||
521 | /* Set asic functions */ | |
522 | r = radeon_asic_init(rdev); | |
523 | if (r) { | |
524 | return r; | |
525 | } | |
526 | ||
ad49f501 DA |
527 | /* set DMA mask + need_dma32 flags. |
528 | * PCIE - can handle 40-bits. | |
529 | * IGP - can handle 40-bits (in theory) | |
530 | * AGP - generally dma32 is safest | |
531 | * PCI - only dma32 | |
532 | */ | |
533 | rdev->need_dma32 = false; | |
534 | if (rdev->flags & RADEON_IS_AGP) | |
535 | rdev->need_dma32 = true; | |
536 | if (rdev->flags & RADEON_IS_PCI) | |
537 | rdev->need_dma32 = true; | |
538 | ||
539 | dma_bits = rdev->need_dma32 ? 32 : 40; | |
540 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); | |
771fe6b9 JG |
541 | if (r) { |
542 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); | |
543 | } | |
544 | ||
545 | /* Registers mapping */ | |
546 | /* TODO: block userspace mapping of io register */ | |
547 | rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2); | |
548 | rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2); | |
549 | rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); | |
550 | if (rdev->rmmio == NULL) { | |
551 | return -ENOMEM; | |
552 | } | |
553 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); | |
554 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); | |
555 | ||
3ce0a23d JG |
556 | rdev->new_init_path = false; |
557 | r = radeon_init(rdev); | |
558 | if (r) { | |
559 | return r; | |
560 | } | |
561 | if (!rdev->new_init_path) { | |
562 | /* Setup errata flags */ | |
563 | radeon_errata(rdev); | |
564 | /* Initialize scratch registers */ | |
565 | radeon_scratch_init(rdev); | |
566 | /* Initialize surface registers */ | |
567 | radeon_surface_init(rdev); | |
568 | ||
569 | /* TODO: disable VGA need to use VGA request */ | |
570 | /* BIOS*/ | |
571 | if (!radeon_get_bios(rdev)) { | |
572 | if (ASIC_IS_AVIVO(rdev)) | |
573 | return -EINVAL; | |
574 | } | |
575 | if (rdev->is_atom_bios) { | |
576 | r = radeon_atombios_init(rdev); | |
577 | if (r) { | |
578 | return r; | |
579 | } | |
580 | } else { | |
581 | r = radeon_combios_init(rdev); | |
582 | if (r) { | |
583 | return r; | |
584 | } | |
585 | } | |
586 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
587 | if (radeon_gpu_reset(rdev)) { | |
588 | /* FIXME: what do we want to do here ? */ | |
589 | } | |
590 | /* check if cards are posted or not */ | |
591 | if (!radeon_card_posted(rdev) && rdev->bios) { | |
592 | DRM_INFO("GPU not posted. posting now...\n"); | |
593 | if (rdev->is_atom_bios) { | |
594 | atom_asic_init(rdev->mode_info.atom_context); | |
595 | } else { | |
596 | radeon_combios_asic_init(rdev->ddev); | |
597 | } | |
598 | } | |
599 | /* Initialize clocks */ | |
600 | r = radeon_clocks_init(rdev); | |
771fe6b9 JG |
601 | if (r) { |
602 | return r; | |
603 | } | |
3ce0a23d JG |
604 | /* Get vram informations */ |
605 | radeon_vram_info(rdev); | |
606 | ||
3ce0a23d JG |
607 | /* Initialize memory controller (also test AGP) */ |
608 | r = radeon_mc_init(rdev); | |
771fe6b9 JG |
609 | if (r) { |
610 | return r; | |
611 | } | |
3ce0a23d JG |
612 | /* Fence driver */ |
613 | r = radeon_fence_driver_init(rdev); | |
771fe6b9 | 614 | if (r) { |
771fe6b9 JG |
615 | return r; |
616 | } | |
3ce0a23d | 617 | r = radeon_irq_kms_init(rdev); |
771fe6b9 | 618 | if (r) { |
771fe6b9 JG |
619 | return r; |
620 | } | |
3ce0a23d JG |
621 | /* Memory manager */ |
622 | r = radeon_object_init(rdev); | |
771fe6b9 | 623 | if (r) { |
771fe6b9 JG |
624 | return r; |
625 | } | |
3ce0a23d JG |
626 | /* Initialize GART (initialize after TTM so we can allocate |
627 | * memory through TTM but finalize after TTM) */ | |
628 | r = radeon_gart_enable(rdev); | |
629 | if (!r) { | |
630 | r = radeon_gem_init(rdev); | |
631 | } | |
632 | ||
633 | /* 1M ring buffer */ | |
634 | if (!r) { | |
635 | r = radeon_cp_init(rdev, 1024 * 1024); | |
636 | } | |
637 | if (!r) { | |
638 | r = radeon_wb_init(rdev); | |
639 | if (r) { | |
640 | DRM_ERROR("radeon: failled initializing WB (%d).\n", r); | |
641 | return r; | |
642 | } | |
643 | } | |
644 | if (!r) { | |
645 | r = radeon_ib_pool_init(rdev); | |
646 | if (r) { | |
647 | DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); | |
648 | return r; | |
649 | } | |
650 | } | |
651 | if (!r) { | |
652 | r = radeon_ib_test(rdev); | |
653 | if (r) { | |
654 | DRM_ERROR("radeon: failled testing IB (%d).\n", r); | |
655 | return r; | |
656 | } | |
657 | } | |
771fe6b9 | 658 | } |
6cf8a3f5 | 659 | DRM_INFO("radeon: kernel modesetting successfully initialized.\n"); |
ecc0b326 MD |
660 | if (radeon_testing) { |
661 | radeon_test_moves(rdev); | |
662 | } | |
771fe6b9 JG |
663 | if (radeon_benchmarking) { |
664 | radeon_benchmark(rdev); | |
665 | } | |
6cf8a3f5 | 666 | return 0; |
771fe6b9 JG |
667 | } |
668 | ||
669 | void radeon_device_fini(struct radeon_device *rdev) | |
670 | { | |
771fe6b9 JG |
671 | DRM_INFO("radeon: finishing device.\n"); |
672 | rdev->shutdown = true; | |
673 | /* Order matter so becarefull if you rearrange anythings */ | |
3ce0a23d JG |
674 | if (!rdev->new_init_path) { |
675 | radeon_ib_pool_fini(rdev); | |
676 | radeon_cp_fini(rdev); | |
677 | radeon_wb_fini(rdev); | |
678 | radeon_gem_fini(rdev); | |
679 | radeon_mc_fini(rdev); | |
771fe6b9 | 680 | #if __OS_HAS_AGP |
3ce0a23d | 681 | radeon_agp_fini(rdev); |
771fe6b9 | 682 | #endif |
3ce0a23d JG |
683 | radeon_irq_kms_fini(rdev); |
684 | radeon_fence_driver_fini(rdev); | |
685 | radeon_clocks_fini(rdev); | |
686 | radeon_object_fini(rdev); | |
687 | if (rdev->is_atom_bios) { | |
688 | radeon_atombios_fini(rdev); | |
689 | } else { | |
690 | radeon_combios_fini(rdev); | |
691 | } | |
692 | kfree(rdev->bios); | |
693 | rdev->bios = NULL; | |
771fe6b9 | 694 | } else { |
3ce0a23d | 695 | radeon_fini(rdev); |
771fe6b9 | 696 | } |
771fe6b9 JG |
697 | iounmap(rdev->rmmio); |
698 | rdev->rmmio = NULL; | |
699 | } | |
700 | ||
701 | ||
702 | /* | |
703 | * Suspend & resume. | |
704 | */ | |
705 | int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) | |
706 | { | |
707 | struct radeon_device *rdev = dev->dev_private; | |
708 | struct drm_crtc *crtc; | |
709 | ||
710 | if (dev == NULL || rdev == NULL) { | |
711 | return -ENODEV; | |
712 | } | |
713 | if (state.event == PM_EVENT_PRETHAW) { | |
714 | return 0; | |
715 | } | |
716 | /* unpin the front buffers */ | |
717 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
718 | struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); | |
719 | struct radeon_object *robj; | |
720 | ||
721 | if (rfb == NULL || rfb->obj == NULL) { | |
722 | continue; | |
723 | } | |
724 | robj = rfb->obj->driver_private; | |
725 | if (robj != rdev->fbdev_robj) { | |
726 | radeon_object_unpin(robj); | |
727 | } | |
728 | } | |
729 | /* evict vram memory */ | |
730 | radeon_object_evict_vram(rdev); | |
731 | /* wait for gpu to finish processing current batch */ | |
732 | radeon_fence_wait_last(rdev); | |
733 | ||
3ce0a23d JG |
734 | if (!rdev->new_init_path) { |
735 | radeon_cp_disable(rdev); | |
736 | radeon_gart_disable(rdev); | |
9f022ddf JG |
737 | rdev->irq.sw_int = false; |
738 | radeon_irq_set(rdev); | |
3ce0a23d JG |
739 | } else { |
740 | radeon_suspend(rdev); | |
741 | } | |
771fe6b9 JG |
742 | /* evict remaining vram memory */ |
743 | radeon_object_evict_vram(rdev); | |
744 | ||
771fe6b9 JG |
745 | pci_save_state(dev->pdev); |
746 | if (state.event == PM_EVENT_SUSPEND) { | |
747 | /* Shut down the device */ | |
748 | pci_disable_device(dev->pdev); | |
749 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
750 | } | |
751 | acquire_console_sem(); | |
752 | fb_set_suspend(rdev->fbdev_info, 1); | |
753 | release_console_sem(); | |
754 | return 0; | |
755 | } | |
756 | ||
757 | int radeon_resume_kms(struct drm_device *dev) | |
758 | { | |
759 | struct radeon_device *rdev = dev->dev_private; | |
760 | int r; | |
761 | ||
762 | acquire_console_sem(); | |
763 | pci_set_power_state(dev->pdev, PCI_D0); | |
764 | pci_restore_state(dev->pdev); | |
765 | if (pci_enable_device(dev->pdev)) { | |
766 | release_console_sem(); | |
767 | return -1; | |
768 | } | |
769 | pci_set_master(dev->pdev); | |
770 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
3ce0a23d | 771 | if (!rdev->new_init_path) { |
9f022ddf JG |
772 | if (radeon_gpu_reset(rdev)) { |
773 | /* FIXME: what do we want to do here ? */ | |
774 | } | |
3ce0a23d JG |
775 | /* post card */ |
776 | if (rdev->is_atom_bios) { | |
777 | atom_asic_init(rdev->mode_info.atom_context); | |
778 | } else { | |
779 | radeon_combios_asic_init(rdev->ddev); | |
780 | } | |
781 | /* Initialize clocks */ | |
782 | r = radeon_clocks_init(rdev); | |
783 | if (r) { | |
784 | release_console_sem(); | |
785 | return r; | |
786 | } | |
787 | /* Enable IRQ */ | |
788 | rdev->irq.sw_int = true; | |
789 | radeon_irq_set(rdev); | |
790 | /* Initialize GPU Memory Controller */ | |
791 | r = radeon_mc_init(rdev); | |
792 | if (r) { | |
793 | goto out; | |
794 | } | |
795 | r = radeon_gart_enable(rdev); | |
796 | if (r) { | |
797 | goto out; | |
798 | } | |
799 | r = radeon_cp_init(rdev, rdev->cp.ring_size); | |
800 | if (r) { | |
801 | goto out; | |
802 | } | |
771fe6b9 | 803 | } else { |
3ce0a23d | 804 | radeon_resume(rdev); |
771fe6b9 JG |
805 | } |
806 | out: | |
807 | fb_set_suspend(rdev->fbdev_info, 0); | |
808 | release_console_sem(); | |
809 | ||
810 | /* blat the mode back in */ | |
811 | drm_helper_resume_force_mode(dev); | |
812 | return 0; | |
813 | } | |
814 | ||
815 | ||
816 | /* | |
817 | * Debugfs | |
818 | */ | |
819 | struct radeon_debugfs { | |
820 | struct drm_info_list *files; | |
821 | unsigned num_files; | |
822 | }; | |
823 | static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES]; | |
824 | static unsigned _radeon_debugfs_count = 0; | |
825 | ||
826 | int radeon_debugfs_add_files(struct radeon_device *rdev, | |
827 | struct drm_info_list *files, | |
828 | unsigned nfiles) | |
829 | { | |
830 | unsigned i; | |
831 | ||
832 | for (i = 0; i < _radeon_debugfs_count; i++) { | |
833 | if (_radeon_debugfs[i].files == files) { | |
834 | /* Already registered */ | |
835 | return 0; | |
836 | } | |
837 | } | |
838 | if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) { | |
839 | DRM_ERROR("Reached maximum number of debugfs files.\n"); | |
840 | DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n"); | |
841 | return -EINVAL; | |
842 | } | |
843 | _radeon_debugfs[_radeon_debugfs_count].files = files; | |
844 | _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles; | |
845 | _radeon_debugfs_count++; | |
846 | #if defined(CONFIG_DEBUG_FS) | |
847 | drm_debugfs_create_files(files, nfiles, | |
848 | rdev->ddev->control->debugfs_root, | |
849 | rdev->ddev->control); | |
850 | drm_debugfs_create_files(files, nfiles, | |
851 | rdev->ddev->primary->debugfs_root, | |
852 | rdev->ddev->primary); | |
853 | #endif | |
854 | return 0; | |
855 | } | |
856 | ||
857 | #if defined(CONFIG_DEBUG_FS) | |
858 | int radeon_debugfs_init(struct drm_minor *minor) | |
859 | { | |
860 | return 0; | |
861 | } | |
862 | ||
863 | void radeon_debugfs_cleanup(struct drm_minor *minor) | |
864 | { | |
865 | unsigned i; | |
866 | ||
867 | for (i = 0; i < _radeon_debugfs_count; i++) { | |
868 | drm_debugfs_remove_files(_radeon_debugfs[i].files, | |
869 | _radeon_debugfs[i].num_files, minor); | |
870 | } | |
871 | } | |
872 | #endif |