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Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/console.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
771fe6b9 JG |
30 | #include <drm/drmP.h> |
31 | #include <drm/drm_crtc_helper.h> | |
32 | #include <drm/radeon_drm.h> | |
28d52043 | 33 | #include <linux/vgaarb.h> |
6a9ee8af | 34 | #include <linux/vga_switcheroo.h> |
771fe6b9 JG |
35 | #include "radeon_reg.h" |
36 | #include "radeon.h" | |
771fe6b9 JG |
37 | #include "atom.h" |
38 | ||
1b5331d9 JG |
39 | static const char radeon_family_name[][16] = { |
40 | "R100", | |
41 | "RV100", | |
42 | "RS100", | |
43 | "RV200", | |
44 | "RS200", | |
45 | "R200", | |
46 | "RV250", | |
47 | "RS300", | |
48 | "RV280", | |
49 | "R300", | |
50 | "R350", | |
51 | "RV350", | |
52 | "RV380", | |
53 | "R420", | |
54 | "R423", | |
55 | "RV410", | |
56 | "RS400", | |
57 | "RS480", | |
58 | "RS600", | |
59 | "RS690", | |
60 | "RS740", | |
61 | "RV515", | |
62 | "R520", | |
63 | "RV530", | |
64 | "RV560", | |
65 | "RV570", | |
66 | "R580", | |
67 | "R600", | |
68 | "RV610", | |
69 | "RV630", | |
70 | "RV670", | |
71 | "RV620", | |
72 | "RV635", | |
73 | "RS780", | |
74 | "RS880", | |
75 | "RV770", | |
76 | "RV730", | |
77 | "RV710", | |
78 | "RV740", | |
79 | "CEDAR", | |
80 | "REDWOOD", | |
81 | "JUNIPER", | |
82 | "CYPRESS", | |
83 | "HEMLOCK", | |
b08ebe7e | 84 | "PALM", |
4df64e65 AD |
85 | "SUMO", |
86 | "SUMO2", | |
1fe18305 AD |
87 | "BARTS", |
88 | "TURKS", | |
89 | "CAICOS", | |
b7cfc9fe | 90 | "CAYMAN", |
1b5331d9 JG |
91 | "LAST", |
92 | }; | |
93 | ||
b1e3a6d1 MD |
94 | /* |
95 | * Clear GPU surface registers. | |
96 | */ | |
3ce0a23d | 97 | void radeon_surface_init(struct radeon_device *rdev) |
b1e3a6d1 MD |
98 | { |
99 | /* FIXME: check this out */ | |
100 | if (rdev->family < CHIP_R600) { | |
101 | int i; | |
102 | ||
550e2d92 DA |
103 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
104 | if (rdev->surface_regs[i].bo) | |
105 | radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); | |
106 | else | |
107 | radeon_clear_surface_reg(rdev, i); | |
b1e3a6d1 | 108 | } |
e024e110 DA |
109 | /* enable surfaces */ |
110 | WREG32(RADEON_SURFACE_CNTL, 0); | |
b1e3a6d1 MD |
111 | } |
112 | } | |
113 | ||
771fe6b9 JG |
114 | /* |
115 | * GPU scratch registers helpers function. | |
116 | */ | |
3ce0a23d | 117 | void radeon_scratch_init(struct radeon_device *rdev) |
771fe6b9 JG |
118 | { |
119 | int i; | |
120 | ||
121 | /* FIXME: check this out */ | |
122 | if (rdev->family < CHIP_R300) { | |
123 | rdev->scratch.num_reg = 5; | |
124 | } else { | |
125 | rdev->scratch.num_reg = 7; | |
126 | } | |
724c80e1 | 127 | rdev->scratch.reg_base = RADEON_SCRATCH_REG0; |
771fe6b9 JG |
128 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
129 | rdev->scratch.free[i] = true; | |
724c80e1 | 130 | rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); |
771fe6b9 JG |
131 | } |
132 | } | |
133 | ||
134 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) | |
135 | { | |
136 | int i; | |
137 | ||
138 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
139 | if (rdev->scratch.free[i]) { | |
140 | rdev->scratch.free[i] = false; | |
141 | *reg = rdev->scratch.reg[i]; | |
142 | return 0; | |
143 | } | |
144 | } | |
145 | return -EINVAL; | |
146 | } | |
147 | ||
148 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) | |
149 | { | |
150 | int i; | |
151 | ||
152 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
153 | if (rdev->scratch.reg[i] == reg) { | |
154 | rdev->scratch.free[i] = true; | |
155 | return; | |
156 | } | |
157 | } | |
158 | } | |
159 | ||
724c80e1 AD |
160 | void radeon_wb_disable(struct radeon_device *rdev) |
161 | { | |
162 | int r; | |
163 | ||
164 | if (rdev->wb.wb_obj) { | |
165 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); | |
166 | if (unlikely(r != 0)) | |
167 | return; | |
168 | radeon_bo_kunmap(rdev->wb.wb_obj); | |
169 | radeon_bo_unpin(rdev->wb.wb_obj); | |
170 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
171 | } | |
172 | rdev->wb.enabled = false; | |
173 | } | |
174 | ||
175 | void radeon_wb_fini(struct radeon_device *rdev) | |
176 | { | |
177 | radeon_wb_disable(rdev); | |
178 | if (rdev->wb.wb_obj) { | |
179 | radeon_bo_unref(&rdev->wb.wb_obj); | |
180 | rdev->wb.wb = NULL; | |
181 | rdev->wb.wb_obj = NULL; | |
182 | } | |
183 | } | |
184 | ||
185 | int radeon_wb_init(struct radeon_device *rdev) | |
186 | { | |
187 | int r; | |
188 | ||
189 | if (rdev->wb.wb_obj == NULL) { | |
441921d5 | 190 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, |
724c80e1 AD |
191 | RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj); |
192 | if (r) { | |
193 | dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); | |
194 | return r; | |
195 | } | |
196 | } | |
197 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); | |
198 | if (unlikely(r != 0)) { | |
199 | radeon_wb_fini(rdev); | |
200 | return r; | |
201 | } | |
202 | r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, | |
203 | &rdev->wb.gpu_addr); | |
204 | if (r) { | |
205 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
206 | dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); | |
207 | radeon_wb_fini(rdev); | |
208 | return r; | |
209 | } | |
210 | r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); | |
211 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
212 | if (r) { | |
213 | dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); | |
214 | radeon_wb_fini(rdev); | |
215 | return r; | |
216 | } | |
217 | ||
d0f8a854 AD |
218 | /* disable event_write fences */ |
219 | rdev->wb.use_event = false; | |
724c80e1 AD |
220 | /* disabled via module param */ |
221 | if (radeon_no_wb == 1) | |
222 | rdev->wb.enabled = false; | |
223 | else { | |
224 | /* often unreliable on AGP */ | |
225 | if (rdev->flags & RADEON_IS_AGP) { | |
226 | rdev->wb.enabled = false; | |
d0f8a854 | 227 | } else { |
724c80e1 | 228 | rdev->wb.enabled = true; |
d0f8a854 AD |
229 | /* event_write fences are only available on r600+ */ |
230 | if (rdev->family >= CHIP_R600) | |
231 | rdev->wb.use_event = true; | |
232 | } | |
724c80e1 | 233 | } |
7d52785d AD |
234 | /* always use writeback/events on NI */ |
235 | if (ASIC_IS_DCE5(rdev)) { | |
236 | rdev->wb.enabled = true; | |
237 | rdev->wb.use_event = true; | |
238 | } | |
724c80e1 AD |
239 | |
240 | dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
d594e46a JG |
245 | /** |
246 | * radeon_vram_location - try to find VRAM location | |
247 | * @rdev: radeon device structure holding all necessary informations | |
248 | * @mc: memory controller structure holding memory informations | |
249 | * @base: base address at which to put VRAM | |
250 | * | |
251 | * Function will place try to place VRAM at base address provided | |
252 | * as parameter (which is so far either PCI aperture address or | |
253 | * for IGP TOM base address). | |
254 | * | |
255 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
256 | * address space then we limit the VRAM size to the aperture. | |
257 | * | |
258 | * If we are using AGP and if the AGP aperture doesn't allow us to have | |
259 | * room for all the VRAM than we restrict the VRAM to the PCI aperture | |
260 | * size and print a warning. | |
261 | * | |
262 | * This function will never fails, worst case are limiting VRAM. | |
263 | * | |
264 | * Note: GTT start, end, size should be initialized before calling this | |
265 | * function on AGP platform. | |
266 | * | |
25985edc | 267 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, |
d594e46a JG |
268 | * this shouldn't be a problem as we are using the PCI aperture as a reference. |
269 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
270 | * not IGP. | |
271 | * | |
272 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
273 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
274 | * Novell bug 204882 + along with lots of ubuntu ones | |
275 | * | |
276 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
277 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
278 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
279 | * ones) | |
280 | * | |
281 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
282 | * explicitly check for that thought. | |
283 | * | |
284 | * FIXME: when reducing VRAM size align new size on power of 2. | |
771fe6b9 | 285 | */ |
d594e46a | 286 | void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
771fe6b9 | 287 | { |
d594e46a JG |
288 | mc->vram_start = base; |
289 | if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { | |
290 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); | |
291 | mc->real_vram_size = mc->aper_size; | |
292 | mc->mc_vram_size = mc->aper_size; | |
293 | } | |
294 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
2cbeb4ef | 295 | if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { |
d594e46a JG |
296 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
297 | mc->real_vram_size = mc->aper_size; | |
298 | mc->mc_vram_size = mc->aper_size; | |
299 | } | |
300 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
dd7cc55a | 301 | dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", |
d594e46a JG |
302 | mc->mc_vram_size >> 20, mc->vram_start, |
303 | mc->vram_end, mc->real_vram_size >> 20); | |
304 | } | |
771fe6b9 | 305 | |
d594e46a JG |
306 | /** |
307 | * radeon_gtt_location - try to find GTT location | |
308 | * @rdev: radeon device structure holding all necessary informations | |
309 | * @mc: memory controller structure holding memory informations | |
310 | * | |
311 | * Function will place try to place GTT before or after VRAM. | |
312 | * | |
313 | * If GTT size is bigger than space left then we ajust GTT size. | |
314 | * Thus function will never fails. | |
315 | * | |
316 | * FIXME: when reducing GTT size align new size on power of 2. | |
317 | */ | |
318 | void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) | |
319 | { | |
320 | u64 size_af, size_bf; | |
321 | ||
8d369bb1 AD |
322 | size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; |
323 | size_bf = mc->vram_start & ~mc->gtt_base_align; | |
d594e46a JG |
324 | if (size_bf > size_af) { |
325 | if (mc->gtt_size > size_bf) { | |
326 | dev_warn(rdev->dev, "limiting GTT\n"); | |
327 | mc->gtt_size = size_bf; | |
771fe6b9 | 328 | } |
8d369bb1 | 329 | mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; |
771fe6b9 | 330 | } else { |
d594e46a JG |
331 | if (mc->gtt_size > size_af) { |
332 | dev_warn(rdev->dev, "limiting GTT\n"); | |
333 | mc->gtt_size = size_af; | |
334 | } | |
8d369bb1 | 335 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; |
771fe6b9 | 336 | } |
d594e46a | 337 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; |
dd7cc55a | 338 | dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", |
d594e46a | 339 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); |
771fe6b9 JG |
340 | } |
341 | ||
771fe6b9 JG |
342 | /* |
343 | * GPU helpers function. | |
344 | */ | |
9f022ddf | 345 | bool radeon_card_posted(struct radeon_device *rdev) |
771fe6b9 JG |
346 | { |
347 | uint32_t reg; | |
348 | ||
349 | /* first check CRTCs */ | |
18007401 AD |
350 | if (ASIC_IS_DCE41(rdev)) { |
351 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | | |
352 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); | |
353 | if (reg & EVERGREEN_CRTC_MASTER_EN) | |
354 | return true; | |
355 | } else if (ASIC_IS_DCE4(rdev)) { | |
bcc1c2a1 AD |
356 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
357 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | | |
358 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | | |
359 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | | |
360 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | | |
361 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); | |
362 | if (reg & EVERGREEN_CRTC_MASTER_EN) | |
363 | return true; | |
364 | } else if (ASIC_IS_AVIVO(rdev)) { | |
771fe6b9 JG |
365 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
366 | RREG32(AVIVO_D2CRTC_CONTROL); | |
367 | if (reg & AVIVO_CRTC_EN) { | |
368 | return true; | |
369 | } | |
370 | } else { | |
371 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | | |
372 | RREG32(RADEON_CRTC2_GEN_CNTL); | |
373 | if (reg & RADEON_CRTC_EN) { | |
374 | return true; | |
375 | } | |
376 | } | |
377 | ||
378 | /* then check MEM_SIZE, in case the crtcs are off */ | |
379 | if (rdev->family >= CHIP_R600) | |
380 | reg = RREG32(R600_CONFIG_MEMSIZE); | |
381 | else | |
382 | reg = RREG32(RADEON_CONFIG_MEMSIZE); | |
383 | ||
384 | if (reg) | |
385 | return true; | |
386 | ||
387 | return false; | |
388 | ||
389 | } | |
390 | ||
f47299c5 AD |
391 | void radeon_update_bandwidth_info(struct radeon_device *rdev) |
392 | { | |
393 | fixed20_12 a; | |
8807286e AD |
394 | u32 sclk = rdev->pm.current_sclk; |
395 | u32 mclk = rdev->pm.current_mclk; | |
f47299c5 | 396 | |
8807286e AD |
397 | /* sclk/mclk in Mhz */ |
398 | a.full = dfixed_const(100); | |
399 | rdev->pm.sclk.full = dfixed_const(sclk); | |
400 | rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); | |
401 | rdev->pm.mclk.full = dfixed_const(mclk); | |
402 | rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); | |
f47299c5 | 403 | |
8807286e | 404 | if (rdev->flags & RADEON_IS_IGP) { |
68adac5e | 405 | a.full = dfixed_const(16); |
f47299c5 | 406 | /* core_bandwidth = sclk(Mhz) * 16 */ |
68adac5e | 407 | rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); |
f47299c5 AD |
408 | } |
409 | } | |
410 | ||
72542d77 DA |
411 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
412 | { | |
413 | if (radeon_card_posted(rdev)) | |
414 | return true; | |
415 | ||
416 | if (rdev->bios) { | |
417 | DRM_INFO("GPU not posted. posting now...\n"); | |
418 | if (rdev->is_atom_bios) | |
419 | atom_asic_init(rdev->mode_info.atom_context); | |
420 | else | |
421 | radeon_combios_asic_init(rdev->ddev); | |
422 | return true; | |
423 | } else { | |
424 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); | |
425 | return false; | |
426 | } | |
427 | } | |
428 | ||
3ce0a23d JG |
429 | int radeon_dummy_page_init(struct radeon_device *rdev) |
430 | { | |
82568565 DA |
431 | if (rdev->dummy_page.page) |
432 | return 0; | |
3ce0a23d JG |
433 | rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); |
434 | if (rdev->dummy_page.page == NULL) | |
435 | return -ENOMEM; | |
436 | rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, | |
437 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
a30f6fb7 BH |
438 | if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) { |
439 | dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
3ce0a23d JG |
440 | __free_page(rdev->dummy_page.page); |
441 | rdev->dummy_page.page = NULL; | |
442 | return -ENOMEM; | |
443 | } | |
444 | return 0; | |
445 | } | |
446 | ||
447 | void radeon_dummy_page_fini(struct radeon_device *rdev) | |
448 | { | |
449 | if (rdev->dummy_page.page == NULL) | |
450 | return; | |
451 | pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, | |
452 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
453 | __free_page(rdev->dummy_page.page); | |
454 | rdev->dummy_page.page = NULL; | |
455 | } | |
456 | ||
771fe6b9 | 457 | |
771fe6b9 JG |
458 | /* ATOM accessor methods */ |
459 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
460 | { | |
461 | struct radeon_device *rdev = info->dev->dev_private; | |
462 | uint32_t r; | |
463 | ||
464 | r = rdev->pll_rreg(rdev, reg); | |
465 | return r; | |
466 | } | |
467 | ||
468 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
469 | { | |
470 | struct radeon_device *rdev = info->dev->dev_private; | |
471 | ||
472 | rdev->pll_wreg(rdev, reg, val); | |
473 | } | |
474 | ||
475 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
476 | { | |
477 | struct radeon_device *rdev = info->dev->dev_private; | |
478 | uint32_t r; | |
479 | ||
480 | r = rdev->mc_rreg(rdev, reg); | |
481 | return r; | |
482 | } | |
483 | ||
484 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
485 | { | |
486 | struct radeon_device *rdev = info->dev->dev_private; | |
487 | ||
488 | rdev->mc_wreg(rdev, reg, val); | |
489 | } | |
490 | ||
491 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
492 | { | |
493 | struct radeon_device *rdev = info->dev->dev_private; | |
494 | ||
495 | WREG32(reg*4, val); | |
496 | } | |
497 | ||
498 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
499 | { | |
500 | struct radeon_device *rdev = info->dev->dev_private; | |
501 | uint32_t r; | |
502 | ||
503 | r = RREG32(reg*4); | |
504 | return r; | |
505 | } | |
506 | ||
351a52a2 AD |
507 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) |
508 | { | |
509 | struct radeon_device *rdev = info->dev->dev_private; | |
510 | ||
511 | WREG32_IO(reg*4, val); | |
512 | } | |
513 | ||
514 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
515 | { | |
516 | struct radeon_device *rdev = info->dev->dev_private; | |
517 | uint32_t r; | |
518 | ||
519 | r = RREG32_IO(reg*4); | |
520 | return r; | |
521 | } | |
522 | ||
771fe6b9 JG |
523 | int radeon_atombios_init(struct radeon_device *rdev) |
524 | { | |
61c4b24b MF |
525 | struct card_info *atom_card_info = |
526 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
527 | ||
528 | if (!atom_card_info) | |
529 | return -ENOMEM; | |
530 | ||
531 | rdev->mode_info.atom_card_info = atom_card_info; | |
532 | atom_card_info->dev = rdev->ddev; | |
533 | atom_card_info->reg_read = cail_reg_read; | |
534 | atom_card_info->reg_write = cail_reg_write; | |
351a52a2 AD |
535 | /* needed for iio ops */ |
536 | if (rdev->rio_mem) { | |
537 | atom_card_info->ioreg_read = cail_ioreg_read; | |
538 | atom_card_info->ioreg_write = cail_ioreg_write; | |
539 | } else { | |
540 | DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); | |
541 | atom_card_info->ioreg_read = cail_reg_read; | |
542 | atom_card_info->ioreg_write = cail_reg_write; | |
543 | } | |
61c4b24b MF |
544 | atom_card_info->mc_read = cail_mc_read; |
545 | atom_card_info->mc_write = cail_mc_write; | |
546 | atom_card_info->pll_read = cail_pll_read; | |
547 | atom_card_info->pll_write = cail_pll_write; | |
548 | ||
549 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); | |
c31ad97f | 550 | mutex_init(&rdev->mode_info.atom_context->mutex); |
771fe6b9 | 551 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
d904ef9b | 552 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
771fe6b9 JG |
553 | return 0; |
554 | } | |
555 | ||
556 | void radeon_atombios_fini(struct radeon_device *rdev) | |
557 | { | |
4a04a844 JG |
558 | if (rdev->mode_info.atom_context) { |
559 | kfree(rdev->mode_info.atom_context->scratch); | |
560 | kfree(rdev->mode_info.atom_context); | |
561 | } | |
61c4b24b | 562 | kfree(rdev->mode_info.atom_card_info); |
771fe6b9 JG |
563 | } |
564 | ||
565 | int radeon_combios_init(struct radeon_device *rdev) | |
566 | { | |
567 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); | |
568 | return 0; | |
569 | } | |
570 | ||
571 | void radeon_combios_fini(struct radeon_device *rdev) | |
572 | { | |
573 | } | |
574 | ||
28d52043 DA |
575 | /* if we get transitioned to only one device, tak VGA back */ |
576 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) | |
577 | { | |
578 | struct radeon_device *rdev = cookie; | |
28d52043 DA |
579 | radeon_vga_set_state(rdev, state); |
580 | if (state) | |
581 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
582 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
583 | else | |
584 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
585 | } | |
c1176d6f | 586 | |
36421338 JG |
587 | void radeon_check_arguments(struct radeon_device *rdev) |
588 | { | |
589 | /* vramlimit must be a power of two */ | |
590 | switch (radeon_vram_limit) { | |
591 | case 0: | |
592 | case 4: | |
593 | case 8: | |
594 | case 16: | |
595 | case 32: | |
596 | case 64: | |
597 | case 128: | |
598 | case 256: | |
599 | case 512: | |
600 | case 1024: | |
601 | case 2048: | |
602 | case 4096: | |
603 | break; | |
604 | default: | |
605 | dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", | |
606 | radeon_vram_limit); | |
607 | radeon_vram_limit = 0; | |
608 | break; | |
609 | } | |
610 | radeon_vram_limit = radeon_vram_limit << 20; | |
611 | /* gtt size must be power of two and greater or equal to 32M */ | |
612 | switch (radeon_gart_size) { | |
613 | case 4: | |
614 | case 8: | |
615 | case 16: | |
616 | dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", | |
617 | radeon_gart_size); | |
618 | radeon_gart_size = 512; | |
619 | break; | |
620 | case 32: | |
621 | case 64: | |
622 | case 128: | |
623 | case 256: | |
624 | case 512: | |
625 | case 1024: | |
626 | case 2048: | |
627 | case 4096: | |
628 | break; | |
629 | default: | |
630 | dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", | |
631 | radeon_gart_size); | |
632 | radeon_gart_size = 512; | |
633 | break; | |
634 | } | |
635 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
636 | /* AGP mode can only be -1, 1, 2, 4, 8 */ | |
637 | switch (radeon_agpmode) { | |
638 | case -1: | |
639 | case 0: | |
640 | case 1: | |
641 | case 2: | |
642 | case 4: | |
643 | case 8: | |
644 | break; | |
645 | default: | |
646 | dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " | |
647 | "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); | |
648 | radeon_agpmode = 0; | |
649 | break; | |
650 | } | |
651 | } | |
652 | ||
6a9ee8af DA |
653 | static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
654 | { | |
655 | struct drm_device *dev = pci_get_drvdata(pdev); | |
6a9ee8af DA |
656 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; |
657 | if (state == VGA_SWITCHEROO_ON) { | |
658 | printk(KERN_INFO "radeon: switched on\n"); | |
659 | /* don't suspend or resume card normally */ | |
5bcf719b | 660 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af | 661 | radeon_resume_kms(dev); |
5bcf719b | 662 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
fbf81762 | 663 | drm_kms_helper_poll_enable(dev); |
6a9ee8af DA |
664 | } else { |
665 | printk(KERN_INFO "radeon: switched off\n"); | |
fbf81762 | 666 | drm_kms_helper_poll_disable(dev); |
5bcf719b | 667 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af | 668 | radeon_suspend_kms(dev, pmm); |
5bcf719b | 669 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
670 | } |
671 | } | |
672 | ||
673 | static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) | |
674 | { | |
675 | struct drm_device *dev = pci_get_drvdata(pdev); | |
676 | bool can_switch; | |
677 | ||
678 | spin_lock(&dev->count_lock); | |
679 | can_switch = (dev->open_count == 0); | |
680 | spin_unlock(&dev->count_lock); | |
681 | return can_switch; | |
682 | } | |
683 | ||
684 | ||
771fe6b9 JG |
685 | int radeon_device_init(struct radeon_device *rdev, |
686 | struct drm_device *ddev, | |
687 | struct pci_dev *pdev, | |
688 | uint32_t flags) | |
689 | { | |
351a52a2 | 690 | int r, i; |
ad49f501 | 691 | int dma_bits; |
771fe6b9 | 692 | |
771fe6b9 | 693 | rdev->shutdown = false; |
9f022ddf | 694 | rdev->dev = &pdev->dev; |
771fe6b9 JG |
695 | rdev->ddev = ddev; |
696 | rdev->pdev = pdev; | |
697 | rdev->flags = flags; | |
698 | rdev->family = flags & RADEON_FAMILY_MASK; | |
699 | rdev->is_atom_bios = false; | |
700 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; | |
701 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
702 | rdev->gpu_lockup = false; | |
733289c2 | 703 | rdev->accel_working = false; |
1b5331d9 JG |
704 | |
705 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n", | |
706 | radeon_family_name[rdev->family], pdev->vendor, pdev->device); | |
707 | ||
771fe6b9 JG |
708 | /* mutex initialization are all done here so we |
709 | * can recall function without having locking issues */ | |
710 | mutex_init(&rdev->cs_mutex); | |
711 | mutex_init(&rdev->ib_pool.mutex); | |
712 | mutex_init(&rdev->cp.mutex); | |
40bacf16 | 713 | mutex_init(&rdev->dc_hw_i2c_mutex); |
d8f60cfc AD |
714 | if (rdev->family >= CHIP_R600) |
715 | spin_lock_init(&rdev->ih.lock); | |
4c788679 | 716 | mutex_init(&rdev->gem.mutex); |
c913e23a | 717 | mutex_init(&rdev->pm.mutex); |
5876dd24 | 718 | mutex_init(&rdev->vram_mutex); |
771fe6b9 | 719 | rwlock_init(&rdev->fence_drv.lock); |
9f022ddf | 720 | INIT_LIST_HEAD(&rdev->gem.objects); |
73a6d3fc | 721 | init_waitqueue_head(&rdev->irq.vblank_queue); |
2031f77c | 722 | init_waitqueue_head(&rdev->irq.idle_queue); |
771fe6b9 | 723 | |
4aac0473 JG |
724 | /* Set asic functions */ |
725 | r = radeon_asic_init(rdev); | |
36421338 | 726 | if (r) |
4aac0473 | 727 | return r; |
36421338 | 728 | radeon_check_arguments(rdev); |
4aac0473 | 729 | |
f95df9ca AD |
730 | /* all of the newer IGP chips have an internal gart |
731 | * However some rs4xx report as AGP, so remove that here. | |
732 | */ | |
733 | if ((rdev->family >= CHIP_RS400) && | |
734 | (rdev->flags & RADEON_IS_IGP)) { | |
735 | rdev->flags &= ~RADEON_IS_AGP; | |
736 | } | |
737 | ||
30256a3f | 738 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
b574f251 | 739 | radeon_agp_disable(rdev); |
771fe6b9 JG |
740 | } |
741 | ||
ad49f501 DA |
742 | /* set DMA mask + need_dma32 flags. |
743 | * PCIE - can handle 40-bits. | |
744 | * IGP - can handle 40-bits (in theory) | |
745 | * AGP - generally dma32 is safest | |
746 | * PCI - only dma32 | |
747 | */ | |
748 | rdev->need_dma32 = false; | |
749 | if (rdev->flags & RADEON_IS_AGP) | |
750 | rdev->need_dma32 = true; | |
751 | if (rdev->flags & RADEON_IS_PCI) | |
752 | rdev->need_dma32 = true; | |
753 | ||
754 | dma_bits = rdev->need_dma32 ? 32 : 40; | |
755 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); | |
771fe6b9 JG |
756 | if (r) { |
757 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); | |
758 | } | |
759 | ||
760 | /* Registers mapping */ | |
761 | /* TODO: block userspace mapping of io register */ | |
01d73a69 JC |
762 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); |
763 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); | |
771fe6b9 JG |
764 | rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); |
765 | if (rdev->rmmio == NULL) { | |
766 | return -ENOMEM; | |
767 | } | |
768 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); | |
769 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); | |
770 | ||
351a52a2 AD |
771 | /* io port mapping */ |
772 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
773 | if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { | |
774 | rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); | |
775 | rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); | |
776 | break; | |
777 | } | |
778 | } | |
779 | if (rdev->rio_mem == NULL) | |
780 | DRM_ERROR("Unable to find PCI I/O BAR\n"); | |
781 | ||
28d52043 | 782 | /* if we have > 1 VGA cards, then disable the radeon VGA resources */ |
93239ea1 DA |
783 | /* this will fail for cards that aren't VGA class devices, just |
784 | * ignore it */ | |
785 | vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); | |
6a9ee8af DA |
786 | vga_switcheroo_register_client(rdev->pdev, |
787 | radeon_switcheroo_set_state, | |
8d608aa6 | 788 | NULL, |
6a9ee8af | 789 | radeon_switcheroo_can_switch); |
28d52043 | 790 | |
3ce0a23d | 791 | r = radeon_init(rdev); |
b574f251 | 792 | if (r) |
3ce0a23d | 793 | return r; |
3ce0a23d | 794 | |
b574f251 JG |
795 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
796 | /* Acceleration not working on AGP card try again | |
797 | * with fallback to PCI or PCIE GART | |
798 | */ | |
a2d07b74 | 799 | radeon_asic_reset(rdev); |
b574f251 JG |
800 | radeon_fini(rdev); |
801 | radeon_agp_disable(rdev); | |
802 | r = radeon_init(rdev); | |
4aac0473 JG |
803 | if (r) |
804 | return r; | |
771fe6b9 | 805 | } |
ecc0b326 MD |
806 | if (radeon_testing) { |
807 | radeon_test_moves(rdev); | |
808 | } | |
771fe6b9 JG |
809 | if (radeon_benchmarking) { |
810 | radeon_benchmark(rdev); | |
811 | } | |
6cf8a3f5 | 812 | return 0; |
771fe6b9 JG |
813 | } |
814 | ||
815 | void radeon_device_fini(struct radeon_device *rdev) | |
816 | { | |
771fe6b9 JG |
817 | DRM_INFO("radeon: finishing device.\n"); |
818 | rdev->shutdown = true; | |
90aca4d2 JG |
819 | /* evict vram memory */ |
820 | radeon_bo_evict_vram(rdev); | |
62a8ea3f | 821 | radeon_fini(rdev); |
6a9ee8af | 822 | vga_switcheroo_unregister_client(rdev->pdev); |
c1176d6f | 823 | vga_client_register(rdev->pdev, NULL, NULL, NULL); |
e0a2ca73 AD |
824 | if (rdev->rio_mem) |
825 | pci_iounmap(rdev->pdev, rdev->rio_mem); | |
351a52a2 | 826 | rdev->rio_mem = NULL; |
771fe6b9 JG |
827 | iounmap(rdev->rmmio); |
828 | rdev->rmmio = NULL; | |
829 | } | |
830 | ||
831 | ||
832 | /* | |
833 | * Suspend & resume. | |
834 | */ | |
835 | int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) | |
836 | { | |
875c1866 | 837 | struct radeon_device *rdev; |
771fe6b9 | 838 | struct drm_crtc *crtc; |
d8dcaa1d | 839 | struct drm_connector *connector; |
4c788679 | 840 | int r; |
771fe6b9 | 841 | |
875c1866 | 842 | if (dev == NULL || dev->dev_private == NULL) { |
771fe6b9 JG |
843 | return -ENODEV; |
844 | } | |
845 | if (state.event == PM_EVENT_PRETHAW) { | |
846 | return 0; | |
847 | } | |
875c1866 DJ |
848 | rdev = dev->dev_private; |
849 | ||
5bcf719b | 850 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
6a9ee8af | 851 | return 0; |
d8dcaa1d AD |
852 | |
853 | /* turn off display hw */ | |
854 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
855 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
856 | } | |
857 | ||
771fe6b9 JG |
858 | /* unpin the front buffers */ |
859 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
860 | struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); | |
4c788679 | 861 | struct radeon_bo *robj; |
771fe6b9 JG |
862 | |
863 | if (rfb == NULL || rfb->obj == NULL) { | |
864 | continue; | |
865 | } | |
7e4d15d9 | 866 | robj = gem_to_radeon_bo(rfb->obj); |
38651674 DA |
867 | /* don't unpin kernel fb objects */ |
868 | if (!radeon_fbdev_robj_is_fb(rdev, robj)) { | |
4c788679 | 869 | r = radeon_bo_reserve(robj, false); |
38651674 | 870 | if (r == 0) { |
4c788679 JG |
871 | radeon_bo_unpin(robj); |
872 | radeon_bo_unreserve(robj); | |
873 | } | |
771fe6b9 JG |
874 | } |
875 | } | |
876 | /* evict vram memory */ | |
4c788679 | 877 | radeon_bo_evict_vram(rdev); |
771fe6b9 JG |
878 | /* wait for gpu to finish processing current batch */ |
879 | radeon_fence_wait_last(rdev); | |
880 | ||
f657c2a7 YZ |
881 | radeon_save_bios_scratch_regs(rdev); |
882 | ||
ce8f5370 | 883 | radeon_pm_suspend(rdev); |
62a8ea3f | 884 | radeon_suspend(rdev); |
d4877cf2 | 885 | radeon_hpd_fini(rdev); |
771fe6b9 | 886 | /* evict remaining vram memory */ |
4c788679 | 887 | radeon_bo_evict_vram(rdev); |
771fe6b9 | 888 | |
10b06122 JG |
889 | radeon_agp_suspend(rdev); |
890 | ||
771fe6b9 JG |
891 | pci_save_state(dev->pdev); |
892 | if (state.event == PM_EVENT_SUSPEND) { | |
893 | /* Shut down the device */ | |
894 | pci_disable_device(dev->pdev); | |
895 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
896 | } | |
ac751efa | 897 | console_lock(); |
38651674 | 898 | radeon_fbdev_set_suspend(rdev, 1); |
ac751efa | 899 | console_unlock(); |
771fe6b9 JG |
900 | return 0; |
901 | } | |
902 | ||
903 | int radeon_resume_kms(struct drm_device *dev) | |
904 | { | |
09bdf591 | 905 | struct drm_connector *connector; |
771fe6b9 | 906 | struct radeon_device *rdev = dev->dev_private; |
771fe6b9 | 907 | |
5bcf719b | 908 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
6a9ee8af DA |
909 | return 0; |
910 | ||
ac751efa | 911 | console_lock(); |
771fe6b9 JG |
912 | pci_set_power_state(dev->pdev, PCI_D0); |
913 | pci_restore_state(dev->pdev); | |
914 | if (pci_enable_device(dev->pdev)) { | |
ac751efa | 915 | console_unlock(); |
771fe6b9 JG |
916 | return -1; |
917 | } | |
918 | pci_set_master(dev->pdev); | |
0ebf1717 DA |
919 | /* resume AGP if in use */ |
920 | radeon_agp_resume(rdev); | |
62a8ea3f | 921 | radeon_resume(rdev); |
ce8f5370 | 922 | radeon_pm_resume(rdev); |
f657c2a7 | 923 | radeon_restore_bios_scratch_regs(rdev); |
09bdf591 | 924 | |
38651674 | 925 | radeon_fbdev_set_suspend(rdev, 0); |
ac751efa | 926 | console_unlock(); |
771fe6b9 | 927 | |
ac89af1e AD |
928 | /* init dig PHYs */ |
929 | if (rdev->is_atom_bios) | |
930 | radeon_atom_encoder_init(rdev); | |
d4877cf2 AD |
931 | /* reset hpd state */ |
932 | radeon_hpd_init(rdev); | |
771fe6b9 JG |
933 | /* blat the mode back in */ |
934 | drm_helper_resume_force_mode(dev); | |
a93f344d AD |
935 | /* turn on display hw */ |
936 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
937 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
938 | } | |
771fe6b9 JG |
939 | return 0; |
940 | } | |
941 | ||
90aca4d2 JG |
942 | int radeon_gpu_reset(struct radeon_device *rdev) |
943 | { | |
944 | int r; | |
8fd1b84c | 945 | int resched; |
90aca4d2 JG |
946 | |
947 | radeon_save_bios_scratch_regs(rdev); | |
8fd1b84c DA |
948 | /* block TTM */ |
949 | resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); | |
90aca4d2 JG |
950 | radeon_suspend(rdev); |
951 | ||
952 | r = radeon_asic_reset(rdev); | |
953 | if (!r) { | |
954 | dev_info(rdev->dev, "GPU reset succeed\n"); | |
955 | radeon_resume(rdev); | |
956 | radeon_restore_bios_scratch_regs(rdev); | |
957 | drm_helper_resume_force_mode(rdev->ddev); | |
8fd1b84c | 958 | ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); |
90aca4d2 JG |
959 | return 0; |
960 | } | |
961 | /* bad news, how to tell it to userspace ? */ | |
962 | dev_info(rdev->dev, "GPU reset failed\n"); | |
963 | return r; | |
964 | } | |
965 | ||
771fe6b9 JG |
966 | |
967 | /* | |
968 | * Debugfs | |
969 | */ | |
970 | struct radeon_debugfs { | |
971 | struct drm_info_list *files; | |
972 | unsigned num_files; | |
973 | }; | |
974 | static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES]; | |
975 | static unsigned _radeon_debugfs_count = 0; | |
976 | ||
977 | int radeon_debugfs_add_files(struct radeon_device *rdev, | |
978 | struct drm_info_list *files, | |
979 | unsigned nfiles) | |
980 | { | |
981 | unsigned i; | |
982 | ||
983 | for (i = 0; i < _radeon_debugfs_count; i++) { | |
984 | if (_radeon_debugfs[i].files == files) { | |
985 | /* Already registered */ | |
986 | return 0; | |
987 | } | |
988 | } | |
989 | if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) { | |
990 | DRM_ERROR("Reached maximum number of debugfs files.\n"); | |
991 | DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n"); | |
992 | return -EINVAL; | |
993 | } | |
994 | _radeon_debugfs[_radeon_debugfs_count].files = files; | |
995 | _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles; | |
996 | _radeon_debugfs_count++; | |
997 | #if defined(CONFIG_DEBUG_FS) | |
998 | drm_debugfs_create_files(files, nfiles, | |
999 | rdev->ddev->control->debugfs_root, | |
1000 | rdev->ddev->control); | |
1001 | drm_debugfs_create_files(files, nfiles, | |
1002 | rdev->ddev->primary->debugfs_root, | |
1003 | rdev->ddev->primary); | |
1004 | #endif | |
1005 | return 0; | |
1006 | } | |
1007 | ||
1008 | #if defined(CONFIG_DEBUG_FS) | |
1009 | int radeon_debugfs_init(struct drm_minor *minor) | |
1010 | { | |
1011 | return 0; | |
1012 | } | |
1013 | ||
1014 | void radeon_debugfs_cleanup(struct drm_minor *minor) | |
1015 | { | |
1016 | unsigned i; | |
1017 | ||
1018 | for (i = 0; i < _radeon_debugfs_count; i++) { | |
1019 | drm_debugfs_remove_files(_radeon_debugfs[i].files, | |
1020 | _radeon_debugfs[i].num_files, minor); | |
1021 | } | |
1022 | } | |
1023 | #endif |