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drm/radeon/kms: adjust default clock/vddc tracking for pm on DCE5
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / radeon / radeon_device.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/console.h>
5a0e3ad6 29#include <linux/slab.h>
771fe6b9
JG		 30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
28d52043 33#include <linux/vgaarb.h>
6a9ee8af 34#include <linux/vga_switcheroo.h>
771fe6b9
JG		 35#include "radeon_reg.h"
36#include "radeon.h"
771fe6b9
JG		 37#include "atom.h"
38
1b5331d9
JG		 39static const char radeon_family_name[][16] = {
40 "R100",
41 "RV100",
42 "RS100",
43 "RV200",
44 "RS200",
45 "R200",
46 "RV250",
47 "RS300",
48 "RV280",
49 "R300",
50 "R350",
51 "RV350",
52 "RV380",
53 "R420",
54 "R423",
55 "RV410",
56 "RS400",
57 "RS480",
58 "RS600",
59 "RS690",
60 "RS740",
61 "RV515",
62 "R520",
63 "RV530",
64 "RV560",
65 "RV570",
66 "R580",
67 "R600",
68 "RV610",
69 "RV630",
70 "RV670",
71 "RV620",
72 "RV635",
73 "RS780",
74 "RS880",
75 "RV770",
76 "RV730",
77 "RV710",
78 "RV740",
79 "CEDAR",
80 "REDWOOD",
81 "JUNIPER",
82 "CYPRESS",
83 "HEMLOCK",
b08ebe7e 84 "PALM",
1fe18305
AD		 85 "BARTS",
86 "TURKS",
87 "CAICOS",
1b5331d9
JG		 88 "LAST",
89};
90
b1e3a6d1
MD		 91/*
92 * Clear GPU surface registers.
93 */
3ce0a23d 94void radeon_surface_init(struct radeon_device *rdev)
b1e3a6d1
MD		 95{
96 /* FIXME: check this out */
97 if (rdev->family < CHIP_R600) {
98 int i;
99
550e2d92
DA		 100 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
101 if (rdev->surface_regs[i].bo)
102 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
103 else
104 radeon_clear_surface_reg(rdev, i);
b1e3a6d1 105 }
e024e110
DA		 106 /* enable surfaces */
107 WREG32(RADEON_SURFACE_CNTL, 0);
b1e3a6d1
MD		 108 }
109}
110
771fe6b9
JG		 111/*
112 * GPU scratch registers helpers function.
113 */
3ce0a23d 114void radeon_scratch_init(struct radeon_device *rdev)
771fe6b9
JG		 115{
116 int i;
117
118 /* FIXME: check this out */
119 if (rdev->family < CHIP_R300) {
120 rdev->scratch.num_reg = 5;
121 } else {
122 rdev->scratch.num_reg = 7;
123 }
724c80e1 124 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
771fe6b9
JG		 125 for (i = 0; i < rdev->scratch.num_reg; i++) {
126 rdev->scratch.free[i] = true;
724c80e1 127 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
771fe6b9
JG		 128 }
129}
130
131int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
132{
133 int i;
134
135 for (i = 0; i < rdev->scratch.num_reg; i++) {
136 if (rdev->scratch.free[i]) {
137 rdev->scratch.free[i] = false;
138 *reg = rdev->scratch.reg[i];
139 return 0;
140 }
141 }
142 return -EINVAL;
143}
144
145void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
146{
147 int i;
148
149 for (i = 0; i < rdev->scratch.num_reg; i++) {
150 if (rdev->scratch.reg[i] == reg) {
151 rdev->scratch.free[i] = true;
152 return;
153 }
154 }
155}
156
724c80e1
AD		 157void radeon_wb_disable(struct radeon_device *rdev)
158{
159 int r;
160
161 if (rdev->wb.wb_obj) {
162 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
163 if (unlikely(r != 0))
164 return;
165 radeon_bo_kunmap(rdev->wb.wb_obj);
166 radeon_bo_unpin(rdev->wb.wb_obj);
167 radeon_bo_unreserve(rdev->wb.wb_obj);
168 }
169 rdev->wb.enabled = false;
170}
171
172void radeon_wb_fini(struct radeon_device *rdev)
173{
174 radeon_wb_disable(rdev);
175 if (rdev->wb.wb_obj) {
176 radeon_bo_unref(&rdev->wb.wb_obj);
177 rdev->wb.wb = NULL;
178 rdev->wb.wb_obj = NULL;
179 }
180}
181
182int radeon_wb_init(struct radeon_device *rdev)
183{
184 int r;
185
186 if (rdev->wb.wb_obj == NULL) {
268b2510 187 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
724c80e1
AD		 188 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
189 if (r) {
190 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
191 return r;
192 }
193 }
194 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
195 if (unlikely(r != 0)) {
196 radeon_wb_fini(rdev);
197 return r;
198 }
199 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
200 &rdev->wb.gpu_addr);
201 if (r) {
202 radeon_bo_unreserve(rdev->wb.wb_obj);
203 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
204 radeon_wb_fini(rdev);
205 return r;
206 }
207 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
208 radeon_bo_unreserve(rdev->wb.wb_obj);
209 if (r) {
210 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
211 radeon_wb_fini(rdev);
212 return r;
213 }
214
d0f8a854
AD		 215 /* disable event_write fences */
216 rdev->wb.use_event = false;
724c80e1
AD		 217 /* disabled via module param */
218 if (radeon_no_wb == 1)
219 rdev->wb.enabled = false;
220 else {
221 /* often unreliable on AGP */
222 if (rdev->flags & RADEON_IS_AGP) {
223 rdev->wb.enabled = false;
d0f8a854 224 } else {
724c80e1 225 rdev->wb.enabled = true;
d0f8a854
AD		 226 /* event_write fences are only available on r600+ */
227 if (rdev->family >= CHIP_R600)
228 rdev->wb.use_event = true;
229 }
724c80e1
AD		 230 }
231
232 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
233
234 return 0;
235}
236
d594e46a
JG		 237/**
238 * radeon_vram_location - try to find VRAM location
239 * @rdev: radeon device structure holding all necessary informations
240 * @mc: memory controller structure holding memory informations
241 * @base: base address at which to put VRAM
242 *
243 * Function will place try to place VRAM at base address provided
244 * as parameter (which is so far either PCI aperture address or
245 * for IGP TOM base address).
246 *
247 * If there is not enough space to fit the unvisible VRAM in the 32bits
248 * address space then we limit the VRAM size to the aperture.
249 *
250 * If we are using AGP and if the AGP aperture doesn't allow us to have
251 * room for all the VRAM than we restrict the VRAM to the PCI aperture
252 * size and print a warning.
253 *
254 * This function will never fails, worst case are limiting VRAM.
255 *
256 * Note: GTT start, end, size should be initialized before calling this
257 * function on AGP platform.
258 *
259 * Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
260 * this shouldn't be a problem as we are using the PCI aperture as a reference.
261 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
262 * not IGP.
263 *
264 * Note: we use mc_vram_size as on some board we need to program the mc to
265 * cover the whole aperture even if VRAM size is inferior to aperture size
266 * Novell bug 204882 + along with lots of ubuntu ones
267 *
268 * Note: when limiting vram it's safe to overwritte real_vram_size because
269 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
270 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
271 * ones)
272 *
273 * Note: IGP TOM addr should be the same as the aperture addr, we don't
274 * explicitly check for that thought.
275 *
276 * FIXME: when reducing VRAM size align new size on power of 2.
771fe6b9 277 */
d594e46a 278void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
771fe6b9 279{
d594e46a
JG		 280 mc->vram_start = base;
281 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
282 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
283 mc->real_vram_size = mc->aper_size;
284 mc->mc_vram_size = mc->aper_size;
285 }
286 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
2cbeb4ef 287 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
d594e46a
JG		 288 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
289 mc->real_vram_size = mc->aper_size;
290 mc->mc_vram_size = mc->aper_size;
291 }
292 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
dd7cc55a 293 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
d594e46a
JG		 294 mc->mc_vram_size >> 20, mc->vram_start,
295 mc->vram_end, mc->real_vram_size >> 20);
296}
771fe6b9 297
d594e46a
JG		 298/**
299 * radeon_gtt_location - try to find GTT location
300 * @rdev: radeon device structure holding all necessary informations
301 * @mc: memory controller structure holding memory informations
302 *
303 * Function will place try to place GTT before or after VRAM.
304 *
305 * If GTT size is bigger than space left then we ajust GTT size.
306 * Thus function will never fails.
307 *
308 * FIXME: when reducing GTT size align new size on power of 2.
309 */
310void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
311{
312 u64 size_af, size_bf;
313
8d369bb1
AD		 314 size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
315 size_bf = mc->vram_start & ~mc->gtt_base_align;
d594e46a
JG		 316 if (size_bf > size_af) {
317 if (mc->gtt_size > size_bf) {
318 dev_warn(rdev->dev, "limiting GTT\n");
319 mc->gtt_size = size_bf;
771fe6b9 320 }
8d369bb1 321 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
771fe6b9 322 } else {
d594e46a
JG		 323 if (mc->gtt_size > size_af) {
324 dev_warn(rdev->dev, "limiting GTT\n");
325 mc->gtt_size = size_af;
326 }
8d369bb1 327 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
771fe6b9 328 }
d594e46a 329 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
dd7cc55a 330 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
d594e46a 331 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
771fe6b9
JG		 332}
333
771fe6b9
JG		 334/*
335 * GPU helpers function.
336 */
9f022ddf 337bool radeon_card_posted(struct radeon_device *rdev)
771fe6b9
JG		 338{
339 uint32_t reg;
340
341 /* first check CRTCs */
18007401
AD		 342 if (ASIC_IS_DCE41(rdev)) {
343 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
344 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
345 if (reg & EVERGREEN_CRTC_MASTER_EN)
346 return true;
347 } else if (ASIC_IS_DCE4(rdev)) {
bcc1c2a1
AD		 348 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
349 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
350 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
351 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
352 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
353 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
354 if (reg & EVERGREEN_CRTC_MASTER_EN)
355 return true;
356 } else if (ASIC_IS_AVIVO(rdev)) {
771fe6b9
JG		 357 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
358 RREG32(AVIVO_D2CRTC_CONTROL);
359 if (reg & AVIVO_CRTC_EN) {
360 return true;
361 }
362 } else {
363 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
364 RREG32(RADEON_CRTC2_GEN_CNTL);
365 if (reg & RADEON_CRTC_EN) {
366 return true;
367 }
368 }
369
370 /* then check MEM_SIZE, in case the crtcs are off */
371 if (rdev->family >= CHIP_R600)
372 reg = RREG32(R600_CONFIG_MEMSIZE);
373 else
374 reg = RREG32(RADEON_CONFIG_MEMSIZE);
375
376 if (reg)
377 return true;
378
379 return false;
380
381}
382
f47299c5
AD		 383void radeon_update_bandwidth_info(struct radeon_device *rdev)
384{
385 fixed20_12 a;
8807286e
AD		 386 u32 sclk = rdev->pm.current_sclk;
387 u32 mclk = rdev->pm.current_mclk;
f47299c5 388
8807286e
AD		 389 /* sclk/mclk in Mhz */
390 a.full = dfixed_const(100);
391 rdev->pm.sclk.full = dfixed_const(sclk);
392 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
393 rdev->pm.mclk.full = dfixed_const(mclk);
394 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
f47299c5 395
8807286e 396 if (rdev->flags & RADEON_IS_IGP) {
68adac5e 397 a.full = dfixed_const(16);
f47299c5 398 /* core_bandwidth = sclk(Mhz) * 16 */
68adac5e 399 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
f47299c5
AD		 400 }
401}
402
72542d77
DA		 403bool radeon_boot_test_post_card(struct radeon_device *rdev)
404{
405 if (radeon_card_posted(rdev))
406 return true;
407
408 if (rdev->bios) {
409 DRM_INFO("GPU not posted. posting now...\n");
410 if (rdev->is_atom_bios)
411 atom_asic_init(rdev->mode_info.atom_context);
412 else
413 radeon_combios_asic_init(rdev->ddev);
414 return true;
415 } else {
416 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
417 return false;
418 }
419}
420
3ce0a23d
JG		 421int radeon_dummy_page_init(struct radeon_device *rdev)
422{
82568565
DA		 423 if (rdev->dummy_page.page)
424 return 0;
3ce0a23d
JG		 425 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
426 if (rdev->dummy_page.page == NULL)
427 return -ENOMEM;
428 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
429 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
a30f6fb7
BH		 430 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
431 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
3ce0a23d
JG		 432 __free_page(rdev->dummy_page.page);
433 rdev->dummy_page.page = NULL;
434 return -ENOMEM;
435 }
436 return 0;
437}
438
439void radeon_dummy_page_fini(struct radeon_device *rdev)
440{
441 if (rdev->dummy_page.page == NULL)
442 return;
443 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
444 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
445 __free_page(rdev->dummy_page.page);
446 rdev->dummy_page.page = NULL;
447}
448
771fe6b9 449
771fe6b9
JG		 450/* ATOM accessor methods */
451static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
452{
453 struct radeon_device *rdev = info->dev->dev_private;
454 uint32_t r;
455
456 r = rdev->pll_rreg(rdev, reg);
457 return r;
458}
459
460static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
461{
462 struct radeon_device *rdev = info->dev->dev_private;
463
464 rdev->pll_wreg(rdev, reg, val);
465}
466
467static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
468{
469 struct radeon_device *rdev = info->dev->dev_private;
470 uint32_t r;
471
472 r = rdev->mc_rreg(rdev, reg);
473 return r;
474}
475
476static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
477{
478 struct radeon_device *rdev = info->dev->dev_private;
479
480 rdev->mc_wreg(rdev, reg, val);
481}
482
483static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
484{
485 struct radeon_device *rdev = info->dev->dev_private;
486
487 WREG32(reg*4, val);
488}
489
490static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
491{
492 struct radeon_device *rdev = info->dev->dev_private;
493 uint32_t r;
494
495 r = RREG32(reg*4);
496 return r;
497}
498
351a52a2
AD		 499static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
500{
501 struct radeon_device *rdev = info->dev->dev_private;
502
503 WREG32_IO(reg*4, val);
504}
505
506static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
507{
508 struct radeon_device *rdev = info->dev->dev_private;
509 uint32_t r;
510
511 r = RREG32_IO(reg*4);
512 return r;
513}
514
771fe6b9
JG		 515int radeon_atombios_init(struct radeon_device *rdev)
516{
61c4b24b
MF		 517 struct card_info *atom_card_info =
518 kzalloc(sizeof(struct card_info), GFP_KERNEL);
519
520 if (!atom_card_info)
521 return -ENOMEM;
522
523 rdev->mode_info.atom_card_info = atom_card_info;
524 atom_card_info->dev = rdev->ddev;
525 atom_card_info->reg_read = cail_reg_read;
526 atom_card_info->reg_write = cail_reg_write;
351a52a2
AD		 527 /* needed for iio ops */
528 if (rdev->rio_mem) {
529 atom_card_info->ioreg_read = cail_ioreg_read;
530 atom_card_info->ioreg_write = cail_ioreg_write;
531 } else {
532 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
533 atom_card_info->ioreg_read = cail_reg_read;
534 atom_card_info->ioreg_write = cail_reg_write;
535 }
61c4b24b
MF		 536 atom_card_info->mc_read = cail_mc_read;
537 atom_card_info->mc_write = cail_mc_write;
538 atom_card_info->pll_read = cail_pll_read;
539 atom_card_info->pll_write = cail_pll_write;
540
541 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
c31ad97f 542 mutex_init(&rdev->mode_info.atom_context->mutex);
771fe6b9 543 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
d904ef9b 544 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
771fe6b9
JG		 545 return 0;
546}
547
548void radeon_atombios_fini(struct radeon_device *rdev)
549{
4a04a844
JG		 550 if (rdev->mode_info.atom_context) {
551 kfree(rdev->mode_info.atom_context->scratch);
552 kfree(rdev->mode_info.atom_context);
553 }
61c4b24b 554 kfree(rdev->mode_info.atom_card_info);
771fe6b9
JG		 555}
556
557int radeon_combios_init(struct radeon_device *rdev)
558{
559 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
560 return 0;
561}
562
563void radeon_combios_fini(struct radeon_device *rdev)
564{
565}
566
28d52043
DA		 567/* if we get transitioned to only one device, tak VGA back */
568static unsigned int radeon_vga_set_decode(void *cookie, bool state)
569{
570 struct radeon_device *rdev = cookie;
28d52043
DA		 571 radeon_vga_set_state(rdev, state);
572 if (state)
573 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
574 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
575 else
576 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
577}
c1176d6f 578
36421338
JG		 579void radeon_check_arguments(struct radeon_device *rdev)
580{
581 /* vramlimit must be a power of two */
582 switch (radeon_vram_limit) {
583 case 0:
584 case 4:
585 case 8:
586 case 16:
587 case 32:
588 case 64:
589 case 128:
590 case 256:
591 case 512:
592 case 1024:
593 case 2048:
594 case 4096:
595 break;
596 default:
597 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
598 radeon_vram_limit);
599 radeon_vram_limit = 0;
600 break;
601 }
602 radeon_vram_limit = radeon_vram_limit << 20;
603 /* gtt size must be power of two and greater or equal to 32M */
604 switch (radeon_gart_size) {
605 case 4:
606 case 8:
607 case 16:
608 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
609 radeon_gart_size);
610 radeon_gart_size = 512;
611 break;
612 case 32:
613 case 64:
614 case 128:
615 case 256:
616 case 512:
617 case 1024:
618 case 2048:
619 case 4096:
620 break;
621 default:
622 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
623 radeon_gart_size);
624 radeon_gart_size = 512;
625 break;
626 }
627 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
628 /* AGP mode can only be -1, 1, 2, 4, 8 */
629 switch (radeon_agpmode) {
630 case -1:
631 case 0:
632 case 1:
633 case 2:
634 case 4:
635 case 8:
636 break;
637 default:
638 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
639 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
640 radeon_agpmode = 0;
641 break;
642 }
643}
644
6a9ee8af
DA		 645static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
646{
647 struct drm_device *dev = pci_get_drvdata(pdev);
6a9ee8af
DA		 648 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
649 if (state == VGA_SWITCHEROO_ON) {
650 printk(KERN_INFO "radeon: switched on\n");
651 /* don't suspend or resume card normally */
5bcf719b 652 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
6a9ee8af 653 radeon_resume_kms(dev);
5bcf719b 654 dev->switch_power_state = DRM_SWITCH_POWER_ON;
fbf81762 655 drm_kms_helper_poll_enable(dev);
6a9ee8af
DA		 656 } else {
657 printk(KERN_INFO "radeon: switched off\n");
fbf81762 658 drm_kms_helper_poll_disable(dev);
5bcf719b 659 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
6a9ee8af 660 radeon_suspend_kms(dev, pmm);
5bcf719b 661 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
6a9ee8af
DA		 662 }
663}
664
665static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
666{
667 struct drm_device *dev = pci_get_drvdata(pdev);
668 bool can_switch;
669
670 spin_lock(&dev->count_lock);
671 can_switch = (dev->open_count == 0);
672 spin_unlock(&dev->count_lock);
673 return can_switch;
674}
675
676
771fe6b9
JG		 677int radeon_device_init(struct radeon_device *rdev,
678 struct drm_device *ddev,
679 struct pci_dev *pdev,
680 uint32_t flags)
681{
351a52a2 682 int r, i;
ad49f501 683 int dma_bits;
771fe6b9 684
771fe6b9 685 rdev->shutdown = false;
9f022ddf 686 rdev->dev = &pdev->dev;
771fe6b9
JG		 687 rdev->ddev = ddev;
688 rdev->pdev = pdev;
689 rdev->flags = flags;
690 rdev->family = flags & RADEON_FAMILY_MASK;
691 rdev->is_atom_bios = false;
692 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
693 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
694 rdev->gpu_lockup = false;
733289c2 695 rdev->accel_working = false;
1b5331d9
JG		 696
697 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n",
698 radeon_family_name[rdev->family], pdev->vendor, pdev->device);
699
771fe6b9
JG		 700 /* mutex initialization are all done here so we
701 * can recall function without having locking issues */
702 mutex_init(&rdev->cs_mutex);
703 mutex_init(&rdev->ib_pool.mutex);
704 mutex_init(&rdev->cp.mutex);
40bacf16 705 mutex_init(&rdev->dc_hw_i2c_mutex);
d8f60cfc
AD		 706 if (rdev->family >= CHIP_R600)
707 spin_lock_init(&rdev->ih.lock);
4c788679 708 mutex_init(&rdev->gem.mutex);
c913e23a 709 mutex_init(&rdev->pm.mutex);
5876dd24 710 mutex_init(&rdev->vram_mutex);
771fe6b9 711 rwlock_init(&rdev->fence_drv.lock);
9f022ddf 712 INIT_LIST_HEAD(&rdev->gem.objects);
73a6d3fc 713 init_waitqueue_head(&rdev->irq.vblank_queue);
2031f77c 714 init_waitqueue_head(&rdev->irq.idle_queue);
771fe6b9 715
4aac0473
JG		 716 /* Set asic functions */
717 r = radeon_asic_init(rdev);
36421338 718 if (r)
4aac0473 719 return r;
36421338 720 radeon_check_arguments(rdev);
4aac0473 721
f95df9ca
AD		 722 /* all of the newer IGP chips have an internal gart
723 * However some rs4xx report as AGP, so remove that here.
724 */
725 if ((rdev->family >= CHIP_RS400) &&
726 (rdev->flags & RADEON_IS_IGP)) {
727 rdev->flags &= ~RADEON_IS_AGP;
728 }
729
30256a3f 730 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
b574f251 731 radeon_agp_disable(rdev);
771fe6b9
JG		 732 }
733
ad49f501
DA		 734 /* set DMA mask + need_dma32 flags.
735 * PCIE - can handle 40-bits.
736 * IGP - can handle 40-bits (in theory)
737 * AGP - generally dma32 is safest
738 * PCI - only dma32
739 */
740 rdev->need_dma32 = false;
741 if (rdev->flags & RADEON_IS_AGP)
742 rdev->need_dma32 = true;
743 if (rdev->flags & RADEON_IS_PCI)
744 rdev->need_dma32 = true;
745
746 dma_bits = rdev->need_dma32 ? 32 : 40;
747 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
771fe6b9
JG		 748 if (r) {
749 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
750 }
751
752 /* Registers mapping */
753 /* TODO: block userspace mapping of io register */
01d73a69
JC		 754 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
755 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
771fe6b9
JG		 756 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
757 if (rdev->rmmio == NULL) {
758 return -ENOMEM;
759 }
760 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
761 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
762
351a52a2
AD		 763 /* io port mapping */
764 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
765 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
766 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
767 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
768 break;
769 }
770 }
771 if (rdev->rio_mem == NULL)
772 DRM_ERROR("Unable to find PCI I/O BAR\n");
773
28d52043 774 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
93239ea1
DA		 775 /* this will fail for cards that aren't VGA class devices, just
776 * ignore it */
777 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
6a9ee8af
DA		 778 vga_switcheroo_register_client(rdev->pdev,
779 radeon_switcheroo_set_state,
8d608aa6 780 NULL,
6a9ee8af 781 radeon_switcheroo_can_switch);
28d52043 782
3ce0a23d 783 r = radeon_init(rdev);
b574f251 784 if (r)
3ce0a23d 785 return r;
3ce0a23d 786
b574f251
JG		 787 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
788 /* Acceleration not working on AGP card try again
789 * with fallback to PCI or PCIE GART
790 */
a2d07b74 791 radeon_asic_reset(rdev);
b574f251
JG		 792 radeon_fini(rdev);
793 radeon_agp_disable(rdev);
794 r = radeon_init(rdev);
4aac0473
JG		 795 if (r)
796 return r;
771fe6b9 797 }
ecc0b326
MD		 798 if (radeon_testing) {
799 radeon_test_moves(rdev);
800 }
771fe6b9
JG		 801 if (radeon_benchmarking) {
802 radeon_benchmark(rdev);
803 }
6cf8a3f5 804 return 0;
771fe6b9
JG		 805}
806
807void radeon_device_fini(struct radeon_device *rdev)
808{
771fe6b9
JG		 809 DRM_INFO("radeon: finishing device.\n");
810 rdev->shutdown = true;
90aca4d2
JG		 811 /* evict vram memory */
812 radeon_bo_evict_vram(rdev);
62a8ea3f 813 radeon_fini(rdev);
6a9ee8af 814 vga_switcheroo_unregister_client(rdev->pdev);
c1176d6f 815 vga_client_register(rdev->pdev, NULL, NULL, NULL);
e0a2ca73
AD		 816 if (rdev->rio_mem)
817 pci_iounmap(rdev->pdev, rdev->rio_mem);
351a52a2 818 rdev->rio_mem = NULL;
771fe6b9
JG		 819 iounmap(rdev->rmmio);
820 rdev->rmmio = NULL;
821}
822
823
824/*
825 * Suspend & resume.
826 */
827int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
828{
875c1866 829 struct radeon_device *rdev;
771fe6b9 830 struct drm_crtc *crtc;
d8dcaa1d 831 struct drm_connector *connector;
4c788679 832 int r;
771fe6b9 833
875c1866 834 if (dev == NULL || dev->dev_private == NULL) {
771fe6b9
JG		 835 return -ENODEV;
836 }
837 if (state.event == PM_EVENT_PRETHAW) {
838 return 0;
839 }
875c1866
DJ		 840 rdev = dev->dev_private;
841
5bcf719b 842 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
6a9ee8af 843 return 0;
d8dcaa1d
AD		 844
845 /* turn off display hw */
846 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
847 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
848 }
849
771fe6b9
JG		 850 /* unpin the front buffers */
851 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
852 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
4c788679 853 struct radeon_bo *robj;
771fe6b9
JG		 854
855 if (rfb == NULL || rfb->obj == NULL) {
856 continue;
857 }
858 robj = rfb->obj->driver_private;
38651674
DA		 859 /* don't unpin kernel fb objects */
860 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
4c788679 861 r = radeon_bo_reserve(robj, false);
38651674 862 if (r == 0) {
4c788679
JG		 863 radeon_bo_unpin(robj);
864 radeon_bo_unreserve(robj);
865 }
771fe6b9
JG		 866 }
867 }
868 /* evict vram memory */
4c788679 869 radeon_bo_evict_vram(rdev);
771fe6b9
JG		 870 /* wait for gpu to finish processing current batch */
871 radeon_fence_wait_last(rdev);
872
f657c2a7
YZ		 873 radeon_save_bios_scratch_regs(rdev);
874
ce8f5370 875 radeon_pm_suspend(rdev);
62a8ea3f 876 radeon_suspend(rdev);
d4877cf2 877 radeon_hpd_fini(rdev);
771fe6b9 878 /* evict remaining vram memory */
4c788679 879 radeon_bo_evict_vram(rdev);
771fe6b9 880
10b06122
JG		 881 radeon_agp_suspend(rdev);
882
771fe6b9
JG		 883 pci_save_state(dev->pdev);
884 if (state.event == PM_EVENT_SUSPEND) {
885 /* Shut down the device */
886 pci_disable_device(dev->pdev);
887 pci_set_power_state(dev->pdev, PCI_D3hot);
888 }
889 acquire_console_sem();
38651674 890 radeon_fbdev_set_suspend(rdev, 1);
771fe6b9
JG		 891 release_console_sem();
892 return 0;
893}
894
895int radeon_resume_kms(struct drm_device *dev)
896{
09bdf591 897 struct drm_connector *connector;
771fe6b9 898 struct radeon_device *rdev = dev->dev_private;
771fe6b9 899
5bcf719b 900 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
6a9ee8af
DA		 901 return 0;
902
771fe6b9
JG		 903 acquire_console_sem();
904 pci_set_power_state(dev->pdev, PCI_D0);
905 pci_restore_state(dev->pdev);
906 if (pci_enable_device(dev->pdev)) {
907 release_console_sem();
908 return -1;
909 }
910 pci_set_master(dev->pdev);
0ebf1717
DA		 911 /* resume AGP if in use */
912 radeon_agp_resume(rdev);
62a8ea3f 913 radeon_resume(rdev);
ce8f5370 914 radeon_pm_resume(rdev);
f657c2a7 915 radeon_restore_bios_scratch_regs(rdev);
09bdf591 916
38651674 917 radeon_fbdev_set_suspend(rdev, 0);
771fe6b9
JG		 918 release_console_sem();
919
d4877cf2
AD		 920 /* reset hpd state */
921 radeon_hpd_init(rdev);
771fe6b9
JG		 922 /* blat the mode back in */
923 drm_helper_resume_force_mode(dev);
a93f344d
AD		 924 /* turn on display hw */
925 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
926 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
927 }
771fe6b9
JG		 928 return 0;
929}
930
90aca4d2
JG		 931int radeon_gpu_reset(struct radeon_device *rdev)
932{
933 int r;
934
935 radeon_save_bios_scratch_regs(rdev);
936 radeon_suspend(rdev);
937
938 r = radeon_asic_reset(rdev);
939 if (!r) {
940 dev_info(rdev->dev, "GPU reset succeed\n");
941 radeon_resume(rdev);
942 radeon_restore_bios_scratch_regs(rdev);
943 drm_helper_resume_force_mode(rdev->ddev);
944 return 0;
945 }
946 /* bad news, how to tell it to userspace ? */
947 dev_info(rdev->dev, "GPU reset failed\n");
948 return r;
949}
950
771fe6b9
JG		 951
952/*
953 * Debugfs
954 */
955struct radeon_debugfs {
956 struct drm_info_list *files;
957 unsigned num_files;
958};
959static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
960static unsigned _radeon_debugfs_count = 0;
961
962int radeon_debugfs_add_files(struct radeon_device *rdev,
963 struct drm_info_list *files,
964 unsigned nfiles)
965{
966 unsigned i;
967
968 for (i = 0; i < _radeon_debugfs_count; i++) {
969 if (_radeon_debugfs[i].files == files) {
970 /* Already registered */
971 return 0;
972 }
973 }
974 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
975 DRM_ERROR("Reached maximum number of debugfs files.\n");
976 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
977 return -EINVAL;
978 }
979 _radeon_debugfs[_radeon_debugfs_count].files = files;
980 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
981 _radeon_debugfs_count++;
982#if defined(CONFIG_DEBUG_FS)
983 drm_debugfs_create_files(files, nfiles,
984 rdev->ddev->control->debugfs_root,
985 rdev->ddev->control);
986 drm_debugfs_create_files(files, nfiles,
987 rdev->ddev->primary->debugfs_root,
988 rdev->ddev->primary);
989#endif
990 return 0;
991}
992
993#if defined(CONFIG_DEBUG_FS)
994int radeon_debugfs_init(struct drm_minor *minor)
995{
996 return 0;
997}
998
999void radeon_debugfs_cleanup(struct drm_minor *minor)
1000{
1001 unsigned i;
1002
1003 for (i = 0; i < _radeon_debugfs_count; i++) {
1004 drm_debugfs_remove_files(_radeon_debugfs[i].files,
1005 _radeon_debugfs[i].num_files, minor);
1006 }
1007}
1008#endif
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