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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / radeon / radeon_device.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/console.h>
29#include <drm/drmP.h>
30#include <drm/drm_crtc_helper.h>
31#include <drm/radeon_drm.h>
28d52043 32#include <linux/vgaarb.h>
6a9ee8af 33#include <linux/vga_switcheroo.h>
771fe6b9
JG		 34#include "radeon_reg.h"
35#include "radeon.h"
36#include "radeon_asic.h"
37#include "atom.h"
38
b1e3a6d1
MD		 39/*
40 * Clear GPU surface registers.
41 */
3ce0a23d 42void radeon_surface_init(struct radeon_device *rdev)
b1e3a6d1
MD		 43{
44 /* FIXME: check this out */
45 if (rdev->family < CHIP_R600) {
46 int i;
47
550e2d92
DA		 48 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
49 if (rdev->surface_regs[i].bo)
50 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
51 else
52 radeon_clear_surface_reg(rdev, i);
b1e3a6d1 53 }
e024e110
DA		 54 /* enable surfaces */
55 WREG32(RADEON_SURFACE_CNTL, 0);
b1e3a6d1
MD		 56 }
57}
58
771fe6b9
JG		 59/*
60 * GPU scratch registers helpers function.
61 */
3ce0a23d 62void radeon_scratch_init(struct radeon_device *rdev)
771fe6b9
JG		 63{
64 int i;
65
66 /* FIXME: check this out */
67 if (rdev->family < CHIP_R300) {
68 rdev->scratch.num_reg = 5;
69 } else {
70 rdev->scratch.num_reg = 7;
71 }
72 for (i = 0; i < rdev->scratch.num_reg; i++) {
73 rdev->scratch.free[i] = true;
74 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
75 }
76}
77
78int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
79{
80 int i;
81
82 for (i = 0; i < rdev->scratch.num_reg; i++) {
83 if (rdev->scratch.free[i]) {
84 rdev->scratch.free[i] = false;
85 *reg = rdev->scratch.reg[i];
86 return 0;
87 }
88 }
89 return -EINVAL;
90}
91
92void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
93{
94 int i;
95
96 for (i = 0; i < rdev->scratch.num_reg; i++) {
97 if (rdev->scratch.reg[i] == reg) {
98 rdev->scratch.free[i] = true;
99 return;
100 }
101 }
102}
103
d594e46a
JG		 104/**
105 * radeon_vram_location - try to find VRAM location
106 * @rdev: radeon device structure holding all necessary informations
107 * @mc: memory controller structure holding memory informations
108 * @base: base address at which to put VRAM
109 *
110 * Function will place try to place VRAM at base address provided
111 * as parameter (which is so far either PCI aperture address or
112 * for IGP TOM base address).
113 *
114 * If there is not enough space to fit the unvisible VRAM in the 32bits
115 * address space then we limit the VRAM size to the aperture.
116 *
117 * If we are using AGP and if the AGP aperture doesn't allow us to have
118 * room for all the VRAM than we restrict the VRAM to the PCI aperture
119 * size and print a warning.
120 *
121 * This function will never fails, worst case are limiting VRAM.
122 *
123 * Note: GTT start, end, size should be initialized before calling this
124 * function on AGP platform.
125 *
126 * Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
127 * this shouldn't be a problem as we are using the PCI aperture as a reference.
128 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
129 * not IGP.
130 *
131 * Note: we use mc_vram_size as on some board we need to program the mc to
132 * cover the whole aperture even if VRAM size is inferior to aperture size
133 * Novell bug 204882 + along with lots of ubuntu ones
134 *
135 * Note: when limiting vram it's safe to overwritte real_vram_size because
136 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
137 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
138 * ones)
139 *
140 * Note: IGP TOM addr should be the same as the aperture addr, we don't
141 * explicitly check for that thought.
142 *
143 * FIXME: when reducing VRAM size align new size on power of 2.
771fe6b9 144 */
d594e46a 145void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
771fe6b9 146{
d594e46a
JG		 147 mc->vram_start = base;
148 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
149 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
150 mc->real_vram_size = mc->aper_size;
151 mc->mc_vram_size = mc->aper_size;
152 }
153 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
154 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) {
155 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
156 mc->real_vram_size = mc->aper_size;
157 mc->mc_vram_size = mc->aper_size;
158 }
159 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
160 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
161 mc->mc_vram_size >> 20, mc->vram_start,
162 mc->vram_end, mc->real_vram_size >> 20);
163}
771fe6b9 164
d594e46a
JG		 165/**
166 * radeon_gtt_location - try to find GTT location
167 * @rdev: radeon device structure holding all necessary informations
168 * @mc: memory controller structure holding memory informations
169 *
170 * Function will place try to place GTT before or after VRAM.
171 *
172 * If GTT size is bigger than space left then we ajust GTT size.
173 * Thus function will never fails.
174 *
175 * FIXME: when reducing GTT size align new size on power of 2.
176 */
177void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
178{
179 u64 size_af, size_bf;
180
181 size_af = 0xFFFFFFFF - mc->vram_end;
182 size_bf = mc->vram_start;
183 if (size_bf > size_af) {
184 if (mc->gtt_size > size_bf) {
185 dev_warn(rdev->dev, "limiting GTT\n");
186 mc->gtt_size = size_bf;
771fe6b9 187 }
d594e46a 188 mc->gtt_start = mc->vram_start - mc->gtt_size;
771fe6b9 189 } else {
d594e46a
JG		 190 if (mc->gtt_size > size_af) {
191 dev_warn(rdev->dev, "limiting GTT\n");
192 mc->gtt_size = size_af;
193 }
194 mc->gtt_start = mc->vram_end + 1;
771fe6b9 195 }
d594e46a
JG		 196 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
197 dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
198 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
771fe6b9
JG		 199}
200
771fe6b9
JG		 201/*
202 * GPU helpers function.
203 */
9f022ddf 204bool radeon_card_posted(struct radeon_device *rdev)
771fe6b9
JG		 205{
206 uint32_t reg;
207
208 /* first check CRTCs */
bcc1c2a1
AD		 209 if (ASIC_IS_DCE4(rdev)) {
210 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
211 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
212 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
213 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
214 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
215 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
216 if (reg & EVERGREEN_CRTC_MASTER_EN)
217 return true;
218 } else if (ASIC_IS_AVIVO(rdev)) {
771fe6b9
JG		 219 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
220 RREG32(AVIVO_D2CRTC_CONTROL);
221 if (reg & AVIVO_CRTC_EN) {
222 return true;
223 }
224 } else {
225 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
226 RREG32(RADEON_CRTC2_GEN_CNTL);
227 if (reg & RADEON_CRTC_EN) {
228 return true;
229 }
230 }
231
232 /* then check MEM_SIZE, in case the crtcs are off */
233 if (rdev->family >= CHIP_R600)
234 reg = RREG32(R600_CONFIG_MEMSIZE);
235 else
236 reg = RREG32(RADEON_CONFIG_MEMSIZE);
237
238 if (reg)
239 return true;
240
241 return false;
242
243}
244
72542d77
DA		 245bool radeon_boot_test_post_card(struct radeon_device *rdev)
246{
247 if (radeon_card_posted(rdev))
248 return true;
249
250 if (rdev->bios) {
251 DRM_INFO("GPU not posted. posting now...\n");
252 if (rdev->is_atom_bios)
253 atom_asic_init(rdev->mode_info.atom_context);
254 else
255 radeon_combios_asic_init(rdev->ddev);
256 return true;
257 } else {
258 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
259 return false;
260 }
261}
262
3ce0a23d
JG		 263int radeon_dummy_page_init(struct radeon_device *rdev)
264{
82568565
DA		 265 if (rdev->dummy_page.page)
266 return 0;
3ce0a23d
JG		 267 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
268 if (rdev->dummy_page.page == NULL)
269 return -ENOMEM;
270 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
271 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
272 if (!rdev->dummy_page.addr) {
273 __free_page(rdev->dummy_page.page);
274 rdev->dummy_page.page = NULL;
275 return -ENOMEM;
276 }
277 return 0;
278}
279
280void radeon_dummy_page_fini(struct radeon_device *rdev)
281{
282 if (rdev->dummy_page.page == NULL)
283 return;
284 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
285 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
286 __free_page(rdev->dummy_page.page);
287 rdev->dummy_page.page = NULL;
288}
289
771fe6b9
JG		 290
291/*
292 * Registers accessors functions.
293 */
294uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
295{
296 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
297 BUG_ON(1);
298 return 0;
299}
300
301void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
302{
303 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
304 reg, v);
305 BUG_ON(1);
306}
307
308void radeon_register_accessor_init(struct radeon_device *rdev)
309{
771fe6b9
JG		 310 rdev->mc_rreg = &radeon_invalid_rreg;
311 rdev->mc_wreg = &radeon_invalid_wreg;
312 rdev->pll_rreg = &radeon_invalid_rreg;
313 rdev->pll_wreg = &radeon_invalid_wreg;
771fe6b9
JG		 314 rdev->pciep_rreg = &radeon_invalid_rreg;
315 rdev->pciep_wreg = &radeon_invalid_wreg;
316
317 /* Don't change order as we are overridding accessor. */
318 if (rdev->family < CHIP_RV515) {
de1b2898
DA		 319 rdev->pcie_reg_mask = 0xff;
320 } else {
321 rdev->pcie_reg_mask = 0x7ff;
771fe6b9
JG		 322 }
323 /* FIXME: not sure here */
324 if (rdev->family <= CHIP_R580) {
325 rdev->pll_rreg = &r100_pll_rreg;
326 rdev->pll_wreg = &r100_pll_wreg;
327 }
905b6822
JG		 328 if (rdev->family >= CHIP_R420) {
329 rdev->mc_rreg = &r420_mc_rreg;
330 rdev->mc_wreg = &r420_mc_wreg;
331 }
771fe6b9
JG		 332 if (rdev->family >= CHIP_RV515) {
333 rdev->mc_rreg = &rv515_mc_rreg;
334 rdev->mc_wreg = &rv515_mc_wreg;
335 }
336 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
337 rdev->mc_rreg = &rs400_mc_rreg;
338 rdev->mc_wreg = &rs400_mc_wreg;
339 }
340 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
341 rdev->mc_rreg = &rs690_mc_rreg;
342 rdev->mc_wreg = &rs690_mc_wreg;
343 }
344 if (rdev->family == CHIP_RS600) {
345 rdev->mc_rreg = &rs600_mc_rreg;
346 rdev->mc_wreg = &rs600_mc_wreg;
347 }
bcc1c2a1 348 if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
771fe6b9
JG		 349 rdev->pciep_rreg = &r600_pciep_rreg;
350 rdev->pciep_wreg = &r600_pciep_wreg;
351 }
352}
353
354
355/*
356 * ASIC
357 */
358int radeon_asic_init(struct radeon_device *rdev)
359{
360 radeon_register_accessor_init(rdev);
361 switch (rdev->family) {
362 case CHIP_R100:
363 case CHIP_RV100:
364 case CHIP_RS100:
365 case CHIP_RV200:
366 case CHIP_RS200:
44ca7478
PN		 367 rdev->asic = &r100_asic;
368 break;
771fe6b9
JG		 369 case CHIP_R200:
370 case CHIP_RV250:
371 case CHIP_RS300:
372 case CHIP_RV280:
44ca7478 373 rdev->asic = &r200_asic;
771fe6b9
JG		 374 break;
375 case CHIP_R300:
376 case CHIP_R350:
377 case CHIP_RV350:
378 case CHIP_RV380:
d80eeb0f
PN		 379 if (rdev->flags & RADEON_IS_PCIE)
380 rdev->asic = &r300_asic_pcie;
381 else
382 rdev->asic = &r300_asic;
771fe6b9
JG		 383 break;
384 case CHIP_R420:
385 case CHIP_R423:
386 case CHIP_RV410:
387 rdev->asic = &r420_asic;
388 break;
389 case CHIP_RS400:
390 case CHIP_RS480:
391 rdev->asic = &rs400_asic;
392 break;
393 case CHIP_RS600:
394 rdev->asic = &rs600_asic;
395 break;
396 case CHIP_RS690:
397 case CHIP_RS740:
398 rdev->asic = &rs690_asic;
399 break;
400 case CHIP_RV515:
401 rdev->asic = &rv515_asic;
402 break;
403 case CHIP_R520:
404 case CHIP_RV530:
405 case CHIP_RV560:
406 case CHIP_RV570:
407 case CHIP_R580:
408 rdev->asic = &r520_asic;
409 break;
410 case CHIP_R600:
411 case CHIP_RV610:
412 case CHIP_RV630:
413 case CHIP_RV620:
414 case CHIP_RV635:
415 case CHIP_RV670:
416 case CHIP_RS780:
3ce0a23d
JG		 417 case CHIP_RS880:
418 rdev->asic = &r600_asic;
419 break;
771fe6b9
JG		 420 case CHIP_RV770:
421 case CHIP_RV730:
422 case CHIP_RV710:
3ce0a23d
JG		 423 case CHIP_RV740:
424 rdev->asic = &rv770_asic;
425 break;
bcc1c2a1
AD		 426 case CHIP_CEDAR:
427 case CHIP_REDWOOD:
428 case CHIP_JUNIPER:
429 case CHIP_CYPRESS:
430 case CHIP_HEMLOCK:
431 rdev->asic = &evergreen_asic;
432 break;
771fe6b9
JG		 433 default:
434 /* FIXME: not supported yet */
435 return -EINVAL;
436 }
5ea597f3
RM		 437
438 if (rdev->flags & RADEON_IS_IGP) {
439 rdev->asic->get_memory_clock = NULL;
440 rdev->asic->set_memory_clock = NULL;
441 }
442
771fe6b9
JG		 443 return 0;
444}
445
446
447/*
448 * Wrapper around modesetting bits.
449 */
450int radeon_clocks_init(struct radeon_device *rdev)
451{
452 int r;
453
771fe6b9
JG		 454 r = radeon_static_clocks_init(rdev->ddev);
455 if (r) {
456 return r;
457 }
458 DRM_INFO("Clocks initialized !\n");
459 return 0;
460}
461
462void radeon_clocks_fini(struct radeon_device *rdev)
463{
464}
465
466/* ATOM accessor methods */
467static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
468{
469 struct radeon_device *rdev = info->dev->dev_private;
470 uint32_t r;
471
472 r = rdev->pll_rreg(rdev, reg);
473 return r;
474}
475
476static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
477{
478 struct radeon_device *rdev = info->dev->dev_private;
479
480 rdev->pll_wreg(rdev, reg, val);
481}
482
483static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
484{
485 struct radeon_device *rdev = info->dev->dev_private;
486 uint32_t r;
487
488 r = rdev->mc_rreg(rdev, reg);
489 return r;
490}
491
492static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
493{
494 struct radeon_device *rdev = info->dev->dev_private;
495
496 rdev->mc_wreg(rdev, reg, val);
497}
498
499static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
500{
501 struct radeon_device *rdev = info->dev->dev_private;
502
503 WREG32(reg*4, val);
504}
505
506static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
507{
508 struct radeon_device *rdev = info->dev->dev_private;
509 uint32_t r;
510
511 r = RREG32(reg*4);
512 return r;
513}
514
771fe6b9
JG		 515int radeon_atombios_init(struct radeon_device *rdev)
516{
61c4b24b
MF		 517 struct card_info *atom_card_info =
518 kzalloc(sizeof(struct card_info), GFP_KERNEL);
519
520 if (!atom_card_info)
521 return -ENOMEM;
522
523 rdev->mode_info.atom_card_info = atom_card_info;
524 atom_card_info->dev = rdev->ddev;
525 atom_card_info->reg_read = cail_reg_read;
526 atom_card_info->reg_write = cail_reg_write;
527 atom_card_info->mc_read = cail_mc_read;
528 atom_card_info->mc_write = cail_mc_write;
529 atom_card_info->pll_read = cail_pll_read;
530 atom_card_info->pll_write = cail_pll_write;
531
532 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
c31ad97f 533 mutex_init(&rdev->mode_info.atom_context->mutex);
771fe6b9 534 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
d904ef9b 535 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
771fe6b9
JG		 536 return 0;
537}
538
539void radeon_atombios_fini(struct radeon_device *rdev)
540{
4a04a844
JG		 541 if (rdev->mode_info.atom_context) {
542 kfree(rdev->mode_info.atom_context->scratch);
543 kfree(rdev->mode_info.atom_context);
544 }
61c4b24b 545 kfree(rdev->mode_info.atom_card_info);
771fe6b9
JG		 546}
547
548int radeon_combios_init(struct radeon_device *rdev)
549{
550 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
551 return 0;
552}
553
554void radeon_combios_fini(struct radeon_device *rdev)
555{
556}
557
28d52043
DA		 558/* if we get transitioned to only one device, tak VGA back */
559static unsigned int radeon_vga_set_decode(void *cookie, bool state)
560{
561 struct radeon_device *rdev = cookie;
28d52043
DA		 562 radeon_vga_set_state(rdev, state);
563 if (state)
564 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
565 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
566 else
567 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
568}
c1176d6f 569
b574f251
JG		 570void radeon_agp_disable(struct radeon_device *rdev)
571{
572 rdev->flags &= ~RADEON_IS_AGP;
573 if (rdev->family >= CHIP_R600) {
574 DRM_INFO("Forcing AGP to PCIE mode\n");
575 rdev->flags |= RADEON_IS_PCIE;
576 } else if (rdev->family >= CHIP_RV515 ||
577 rdev->family == CHIP_RV380 ||
578 rdev->family == CHIP_RV410 ||
579 rdev->family == CHIP_R423) {
580 DRM_INFO("Forcing AGP to PCIE mode\n");
581 rdev->flags |= RADEON_IS_PCIE;
582 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
583 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
584 } else {
585 DRM_INFO("Forcing AGP to PCI mode\n");
586 rdev->flags |= RADEON_IS_PCI;
587 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
588 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
589 }
700a0cc0 590 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
b574f251 591}
771fe6b9 592
36421338
JG		 593void radeon_check_arguments(struct radeon_device *rdev)
594{
595 /* vramlimit must be a power of two */
596 switch (radeon_vram_limit) {
597 case 0:
598 case 4:
599 case 8:
600 case 16:
601 case 32:
602 case 64:
603 case 128:
604 case 256:
605 case 512:
606 case 1024:
607 case 2048:
608 case 4096:
609 break;
610 default:
611 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
612 radeon_vram_limit);
613 radeon_vram_limit = 0;
614 break;
615 }
616 radeon_vram_limit = radeon_vram_limit << 20;
617 /* gtt size must be power of two and greater or equal to 32M */
618 switch (radeon_gart_size) {
619 case 4:
620 case 8:
621 case 16:
622 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
623 radeon_gart_size);
624 radeon_gart_size = 512;
625 break;
626 case 32:
627 case 64:
628 case 128:
629 case 256:
630 case 512:
631 case 1024:
632 case 2048:
633 case 4096:
634 break;
635 default:
636 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
637 radeon_gart_size);
638 radeon_gart_size = 512;
639 break;
640 }
641 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
642 /* AGP mode can only be -1, 1, 2, 4, 8 */
643 switch (radeon_agpmode) {
644 case -1:
645 case 0:
646 case 1:
647 case 2:
648 case 4:
649 case 8:
650 break;
651 default:
652 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
653 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
654 radeon_agpmode = 0;
655 break;
656 }
657}
658
6a9ee8af
DA		 659static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
660{
661 struct drm_device *dev = pci_get_drvdata(pdev);
662 struct radeon_device *rdev = dev->dev_private;
663 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
664 if (state == VGA_SWITCHEROO_ON) {
665 printk(KERN_INFO "radeon: switched on\n");
666 /* don't suspend or resume card normally */
667 rdev->powered_down = false;
668 radeon_resume_kms(dev);
669 } else {
670 printk(KERN_INFO "radeon: switched off\n");
671 radeon_suspend_kms(dev, pmm);
672 /* don't suspend or resume card normally */
673 rdev->powered_down = true;
674 }
675}
676
677static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
678{
679 struct drm_device *dev = pci_get_drvdata(pdev);
680 bool can_switch;
681
682 spin_lock(&dev->count_lock);
683 can_switch = (dev->open_count == 0);
684 spin_unlock(&dev->count_lock);
685 return can_switch;
686}
687
688
771fe6b9
JG		 689int radeon_device_init(struct radeon_device *rdev,
690 struct drm_device *ddev,
691 struct pci_dev *pdev,
692 uint32_t flags)
693{
6cf8a3f5 694 int r;
ad49f501 695 int dma_bits;
771fe6b9
JG		 696
697 DRM_INFO("radeon: Initializing kernel modesetting.\n");
698 rdev->shutdown = false;
9f022ddf 699 rdev->dev = &pdev->dev;
771fe6b9
JG		 700 rdev->ddev = ddev;
701 rdev->pdev = pdev;
702 rdev->flags = flags;
703 rdev->family = flags & RADEON_FAMILY_MASK;
704 rdev->is_atom_bios = false;
705 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
706 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
707 rdev->gpu_lockup = false;
733289c2 708 rdev->accel_working = false;
771fe6b9
JG		 709 /* mutex initialization are all done here so we
710 * can recall function without having locking issues */
711 mutex_init(&rdev->cs_mutex);
712 mutex_init(&rdev->ib_pool.mutex);
713 mutex_init(&rdev->cp.mutex);
40bacf16 714 mutex_init(&rdev->dc_hw_i2c_mutex);
d8f60cfc
AD		 715 if (rdev->family >= CHIP_R600)
716 spin_lock_init(&rdev->ih.lock);
4c788679 717 mutex_init(&rdev->gem.mutex);
c913e23a 718 mutex_init(&rdev->pm.mutex);
771fe6b9 719 rwlock_init(&rdev->fence_drv.lock);
9f022ddf 720 INIT_LIST_HEAD(&rdev->gem.objects);
73a6d3fc 721 init_waitqueue_head(&rdev->irq.vblank_queue);
771fe6b9 722
d4877cf2
AD		 723 /* setup workqueue */
724 rdev->wq = create_workqueue("radeon");
725 if (rdev->wq == NULL)
726 return -ENOMEM;
727
4aac0473
JG		 728 /* Set asic functions */
729 r = radeon_asic_init(rdev);
36421338 730 if (r)
4aac0473 731 return r;
36421338 732 radeon_check_arguments(rdev);
4aac0473 733
30256a3f 734 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
b574f251 735 radeon_agp_disable(rdev);
771fe6b9
JG		 736 }
737
ad49f501
DA		 738 /* set DMA mask + need_dma32 flags.
739 * PCIE - can handle 40-bits.
740 * IGP - can handle 40-bits (in theory)
741 * AGP - generally dma32 is safest
742 * PCI - only dma32
743 */
744 rdev->need_dma32 = false;
745 if (rdev->flags & RADEON_IS_AGP)
746 rdev->need_dma32 = true;
747 if (rdev->flags & RADEON_IS_PCI)
748 rdev->need_dma32 = true;
749
750 dma_bits = rdev->need_dma32 ? 32 : 40;
751 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
771fe6b9
JG		 752 if (r) {
753 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
754 }
755
756 /* Registers mapping */
757 /* TODO: block userspace mapping of io register */
758 rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
759 rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
760 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
761 if (rdev->rmmio == NULL) {
762 return -ENOMEM;
763 }
764 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
765 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
766
28d52043 767 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
93239ea1
DA		 768 /* this will fail for cards that aren't VGA class devices, just
769 * ignore it */
770 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
6a9ee8af
DA		 771 vga_switcheroo_register_client(rdev->pdev,
772 radeon_switcheroo_set_state,
773 radeon_switcheroo_can_switch);
28d52043 774
3ce0a23d 775 r = radeon_init(rdev);
b574f251 776 if (r)
3ce0a23d 777 return r;
3ce0a23d 778
b574f251
JG		 779 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
780 /* Acceleration not working on AGP card try again
781 * with fallback to PCI or PCIE GART
782 */
1a029b76 783 radeon_gpu_reset(rdev);
b574f251
JG		 784 radeon_fini(rdev);
785 radeon_agp_disable(rdev);
786 r = radeon_init(rdev);
4aac0473
JG		 787 if (r)
788 return r;
771fe6b9 789 }
ecc0b326
MD		 790 if (radeon_testing) {
791 radeon_test_moves(rdev);
792 }
771fe6b9
JG		 793 if (radeon_benchmarking) {
794 radeon_benchmark(rdev);
795 }
6cf8a3f5 796 return 0;
771fe6b9
JG		 797}
798
799void radeon_device_fini(struct radeon_device *rdev)
800{
771fe6b9
JG		 801 DRM_INFO("radeon: finishing device.\n");
802 rdev->shutdown = true;
62a8ea3f 803 radeon_fini(rdev);
d4877cf2 804 destroy_workqueue(rdev->wq);
6a9ee8af 805 vga_switcheroo_unregister_client(rdev->pdev);
c1176d6f 806 vga_client_register(rdev->pdev, NULL, NULL, NULL);
771fe6b9
JG		 807 iounmap(rdev->rmmio);
808 rdev->rmmio = NULL;
809}
810
811
812/*
813 * Suspend & resume.
814 */
815int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
816{
875c1866 817 struct radeon_device *rdev;
771fe6b9 818 struct drm_crtc *crtc;
4c788679 819 int r;
771fe6b9 820
875c1866 821 if (dev == NULL || dev->dev_private == NULL) {
771fe6b9
JG		 822 return -ENODEV;
823 }
824 if (state.event == PM_EVENT_PRETHAW) {
825 return 0;
826 }
875c1866
DJ		 827 rdev = dev->dev_private;
828
6a9ee8af
DA		 829 if (rdev->powered_down)
830 return 0;
771fe6b9
JG		 831 /* unpin the front buffers */
832 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
833 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
4c788679 834 struct radeon_bo *robj;
771fe6b9
JG		 835
836 if (rfb == NULL || rfb->obj == NULL) {
837 continue;
838 }
839 robj = rfb->obj->driver_private;
4c788679
JG		 840 if (robj != rdev->fbdev_rbo) {
841 r = radeon_bo_reserve(robj, false);
842 if (unlikely(r == 0)) {
843 radeon_bo_unpin(robj);
844 radeon_bo_unreserve(robj);
845 }
771fe6b9
JG		 846 }
847 }
848 /* evict vram memory */
4c788679 849 radeon_bo_evict_vram(rdev);
771fe6b9
JG		 850 /* wait for gpu to finish processing current batch */
851 radeon_fence_wait_last(rdev);
852
f657c2a7
YZ		 853 radeon_save_bios_scratch_regs(rdev);
854
62a8ea3f 855 radeon_suspend(rdev);
d4877cf2 856 radeon_hpd_fini(rdev);
771fe6b9 857 /* evict remaining vram memory */
4c788679 858 radeon_bo_evict_vram(rdev);
771fe6b9 859
771fe6b9
JG		 860 pci_save_state(dev->pdev);
861 if (state.event == PM_EVENT_SUSPEND) {
862 /* Shut down the device */
863 pci_disable_device(dev->pdev);
864 pci_set_power_state(dev->pdev, PCI_D3hot);
865 }
866 acquire_console_sem();
867 fb_set_suspend(rdev->fbdev_info, 1);
868 release_console_sem();
869 return 0;
870}
871
872int radeon_resume_kms(struct drm_device *dev)
873{
874 struct radeon_device *rdev = dev->dev_private;
771fe6b9 875
6a9ee8af
DA		 876 if (rdev->powered_down)
877 return 0;
878
771fe6b9
JG		 879 acquire_console_sem();
880 pci_set_power_state(dev->pdev, PCI_D0);
881 pci_restore_state(dev->pdev);
882 if (pci_enable_device(dev->pdev)) {
883 release_console_sem();
884 return -1;
885 }
886 pci_set_master(dev->pdev);
0ebf1717
DA		 887 /* resume AGP if in use */
888 radeon_agp_resume(rdev);
62a8ea3f 889 radeon_resume(rdev);
f657c2a7 890 radeon_restore_bios_scratch_regs(rdev);
771fe6b9
JG		 891 fb_set_suspend(rdev->fbdev_info, 0);
892 release_console_sem();
893
d4877cf2
AD		 894 /* reset hpd state */
895 radeon_hpd_init(rdev);
771fe6b9
JG		 896 /* blat the mode back in */
897 drm_helper_resume_force_mode(dev);
898 return 0;
899}
900
901
902/*
903 * Debugfs
904 */
905struct radeon_debugfs {
906 struct drm_info_list *files;
907 unsigned num_files;
908};
909static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
910static unsigned _radeon_debugfs_count = 0;
911
912int radeon_debugfs_add_files(struct radeon_device *rdev,
913 struct drm_info_list *files,
914 unsigned nfiles)
915{
916 unsigned i;
917
918 for (i = 0; i < _radeon_debugfs_count; i++) {
919 if (_radeon_debugfs[i].files == files) {
920 /* Already registered */
921 return 0;
922 }
923 }
924 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
925 DRM_ERROR("Reached maximum number of debugfs files.\n");
926 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
927 return -EINVAL;
928 }
929 _radeon_debugfs[_radeon_debugfs_count].files = files;
930 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
931 _radeon_debugfs_count++;
932#if defined(CONFIG_DEBUG_FS)
933 drm_debugfs_create_files(files, nfiles,
934 rdev->ddev->control->debugfs_root,
935 rdev->ddev->control);
936 drm_debugfs_create_files(files, nfiles,
937 rdev->ddev->primary->debugfs_root,
938 rdev->ddev->primary);
939#endif
940 return 0;
941}
942
943#if defined(CONFIG_DEBUG_FS)
944int radeon_debugfs_init(struct drm_minor *minor)
945{
946 return 0;
947}
948
949void radeon_debugfs_cleanup(struct drm_minor *minor)
950{
951 unsigned i;
952
953 for (i = 0; i < _radeon_debugfs_count; i++) {
954 drm_debugfs_remove_files(_radeon_debugfs[i].files,
955 _radeon_debugfs[i].num_files, minor);
956 }
957}
958#endif
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