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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include "drmP.h" | |
27 | #include "radeon_drm.h" | |
28 | #include "radeon.h" | |
29 | ||
30 | #include "atom.h" | |
31 | #include <asm/div64.h> | |
32 | ||
33 | #include "drm_crtc_helper.h" | |
34 | #include "drm_edid.h" | |
35 | ||
36 | static int radeon_ddc_dump(struct drm_connector *connector); | |
37 | ||
38 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) | |
39 | { | |
40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
41 | struct drm_device *dev = crtc->dev; | |
42 | struct radeon_device *rdev = dev->dev_private; | |
43 | int i; | |
44 | ||
45 | DRM_DEBUG("%d\n", radeon_crtc->crtc_id); | |
46 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); | |
47 | ||
48 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); | |
49 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); | |
50 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); | |
51 | ||
52 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); | |
53 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); | |
54 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); | |
55 | ||
56 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); | |
57 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); | |
58 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); | |
59 | ||
60 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); | |
61 | for (i = 0; i < 256; i++) { | |
62 | WREG32(AVIVO_DC_LUT_30_COLOR, | |
63 | (radeon_crtc->lut_r[i] << 20) | | |
64 | (radeon_crtc->lut_g[i] << 10) | | |
65 | (radeon_crtc->lut_b[i] << 0)); | |
66 | } | |
67 | ||
68 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); | |
69 | } | |
70 | ||
71 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) | |
72 | { | |
73 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
74 | struct drm_device *dev = crtc->dev; | |
75 | struct radeon_device *rdev = dev->dev_private; | |
76 | int i; | |
77 | uint32_t dac2_cntl; | |
78 | ||
79 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); | |
80 | if (radeon_crtc->crtc_id == 0) | |
81 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; | |
82 | else | |
83 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; | |
84 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); | |
85 | ||
86 | WREG8(RADEON_PALETTE_INDEX, 0); | |
87 | for (i = 0; i < 256; i++) { | |
88 | WREG32(RADEON_PALETTE_30_DATA, | |
89 | (radeon_crtc->lut_r[i] << 20) | | |
90 | (radeon_crtc->lut_g[i] << 10) | | |
91 | (radeon_crtc->lut_b[i] << 0)); | |
92 | } | |
93 | } | |
94 | ||
95 | void radeon_crtc_load_lut(struct drm_crtc *crtc) | |
96 | { | |
97 | struct drm_device *dev = crtc->dev; | |
98 | struct radeon_device *rdev = dev->dev_private; | |
99 | ||
100 | if (!crtc->enabled) | |
101 | return; | |
102 | ||
103 | if (ASIC_IS_AVIVO(rdev)) | |
104 | avivo_crtc_load_lut(crtc); | |
105 | else | |
106 | legacy_crtc_load_lut(crtc); | |
107 | } | |
108 | ||
b8c00ac5 | 109 | /** Sets the color ramps on behalf of fbcon */ |
771fe6b9 JG |
110 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
111 | u16 blue, int regno) | |
112 | { | |
113 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
114 | ||
771fe6b9 JG |
115 | radeon_crtc->lut_r[regno] = red >> 6; |
116 | radeon_crtc->lut_g[regno] = green >> 6; | |
117 | radeon_crtc->lut_b[regno] = blue >> 6; | |
118 | } | |
119 | ||
b8c00ac5 DA |
120 | /** Gets the color ramps on behalf of fbcon */ |
121 | void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, | |
122 | u16 *blue, int regno) | |
123 | { | |
124 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
125 | ||
126 | *red = radeon_crtc->lut_r[regno] << 6; | |
127 | *green = radeon_crtc->lut_g[regno] << 6; | |
128 | *blue = radeon_crtc->lut_b[regno] << 6; | |
129 | } | |
130 | ||
771fe6b9 JG |
131 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
132 | u16 *blue, uint32_t size) | |
133 | { | |
134 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
b8c00ac5 | 135 | int i; |
771fe6b9 JG |
136 | |
137 | if (size != 256) { | |
138 | return; | |
139 | } | |
771fe6b9 | 140 | |
b8c00ac5 DA |
141 | /* userspace palettes are always correct as is */ |
142 | for (i = 0; i < 256; i++) { | |
143 | radeon_crtc->lut_r[i] = red[i] >> 6; | |
144 | radeon_crtc->lut_g[i] = green[i] >> 6; | |
145 | radeon_crtc->lut_b[i] = blue[i] >> 6; | |
771fe6b9 | 146 | } |
771fe6b9 JG |
147 | radeon_crtc_load_lut(crtc); |
148 | } | |
149 | ||
150 | static void radeon_crtc_destroy(struct drm_crtc *crtc) | |
151 | { | |
152 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
153 | ||
771fe6b9 JG |
154 | drm_crtc_cleanup(crtc); |
155 | kfree(radeon_crtc); | |
156 | } | |
157 | ||
158 | static const struct drm_crtc_funcs radeon_crtc_funcs = { | |
159 | .cursor_set = radeon_crtc_cursor_set, | |
160 | .cursor_move = radeon_crtc_cursor_move, | |
161 | .gamma_set = radeon_crtc_gamma_set, | |
162 | .set_config = drm_crtc_helper_set_config, | |
163 | .destroy = radeon_crtc_destroy, | |
164 | }; | |
165 | ||
166 | static void radeon_crtc_init(struct drm_device *dev, int index) | |
167 | { | |
168 | struct radeon_device *rdev = dev->dev_private; | |
169 | struct radeon_crtc *radeon_crtc; | |
170 | int i; | |
171 | ||
172 | radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
173 | if (radeon_crtc == NULL) | |
174 | return; | |
175 | ||
176 | drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); | |
177 | ||
178 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); | |
179 | radeon_crtc->crtc_id = index; | |
c93bb85b | 180 | rdev->mode_info.crtcs[index] = radeon_crtc; |
771fe6b9 | 181 | |
785b93ef | 182 | #if 0 |
771fe6b9 JG |
183 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
184 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); | |
185 | radeon_crtc->mode_set.num_connectors = 0; | |
785b93ef | 186 | #endif |
771fe6b9 JG |
187 | |
188 | for (i = 0; i < 256; i++) { | |
189 | radeon_crtc->lut_r[i] = i << 2; | |
190 | radeon_crtc->lut_g[i] = i << 2; | |
191 | radeon_crtc->lut_b[i] = i << 2; | |
192 | } | |
193 | ||
194 | if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) | |
195 | radeon_atombios_init_crtc(dev, radeon_crtc); | |
196 | else | |
197 | radeon_legacy_init_crtc(dev, radeon_crtc); | |
198 | } | |
199 | ||
200 | static const char *encoder_names[34] = { | |
201 | "NONE", | |
202 | "INTERNAL_LVDS", | |
203 | "INTERNAL_TMDS1", | |
204 | "INTERNAL_TMDS2", | |
205 | "INTERNAL_DAC1", | |
206 | "INTERNAL_DAC2", | |
207 | "INTERNAL_SDVOA", | |
208 | "INTERNAL_SDVOB", | |
209 | "SI170B", | |
210 | "CH7303", | |
211 | "CH7301", | |
212 | "INTERNAL_DVO1", | |
213 | "EXTERNAL_SDVOA", | |
214 | "EXTERNAL_SDVOB", | |
215 | "TITFP513", | |
216 | "INTERNAL_LVTM1", | |
217 | "VT1623", | |
218 | "HDMI_SI1930", | |
219 | "HDMI_INTERNAL", | |
220 | "INTERNAL_KLDSCP_TMDS1", | |
221 | "INTERNAL_KLDSCP_DVO1", | |
222 | "INTERNAL_KLDSCP_DAC1", | |
223 | "INTERNAL_KLDSCP_DAC2", | |
224 | "SI178", | |
225 | "MVPU_FPGA", | |
226 | "INTERNAL_DDI", | |
227 | "VT1625", | |
228 | "HDMI_SI1932", | |
229 | "DP_AN9801", | |
230 | "DP_DP501", | |
231 | "INTERNAL_UNIPHY", | |
232 | "INTERNAL_KLDSCP_LVTMA", | |
233 | "INTERNAL_UNIPHY1", | |
234 | "INTERNAL_UNIPHY2", | |
235 | }; | |
236 | ||
237 | static const char *connector_names[13] = { | |
238 | "Unknown", | |
239 | "VGA", | |
240 | "DVI-I", | |
241 | "DVI-D", | |
242 | "DVI-A", | |
243 | "Composite", | |
244 | "S-video", | |
245 | "LVDS", | |
246 | "Component", | |
247 | "DIN", | |
248 | "DisplayPort", | |
249 | "HDMI-A", | |
250 | "HDMI-B", | |
251 | }; | |
252 | ||
eed45b30 AD |
253 | static const char *hpd_names[7] = { |
254 | "NONE", | |
255 | "HPD1", | |
256 | "HPD2", | |
257 | "HPD3", | |
258 | "HPD4", | |
259 | "HPD5", | |
260 | "HPD6", | |
261 | }; | |
262 | ||
771fe6b9 JG |
263 | static void radeon_print_display_setup(struct drm_device *dev) |
264 | { | |
265 | struct drm_connector *connector; | |
266 | struct radeon_connector *radeon_connector; | |
267 | struct drm_encoder *encoder; | |
268 | struct radeon_encoder *radeon_encoder; | |
269 | uint32_t devices; | |
270 | int i = 0; | |
271 | ||
272 | DRM_INFO("Radeon Display Connectors\n"); | |
273 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
274 | radeon_connector = to_radeon_connector(connector); | |
275 | DRM_INFO("Connector %d:\n", i); | |
276 | DRM_INFO(" %s\n", connector_names[connector->connector_type]); | |
eed45b30 AD |
277 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
278 | DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); | |
771fe6b9 JG |
279 | if (radeon_connector->ddc_bus) |
280 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", | |
281 | radeon_connector->ddc_bus->rec.mask_clk_reg, | |
282 | radeon_connector->ddc_bus->rec.mask_data_reg, | |
283 | radeon_connector->ddc_bus->rec.a_clk_reg, | |
284 | radeon_connector->ddc_bus->rec.a_data_reg, | |
9b9fe724 AD |
285 | radeon_connector->ddc_bus->rec.en_clk_reg, |
286 | radeon_connector->ddc_bus->rec.en_data_reg, | |
287 | radeon_connector->ddc_bus->rec.y_clk_reg, | |
288 | radeon_connector->ddc_bus->rec.y_data_reg); | |
771fe6b9 JG |
289 | DRM_INFO(" Encoders:\n"); |
290 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
291 | radeon_encoder = to_radeon_encoder(encoder); | |
292 | devices = radeon_encoder->devices & radeon_connector->devices; | |
293 | if (devices) { | |
294 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) | |
295 | DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
296 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) | |
297 | DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
298 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) | |
299 | DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
300 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) | |
301 | DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
302 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) | |
303 | DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
304 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) | |
305 | DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
306 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) | |
307 | DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
308 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) | |
309 | DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
310 | if (devices & ATOM_DEVICE_TV1_SUPPORT) | |
311 | DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
312 | if (devices & ATOM_DEVICE_CV_SUPPORT) | |
313 | DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
314 | } | |
315 | } | |
316 | i++; | |
317 | } | |
318 | } | |
319 | ||
4ce001ab | 320 | static bool radeon_setup_enc_conn(struct drm_device *dev) |
771fe6b9 JG |
321 | { |
322 | struct radeon_device *rdev = dev->dev_private; | |
323 | struct drm_connector *drm_connector; | |
324 | bool ret = false; | |
325 | ||
326 | if (rdev->bios) { | |
327 | if (rdev->is_atom_bios) { | |
328 | if (rdev->family >= CHIP_R600) | |
329 | ret = radeon_get_atom_connector_info_from_object_table(dev); | |
330 | else | |
331 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); | |
332 | } else | |
333 | ret = radeon_get_legacy_connector_info_from_bios(dev); | |
334 | } else { | |
335 | if (!ASIC_IS_AVIVO(rdev)) | |
336 | ret = radeon_get_legacy_connector_info_from_table(dev); | |
337 | } | |
338 | if (ret) { | |
1f3b6a45 | 339 | radeon_setup_encoder_clones(dev); |
771fe6b9 JG |
340 | radeon_print_display_setup(dev); |
341 | list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) | |
342 | radeon_ddc_dump(drm_connector); | |
343 | } | |
344 | ||
345 | return ret; | |
346 | } | |
347 | ||
348 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) | |
349 | { | |
771fe6b9 JG |
350 | int ret = 0; |
351 | ||
746c1aa4 DA |
352 | if (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) { |
353 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; | |
9fa05c98 AD |
354 | if (dig->dp_i2c_bus) |
355 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter); | |
746c1aa4 | 356 | } |
771fe6b9 JG |
357 | if (!radeon_connector->ddc_bus) |
358 | return -1; | |
4ce001ab | 359 | if (!radeon_connector->edid) { |
ab1e9ea0 | 360 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); |
0294cf4f | 361 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); |
ab1e9ea0 | 362 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); |
0294cf4f AD |
363 | } |
364 | ||
365 | if (radeon_connector->edid) { | |
366 | drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); | |
367 | ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); | |
771fe6b9 JG |
368 | return ret; |
369 | } | |
370 | drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); | |
42dea5dd | 371 | return 0; |
771fe6b9 JG |
372 | } |
373 | ||
374 | static int radeon_ddc_dump(struct drm_connector *connector) | |
375 | { | |
376 | struct edid *edid; | |
377 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
378 | int ret = 0; | |
379 | ||
380 | if (!radeon_connector->ddc_bus) | |
381 | return -1; | |
ab1e9ea0 | 382 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); |
771fe6b9 | 383 | edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); |
ab1e9ea0 | 384 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); |
771fe6b9 JG |
385 | if (edid) { |
386 | kfree(edid); | |
387 | } | |
388 | return ret; | |
389 | } | |
390 | ||
391 | static inline uint32_t radeon_div(uint64_t n, uint32_t d) | |
392 | { | |
393 | uint64_t mod; | |
394 | ||
395 | n += d / 2; | |
396 | ||
397 | mod = do_div(n, d); | |
398 | return n; | |
399 | } | |
400 | ||
401 | void radeon_compute_pll(struct radeon_pll *pll, | |
402 | uint64_t freq, | |
403 | uint32_t *dot_clock_p, | |
404 | uint32_t *fb_div_p, | |
405 | uint32_t *frac_fb_div_p, | |
406 | uint32_t *ref_div_p, | |
407 | uint32_t *post_div_p, | |
408 | int flags) | |
409 | { | |
410 | uint32_t min_ref_div = pll->min_ref_div; | |
411 | uint32_t max_ref_div = pll->max_ref_div; | |
412 | uint32_t min_fractional_feed_div = 0; | |
413 | uint32_t max_fractional_feed_div = 0; | |
414 | uint32_t best_vco = pll->best_vco; | |
415 | uint32_t best_post_div = 1; | |
416 | uint32_t best_ref_div = 1; | |
417 | uint32_t best_feedback_div = 1; | |
418 | uint32_t best_frac_feedback_div = 0; | |
419 | uint32_t best_freq = -1; | |
420 | uint32_t best_error = 0xffffffff; | |
421 | uint32_t best_vco_diff = 1; | |
422 | uint32_t post_div; | |
423 | ||
424 | DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); | |
425 | freq = freq * 1000; | |
426 | ||
427 | if (flags & RADEON_PLL_USE_REF_DIV) | |
428 | min_ref_div = max_ref_div = pll->reference_div; | |
429 | else { | |
430 | while (min_ref_div < max_ref_div-1) { | |
431 | uint32_t mid = (min_ref_div + max_ref_div) / 2; | |
432 | uint32_t pll_in = pll->reference_freq / mid; | |
433 | if (pll_in < pll->pll_in_min) | |
434 | max_ref_div = mid; | |
435 | else if (pll_in > pll->pll_in_max) | |
436 | min_ref_div = mid; | |
437 | else | |
438 | break; | |
439 | } | |
440 | } | |
441 | ||
442 | if (flags & RADEON_PLL_USE_FRAC_FB_DIV) { | |
443 | min_fractional_feed_div = pll->min_frac_feedback_div; | |
444 | max_fractional_feed_div = pll->max_frac_feedback_div; | |
445 | } | |
446 | ||
447 | for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) { | |
448 | uint32_t ref_div; | |
449 | ||
450 | if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) | |
451 | continue; | |
452 | ||
453 | /* legacy radeons only have a few post_divs */ | |
454 | if (flags & RADEON_PLL_LEGACY) { | |
455 | if ((post_div == 5) || | |
456 | (post_div == 7) || | |
457 | (post_div == 9) || | |
458 | (post_div == 10) || | |
459 | (post_div == 11) || | |
460 | (post_div == 13) || | |
461 | (post_div == 14) || | |
462 | (post_div == 15)) | |
463 | continue; | |
464 | } | |
465 | ||
466 | for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { | |
467 | uint32_t feedback_div, current_freq = 0, error, vco_diff; | |
468 | uint32_t pll_in = pll->reference_freq / ref_div; | |
469 | uint32_t min_feed_div = pll->min_feedback_div; | |
470 | uint32_t max_feed_div = pll->max_feedback_div + 1; | |
471 | ||
472 | if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) | |
473 | continue; | |
474 | ||
475 | while (min_feed_div < max_feed_div) { | |
476 | uint32_t vco; | |
477 | uint32_t min_frac_feed_div = min_fractional_feed_div; | |
478 | uint32_t max_frac_feed_div = max_fractional_feed_div + 1; | |
479 | uint32_t frac_feedback_div; | |
480 | uint64_t tmp; | |
481 | ||
482 | feedback_div = (min_feed_div + max_feed_div) / 2; | |
483 | ||
484 | tmp = (uint64_t)pll->reference_freq * feedback_div; | |
485 | vco = radeon_div(tmp, ref_div); | |
486 | ||
487 | if (vco < pll->pll_out_min) { | |
488 | min_feed_div = feedback_div + 1; | |
489 | continue; | |
490 | } else if (vco > pll->pll_out_max) { | |
491 | max_feed_div = feedback_div; | |
492 | continue; | |
493 | } | |
494 | ||
495 | while (min_frac_feed_div < max_frac_feed_div) { | |
496 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; | |
497 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; | |
498 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; | |
499 | current_freq = radeon_div(tmp, ref_div * post_div); | |
500 | ||
d0e275a9 AD |
501 | if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
502 | error = freq - current_freq; | |
503 | error = error < 0 ? 0xffffffff : error; | |
504 | } else | |
505 | error = abs(current_freq - freq); | |
771fe6b9 JG |
506 | vco_diff = abs(vco - best_vco); |
507 | ||
508 | if ((best_vco == 0 && error < best_error) || | |
509 | (best_vco != 0 && | |
510 | (error < best_error - 100 || | |
511 | (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { | |
512 | best_post_div = post_div; | |
513 | best_ref_div = ref_div; | |
514 | best_feedback_div = feedback_div; | |
515 | best_frac_feedback_div = frac_feedback_div; | |
516 | best_freq = current_freq; | |
517 | best_error = error; | |
518 | best_vco_diff = vco_diff; | |
519 | } else if (current_freq == freq) { | |
520 | if (best_freq == -1) { | |
521 | best_post_div = post_div; | |
522 | best_ref_div = ref_div; | |
523 | best_feedback_div = feedback_div; | |
524 | best_frac_feedback_div = frac_feedback_div; | |
525 | best_freq = current_freq; | |
526 | best_error = error; | |
527 | best_vco_diff = vco_diff; | |
528 | } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || | |
529 | ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || | |
530 | ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || | |
531 | ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || | |
532 | ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || | |
533 | ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { | |
534 | best_post_div = post_div; | |
535 | best_ref_div = ref_div; | |
536 | best_feedback_div = feedback_div; | |
537 | best_frac_feedback_div = frac_feedback_div; | |
538 | best_freq = current_freq; | |
539 | best_error = error; | |
540 | best_vco_diff = vco_diff; | |
541 | } | |
542 | } | |
543 | if (current_freq < freq) | |
544 | min_frac_feed_div = frac_feedback_div + 1; | |
545 | else | |
546 | max_frac_feed_div = frac_feedback_div; | |
547 | } | |
548 | if (current_freq < freq) | |
549 | min_feed_div = feedback_div + 1; | |
550 | else | |
551 | max_feed_div = feedback_div; | |
552 | } | |
553 | } | |
554 | } | |
555 | ||
556 | *dot_clock_p = best_freq / 10000; | |
557 | *fb_div_p = best_feedback_div; | |
558 | *frac_fb_div_p = best_frac_feedback_div; | |
559 | *ref_div_p = best_ref_div; | |
560 | *post_div_p = best_post_div; | |
561 | } | |
562 | ||
b27b6375 AD |
563 | void radeon_compute_pll_avivo(struct radeon_pll *pll, |
564 | uint64_t freq, | |
565 | uint32_t *dot_clock_p, | |
566 | uint32_t *fb_div_p, | |
567 | uint32_t *frac_fb_div_p, | |
568 | uint32_t *ref_div_p, | |
569 | uint32_t *post_div_p, | |
570 | int flags) | |
571 | { | |
572 | fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq; | |
573 | fixed20_12 pll_out_max, pll_out_min; | |
574 | fixed20_12 pll_in_max, pll_in_min; | |
575 | fixed20_12 reference_freq; | |
576 | fixed20_12 error, ffreq, a, b; | |
577 | ||
578 | pll_out_max.full = rfixed_const(pll->pll_out_max); | |
579 | pll_out_min.full = rfixed_const(pll->pll_out_min); | |
580 | pll_in_max.full = rfixed_const(pll->pll_in_max); | |
581 | pll_in_min.full = rfixed_const(pll->pll_in_min); | |
582 | reference_freq.full = rfixed_const(pll->reference_freq); | |
583 | do_div(freq, 10); | |
584 | ffreq.full = rfixed_const(freq); | |
585 | error.full = rfixed_const(100 * 100); | |
586 | ||
587 | /* max p */ | |
588 | p.full = rfixed_div(pll_out_max, ffreq); | |
589 | p.full = rfixed_floor(p); | |
590 | ||
591 | /* min m */ | |
592 | m.full = rfixed_div(reference_freq, pll_in_max); | |
593 | m.full = rfixed_ceil(m); | |
594 | ||
595 | while (1) { | |
596 | n.full = rfixed_div(ffreq, reference_freq); | |
597 | n.full = rfixed_mul(n, m); | |
598 | n.full = rfixed_mul(n, p); | |
599 | ||
600 | f_vco.full = rfixed_div(n, m); | |
601 | f_vco.full = rfixed_mul(f_vco, reference_freq); | |
602 | ||
603 | f_pclk.full = rfixed_div(f_vco, p); | |
604 | ||
605 | if (f_pclk.full > ffreq.full) | |
606 | error.full = f_pclk.full - ffreq.full; | |
607 | else | |
608 | error.full = ffreq.full - f_pclk.full; | |
609 | error.full = rfixed_div(error, f_pclk); | |
610 | a.full = rfixed_const(100 * 100); | |
611 | error.full = rfixed_mul(error, a); | |
612 | ||
613 | a.full = rfixed_mul(m, p); | |
614 | a.full = rfixed_div(n, a); | |
615 | best_freq.full = rfixed_mul(reference_freq, a); | |
616 | ||
617 | if (rfixed_trunc(error) < 25) | |
618 | break; | |
619 | ||
620 | a.full = rfixed_const(1); | |
621 | m.full = m.full + a.full; | |
622 | a.full = rfixed_div(reference_freq, m); | |
623 | if (a.full >= pll_in_min.full) | |
624 | continue; | |
625 | ||
626 | m.full = rfixed_div(reference_freq, pll_in_max); | |
627 | m.full = rfixed_ceil(m); | |
628 | a.full= rfixed_const(1); | |
629 | p.full = p.full - a.full; | |
630 | a.full = rfixed_mul(p, ffreq); | |
631 | if (a.full >= pll_out_min.full) | |
632 | continue; | |
633 | else { | |
634 | DRM_ERROR("Unable to find pll dividers\n"); | |
635 | break; | |
636 | } | |
637 | } | |
638 | ||
639 | a.full = rfixed_const(10); | |
640 | b.full = rfixed_mul(n, a); | |
641 | ||
642 | frac_n.full = rfixed_floor(n); | |
643 | frac_n.full = rfixed_mul(frac_n, a); | |
644 | frac_n.full = b.full - frac_n.full; | |
645 | ||
646 | *dot_clock_p = rfixed_trunc(best_freq); | |
647 | *fb_div_p = rfixed_trunc(n); | |
648 | *frac_fb_div_p = rfixed_trunc(frac_n); | |
649 | *ref_div_p = rfixed_trunc(m); | |
650 | *post_div_p = rfixed_trunc(p); | |
651 | ||
652 | DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p); | |
653 | } | |
654 | ||
771fe6b9 JG |
655 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) |
656 | { | |
657 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); | |
658 | struct drm_device *dev = fb->dev; | |
659 | ||
660 | if (fb->fbdev) | |
661 | radeonfb_remove(dev, fb); | |
662 | ||
663 | if (radeon_fb->obj) { | |
664 | radeon_gem_object_unpin(radeon_fb->obj); | |
665 | mutex_lock(&dev->struct_mutex); | |
666 | drm_gem_object_unreference(radeon_fb->obj); | |
667 | mutex_unlock(&dev->struct_mutex); | |
668 | } | |
669 | drm_framebuffer_cleanup(fb); | |
670 | kfree(radeon_fb); | |
671 | } | |
672 | ||
673 | static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
674 | struct drm_file *file_priv, | |
675 | unsigned int *handle) | |
676 | { | |
677 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); | |
678 | ||
679 | return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); | |
680 | } | |
681 | ||
682 | static const struct drm_framebuffer_funcs radeon_fb_funcs = { | |
683 | .destroy = radeon_user_framebuffer_destroy, | |
684 | .create_handle = radeon_user_framebuffer_create_handle, | |
685 | }; | |
686 | ||
687 | struct drm_framebuffer * | |
688 | radeon_framebuffer_create(struct drm_device *dev, | |
689 | struct drm_mode_fb_cmd *mode_cmd, | |
690 | struct drm_gem_object *obj) | |
691 | { | |
692 | struct radeon_framebuffer *radeon_fb; | |
693 | ||
694 | radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); | |
695 | if (radeon_fb == NULL) { | |
696 | return NULL; | |
697 | } | |
698 | drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs); | |
699 | drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd); | |
700 | radeon_fb->obj = obj; | |
701 | return &radeon_fb->base; | |
702 | } | |
703 | ||
704 | static struct drm_framebuffer * | |
705 | radeon_user_framebuffer_create(struct drm_device *dev, | |
706 | struct drm_file *file_priv, | |
707 | struct drm_mode_fb_cmd *mode_cmd) | |
708 | { | |
709 | struct drm_gem_object *obj; | |
710 | ||
711 | obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); | |
712 | ||
713 | return radeon_framebuffer_create(dev, mode_cmd, obj); | |
714 | } | |
715 | ||
716 | static const struct drm_mode_config_funcs radeon_mode_funcs = { | |
717 | .fb_create = radeon_user_framebuffer_create, | |
718 | .fb_changed = radeonfb_probe, | |
719 | }; | |
720 | ||
445282db DA |
721 | struct drm_prop_enum_list { |
722 | int type; | |
723 | char *name; | |
724 | }; | |
725 | ||
726 | static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = | |
727 | { { 0, "driver" }, | |
728 | { 1, "bios" }, | |
729 | }; | |
730 | ||
731 | static struct drm_prop_enum_list radeon_tv_std_enum_list[] = | |
732 | { { TV_STD_NTSC, "ntsc" }, | |
733 | { TV_STD_PAL, "pal" }, | |
734 | { TV_STD_PAL_M, "pal-m" }, | |
735 | { TV_STD_PAL_60, "pal-60" }, | |
736 | { TV_STD_NTSC_J, "ntsc-j" }, | |
737 | { TV_STD_SCART_PAL, "scart-pal" }, | |
738 | { TV_STD_PAL_CN, "pal-cn" }, | |
739 | { TV_STD_SECAM, "secam" }, | |
740 | }; | |
741 | ||
d79766fa | 742 | static int radeon_modeset_create_props(struct radeon_device *rdev) |
445282db DA |
743 | { |
744 | int i, sz; | |
745 | ||
746 | if (rdev->is_atom_bios) { | |
747 | rdev->mode_info.coherent_mode_property = | |
748 | drm_property_create(rdev->ddev, | |
749 | DRM_MODE_PROP_RANGE, | |
750 | "coherent", 2); | |
751 | if (!rdev->mode_info.coherent_mode_property) | |
752 | return -ENOMEM; | |
753 | ||
754 | rdev->mode_info.coherent_mode_property->values[0] = 0; | |
390d0bbe | 755 | rdev->mode_info.coherent_mode_property->values[1] = 1; |
445282db DA |
756 | } |
757 | ||
758 | if (!ASIC_IS_AVIVO(rdev)) { | |
759 | sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); | |
760 | rdev->mode_info.tmds_pll_property = | |
761 | drm_property_create(rdev->ddev, | |
762 | DRM_MODE_PROP_ENUM, | |
763 | "tmds_pll", sz); | |
764 | for (i = 0; i < sz; i++) { | |
765 | drm_property_add_enum(rdev->mode_info.tmds_pll_property, | |
766 | i, | |
767 | radeon_tmds_pll_enum_list[i].type, | |
768 | radeon_tmds_pll_enum_list[i].name); | |
769 | } | |
770 | } | |
771 | ||
772 | rdev->mode_info.load_detect_property = | |
773 | drm_property_create(rdev->ddev, | |
774 | DRM_MODE_PROP_RANGE, | |
775 | "load detection", 2); | |
776 | if (!rdev->mode_info.load_detect_property) | |
777 | return -ENOMEM; | |
778 | rdev->mode_info.load_detect_property->values[0] = 0; | |
390d0bbe | 779 | rdev->mode_info.load_detect_property->values[1] = 1; |
445282db DA |
780 | |
781 | drm_mode_create_scaling_mode_property(rdev->ddev); | |
782 | ||
783 | sz = ARRAY_SIZE(radeon_tv_std_enum_list); | |
784 | rdev->mode_info.tv_std_property = | |
785 | drm_property_create(rdev->ddev, | |
786 | DRM_MODE_PROP_ENUM, | |
787 | "tv standard", sz); | |
788 | for (i = 0; i < sz; i++) { | |
789 | drm_property_add_enum(rdev->mode_info.tv_std_property, | |
790 | i, | |
791 | radeon_tv_std_enum_list[i].type, | |
792 | radeon_tv_std_enum_list[i].name); | |
793 | } | |
794 | ||
795 | return 0; | |
796 | } | |
797 | ||
771fe6b9 JG |
798 | int radeon_modeset_init(struct radeon_device *rdev) |
799 | { | |
800 | int num_crtc = 2, i; | |
801 | int ret; | |
802 | ||
803 | drm_mode_config_init(rdev->ddev); | |
804 | rdev->mode_info.mode_config_initialized = true; | |
805 | ||
806 | rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs; | |
807 | ||
808 | if (ASIC_IS_AVIVO(rdev)) { | |
809 | rdev->ddev->mode_config.max_width = 8192; | |
810 | rdev->ddev->mode_config.max_height = 8192; | |
811 | } else { | |
812 | rdev->ddev->mode_config.max_width = 4096; | |
813 | rdev->ddev->mode_config.max_height = 4096; | |
814 | } | |
815 | ||
816 | rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; | |
817 | ||
445282db DA |
818 | ret = radeon_modeset_create_props(rdev); |
819 | if (ret) { | |
820 | return ret; | |
821 | } | |
dfee5614 DA |
822 | |
823 | if (rdev->flags & RADEON_SINGLE_CRTC) | |
824 | num_crtc = 1; | |
825 | ||
826 | /* allocate crtcs */ | |
771fe6b9 JG |
827 | for (i = 0; i < num_crtc; i++) { |
828 | radeon_crtc_init(rdev->ddev, i); | |
829 | } | |
830 | ||
831 | /* okay we should have all the bios connectors */ | |
832 | ret = radeon_setup_enc_conn(rdev->ddev); | |
833 | if (!ret) { | |
834 | return ret; | |
835 | } | |
d4877cf2 AD |
836 | /* initialize hpd */ |
837 | radeon_hpd_init(rdev); | |
771fe6b9 JG |
838 | drm_helper_initial_config(rdev->ddev); |
839 | return 0; | |
840 | } | |
841 | ||
842 | void radeon_modeset_fini(struct radeon_device *rdev) | |
843 | { | |
844 | if (rdev->mode_info.mode_config_initialized) { | |
d4877cf2 | 845 | radeon_hpd_fini(rdev); |
771fe6b9 JG |
846 | drm_mode_config_cleanup(rdev->ddev); |
847 | rdev->mode_info.mode_config_initialized = false; | |
848 | } | |
849 | } | |
850 | ||
c93bb85b JG |
851 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
852 | struct drm_display_mode *mode, | |
853 | struct drm_display_mode *adjusted_mode) | |
771fe6b9 | 854 | { |
c93bb85b JG |
855 | struct drm_device *dev = crtc->dev; |
856 | struct drm_encoder *encoder; | |
857 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
858 | struct radeon_encoder *radeon_encoder; | |
859 | bool first = true; | |
771fe6b9 | 860 | |
c93bb85b JG |
861 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
862 | radeon_encoder = to_radeon_encoder(encoder); | |
863 | if (encoder->crtc != crtc) | |
864 | continue; | |
865 | if (first) { | |
80297e87 AD |
866 | /* set scaling */ |
867 | if (radeon_encoder->rmx_type == RMX_OFF) | |
868 | radeon_crtc->rmx_type = RMX_OFF; | |
869 | else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || | |
870 | mode->vdisplay < radeon_encoder->native_mode.vdisplay) | |
871 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; | |
872 | else | |
873 | radeon_crtc->rmx_type = RMX_OFF; | |
874 | /* copy native mode */ | |
c93bb85b | 875 | memcpy(&radeon_crtc->native_mode, |
80297e87 | 876 | &radeon_encoder->native_mode, |
de2103e4 | 877 | sizeof(struct drm_display_mode)); |
c93bb85b JG |
878 | first = false; |
879 | } else { | |
880 | if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { | |
881 | /* WARNING: Right now this can't happen but | |
882 | * in the future we need to check that scaling | |
883 | * are consistent accross different encoder | |
884 | * (ie all encoder can work with the same | |
885 | * scaling). | |
886 | */ | |
887 | DRM_ERROR("Scaling not consistent accross encoder.\n"); | |
888 | return false; | |
889 | } | |
771fe6b9 JG |
890 | } |
891 | } | |
c93bb85b JG |
892 | if (radeon_crtc->rmx_type != RMX_OFF) { |
893 | fixed20_12 a, b; | |
894 | a.full = rfixed_const(crtc->mode.vdisplay); | |
de2103e4 | 895 | b.full = rfixed_const(radeon_crtc->native_mode.hdisplay); |
c93bb85b JG |
896 | radeon_crtc->vsc.full = rfixed_div(a, b); |
897 | a.full = rfixed_const(crtc->mode.hdisplay); | |
de2103e4 | 898 | b.full = rfixed_const(radeon_crtc->native_mode.vdisplay); |
c93bb85b | 899 | radeon_crtc->hsc.full = rfixed_div(a, b); |
771fe6b9 | 900 | } else { |
c93bb85b JG |
901 | radeon_crtc->vsc.full = rfixed_const(1); |
902 | radeon_crtc->hsc.full = rfixed_const(1); | |
771fe6b9 | 903 | } |
c93bb85b | 904 | return true; |
771fe6b9 | 905 | } |