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drm/radeon/kms: update new pll algo
[mirror_ubuntu-kernels.git] / drivers / gpu / drm / radeon / radeon_display.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include <asm/div64.h>
32
33#include "drm_crtc_helper.h"
34#include "drm_edid.h"
35
36static int radeon_ddc_dump(struct drm_connector *connector);
37
38static void avivo_crtc_load_lut(struct drm_crtc *crtc)
39{
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 struct drm_device *dev = crtc->dev;
42 struct radeon_device *rdev = dev->dev_private;
43 int i;
44
45 DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
47
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
51
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
55
56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
59
60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61 for (i = 0; i < 256; i++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR,
63 (radeon_crtc->lut_r[i] << 20) |
64 (radeon_crtc->lut_g[i] << 10) |
65 (radeon_crtc->lut_b[i] << 0));
66 }
67
68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
69}
70
bcc1c2a1
AD		 71static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
72{
73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74 struct drm_device *dev = crtc->dev;
75 struct radeon_device *rdev = dev->dev_private;
76 int i;
77
78 DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
79 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
80
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
84
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
88
89 WREG32(EVERGREEN_DC_LUT_RW_MODE, radeon_crtc->crtc_id);
90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK, 0x00000007);
91
92 WREG32(EVERGREEN_DC_LUT_RW_INDEX, 0);
93 for (i = 0; i < 256; i++) {
94 WREG32(EVERGREEN_DC_LUT_30_COLOR,
95 (radeon_crtc->lut_r[i] << 20) |
96 (radeon_crtc->lut_g[i] << 10) |
97 (radeon_crtc->lut_b[i] << 0));
98 }
99}
100
771fe6b9
JG		 101static void legacy_crtc_load_lut(struct drm_crtc *crtc)
102{
103 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
104 struct drm_device *dev = crtc->dev;
105 struct radeon_device *rdev = dev->dev_private;
106 int i;
107 uint32_t dac2_cntl;
108
109 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
110 if (radeon_crtc->crtc_id == 0)
111 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
112 else
113 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
114 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
115
116 WREG8(RADEON_PALETTE_INDEX, 0);
117 for (i = 0; i < 256; i++) {
118 WREG32(RADEON_PALETTE_30_DATA,
119 (radeon_crtc->lut_r[i] << 20) |
120 (radeon_crtc->lut_g[i] << 10) |
121 (radeon_crtc->lut_b[i] << 0));
122 }
123}
124
125void radeon_crtc_load_lut(struct drm_crtc *crtc)
126{
127 struct drm_device *dev = crtc->dev;
128 struct radeon_device *rdev = dev->dev_private;
129
130 if (!crtc->enabled)
131 return;
132
bcc1c2a1
AD		 133 if (ASIC_IS_DCE4(rdev))
134 evergreen_crtc_load_lut(crtc);
135 else if (ASIC_IS_AVIVO(rdev))
771fe6b9
JG		 136 avivo_crtc_load_lut(crtc);
137 else
138 legacy_crtc_load_lut(crtc);
139}
140
b8c00ac5 141/** Sets the color ramps on behalf of fbcon */
771fe6b9
JG		 142void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
143 u16 blue, int regno)
144{
145 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
146
771fe6b9
JG		 147 radeon_crtc->lut_r[regno] = red >> 6;
148 radeon_crtc->lut_g[regno] = green >> 6;
149 radeon_crtc->lut_b[regno] = blue >> 6;
150}
151
b8c00ac5
DA		 152/** Gets the color ramps on behalf of fbcon */
153void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
154 u16 *blue, int regno)
155{
156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
157
158 *red = radeon_crtc->lut_r[regno] << 6;
159 *green = radeon_crtc->lut_g[regno] << 6;
160 *blue = radeon_crtc->lut_b[regno] << 6;
161}
162
771fe6b9
JG		 163static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
164 u16 *blue, uint32_t size)
165{
166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
b8c00ac5 167 int i;
771fe6b9
JG		 168
169 if (size != 256) {
170 return;
171 }
771fe6b9 172
b8c00ac5
DA		 173 /* userspace palettes are always correct as is */
174 for (i = 0; i < 256; i++) {
175 radeon_crtc->lut_r[i] = red[i] >> 6;
176 radeon_crtc->lut_g[i] = green[i] >> 6;
177 radeon_crtc->lut_b[i] = blue[i] >> 6;
771fe6b9 178 }
771fe6b9
JG		 179 radeon_crtc_load_lut(crtc);
180}
181
182static void radeon_crtc_destroy(struct drm_crtc *crtc)
183{
184 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
185
771fe6b9
JG		 186 drm_crtc_cleanup(crtc);
187 kfree(radeon_crtc);
188}
189
190static const struct drm_crtc_funcs radeon_crtc_funcs = {
191 .cursor_set = radeon_crtc_cursor_set,
192 .cursor_move = radeon_crtc_cursor_move,
193 .gamma_set = radeon_crtc_gamma_set,
194 .set_config = drm_crtc_helper_set_config,
195 .destroy = radeon_crtc_destroy,
196};
197
198static void radeon_crtc_init(struct drm_device *dev, int index)
199{
200 struct radeon_device *rdev = dev->dev_private;
201 struct radeon_crtc *radeon_crtc;
202 int i;
203
204 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
205 if (radeon_crtc == NULL)
206 return;
207
208 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
209
210 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
211 radeon_crtc->crtc_id = index;
c93bb85b 212 rdev->mode_info.crtcs[index] = radeon_crtc;
771fe6b9 213
785b93ef 214#if 0
771fe6b9
JG		 215 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
216 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
217 radeon_crtc->mode_set.num_connectors = 0;
785b93ef 218#endif
771fe6b9
JG		 219
220 for (i = 0; i < 256; i++) {
221 radeon_crtc->lut_r[i] = i << 2;
222 radeon_crtc->lut_g[i] = i << 2;
223 radeon_crtc->lut_b[i] = i << 2;
224 }
225
226 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
227 radeon_atombios_init_crtc(dev, radeon_crtc);
228 else
229 radeon_legacy_init_crtc(dev, radeon_crtc);
230}
231
232static const char *encoder_names[34] = {
233 "NONE",
234 "INTERNAL_LVDS",
235 "INTERNAL_TMDS1",
236 "INTERNAL_TMDS2",
237 "INTERNAL_DAC1",
238 "INTERNAL_DAC2",
239 "INTERNAL_SDVOA",
240 "INTERNAL_SDVOB",
241 "SI170B",
242 "CH7303",
243 "CH7301",
244 "INTERNAL_DVO1",
245 "EXTERNAL_SDVOA",
246 "EXTERNAL_SDVOB",
247 "TITFP513",
248 "INTERNAL_LVTM1",
249 "VT1623",
250 "HDMI_SI1930",
251 "HDMI_INTERNAL",
252 "INTERNAL_KLDSCP_TMDS1",
253 "INTERNAL_KLDSCP_DVO1",
254 "INTERNAL_KLDSCP_DAC1",
255 "INTERNAL_KLDSCP_DAC2",
256 "SI178",
257 "MVPU_FPGA",
258 "INTERNAL_DDI",
259 "VT1625",
260 "HDMI_SI1932",
261 "DP_AN9801",
262 "DP_DP501",
263 "INTERNAL_UNIPHY",
264 "INTERNAL_KLDSCP_LVTMA",
265 "INTERNAL_UNIPHY1",
266 "INTERNAL_UNIPHY2",
267};
268
196c58d2 269static const char *connector_names[15] = {
771fe6b9
JG		 270 "Unknown",
271 "VGA",
272 "DVI-I",
273 "DVI-D",
274 "DVI-A",
275 "Composite",
276 "S-video",
277 "LVDS",
278 "Component",
279 "DIN",
280 "DisplayPort",
281 "HDMI-A",
282 "HDMI-B",
196c58d2
AD		 283 "TV",
284 "eDP",
771fe6b9
JG		 285};
286
eed45b30
AD		 287static const char *hpd_names[7] = {
288 "NONE",
289 "HPD1",
290 "HPD2",
291 "HPD3",
292 "HPD4",
293 "HPD5",
294 "HPD6",
295};
296
771fe6b9
JG		 297static void radeon_print_display_setup(struct drm_device *dev)
298{
299 struct drm_connector *connector;
300 struct radeon_connector *radeon_connector;
301 struct drm_encoder *encoder;
302 struct radeon_encoder *radeon_encoder;
303 uint32_t devices;
304 int i = 0;
305
306 DRM_INFO("Radeon Display Connectors\n");
307 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
308 radeon_connector = to_radeon_connector(connector);
309 DRM_INFO("Connector %d:\n", i);
310 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
eed45b30
AD		 311 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
312 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
771fe6b9
JG		 313 if (radeon_connector->ddc_bus)
314 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
315 radeon_connector->ddc_bus->rec.mask_clk_reg,
316 radeon_connector->ddc_bus->rec.mask_data_reg,
317 radeon_connector->ddc_bus->rec.a_clk_reg,
318 radeon_connector->ddc_bus->rec.a_data_reg,
9b9fe724
AD		 319 radeon_connector->ddc_bus->rec.en_clk_reg,
320 radeon_connector->ddc_bus->rec.en_data_reg,
321 radeon_connector->ddc_bus->rec.y_clk_reg,
322 radeon_connector->ddc_bus->rec.y_data_reg);
771fe6b9
JG		 323 DRM_INFO(" Encoders:\n");
324 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
325 radeon_encoder = to_radeon_encoder(encoder);
326 devices = radeon_encoder->devices & radeon_connector->devices;
327 if (devices) {
328 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
329 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
330 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
331 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
332 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
333 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
334 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
335 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
336 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
337 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
338 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
339 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
340 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
341 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
342 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
343 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
344 if (devices & ATOM_DEVICE_TV1_SUPPORT)
345 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
346 if (devices & ATOM_DEVICE_CV_SUPPORT)
347 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
348 }
349 }
350 i++;
351 }
352}
353
4ce001ab 354static bool radeon_setup_enc_conn(struct drm_device *dev)
771fe6b9
JG		 355{
356 struct radeon_device *rdev = dev->dev_private;
357 struct drm_connector *drm_connector;
358 bool ret = false;
359
360 if (rdev->bios) {
361 if (rdev->is_atom_bios) {
362 if (rdev->family >= CHIP_R600)
363 ret = radeon_get_atom_connector_info_from_object_table(dev);
364 else
365 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
b9597a1c 366 } else {
771fe6b9 367 ret = radeon_get_legacy_connector_info_from_bios(dev);
b9597a1c
AD		 368 if (ret == false)
369 ret = radeon_get_legacy_connector_info_from_table(dev);
370 }
771fe6b9
JG		 371 } else {
372 if (!ASIC_IS_AVIVO(rdev))
373 ret = radeon_get_legacy_connector_info_from_table(dev);
374 }
375 if (ret) {
1f3b6a45 376 radeon_setup_encoder_clones(dev);
771fe6b9
JG		 377 radeon_print_display_setup(dev);
378 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
379 radeon_ddc_dump(drm_connector);
380 }
381
382 return ret;
383}
384
385int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
386{
3c537889
AD		 387 struct drm_device *dev = radeon_connector->base.dev;
388 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 389 int ret = 0;
390
196c58d2
AD		 391 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
392 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
746c1aa4 393 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
7a15cbd4
DA		 394 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
395 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
9fa05c98 396 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
746c1aa4 397 }
771fe6b9
JG		 398 if (!radeon_connector->ddc_bus)
399 return -1;
4ce001ab 400 if (!radeon_connector->edid) {
0294cf4f 401 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
0294cf4f 402 }
3c537889
AD		 403 /* some servers provide a hardcoded edid in rom for KVMs */
404 if (!radeon_connector->edid)
405 radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev);
0294cf4f
AD		 406 if (radeon_connector->edid) {
407 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
408 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
771fe6b9
JG		 409 return ret;
410 }
411 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
42dea5dd 412 return 0;
771fe6b9
JG		 413}
414
415static int radeon_ddc_dump(struct drm_connector *connector)
416{
417 struct edid *edid;
418 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
419 int ret = 0;
420
421 if (!radeon_connector->ddc_bus)
422 return -1;
771fe6b9 423 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
771fe6b9
JG		 424 if (edid) {
425 kfree(edid);
426 }
427 return ret;
428}
429
430static inline uint32_t radeon_div(uint64_t n, uint32_t d)
431{
432 uint64_t mod;
433
434 n += d / 2;
435
436 mod = do_div(n, d);
437 return n;
438}
439
7c27f87d
AD		 440static void radeon_compute_pll_legacy(struct radeon_pll *pll,
441 uint64_t freq,
442 uint32_t *dot_clock_p,
443 uint32_t *fb_div_p,
444 uint32_t *frac_fb_div_p,
445 uint32_t *ref_div_p,
446 uint32_t *post_div_p)
771fe6b9
JG		 447{
448 uint32_t min_ref_div = pll->min_ref_div;
449 uint32_t max_ref_div = pll->max_ref_div;
fc10332b
AD		 450 uint32_t min_post_div = pll->min_post_div;
451 uint32_t max_post_div = pll->max_post_div;
771fe6b9
JG		 452 uint32_t min_fractional_feed_div = 0;
453 uint32_t max_fractional_feed_div = 0;
454 uint32_t best_vco = pll->best_vco;
455 uint32_t best_post_div = 1;
456 uint32_t best_ref_div = 1;
457 uint32_t best_feedback_div = 1;
458 uint32_t best_frac_feedback_div = 0;
459 uint32_t best_freq = -1;
460 uint32_t best_error = 0xffffffff;
461 uint32_t best_vco_diff = 1;
462 uint32_t post_div;
463
464 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
465 freq = freq * 1000;
466
fc10332b 467 if (pll->flags & RADEON_PLL_USE_REF_DIV)
771fe6b9
JG		 468 min_ref_div = max_ref_div = pll->reference_div;
469 else {
470 while (min_ref_div < max_ref_div-1) {
471 uint32_t mid = (min_ref_div + max_ref_div) / 2;
472 uint32_t pll_in = pll->reference_freq / mid;
473 if (pll_in < pll->pll_in_min)
474 max_ref_div = mid;
475 else if (pll_in > pll->pll_in_max)
476 min_ref_div = mid;
477 else
478 break;
479 }
480 }
481
fc10332b
AD		 482 if (pll->flags & RADEON_PLL_USE_POST_DIV)
483 min_post_div = max_post_div = pll->post_div;
484
485 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
771fe6b9
JG		 486 min_fractional_feed_div = pll->min_frac_feedback_div;
487 max_fractional_feed_div = pll->max_frac_feedback_div;
488 }
489
fc10332b 490 for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
771fe6b9
JG		 491 uint32_t ref_div;
492
fc10332b 493 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
771fe6b9
JG		 494 continue;
495
496 /* legacy radeons only have a few post_divs */
fc10332b 497 if (pll->flags & RADEON_PLL_LEGACY) {
771fe6b9
JG		 498 if ((post_div == 5) ||
499 (post_div == 7) ||
500 (post_div == 9) ||
501 (post_div == 10) ||
502 (post_div == 11) ||
503 (post_div == 13) ||
504 (post_div == 14) ||
505 (post_div == 15))
506 continue;
507 }
508
509 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
510 uint32_t feedback_div, current_freq = 0, error, vco_diff;
511 uint32_t pll_in = pll->reference_freq / ref_div;
512 uint32_t min_feed_div = pll->min_feedback_div;
513 uint32_t max_feed_div = pll->max_feedback_div + 1;
514
515 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
516 continue;
517
518 while (min_feed_div < max_feed_div) {
519 uint32_t vco;
520 uint32_t min_frac_feed_div = min_fractional_feed_div;
521 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
522 uint32_t frac_feedback_div;
523 uint64_t tmp;
524
525 feedback_div = (min_feed_div + max_feed_div) / 2;
526
527 tmp = (uint64_t)pll->reference_freq * feedback_div;
528 vco = radeon_div(tmp, ref_div);
529
530 if (vco < pll->pll_out_min) {
531 min_feed_div = feedback_div + 1;
532 continue;
533 } else if (vco > pll->pll_out_max) {
534 max_feed_div = feedback_div;
535 continue;
536 }
537
538 while (min_frac_feed_div < max_frac_feed_div) {
539 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
540 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
541 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
542 current_freq = radeon_div(tmp, ref_div * post_div);
543
fc10332b 544 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
d0e275a9
AD		 545 error = freq - current_freq;
546 error = error < 0 ? 0xffffffff : error;
547 } else
548 error = abs(current_freq - freq);
771fe6b9
JG		 549 vco_diff = abs(vco - best_vco);
550
551 if ((best_vco == 0 && error < best_error) ||
552 (best_vco != 0 &&
553 (error < best_error - 100 ||
554 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
555 best_post_div = post_div;
556 best_ref_div = ref_div;
557 best_feedback_div = feedback_div;
558 best_frac_feedback_div = frac_feedback_div;
559 best_freq = current_freq;
560 best_error = error;
561 best_vco_diff = vco_diff;
562 } else if (current_freq == freq) {
563 if (best_freq == -1) {
564 best_post_div = post_div;
565 best_ref_div = ref_div;
566 best_feedback_div = feedback_div;
567 best_frac_feedback_div = frac_feedback_div;
568 best_freq = current_freq;
569 best_error = error;
570 best_vco_diff = vco_diff;
fc10332b
AD		 571 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
572 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
573 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
574 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
575 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
576 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
771fe6b9
JG		 577 best_post_div = post_div;
578 best_ref_div = ref_div;
579 best_feedback_div = feedback_div;
580 best_frac_feedback_div = frac_feedback_div;
581 best_freq = current_freq;
582 best_error = error;
583 best_vco_diff = vco_diff;
584 }
585 }
586 if (current_freq < freq)
587 min_frac_feed_div = frac_feedback_div + 1;
588 else
589 max_frac_feed_div = frac_feedback_div;
590 }
591 if (current_freq < freq)
592 min_feed_div = feedback_div + 1;
593 else
594 max_feed_div = feedback_div;
595 }
596 }
597 }
598
599 *dot_clock_p = best_freq / 10000;
600 *fb_div_p = best_feedback_div;
601 *frac_fb_div_p = best_frac_feedback_div;
602 *ref_div_p = best_ref_div;
603 *post_div_p = best_post_div;
604}
605
383be5d1
AD		 606static bool
607calc_fb_div(struct radeon_pll *pll,
608 uint32_t freq,
609 uint32_t post_div,
610 uint32_t ref_div,
611 uint32_t *fb_div,
612 uint32_t *fb_div_frac)
b27b6375 613{
383be5d1
AD		 614 fixed20_12 feedback_divider, a, b;
615 u32 vco_freq;
b27b6375 616
383be5d1
AD		 617 vco_freq = freq * post_div;
618 /* feedback_divider = vco_freq * ref_div / pll->reference_freq; */
619 a.full = rfixed_const(pll->reference_freq);
620 feedback_divider.full = rfixed_const(vco_freq);
621 feedback_divider.full = rfixed_div(feedback_divider, a);
622 a.full = rfixed_const(ref_div);
623 feedback_divider.full = rfixed_mul(feedback_divider, a);
b27b6375 624
383be5d1
AD		 625 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
626 /* feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; */
627 a.full = rfixed_const(10);
628 feedback_divider.full = rfixed_mul(feedback_divider, a);
629 feedback_divider.full += rfixed_const_half(0);
630 feedback_divider.full = rfixed_floor(feedback_divider);
631 feedback_divider.full = rfixed_div(feedback_divider, a);
632
633 /* *fb_div = floor(feedback_divider); */
634 a.full = rfixed_floor(feedback_divider);
635 *fb_div = rfixed_trunc(a);
636 /* *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; */
637 a.full = rfixed_const(10);
638 b.full = rfixed_mul(feedback_divider, a);
639
640 feedback_divider.full = rfixed_floor(feedback_divider);
641 feedback_divider.full = rfixed_mul(feedback_divider, a);
642 feedback_divider.full = b.full - feedback_divider.full;
643 *fb_div_frac = rfixed_trunc(feedback_divider);
644 } else {
645 /* *fb_div = floor(feedback_divider + 0.5); */
646 feedback_divider.full += rfixed_const_half(0);
647 feedback_divider.full = rfixed_floor(feedback_divider);
b27b6375 648
383be5d1
AD		 649 *fb_div = rfixed_trunc(feedback_divider);
650 *fb_div_frac = 0;
651 }
b27b6375 652
383be5d1
AD		 653 if (((*fb_div) < pll->min_feedback_div) || ((*fb_div) > pll->max_feedback_div))
654 return false;
655 else
656 return true;
657}
b27b6375 658
383be5d1
AD		 659static bool
660calc_fb_ref_div(struct radeon_pll *pll,
661 uint32_t freq,
662 uint32_t post_div,
663 uint32_t *fb_div,
664 uint32_t *fb_div_frac,
665 uint32_t *ref_div)
666{
667 fixed20_12 ffreq, max_error, error, pll_out, a;
668 u32 vco;
b27b6375 669
383be5d1
AD		 670 ffreq.full = rfixed_const(freq);
671 /* max_error = ffreq * 0.0025; */
672 a.full = rfixed_const(400);
673 max_error.full = rfixed_div(ffreq, a);
b27b6375 674
383be5d1
AD		 675 for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) {
676 if (calc_fb_div(pll, freq, post_div, (*ref_div), fb_div, fb_div_frac)) {
677 vco = pll->reference_freq * (((*fb_div) * 10) + (*fb_div_frac));
678 vco = vco / ((*ref_div) * 10);
b27b6375 679
383be5d1
AD		 680 if ((vco < pll->pll_out_min) || (vco > pll->pll_out_max))
681 continue;
b27b6375 682
383be5d1
AD		 683 /* pll_out = vco / post_div; */
684 a.full = rfixed_const(post_div);
685 pll_out.full = rfixed_const(vco);
686 pll_out.full = rfixed_div(pll_out, a);
b27b6375 687
383be5d1
AD		 688 if (pll_out.full >= ffreq.full) {
689 error.full = pll_out.full - ffreq.full;
690 if (error.full <= max_error.full)
691 return true;
692 }
693 }
694 }
695 return false;
696}
697
698static void radeon_compute_pll_new(struct radeon_pll *pll,
699 uint64_t freq,
700 uint32_t *dot_clock_p,
701 uint32_t *fb_div_p,
702 uint32_t *frac_fb_div_p,
703 uint32_t *ref_div_p,
704 uint32_t *post_div_p)
705{
706 u32 fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0;
707 u32 best_freq = 0, vco_frequency;
708
709 /* freq = freq / 10; */
710 do_div(freq, 10);
711
712 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
713 post_div = pll->post_div;
714 if ((post_div < pll->min_post_div) || (post_div > pll->max_post_div))
715 goto done;
716
717 vco_frequency = freq * post_div;
718 if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max))
719 goto done;
720
721 if (pll->flags & RADEON_PLL_USE_REF_DIV) {
722 ref_div = pll->reference_div;
723 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
724 goto done;
725 if (!calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
726 goto done;
727 }
728 } else {
729 for (post_div = pll->max_post_div; post_div >= pll->min_post_div; --post_div) {
730 if (pll->flags & RADEON_PLL_LEGACY) {
731 if ((post_div == 5) ||
732 (post_div == 7) ||
733 (post_div == 9) ||
734 (post_div == 10) ||
735 (post_div == 11))
736 continue;
737 }
738
739 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
740 continue;
741
742 vco_frequency = freq * post_div;
743 if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max))
744 continue;
745 if (pll->flags & RADEON_PLL_USE_REF_DIV) {
746 ref_div = pll->reference_div;
747 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
748 goto done;
749 if (calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
750 break;
751 } else {
752 if (calc_fb_ref_div(pll, freq, post_div, &fb_div, &fb_div_frac, &ref_div))
753 break;
754 }
b27b6375
AD		 755 }
756 }
757
383be5d1
AD		 758 best_freq = pll->reference_freq * 10 * fb_div;
759 best_freq += pll->reference_freq * fb_div_frac;
760 best_freq = best_freq / (ref_div * post_div);
b27b6375 761
383be5d1
AD		 762done:
763 if (best_freq == 0)
764 DRM_ERROR("Couldn't find valid PLL dividers\n");
b27b6375 765
383be5d1
AD		 766 *dot_clock_p = best_freq / 10;
767 *fb_div_p = fb_div;
768 *frac_fb_div_p = fb_div_frac;
769 *ref_div_p = ref_div;
770 *post_div_p = post_div;
b27b6375 771
383be5d1 772 DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
b27b6375
AD		 773}
774
7c27f87d
AD		 775void radeon_compute_pll(struct radeon_pll *pll,
776 uint64_t freq,
777 uint32_t *dot_clock_p,
778 uint32_t *fb_div_p,
779 uint32_t *frac_fb_div_p,
780 uint32_t *ref_div_p,
781 uint32_t *post_div_p)
782{
783 switch (pll->algo) {
383be5d1
AD		 784 case PLL_ALGO_NEW:
785 radeon_compute_pll_new(pll, freq, dot_clock_p, fb_div_p,
786 frac_fb_div_p, ref_div_p, post_div_p);
7c27f87d
AD		 787 break;
788 case PLL_ALGO_LEGACY:
789 default:
790 radeon_compute_pll_legacy(pll, freq, dot_clock_p, fb_div_p,
791 frac_fb_div_p, ref_div_p, post_div_p);
792 break;
793 }
794}
795
771fe6b9
JG		 796static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
797{
798 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
799 struct drm_device *dev = fb->dev;
800
801 if (fb->fbdev)
802 radeonfb_remove(dev, fb);
803
804 if (radeon_fb->obj) {
771fe6b9
JG		 805 mutex_lock(&dev->struct_mutex);
806 drm_gem_object_unreference(radeon_fb->obj);
807 mutex_unlock(&dev->struct_mutex);
808 }
809 drm_framebuffer_cleanup(fb);
810 kfree(radeon_fb);
811}
812
813static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
814 struct drm_file *file_priv,
815 unsigned int *handle)
816{
817 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
818
819 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
820}
821
822static const struct drm_framebuffer_funcs radeon_fb_funcs = {
823 .destroy = radeon_user_framebuffer_destroy,
824 .create_handle = radeon_user_framebuffer_create_handle,
825};
826
827struct drm_framebuffer *
828radeon_framebuffer_create(struct drm_device *dev,
829 struct drm_mode_fb_cmd *mode_cmd,
830 struct drm_gem_object *obj)
831{
832 struct radeon_framebuffer *radeon_fb;
833
834 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
835 if (radeon_fb == NULL) {
836 return NULL;
837 }
838 drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs);
839 drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd);
840 radeon_fb->obj = obj;
841 return &radeon_fb->base;
842}
843
844static struct drm_framebuffer *
845radeon_user_framebuffer_create(struct drm_device *dev,
846 struct drm_file *file_priv,
847 struct drm_mode_fb_cmd *mode_cmd)
848{
849 struct drm_gem_object *obj;
850
851 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
7e71c9e2
JG		 852 if (obj == NULL) {
853 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
854 "can't create framebuffer\n", mode_cmd->handle);
855 return NULL;
856 }
771fe6b9
JG		 857 return radeon_framebuffer_create(dev, mode_cmd, obj);
858}
859
860static const struct drm_mode_config_funcs radeon_mode_funcs = {
861 .fb_create = radeon_user_framebuffer_create,
862 .fb_changed = radeonfb_probe,
863};
864
445282db
DA		 865struct drm_prop_enum_list {
866 int type;
867 char *name;
868};
869
870static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
871{ { 0, "driver" },
872 { 1, "bios" },
873};
874
875static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
876{ { TV_STD_NTSC, "ntsc" },
877 { TV_STD_PAL, "pal" },
878 { TV_STD_PAL_M, "pal-m" },
879 { TV_STD_PAL_60, "pal-60" },
880 { TV_STD_NTSC_J, "ntsc-j" },
881 { TV_STD_SCART_PAL, "scart-pal" },
882 { TV_STD_PAL_CN, "pal-cn" },
883 { TV_STD_SECAM, "secam" },
884};
885
d79766fa 886static int radeon_modeset_create_props(struct radeon_device *rdev)
445282db
DA		 887{
888 int i, sz;
889
890 if (rdev->is_atom_bios) {
891 rdev->mode_info.coherent_mode_property =
892 drm_property_create(rdev->ddev,
893 DRM_MODE_PROP_RANGE,
894 "coherent", 2);
895 if (!rdev->mode_info.coherent_mode_property)
896 return -ENOMEM;
897
898 rdev->mode_info.coherent_mode_property->values[0] = 0;
390d0bbe 899 rdev->mode_info.coherent_mode_property->values[1] = 1;
445282db
DA		 900 }
901
902 if (!ASIC_IS_AVIVO(rdev)) {
903 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
904 rdev->mode_info.tmds_pll_property =
905 drm_property_create(rdev->ddev,
906 DRM_MODE_PROP_ENUM,
907 "tmds_pll", sz);
908 for (i = 0; i < sz; i++) {
909 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
910 i,
911 radeon_tmds_pll_enum_list[i].type,
912 radeon_tmds_pll_enum_list[i].name);
913 }
914 }
915
916 rdev->mode_info.load_detect_property =
917 drm_property_create(rdev->ddev,
918 DRM_MODE_PROP_RANGE,
919 "load detection", 2);
920 if (!rdev->mode_info.load_detect_property)
921 return -ENOMEM;
922 rdev->mode_info.load_detect_property->values[0] = 0;
390d0bbe 923 rdev->mode_info.load_detect_property->values[1] = 1;
445282db
DA		 924
925 drm_mode_create_scaling_mode_property(rdev->ddev);
926
927 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
928 rdev->mode_info.tv_std_property =
929 drm_property_create(rdev->ddev,
930 DRM_MODE_PROP_ENUM,
931 "tv standard", sz);
932 for (i = 0; i < sz; i++) {
933 drm_property_add_enum(rdev->mode_info.tv_std_property,
934 i,
935 radeon_tv_std_enum_list[i].type,
936 radeon_tv_std_enum_list[i].name);
937 }
938
939 return 0;
940}
941
771fe6b9
JG		 942int radeon_modeset_init(struct radeon_device *rdev)
943{
18917b60 944 int i;
771fe6b9
JG		 945 int ret;
946
947 drm_mode_config_init(rdev->ddev);
948 rdev->mode_info.mode_config_initialized = true;
949
950 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
951
952 if (ASIC_IS_AVIVO(rdev)) {
953 rdev->ddev->mode_config.max_width = 8192;
954 rdev->ddev->mode_config.max_height = 8192;
955 } else {
956 rdev->ddev->mode_config.max_width = 4096;
957 rdev->ddev->mode_config.max_height = 4096;
958 }
959
960 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
961
445282db
DA		 962 ret = radeon_modeset_create_props(rdev);
963 if (ret) {
964 return ret;
965 }
dfee5614 966
3c537889
AD		 967 /* check combios for a valid hardcoded EDID - Sun servers */
968 if (!rdev->is_atom_bios) {
969 /* check for hardcoded EDID in BIOS */
970 radeon_combios_check_hardcoded_edid(rdev);
971 }
972
dfee5614 973 if (rdev->flags & RADEON_SINGLE_CRTC)
18917b60 974 rdev->num_crtc = 1;
bcc1c2a1
AD		 975 else {
976 if (ASIC_IS_DCE4(rdev))
977 rdev->num_crtc = 6;
978 else
979 rdev->num_crtc = 2;
980 }
dfee5614
DA		 981
982 /* allocate crtcs */
18917b60 983 for (i = 0; i < rdev->num_crtc; i++) {
771fe6b9
JG		 984 radeon_crtc_init(rdev->ddev, i);
985 }
986
987 /* okay we should have all the bios connectors */
988 ret = radeon_setup_enc_conn(rdev->ddev);
989 if (!ret) {
990 return ret;
991 }
d4877cf2
AD		 992 /* initialize hpd */
993 radeon_hpd_init(rdev);
771fe6b9
JG		 994 drm_helper_initial_config(rdev->ddev);
995 return 0;
996}
997
998void radeon_modeset_fini(struct radeon_device *rdev)
999{
3c537889
AD		 1000 kfree(rdev->mode_info.bios_hardcoded_edid);
1001
771fe6b9 1002 if (rdev->mode_info.mode_config_initialized) {
d4877cf2 1003 radeon_hpd_fini(rdev);
771fe6b9
JG		 1004 drm_mode_config_cleanup(rdev->ddev);
1005 rdev->mode_info.mode_config_initialized = false;
1006 }
1007}
1008
c93bb85b
JG		 1009bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1010 struct drm_display_mode *mode,
1011 struct drm_display_mode *adjusted_mode)
771fe6b9 1012{
c93bb85b
JG		 1013 struct drm_device *dev = crtc->dev;
1014 struct drm_encoder *encoder;
1015 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1016 struct radeon_encoder *radeon_encoder;
1017 bool first = true;
771fe6b9 1018
c93bb85b
JG		 1019 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1020 radeon_encoder = to_radeon_encoder(encoder);
1021 if (encoder->crtc != crtc)
1022 continue;
1023 if (first) {
80297e87
AD		 1024 /* set scaling */
1025 if (radeon_encoder->rmx_type == RMX_OFF)
1026 radeon_crtc->rmx_type = RMX_OFF;
1027 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1028 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1029 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1030 else
1031 radeon_crtc->rmx_type = RMX_OFF;
1032 /* copy native mode */
c93bb85b 1033 memcpy(&radeon_crtc->native_mode,
80297e87 1034 &radeon_encoder->native_mode,
de2103e4 1035 sizeof(struct drm_display_mode));
c93bb85b
JG		 1036 first = false;
1037 } else {
1038 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1039 /* WARNING: Right now this can't happen but
1040 * in the future we need to check that scaling
1041 * are consistent accross different encoder
1042 * (ie all encoder can work with the same
1043 * scaling).
1044 */
1045 DRM_ERROR("Scaling not consistent accross encoder.\n");
1046 return false;
1047 }
771fe6b9
JG		 1048 }
1049 }
c93bb85b
JG		 1050 if (radeon_crtc->rmx_type != RMX_OFF) {
1051 fixed20_12 a, b;
1052 a.full = rfixed_const(crtc->mode.vdisplay);
de2103e4 1053 b.full = rfixed_const(radeon_crtc->native_mode.hdisplay);
c93bb85b
JG		 1054 radeon_crtc->vsc.full = rfixed_div(a, b);
1055 a.full = rfixed_const(crtc->mode.hdisplay);
de2103e4 1056 b.full = rfixed_const(radeon_crtc->native_mode.vdisplay);
c93bb85b 1057 radeon_crtc->hsc.full = rfixed_div(a, b);
771fe6b9 1058 } else {
c93bb85b
JG		 1059 radeon_crtc->vsc.full = rfixed_const(1);
1060 radeon_crtc->hsc.full = rfixed_const(1);
771fe6b9 1061 }
c93bb85b 1062 return true;
771fe6b9 1063}
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