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drm/radeon: clear needs_reset flag if IB test fails
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / radeon_drv.c
CommitLineData
1da177e4
LT
1/**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
760285e7
DH
32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
1da177e4
LT
34#include "radeon_drv.h"
35
760285e7 36#include <drm/drm_pciids.h>
771fe6b9 37#include <linux/console.h>
e0cd3608 38#include <linux/module.h>
10ebc0bc
DA
39#include <linux/pm_runtime.h>
40#include <linux/vga_switcheroo.h>
41#include "drm_crtc_helper.h"
771fe6b9
JG
42/*
43 * KMS wrapper.
0de1a57b
DA
44 * - 2.0.0 - initial interface
45 * - 2.1.0 - add square tiling interface
fdb43528 46 * - 2.2.0 - add r6xx/r7xx const buffer support
cae94b0a 47 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
bc35afdb 48 * - 2.4.0 - add crtc id query
148a03bc 49 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
ab9e1f59 50 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
71901cc4 51 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
58bbf018 52 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
486af189 53 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
b8709894
AD
54 * 2.10.0 - fusion 2D tiling
55 * 2.11.0 - backend map, initial compute support for the CS checker
e70f224c 56 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
dd220a00 57 * 2.13.0 - virtual memory support, streamout
285484e2 58 * 2.14.0 - add evergreen tiling informations
609c1e15 59 * 2.15.0 - add max_pipes query
d2609875 60 * 2.16.0 - fix evergreen 2D tiled surface calculation
7c77bf2a 61 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
0f457e48 62 * 2.18.0 - r600-eg: allow "invalid" DB formats
b51ad12a 63 * 2.19.0 - r600-eg: MSAA textures
6759a0a7 64 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
c116cc94 65 * 2.21.0 - r600-r700: FMASK and CMASK
523885de 66 * 2.22.0 - r600 only: RESOLVE_BOX allowed
46fc8781 67 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
61051afd 68 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
71bfe916 69 * 2.25.0 - eg+: new info request for num SE and num SH
4ac0533a 70 * 2.26.0 - r600-eg: fix htile size computation
8696e33f 71 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
4613ca14 72 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
c18b1170 73 * 2.29.0 - R500 FP16 color clear registers
774c389f 74 * 2.30.0 - fix for FMASK texturing
a0a53aa8 75 * 2.31.0 - Add fastfb support for rs690
902aaef6 76 * 2.32.0 - new info request for rings working
64d7b8be 77 * 2.33.0 - Add SI tiling mode array query
39aee490 78 * 2.34.0 - Add CIK tiling mode array query
32f79a8a 79 * 2.35.0 - Add CIK macrotile mode array query
9482d0d3 80 * 2.36.0 - Fix CIK DCE tiling setup
7c4c62a0 81 * 2.37.0 - allow GS ring setup on r6xx/r7xx
020ff546
MO
82 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
83 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
771fe6b9
JG
84 */
85#define KMS_DRIVER_MAJOR 2
bda72d58 86#define KMS_DRIVER_MINOR 38
771fe6b9
JG
87#define KMS_DRIVER_PATCHLEVEL 0
88int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
89int radeon_driver_unload_kms(struct drm_device *dev);
771fe6b9
JG
90void radeon_driver_lastclose_kms(struct drm_device *dev);
91int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
92void radeon_driver_postclose_kms(struct drm_device *dev,
93 struct drm_file *file_priv);
94void radeon_driver_preclose_kms(struct drm_device *dev,
95 struct drm_file *file_priv);
10ebc0bc
DA
96int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
97int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
771fe6b9
JG
98u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc);
99int radeon_enable_vblank_kms(struct drm_device *dev, int crtc);
100void radeon_disable_vblank_kms(struct drm_device *dev, int crtc);
f5a80209
MK
101int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
102 int *max_error,
103 struct timeval *vblank_time,
104 unsigned flags);
771fe6b9
JG
105void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
106int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
107void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
e9f0d76f 108irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
771fe6b9 109void radeon_gem_object_free(struct drm_gem_object *obj);
721604a1
JG
110int radeon_gem_object_open(struct drm_gem_object *obj,
111 struct drm_file *file_priv);
112void radeon_gem_object_close(struct drm_gem_object *obj,
113 struct drm_file *file_priv);
f5a80209 114extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
abca9e45 115 unsigned int flags,
d47abc58
MK
116 int *vpos, int *hpos, ktime_t *stime,
117 ktime_t *etime);
baa70943 118extern const struct drm_ioctl_desc radeon_ioctls_kms[];
771fe6b9
JG
119extern int radeon_max_kms_ioctl;
120int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
ff72145b
DA
121int radeon_mode_dumb_mmap(struct drm_file *filp,
122 struct drm_device *dev,
123 uint32_t handle, uint64_t *offset_p);
124int radeon_mode_dumb_create(struct drm_file *file_priv,
125 struct drm_device *dev,
126 struct drm_mode_create_dumb *args);
1e6d17a5
AP
127struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
128struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
129 size_t size,
130 struct sg_table *sg);
131int radeon_gem_prime_pin(struct drm_gem_object *obj);
280cf211 132void radeon_gem_prime_unpin(struct drm_gem_object *obj);
1e6d17a5
AP
133void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
134void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
14adc892
CK
135extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
136 unsigned long arg);
ff72145b 137
771fe6b9
JG
138#if defined(CONFIG_DEBUG_FS)
139int radeon_debugfs_init(struct drm_minor *minor);
140void radeon_debugfs_cleanup(struct drm_minor *minor);
141#endif
771fe6b9 142
14adc892
CK
143/* atpx handler */
144#if defined(CONFIG_VGA_SWITCHEROO)
145void radeon_register_atpx_handler(void);
146void radeon_unregister_atpx_handler(void);
10ebc0bc 147bool radeon_is_px(void);
14adc892
CK
148#else
149static inline void radeon_register_atpx_handler(void) {}
150static inline void radeon_unregister_atpx_handler(void) {}
10ebc0bc 151static inline bool radeon_is_px(void) { return false; }
14adc892 152#endif
1da177e4 153
689b9d74 154int radeon_no_wb;
e9ced8e0 155int radeon_modeset = -1;
771fe6b9
JG
156int radeon_dynclks = -1;
157int radeon_r4xx_atom = 0;
158int radeon_agpmode = 0;
159int radeon_vram_limit = 0;
edcd26e8 160int radeon_gart_size = -1; /* auto */
771fe6b9 161int radeon_benchmarking = 0;
ecc0b326 162int radeon_testing = 0;
771fe6b9 163int radeon_connector_table = 0;
4ce001ab 164int radeon_tv = 1;
108dc8e8 165int radeon_audio = -1;
f46c0120 166int radeon_disp_priority = 0;
e2b0a8e1 167int radeon_hw_i2c = 0;
197bbb3d 168int radeon_pcie_gen2 = -1;
a18cee15 169int radeon_msi = -1;
3368ff0c 170int radeon_lockup_timeout = 10000;
a0a53aa8 171int radeon_fastfb = 0;
da321c8a 172int radeon_dpm = -1;
1294d4a3 173int radeon_aspm = -1;
10ebc0bc 174int radeon_runtime_pm = -1;
363eb0b4 175int radeon_hard_reset = 0;
689b9d74 176
61a2d07d 177MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
689b9d74
DA
178module_param_named(no_wb, radeon_no_wb, int, 0444);
179
771fe6b9
JG
180MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
181module_param_named(modeset, radeon_modeset, int, 0400);
182
183MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
184module_param_named(dynclks, radeon_dynclks, int, 0444);
185
186MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
187module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
188
189MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing");
190module_param_named(vramlimit, radeon_vram_limit, int, 0600);
191
192MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
193module_param_named(agpmode, radeon_agpmode, int, 0444);
194
edcd26e8 195MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
771fe6b9
JG
196module_param_named(gartsize, radeon_gart_size, int, 0600);
197
198MODULE_PARM_DESC(benchmark, "Run benchmark");
199module_param_named(benchmark, radeon_benchmarking, int, 0444);
200
ecc0b326
MD
201MODULE_PARM_DESC(test, "Run tests");
202module_param_named(test, radeon_testing, int, 0444);
203
771fe6b9
JG
204MODULE_PARM_DESC(connector_table, "Force connector table");
205module_param_named(connector_table, radeon_connector_table, int, 0444);
4ce001ab
DA
206
207MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
208module_param_named(tv, radeon_tv, int, 0444);
771fe6b9 209
108dc8e8 210MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
dafc3bd5
CK
211module_param_named(audio, radeon_audio, int, 0444);
212
f46c0120
AD
213MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
214module_param_named(disp_priority, radeon_disp_priority, int, 0444);
215
e2b0a8e1
AD
216MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
217module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
218
197bbb3d 219MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
d42dd579
AD
220module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
221
a18cee15
AD
222MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
223module_param_named(msi, radeon_msi, int, 0444);
224
3368ff0c
CK
225MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)");
226module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
227
a0a53aa8
SL
228MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
229module_param_named(fastfb, radeon_fastfb, int, 0444);
230
da321c8a
AD
231MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
232module_param_named(dpm, radeon_dpm, int, 0444);
233
1294d4a3
AD
234MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
235module_param_named(aspm, radeon_aspm, int, 0444);
236
10ebc0bc
DA
237MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
238module_param_named(runpm, radeon_runtime_pm, int, 0444);
239
363eb0b4
AD
240MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
241module_param_named(hard_reset, radeon_hard_reset, int, 0444);
242
14adc892
CK
243static struct pci_device_id pciidlist[] = {
244 radeon_PCI_IDS
245};
246
247MODULE_DEVICE_TABLE(pci, pciidlist);
248
249#ifdef CONFIG_DRM_RADEON_UMS
250
0a3e67a4
JB
251static int radeon_suspend(struct drm_device *dev, pm_message_t state)
252{
253 drm_radeon_private_t *dev_priv = dev->dev_private;
254
03efb885
DA
255 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
256 return 0;
257
0a3e67a4 258 /* Disable *all* interrupts */
800b6995 259 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
0a3e67a4
JB
260 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
261 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
262 return 0;
263}
264
265static int radeon_resume(struct drm_device *dev)
266{
267 drm_radeon_private_t *dev_priv = dev->dev_private;
268
03efb885
DA
269 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
270 return 0;
271
0a3e67a4 272 /* Restore interrupt registers */
800b6995 273 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
0a3e67a4
JB
274 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
275 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
276 return 0;
277}
278
10ebc0bc 279
e08e96de
AV
280static const struct file_operations radeon_driver_old_fops = {
281 .owner = THIS_MODULE,
282 .open = drm_open,
283 .release = drm_release,
284 .unlocked_ioctl = drm_ioctl,
285 .mmap = drm_mmap,
286 .poll = drm_poll,
e08e96de
AV
287 .read = drm_read,
288#ifdef CONFIG_COMPAT
289 .compat_ioctl = radeon_compat_ioctl,
290#endif
291 .llseek = noop_llseek,
292};
293
771fe6b9 294static struct drm_driver driver_old = {
b5e89ed5 295 .driver_features =
28185647 296 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
0a3e67a4 297 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED,
1da177e4 298 .dev_priv_size = sizeof(drm_radeon_buf_priv_t),
22eae947
DA
299 .load = radeon_driver_load,
300 .firstopen = radeon_driver_firstopen,
301 .open = radeon_driver_open,
302 .preclose = radeon_driver_preclose,
303 .postclose = radeon_driver_postclose,
304 .lastclose = radeon_driver_lastclose,
305 .unload = radeon_driver_unload,
0a3e67a4
JB
306 .suspend = radeon_suspend,
307 .resume = radeon_resume,
308 .get_vblank_counter = radeon_get_vblank_counter,
309 .enable_vblank = radeon_enable_vblank,
310 .disable_vblank = radeon_disable_vblank,
60f2ee0b
DA
311 .master_create = radeon_master_create,
312 .master_destroy = radeon_master_destroy,
1da177e4
LT
313 .irq_preinstall = radeon_driver_irq_preinstall,
314 .irq_postinstall = radeon_driver_irq_postinstall,
315 .irq_uninstall = radeon_driver_irq_uninstall,
316 .irq_handler = radeon_driver_irq_handler,
1da177e4
LT
317 .ioctls = radeon_ioctls,
318 .dma_ioctl = radeon_cp_buffers,
e08e96de 319 .fops = &radeon_driver_old_fops,
22eae947
DA
320 .name = DRIVER_NAME,
321 .desc = DRIVER_DESC,
322 .date = DRIVER_DATE,
323 .major = DRIVER_MAJOR,
324 .minor = DRIVER_MINOR,
325 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT
326};
327
14adc892
CK
328#endif
329
771fe6b9
JG
330static struct drm_driver kms_driver;
331
30238151 332static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
a56f7428
BH
333{
334 struct apertures_struct *ap;
335 bool primary = false;
336
337 ap = alloc_apertures(1);
30238151
TR
338 if (!ap)
339 return -ENOMEM;
340
a56f7428
BH
341 ap->ranges[0].base = pci_resource_start(pdev, 0);
342 ap->ranges[0].size = pci_resource_len(pdev, 0);
343
344#ifdef CONFIG_X86
345 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
346#endif
347 remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
348 kfree(ap);
30238151
TR
349
350 return 0;
a56f7428
BH
351}
352
56550d94
GKH
353static int radeon_pci_probe(struct pci_dev *pdev,
354 const struct pci_device_id *ent)
771fe6b9 355{
30238151
TR
356 int ret;
357
a56f7428 358 /* Get rid of things like offb */
30238151
TR
359 ret = radeon_kick_out_firmware_fb(pdev);
360 if (ret)
361 return ret;
a56f7428 362
dcdb1674 363 return drm_get_pci_dev(pdev, ent, &kms_driver);
771fe6b9
JG
364}
365
366static void
367radeon_pci_remove(struct pci_dev *pdev)
368{
369 struct drm_device *dev = pci_get_drvdata(pdev);
370
371 drm_put_dev(dev);
372}
373
7473e830 374static int radeon_pmops_suspend(struct device *dev)
771fe6b9 375{
7473e830
DA
376 struct pci_dev *pdev = to_pci_dev(dev);
377 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 378 return radeon_suspend_kms(drm_dev, true, true);
771fe6b9
JG
379}
380
7473e830 381static int radeon_pmops_resume(struct device *dev)
771fe6b9 382{
7473e830
DA
383 struct pci_dev *pdev = to_pci_dev(dev);
384 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 385 return radeon_resume_kms(drm_dev, true, true);
7473e830
DA
386}
387
388static int radeon_pmops_freeze(struct device *dev)
389{
390 struct pci_dev *pdev = to_pci_dev(dev);
391 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 392 return radeon_suspend_kms(drm_dev, false, true);
771fe6b9
JG
393}
394
7473e830
DA
395static int radeon_pmops_thaw(struct device *dev)
396{
397 struct pci_dev *pdev = to_pci_dev(dev);
398 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc
DA
399 return radeon_resume_kms(drm_dev, false, true);
400}
401
402static int radeon_pmops_runtime_suspend(struct device *dev)
403{
404 struct pci_dev *pdev = to_pci_dev(dev);
405 struct drm_device *drm_dev = pci_get_drvdata(pdev);
406 int ret;
407
408 if (radeon_runtime_pm == 0)
409 return -EINVAL;
410
9babd35a
AD
411 if (radeon_runtime_pm == -1 && !radeon_is_px())
412 return -EINVAL;
413
10ebc0bc
DA
414 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
415 drm_kms_helper_poll_disable(drm_dev);
416 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
417
418 ret = radeon_suspend_kms(drm_dev, false, false);
419 pci_save_state(pdev);
420 pci_disable_device(pdev);
421 pci_set_power_state(pdev, PCI_D3cold);
422 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
423
424 return 0;
425}
426
427static int radeon_pmops_runtime_resume(struct device *dev)
428{
429 struct pci_dev *pdev = to_pci_dev(dev);
430 struct drm_device *drm_dev = pci_get_drvdata(pdev);
431 int ret;
432
433 if (radeon_runtime_pm == 0)
434 return -EINVAL;
435
9babd35a
AD
436 if (radeon_runtime_pm == -1 && !radeon_is_px())
437 return -EINVAL;
438
10ebc0bc
DA
439 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
440
441 pci_set_power_state(pdev, PCI_D0);
442 pci_restore_state(pdev);
443 ret = pci_enable_device(pdev);
444 if (ret)
445 return ret;
446 pci_set_master(pdev);
447
448 ret = radeon_resume_kms(drm_dev, false, false);
449 drm_kms_helper_poll_enable(drm_dev);
450 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
451 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
452 return 0;
453}
454
455static int radeon_pmops_runtime_idle(struct device *dev)
456{
457 struct pci_dev *pdev = to_pci_dev(dev);
458 struct drm_device *drm_dev = pci_get_drvdata(pdev);
459 struct drm_crtc *crtc;
460
461 if (radeon_runtime_pm == 0)
462 return -EBUSY;
463
464 /* are we PX enabled? */
465 if (radeon_runtime_pm == -1 && !radeon_is_px()) {
466 DRM_DEBUG_DRIVER("failing to power off - not px\n");
467 return -EBUSY;
468 }
469
470 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
471 if (crtc->enabled) {
472 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
473 return -EBUSY;
474 }
475 }
476
477 pm_runtime_mark_last_busy(dev);
478 pm_runtime_autosuspend(dev);
479 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
480 return 1;
481}
482
483long radeon_drm_ioctl(struct file *filp,
484 unsigned int cmd, unsigned long arg)
485{
486 struct drm_file *file_priv = filp->private_data;
487 struct drm_device *dev;
488 long ret;
489 dev = file_priv->minor->dev;
490 ret = pm_runtime_get_sync(dev->dev);
491 if (ret < 0)
492 return ret;
493
494 ret = drm_ioctl(filp, cmd, arg);
495
496 pm_runtime_mark_last_busy(dev->dev);
497 pm_runtime_put_autosuspend(dev->dev);
498 return ret;
7473e830
DA
499}
500
501static const struct dev_pm_ops radeon_pm_ops = {
502 .suspend = radeon_pmops_suspend,
503 .resume = radeon_pmops_resume,
504 .freeze = radeon_pmops_freeze,
505 .thaw = radeon_pmops_thaw,
506 .poweroff = radeon_pmops_freeze,
507 .restore = radeon_pmops_resume,
10ebc0bc
DA
508 .runtime_suspend = radeon_pmops_runtime_suspend,
509 .runtime_resume = radeon_pmops_runtime_resume,
510 .runtime_idle = radeon_pmops_runtime_idle,
7473e830
DA
511};
512
e08e96de
AV
513static const struct file_operations radeon_driver_kms_fops = {
514 .owner = THIS_MODULE,
515 .open = drm_open,
516 .release = drm_release,
10ebc0bc 517 .unlocked_ioctl = radeon_drm_ioctl,
e08e96de
AV
518 .mmap = radeon_mmap,
519 .poll = drm_poll,
e08e96de
AV
520 .read = drm_read,
521#ifdef CONFIG_COMPAT
522 .compat_ioctl = radeon_kms_compat_ioctl,
523#endif
524};
525
771fe6b9
JG
526static struct drm_driver kms_driver = {
527 .driver_features =
28185647 528 DRIVER_USE_AGP |
81e95697 529 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
f33bcab9 530 DRIVER_PRIME | DRIVER_RENDER,
771fe6b9
JG
531 .dev_priv_size = 0,
532 .load = radeon_driver_load_kms,
771fe6b9
JG
533 .open = radeon_driver_open_kms,
534 .preclose = radeon_driver_preclose_kms,
535 .postclose = radeon_driver_postclose_kms,
536 .lastclose = radeon_driver_lastclose_kms,
537 .unload = radeon_driver_unload_kms,
771fe6b9
JG
538 .get_vblank_counter = radeon_get_vblank_counter_kms,
539 .enable_vblank = radeon_enable_vblank_kms,
540 .disable_vblank = radeon_disable_vblank_kms,
f5a80209
MK
541 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
542 .get_scanout_position = radeon_get_crtc_scanoutpos,
771fe6b9
JG
543#if defined(CONFIG_DEBUG_FS)
544 .debugfs_init = radeon_debugfs_init,
545 .debugfs_cleanup = radeon_debugfs_cleanup,
546#endif
547 .irq_preinstall = radeon_driver_irq_preinstall_kms,
548 .irq_postinstall = radeon_driver_irq_postinstall_kms,
549 .irq_uninstall = radeon_driver_irq_uninstall_kms,
550 .irq_handler = radeon_driver_irq_handler_kms,
771fe6b9 551 .ioctls = radeon_ioctls_kms,
771fe6b9 552 .gem_free_object = radeon_gem_object_free,
721604a1
JG
553 .gem_open_object = radeon_gem_object_open,
554 .gem_close_object = radeon_gem_object_close,
ff72145b
DA
555 .dumb_create = radeon_mode_dumb_create,
556 .dumb_map_offset = radeon_mode_dumb_mmap,
43387b37 557 .dumb_destroy = drm_gem_dumb_destroy,
e08e96de 558 .fops = &radeon_driver_kms_fops,
40f5cf99
AD
559
560 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
561 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1e6d17a5
AP
562 .gem_prime_export = drm_gem_prime_export,
563 .gem_prime_import = drm_gem_prime_import,
564 .gem_prime_pin = radeon_gem_prime_pin,
280cf211 565 .gem_prime_unpin = radeon_gem_prime_unpin,
1e6d17a5
AP
566 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
567 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
568 .gem_prime_vmap = radeon_gem_prime_vmap,
569 .gem_prime_vunmap = radeon_gem_prime_vunmap,
40f5cf99 570
771fe6b9
JG
571 .name = DRIVER_NAME,
572 .desc = DRIVER_DESC,
573 .date = DRIVER_DATE,
574 .major = KMS_DRIVER_MAJOR,
575 .minor = KMS_DRIVER_MINOR,
576 .patchlevel = KMS_DRIVER_PATCHLEVEL,
577};
771fe6b9
JG
578
579static struct drm_driver *driver;
8410ea3b
DA
580static struct pci_driver *pdriver;
581
14adc892 582#ifdef CONFIG_DRM_RADEON_UMS
8410ea3b
DA
583static struct pci_driver radeon_pci_driver = {
584 .name = DRIVER_NAME,
585 .id_table = pciidlist,
586};
14adc892 587#endif
8410ea3b
DA
588
589static struct pci_driver radeon_kms_pci_driver = {
590 .name = DRIVER_NAME,
591 .id_table = pciidlist,
592 .probe = radeon_pci_probe,
593 .remove = radeon_pci_remove,
7473e830 594 .driver.pm = &radeon_pm_ops,
8410ea3b 595};
771fe6b9 596
1da177e4
LT
597static int __init radeon_init(void)
598{
e9ced8e0
DA
599#ifdef CONFIG_VGA_CONSOLE
600 if (vgacon_text_force() && radeon_modeset == -1) {
601 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
602 radeon_modeset = 0;
603 }
604#endif
605 /* set to modesetting by default if not nomodeset */
606 if (radeon_modeset == -1)
607 radeon_modeset = 1;
608
771fe6b9
JG
609 if (radeon_modeset == 1) {
610 DRM_INFO("radeon kernel modesetting enabled.\n");
611 driver = &kms_driver;
8410ea3b 612 pdriver = &radeon_kms_pci_driver;
771fe6b9
JG
613 driver->driver_features |= DRIVER_MODESET;
614 driver->num_ioctls = radeon_max_kms_ioctl;
6a9ee8af 615 radeon_register_atpx_handler();
14adc892
CK
616
617 } else {
618#ifdef CONFIG_DRM_RADEON_UMS
619 DRM_INFO("radeon userspace modesetting enabled.\n");
620 driver = &driver_old;
621 pdriver = &radeon_pci_driver;
622 driver->driver_features &= ~DRIVER_MODESET;
623 driver->num_ioctls = radeon_max_ioctl;
624#else
625 DRM_ERROR("No UMS support in radeon module!\n");
626 return -EINVAL;
627#endif
771fe6b9 628 }
14adc892
CK
629
630 /* let modprobe override vga console setting */
8410ea3b 631 return drm_pci_init(driver, pdriver);
1da177e4
LT
632}
633
634static void __exit radeon_exit(void)
635{
8410ea3b 636 drm_pci_exit(driver, pdriver);
6a9ee8af 637 radeon_unregister_atpx_handler();
1da177e4
LT
638}
639
176f613e 640module_init(radeon_init);
1da177e4
LT
641module_exit(radeon_exit);
642
b5e89ed5
DA
643MODULE_AUTHOR(DRIVER_AUTHOR);
644MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 645MODULE_LICENSE("GPL and additional rights");