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1da177e4 LT |
1 | /** |
2 | * \file radeon_drv.c | |
3 | * ATI Radeon driver | |
4 | * | |
5 | * \author Gareth Hughes <gareth@valinux.com> | |
6 | */ | |
7 | ||
8 | /* | |
9 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
10 | * All Rights Reserved. | |
11 | * | |
12 | * Permission is hereby granted, free of charge, to any person obtaining a | |
13 | * copy of this software and associated documentation files (the "Software"), | |
14 | * to deal in the Software without restriction, including without limitation | |
15 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
16 | * and/or sell copies of the Software, and to permit persons to whom the | |
17 | * Software is furnished to do so, subject to the following conditions: | |
18 | * | |
19 | * The above copyright notice and this permission notice (including the next | |
20 | * paragraph) shall be included in all copies or substantial portions of the | |
21 | * Software. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
24 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
25 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
26 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
27 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
28 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
29 | * OTHER DEALINGS IN THE SOFTWARE. | |
30 | */ | |
31 | ||
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/radeon_drm.h> | |
1da177e4 LT |
34 | #include "radeon_drv.h" |
35 | ||
760285e7 | 36 | #include <drm/drm_pciids.h> |
771fe6b9 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
771fe6b9 JG |
39 | |
40 | ||
771fe6b9 JG |
41 | /* |
42 | * KMS wrapper. | |
0de1a57b DA |
43 | * - 2.0.0 - initial interface |
44 | * - 2.1.0 - add square tiling interface | |
fdb43528 | 45 | * - 2.2.0 - add r6xx/r7xx const buffer support |
cae94b0a | 46 | * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs |
bc35afdb | 47 | * - 2.4.0 - add crtc id query |
148a03bc | 48 | * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen |
ab9e1f59 | 49 | * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) |
71901cc4 | 50 | * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs |
58bbf018 | 51 | * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query |
486af189 | 52 | * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query |
b8709894 AD |
53 | * 2.10.0 - fusion 2D tiling |
54 | * 2.11.0 - backend map, initial compute support for the CS checker | |
e70f224c | 55 | * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS |
dd220a00 | 56 | * 2.13.0 - virtual memory support, streamout |
285484e2 | 57 | * 2.14.0 - add evergreen tiling informations |
609c1e15 | 58 | * 2.15.0 - add max_pipes query |
d2609875 | 59 | * 2.16.0 - fix evergreen 2D tiled surface calculation |
7c77bf2a | 60 | * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx |
0f457e48 | 61 | * 2.18.0 - r600-eg: allow "invalid" DB formats |
b51ad12a | 62 | * 2.19.0 - r600-eg: MSAA textures |
6759a0a7 | 63 | * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query |
c116cc94 | 64 | * 2.21.0 - r600-r700: FMASK and CMASK |
523885de | 65 | * 2.22.0 - r600 only: RESOLVE_BOX allowed |
46fc8781 | 66 | * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 |
61051afd | 67 | * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures |
71bfe916 | 68 | * 2.25.0 - eg+: new info request for num SE and num SH |
4ac0533a | 69 | * 2.26.0 - r600-eg: fix htile size computation |
771fe6b9 JG |
70 | */ |
71 | #define KMS_DRIVER_MAJOR 2 | |
4ac0533a | 72 | #define KMS_DRIVER_MINOR 26 |
771fe6b9 JG |
73 | #define KMS_DRIVER_PATCHLEVEL 0 |
74 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); | |
75 | int radeon_driver_unload_kms(struct drm_device *dev); | |
76 | int radeon_driver_firstopen_kms(struct drm_device *dev); | |
77 | void radeon_driver_lastclose_kms(struct drm_device *dev); | |
78 | int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); | |
79 | void radeon_driver_postclose_kms(struct drm_device *dev, | |
80 | struct drm_file *file_priv); | |
81 | void radeon_driver_preclose_kms(struct drm_device *dev, | |
82 | struct drm_file *file_priv); | |
83 | int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); | |
84 | int radeon_resume_kms(struct drm_device *dev); | |
85 | u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc); | |
86 | int radeon_enable_vblank_kms(struct drm_device *dev, int crtc); | |
87 | void radeon_disable_vblank_kms(struct drm_device *dev, int crtc); | |
f5a80209 MK |
88 | int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, |
89 | int *max_error, | |
90 | struct timeval *vblank_time, | |
91 | unsigned flags); | |
771fe6b9 JG |
92 | void radeon_driver_irq_preinstall_kms(struct drm_device *dev); |
93 | int radeon_driver_irq_postinstall_kms(struct drm_device *dev); | |
94 | void radeon_driver_irq_uninstall_kms(struct drm_device *dev); | |
95 | irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS); | |
771fe6b9 JG |
96 | int radeon_dma_ioctl_kms(struct drm_device *dev, void *data, |
97 | struct drm_file *file_priv); | |
98 | int radeon_gem_object_init(struct drm_gem_object *obj); | |
99 | void radeon_gem_object_free(struct drm_gem_object *obj); | |
721604a1 JG |
100 | int radeon_gem_object_open(struct drm_gem_object *obj, |
101 | struct drm_file *file_priv); | |
102 | void radeon_gem_object_close(struct drm_gem_object *obj, | |
103 | struct drm_file *file_priv); | |
f5a80209 MK |
104 | extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, |
105 | int *vpos, int *hpos); | |
771fe6b9 JG |
106 | extern struct drm_ioctl_desc radeon_ioctls_kms[]; |
107 | extern int radeon_max_kms_ioctl; | |
108 | int radeon_mmap(struct file *filp, struct vm_area_struct *vma); | |
ff72145b DA |
109 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
110 | struct drm_device *dev, | |
111 | uint32_t handle, uint64_t *offset_p); | |
112 | int radeon_mode_dumb_create(struct drm_file *file_priv, | |
113 | struct drm_device *dev, | |
114 | struct drm_mode_create_dumb *args); | |
115 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, | |
116 | struct drm_device *dev, | |
117 | uint32_t handle); | |
40f5cf99 AD |
118 | struct dma_buf *radeon_gem_prime_export(struct drm_device *dev, |
119 | struct drm_gem_object *obj, | |
120 | int flags); | |
121 | struct drm_gem_object *radeon_gem_prime_import(struct drm_device *dev, | |
122 | struct dma_buf *dma_buf); | |
ff72145b | 123 | |
771fe6b9 JG |
124 | #if defined(CONFIG_DEBUG_FS) |
125 | int radeon_debugfs_init(struct drm_minor *minor); | |
126 | void radeon_debugfs_cleanup(struct drm_minor *minor); | |
127 | #endif | |
771fe6b9 | 128 | |
1da177e4 | 129 | |
689b9d74 | 130 | int radeon_no_wb; |
771fe6b9 JG |
131 | int radeon_modeset = -1; |
132 | int radeon_dynclks = -1; | |
133 | int radeon_r4xx_atom = 0; | |
134 | int radeon_agpmode = 0; | |
135 | int radeon_vram_limit = 0; | |
136 | int radeon_gart_size = 512; /* default gart size */ | |
137 | int radeon_benchmarking = 0; | |
ecc0b326 | 138 | int radeon_testing = 0; |
771fe6b9 | 139 | int radeon_connector_table = 0; |
4ce001ab | 140 | int radeon_tv = 1; |
805c2216 | 141 | int radeon_audio = 0; |
f46c0120 | 142 | int radeon_disp_priority = 0; |
e2b0a8e1 | 143 | int radeon_hw_i2c = 0; |
197bbb3d | 144 | int radeon_pcie_gen2 = -1; |
a18cee15 | 145 | int radeon_msi = -1; |
3368ff0c | 146 | int radeon_lockup_timeout = 10000; |
689b9d74 | 147 | |
61a2d07d | 148 | MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); |
689b9d74 DA |
149 | module_param_named(no_wb, radeon_no_wb, int, 0444); |
150 | ||
771fe6b9 JG |
151 | MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); |
152 | module_param_named(modeset, radeon_modeset, int, 0400); | |
153 | ||
154 | MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); | |
155 | module_param_named(dynclks, radeon_dynclks, int, 0444); | |
156 | ||
157 | MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); | |
158 | module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); | |
159 | ||
160 | MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing"); | |
161 | module_param_named(vramlimit, radeon_vram_limit, int, 0600); | |
162 | ||
163 | MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); | |
164 | module_param_named(agpmode, radeon_agpmode, int, 0444); | |
165 | ||
27d4d052 | 166 | MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc)"); |
771fe6b9 JG |
167 | module_param_named(gartsize, radeon_gart_size, int, 0600); |
168 | ||
169 | MODULE_PARM_DESC(benchmark, "Run benchmark"); | |
170 | module_param_named(benchmark, radeon_benchmarking, int, 0444); | |
171 | ||
ecc0b326 MD |
172 | MODULE_PARM_DESC(test, "Run tests"); |
173 | module_param_named(test, radeon_testing, int, 0444); | |
174 | ||
771fe6b9 JG |
175 | MODULE_PARM_DESC(connector_table, "Force connector table"); |
176 | module_param_named(connector_table, radeon_connector_table, int, 0444); | |
4ce001ab DA |
177 | |
178 | MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); | |
179 | module_param_named(tv, radeon_tv, int, 0444); | |
771fe6b9 | 180 | |
805c2216 | 181 | MODULE_PARM_DESC(audio, "Audio enable (1 = enable)"); |
dafc3bd5 CK |
182 | module_param_named(audio, radeon_audio, int, 0444); |
183 | ||
f46c0120 AD |
184 | MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); |
185 | module_param_named(disp_priority, radeon_disp_priority, int, 0444); | |
186 | ||
e2b0a8e1 AD |
187 | MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); |
188 | module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); | |
189 | ||
197bbb3d | 190 | MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); |
d42dd579 AD |
191 | module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); |
192 | ||
a18cee15 AD |
193 | MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); |
194 | module_param_named(msi, radeon_msi, int, 0444); | |
195 | ||
3368ff0c CK |
196 | MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)"); |
197 | module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); | |
198 | ||
0a3e67a4 JB |
199 | static int radeon_suspend(struct drm_device *dev, pm_message_t state) |
200 | { | |
201 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
202 | ||
03efb885 DA |
203 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
204 | return 0; | |
205 | ||
0a3e67a4 | 206 | /* Disable *all* interrupts */ |
800b6995 | 207 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) |
0a3e67a4 JB |
208 | RADEON_WRITE(R500_DxMODE_INT_MASK, 0); |
209 | RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); | |
210 | return 0; | |
211 | } | |
212 | ||
213 | static int radeon_resume(struct drm_device *dev) | |
214 | { | |
215 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
216 | ||
03efb885 DA |
217 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
218 | return 0; | |
219 | ||
0a3e67a4 | 220 | /* Restore interrupt registers */ |
800b6995 | 221 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) |
0a3e67a4 JB |
222 | RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); |
223 | RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); | |
224 | return 0; | |
225 | } | |
226 | ||
1da177e4 LT |
227 | static struct pci_device_id pciidlist[] = { |
228 | radeon_PCI_IDS | |
229 | }; | |
230 | ||
771fe6b9 JG |
231 | #if defined(CONFIG_DRM_RADEON_KMS) |
232 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
233 | #endif | |
234 | ||
e08e96de AV |
235 | static const struct file_operations radeon_driver_old_fops = { |
236 | .owner = THIS_MODULE, | |
237 | .open = drm_open, | |
238 | .release = drm_release, | |
239 | .unlocked_ioctl = drm_ioctl, | |
240 | .mmap = drm_mmap, | |
241 | .poll = drm_poll, | |
242 | .fasync = drm_fasync, | |
243 | .read = drm_read, | |
244 | #ifdef CONFIG_COMPAT | |
245 | .compat_ioctl = radeon_compat_ioctl, | |
246 | #endif | |
247 | .llseek = noop_llseek, | |
248 | }; | |
249 | ||
771fe6b9 | 250 | static struct drm_driver driver_old = { |
b5e89ed5 DA |
251 | .driver_features = |
252 | DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | | |
0a3e67a4 | 253 | DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED, |
1da177e4 | 254 | .dev_priv_size = sizeof(drm_radeon_buf_priv_t), |
22eae947 DA |
255 | .load = radeon_driver_load, |
256 | .firstopen = radeon_driver_firstopen, | |
257 | .open = radeon_driver_open, | |
258 | .preclose = radeon_driver_preclose, | |
259 | .postclose = radeon_driver_postclose, | |
260 | .lastclose = radeon_driver_lastclose, | |
261 | .unload = radeon_driver_unload, | |
0a3e67a4 JB |
262 | .suspend = radeon_suspend, |
263 | .resume = radeon_resume, | |
264 | .get_vblank_counter = radeon_get_vblank_counter, | |
265 | .enable_vblank = radeon_enable_vblank, | |
266 | .disable_vblank = radeon_disable_vblank, | |
60f2ee0b DA |
267 | .master_create = radeon_master_create, |
268 | .master_destroy = radeon_master_destroy, | |
1da177e4 LT |
269 | .irq_preinstall = radeon_driver_irq_preinstall, |
270 | .irq_postinstall = radeon_driver_irq_postinstall, | |
271 | .irq_uninstall = radeon_driver_irq_uninstall, | |
272 | .irq_handler = radeon_driver_irq_handler, | |
1da177e4 LT |
273 | .ioctls = radeon_ioctls, |
274 | .dma_ioctl = radeon_cp_buffers, | |
e08e96de | 275 | .fops = &radeon_driver_old_fops, |
22eae947 DA |
276 | .name = DRIVER_NAME, |
277 | .desc = DRIVER_DESC, | |
278 | .date = DRIVER_DATE, | |
279 | .major = DRIVER_MAJOR, | |
280 | .minor = DRIVER_MINOR, | |
281 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
282 | }; |
283 | ||
771fe6b9 JG |
284 | static struct drm_driver kms_driver; |
285 | ||
30238151 | 286 | static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) |
a56f7428 BH |
287 | { |
288 | struct apertures_struct *ap; | |
289 | bool primary = false; | |
290 | ||
291 | ap = alloc_apertures(1); | |
30238151 TR |
292 | if (!ap) |
293 | return -ENOMEM; | |
294 | ||
a56f7428 BH |
295 | ap->ranges[0].base = pci_resource_start(pdev, 0); |
296 | ap->ranges[0].size = pci_resource_len(pdev, 0); | |
297 | ||
298 | #ifdef CONFIG_X86 | |
299 | primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
300 | #endif | |
301 | remove_conflicting_framebuffers(ap, "radeondrmfb", primary); | |
302 | kfree(ap); | |
30238151 TR |
303 | |
304 | return 0; | |
a56f7428 BH |
305 | } |
306 | ||
771fe6b9 JG |
307 | static int __devinit |
308 | radeon_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
309 | { | |
30238151 TR |
310 | int ret; |
311 | ||
a56f7428 | 312 | /* Get rid of things like offb */ |
30238151 TR |
313 | ret = radeon_kick_out_firmware_fb(pdev); |
314 | if (ret) | |
315 | return ret; | |
a56f7428 | 316 | |
dcdb1674 | 317 | return drm_get_pci_dev(pdev, ent, &kms_driver); |
771fe6b9 JG |
318 | } |
319 | ||
320 | static void | |
321 | radeon_pci_remove(struct pci_dev *pdev) | |
322 | { | |
323 | struct drm_device *dev = pci_get_drvdata(pdev); | |
324 | ||
325 | drm_put_dev(dev); | |
326 | } | |
327 | ||
328 | static int | |
329 | radeon_pci_suspend(struct pci_dev *pdev, pm_message_t state) | |
330 | { | |
331 | struct drm_device *dev = pci_get_drvdata(pdev); | |
332 | return radeon_suspend_kms(dev, state); | |
333 | } | |
334 | ||
335 | static int | |
336 | radeon_pci_resume(struct pci_dev *pdev) | |
337 | { | |
338 | struct drm_device *dev = pci_get_drvdata(pdev); | |
339 | return radeon_resume_kms(dev); | |
340 | } | |
341 | ||
e08e96de AV |
342 | static const struct file_operations radeon_driver_kms_fops = { |
343 | .owner = THIS_MODULE, | |
344 | .open = drm_open, | |
345 | .release = drm_release, | |
346 | .unlocked_ioctl = drm_ioctl, | |
347 | .mmap = radeon_mmap, | |
348 | .poll = drm_poll, | |
349 | .fasync = drm_fasync, | |
350 | .read = drm_read, | |
351 | #ifdef CONFIG_COMPAT | |
352 | .compat_ioctl = radeon_kms_compat_ioctl, | |
353 | #endif | |
354 | }; | |
355 | ||
771fe6b9 JG |
356 | static struct drm_driver kms_driver = { |
357 | .driver_features = | |
358 | DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | | |
40f5cf99 AD |
359 | DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_GEM | |
360 | DRIVER_PRIME, | |
771fe6b9 JG |
361 | .dev_priv_size = 0, |
362 | .load = radeon_driver_load_kms, | |
363 | .firstopen = radeon_driver_firstopen_kms, | |
364 | .open = radeon_driver_open_kms, | |
365 | .preclose = radeon_driver_preclose_kms, | |
366 | .postclose = radeon_driver_postclose_kms, | |
367 | .lastclose = radeon_driver_lastclose_kms, | |
368 | .unload = radeon_driver_unload_kms, | |
369 | .suspend = radeon_suspend_kms, | |
370 | .resume = radeon_resume_kms, | |
371 | .get_vblank_counter = radeon_get_vblank_counter_kms, | |
372 | .enable_vblank = radeon_enable_vblank_kms, | |
373 | .disable_vblank = radeon_disable_vblank_kms, | |
f5a80209 MK |
374 | .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, |
375 | .get_scanout_position = radeon_get_crtc_scanoutpos, | |
771fe6b9 JG |
376 | #if defined(CONFIG_DEBUG_FS) |
377 | .debugfs_init = radeon_debugfs_init, | |
378 | .debugfs_cleanup = radeon_debugfs_cleanup, | |
379 | #endif | |
380 | .irq_preinstall = radeon_driver_irq_preinstall_kms, | |
381 | .irq_postinstall = radeon_driver_irq_postinstall_kms, | |
382 | .irq_uninstall = radeon_driver_irq_uninstall_kms, | |
383 | .irq_handler = radeon_driver_irq_handler_kms, | |
771fe6b9 JG |
384 | .ioctls = radeon_ioctls_kms, |
385 | .gem_init_object = radeon_gem_object_init, | |
386 | .gem_free_object = radeon_gem_object_free, | |
721604a1 JG |
387 | .gem_open_object = radeon_gem_object_open, |
388 | .gem_close_object = radeon_gem_object_close, | |
771fe6b9 | 389 | .dma_ioctl = radeon_dma_ioctl_kms, |
ff72145b DA |
390 | .dumb_create = radeon_mode_dumb_create, |
391 | .dumb_map_offset = radeon_mode_dumb_mmap, | |
392 | .dumb_destroy = radeon_mode_dumb_destroy, | |
e08e96de | 393 | .fops = &radeon_driver_kms_fops, |
40f5cf99 AD |
394 | |
395 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
396 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
397 | .gem_prime_export = radeon_gem_prime_export, | |
398 | .gem_prime_import = radeon_gem_prime_import, | |
399 | ||
771fe6b9 JG |
400 | .name = DRIVER_NAME, |
401 | .desc = DRIVER_DESC, | |
402 | .date = DRIVER_DATE, | |
403 | .major = KMS_DRIVER_MAJOR, | |
404 | .minor = KMS_DRIVER_MINOR, | |
405 | .patchlevel = KMS_DRIVER_PATCHLEVEL, | |
406 | }; | |
771fe6b9 JG |
407 | |
408 | static struct drm_driver *driver; | |
8410ea3b DA |
409 | static struct pci_driver *pdriver; |
410 | ||
411 | static struct pci_driver radeon_pci_driver = { | |
412 | .name = DRIVER_NAME, | |
413 | .id_table = pciidlist, | |
414 | }; | |
415 | ||
416 | static struct pci_driver radeon_kms_pci_driver = { | |
417 | .name = DRIVER_NAME, | |
418 | .id_table = pciidlist, | |
419 | .probe = radeon_pci_probe, | |
420 | .remove = radeon_pci_remove, | |
421 | .suspend = radeon_pci_suspend, | |
422 | .resume = radeon_pci_resume, | |
423 | }; | |
771fe6b9 | 424 | |
1da177e4 LT |
425 | static int __init radeon_init(void) |
426 | { | |
771fe6b9 | 427 | driver = &driver_old; |
8410ea3b | 428 | pdriver = &radeon_pci_driver; |
771fe6b9 | 429 | driver->num_ioctls = radeon_max_ioctl; |
de05065f DA |
430 | #ifdef CONFIG_VGA_CONSOLE |
431 | if (vgacon_text_force() && radeon_modeset == -1) { | |
432 | DRM_INFO("VGACON disable radeon kernel modesetting.\n"); | |
433 | driver = &driver_old; | |
8410ea3b | 434 | pdriver = &radeon_pci_driver; |
de05065f DA |
435 | driver->driver_features &= ~DRIVER_MODESET; |
436 | radeon_modeset = 0; | |
437 | } | |
438 | #endif | |
771fe6b9 JG |
439 | /* if enabled by default */ |
440 | if (radeon_modeset == -1) { | |
a0cdc649 DA |
441 | #ifdef CONFIG_DRM_RADEON_KMS |
442 | DRM_INFO("radeon defaulting to kernel modesetting.\n"); | |
771fe6b9 | 443 | radeon_modeset = 1; |
a0cdc649 DA |
444 | #else |
445 | DRM_INFO("radeon defaulting to userspace modesetting.\n"); | |
446 | radeon_modeset = 0; | |
447 | #endif | |
771fe6b9 JG |
448 | } |
449 | if (radeon_modeset == 1) { | |
450 | DRM_INFO("radeon kernel modesetting enabled.\n"); | |
451 | driver = &kms_driver; | |
8410ea3b | 452 | pdriver = &radeon_kms_pci_driver; |
771fe6b9 JG |
453 | driver->driver_features |= DRIVER_MODESET; |
454 | driver->num_ioctls = radeon_max_kms_ioctl; | |
6a9ee8af | 455 | radeon_register_atpx_handler(); |
771fe6b9 | 456 | } |
771fe6b9 JG |
457 | /* if the vga console setting is enabled still |
458 | * let modprobe override it */ | |
8410ea3b | 459 | return drm_pci_init(driver, pdriver); |
1da177e4 LT |
460 | } |
461 | ||
462 | static void __exit radeon_exit(void) | |
463 | { | |
8410ea3b | 464 | drm_pci_exit(driver, pdriver); |
6a9ee8af | 465 | radeon_unregister_atpx_handler(); |
1da177e4 LT |
466 | } |
467 | ||
176f613e | 468 | module_init(radeon_init); |
1da177e4 LT |
469 | module_exit(radeon_exit); |
470 | ||
b5e89ed5 DA |
471 | MODULE_AUTHOR(DRIVER_AUTHOR); |
472 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 473 | MODULE_LICENSE("GPL and additional rights"); |