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drm/nouveau: drop DRIVER_PCI_DMA and DRIVER_SG
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / radeon_drv.c
CommitLineData
1da177e4
LT		 1/**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
1da177e4
LT		 34#include "radeon_drv.h"
35
760285e7 36#include <drm/drm_pciids.h>
771fe6b9 37#include <linux/console.h>
e0cd3608 38#include <linux/module.h>
771fe6b9
JG		 39
40
771fe6b9
JG		 41/*
42 * KMS wrapper.
0de1a57b
DA		 43 * - 2.0.0 - initial interface
44 * - 2.1.0 - add square tiling interface
fdb43528 45 * - 2.2.0 - add r6xx/r7xx const buffer support
cae94b0a 46 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
bc35afdb 47 * - 2.4.0 - add crtc id query
148a03bc 48 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
ab9e1f59 49 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
71901cc4 50 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
58bbf018 51 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
486af189 52 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
b8709894
AD		 53 * 2.10.0 - fusion 2D tiling
54 * 2.11.0 - backend map, initial compute support for the CS checker
e70f224c 55 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
dd220a00 56 * 2.13.0 - virtual memory support, streamout
285484e2 57 * 2.14.0 - add evergreen tiling informations
609c1e15 58 * 2.15.0 - add max_pipes query
d2609875 59 * 2.16.0 - fix evergreen 2D tiled surface calculation
7c77bf2a 60 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
0f457e48 61 * 2.18.0 - r600-eg: allow "invalid" DB formats
b51ad12a 62 * 2.19.0 - r600-eg: MSAA textures
6759a0a7 63 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
c116cc94 64 * 2.21.0 - r600-r700: FMASK and CMASK
523885de 65 * 2.22.0 - r600 only: RESOLVE_BOX allowed
46fc8781 66 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
61051afd 67 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
71bfe916 68 * 2.25.0 - eg+: new info request for num SE and num SH
4ac0533a 69 * 2.26.0 - r600-eg: fix htile size computation
8696e33f 70 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
4613ca14 71 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
c18b1170 72 * 2.29.0 - R500 FP16 color clear registers
774c389f 73 * 2.30.0 - fix for FMASK texturing
a0a53aa8 74 * 2.31.0 - Add fastfb support for rs690
902aaef6 75 * 2.32.0 - new info request for rings working
64d7b8be 76 * 2.33.0 - Add SI tiling mode array query
39aee490 77 * 2.34.0 - Add CIK tiling mode array query
771fe6b9
JG		 78 */
79#define KMS_DRIVER_MAJOR 2
39aee490 80#define KMS_DRIVER_MINOR 34
771fe6b9
JG		 81#define KMS_DRIVER_PATCHLEVEL 0
82int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
83int radeon_driver_unload_kms(struct drm_device *dev);
84int radeon_driver_firstopen_kms(struct drm_device *dev);
85void radeon_driver_lastclose_kms(struct drm_device *dev);
86int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
87void radeon_driver_postclose_kms(struct drm_device *dev,
88 struct drm_file *file_priv);
89void radeon_driver_preclose_kms(struct drm_device *dev,
90 struct drm_file *file_priv);
91int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
92int radeon_resume_kms(struct drm_device *dev);
93u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc);
94int radeon_enable_vblank_kms(struct drm_device *dev, int crtc);
95void radeon_disable_vblank_kms(struct drm_device *dev, int crtc);
f5a80209
MK		 96int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
97 int *max_error,
98 struct timeval *vblank_time,
99 unsigned flags);
771fe6b9
JG		 100void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
101int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
102void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
103irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS);
771fe6b9
JG		 104int radeon_gem_object_init(struct drm_gem_object *obj);
105void radeon_gem_object_free(struct drm_gem_object *obj);
721604a1
JG		 106int radeon_gem_object_open(struct drm_gem_object *obj,
107 struct drm_file *file_priv);
108void radeon_gem_object_close(struct drm_gem_object *obj,
109 struct drm_file *file_priv);
f5a80209
MK		 110extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
111 int *vpos, int *hpos);
771fe6b9
JG		 112extern struct drm_ioctl_desc radeon_ioctls_kms[];
113extern int radeon_max_kms_ioctl;
114int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
ff72145b
DA		 115int radeon_mode_dumb_mmap(struct drm_file *filp,
116 struct drm_device *dev,
117 uint32_t handle, uint64_t *offset_p);
118int radeon_mode_dumb_create(struct drm_file *file_priv,
119 struct drm_device *dev,
120 struct drm_mode_create_dumb *args);
121int radeon_mode_dumb_destroy(struct drm_file *file_priv,
122 struct drm_device *dev,
123 uint32_t handle);
1e6d17a5
AP		 124struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
125struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
126 size_t size,
127 struct sg_table *sg);
128int radeon_gem_prime_pin(struct drm_gem_object *obj);
280cf211 129void radeon_gem_prime_unpin(struct drm_gem_object *obj);
1e6d17a5
AP		 130void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
131void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
14adc892
CK		 132extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
133 unsigned long arg);
ff72145b 134
771fe6b9
JG		 135#if defined(CONFIG_DEBUG_FS)
136int radeon_debugfs_init(struct drm_minor *minor);
137void radeon_debugfs_cleanup(struct drm_minor *minor);
138#endif
771fe6b9 139
14adc892
CK		 140/* atpx handler */
141#if defined(CONFIG_VGA_SWITCHEROO)
142void radeon_register_atpx_handler(void);
143void radeon_unregister_atpx_handler(void);
144#else
145static inline void radeon_register_atpx_handler(void) {}
146static inline void radeon_unregister_atpx_handler(void) {}
147#endif
1da177e4 148
689b9d74 149int radeon_no_wb;
e9ced8e0 150int radeon_modeset = -1;
771fe6b9
JG		 151int radeon_dynclks = -1;
152int radeon_r4xx_atom = 0;
153int radeon_agpmode = 0;
154int radeon_vram_limit = 0;
155int radeon_gart_size = 512; /* default gart size */
156int radeon_benchmarking = 0;
ecc0b326 157int radeon_testing = 0;
771fe6b9 158int radeon_connector_table = 0;
4ce001ab 159int radeon_tv = 1;
805c2216 160int radeon_audio = 0;
f46c0120 161int radeon_disp_priority = 0;
e2b0a8e1 162int radeon_hw_i2c = 0;
197bbb3d 163int radeon_pcie_gen2 = -1;
a18cee15 164int radeon_msi = -1;
3368ff0c 165int radeon_lockup_timeout = 10000;
a0a53aa8 166int radeon_fastfb = 0;
da321c8a 167int radeon_dpm = -1;
1294d4a3 168int radeon_aspm = -1;
689b9d74 169
61a2d07d 170MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
689b9d74
DA		 171module_param_named(no_wb, radeon_no_wb, int, 0444);
172
771fe6b9
JG		 173MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
174module_param_named(modeset, radeon_modeset, int, 0400);
175
176MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
177module_param_named(dynclks, radeon_dynclks, int, 0444);
178
179MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
180module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
181
182MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing");
183module_param_named(vramlimit, radeon_vram_limit, int, 0600);
184
185MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
186module_param_named(agpmode, radeon_agpmode, int, 0444);
187
27d4d052 188MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc)");
771fe6b9
JG		 189module_param_named(gartsize, radeon_gart_size, int, 0600);
190
191MODULE_PARM_DESC(benchmark, "Run benchmark");
192module_param_named(benchmark, radeon_benchmarking, int, 0444);
193
ecc0b326
MD		 194MODULE_PARM_DESC(test, "Run tests");
195module_param_named(test, radeon_testing, int, 0444);
196
771fe6b9
JG		 197MODULE_PARM_DESC(connector_table, "Force connector table");
198module_param_named(connector_table, radeon_connector_table, int, 0444);
4ce001ab
DA		 199
200MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
201module_param_named(tv, radeon_tv, int, 0444);
771fe6b9 202
805c2216 203MODULE_PARM_DESC(audio, "Audio enable (1 = enable)");
dafc3bd5
CK		 204module_param_named(audio, radeon_audio, int, 0444);
205
f46c0120
AD		 206MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
207module_param_named(disp_priority, radeon_disp_priority, int, 0444);
208
e2b0a8e1
AD		 209MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
210module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
211
197bbb3d 212MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
d42dd579
AD		 213module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
214
a18cee15
AD		 215MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
216module_param_named(msi, radeon_msi, int, 0444);
217
3368ff0c
CK		 218MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)");
219module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
220
a0a53aa8
SL		 221MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
222module_param_named(fastfb, radeon_fastfb, int, 0444);
223
da321c8a
AD		 224MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
225module_param_named(dpm, radeon_dpm, int, 0444);
226
1294d4a3
AD		 227MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
228module_param_named(aspm, radeon_aspm, int, 0444);
229
14adc892
CK		 230static struct pci_device_id pciidlist[] = {
231 radeon_PCI_IDS
232};
233
234MODULE_DEVICE_TABLE(pci, pciidlist);
235
236#ifdef CONFIG_DRM_RADEON_UMS
237
0a3e67a4
JB		 238static int radeon_suspend(struct drm_device *dev, pm_message_t state)
239{
240 drm_radeon_private_t *dev_priv = dev->dev_private;
241
03efb885
DA		 242 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
243 return 0;
244
0a3e67a4 245 /* Disable *all* interrupts */
800b6995 246 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
0a3e67a4
JB		 247 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
248 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
249 return 0;
250}
251
252static int radeon_resume(struct drm_device *dev)
253{
254 drm_radeon_private_t *dev_priv = dev->dev_private;
255
03efb885
DA		 256 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
257 return 0;
258
0a3e67a4 259 /* Restore interrupt registers */
800b6995 260 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
0a3e67a4
JB		 261 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
262 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
263 return 0;
264}
265
e08e96de
AV		 266static const struct file_operations radeon_driver_old_fops = {
267 .owner = THIS_MODULE,
268 .open = drm_open,
269 .release = drm_release,
270 .unlocked_ioctl = drm_ioctl,
271 .mmap = drm_mmap,
272 .poll = drm_poll,
273 .fasync = drm_fasync,
274 .read = drm_read,
275#ifdef CONFIG_COMPAT
276 .compat_ioctl = radeon_compat_ioctl,
277#endif
278 .llseek = noop_llseek,
279};
280
771fe6b9 281static struct drm_driver driver_old = {
b5e89ed5
DA		 282 .driver_features =
283 DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG |
0a3e67a4 284 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED,
1da177e4 285 .dev_priv_size = sizeof(drm_radeon_buf_priv_t),
22eae947
DA		 286 .load = radeon_driver_load,
287 .firstopen = radeon_driver_firstopen,
288 .open = radeon_driver_open,
289 .preclose = radeon_driver_preclose,
290 .postclose = radeon_driver_postclose,
291 .lastclose = radeon_driver_lastclose,
292 .unload = radeon_driver_unload,
0a3e67a4
JB		 293 .suspend = radeon_suspend,
294 .resume = radeon_resume,
295 .get_vblank_counter = radeon_get_vblank_counter,
296 .enable_vblank = radeon_enable_vblank,
297 .disable_vblank = radeon_disable_vblank,
60f2ee0b
DA		 298 .master_create = radeon_master_create,
299 .master_destroy = radeon_master_destroy,
1da177e4
LT		 300 .irq_preinstall = radeon_driver_irq_preinstall,
301 .irq_postinstall = radeon_driver_irq_postinstall,
302 .irq_uninstall = radeon_driver_irq_uninstall,
303 .irq_handler = radeon_driver_irq_handler,
1da177e4
LT		 304 .ioctls = radeon_ioctls,
305 .dma_ioctl = radeon_cp_buffers,
e08e96de 306 .fops = &radeon_driver_old_fops,
22eae947
DA		 307 .name = DRIVER_NAME,
308 .desc = DRIVER_DESC,
309 .date = DRIVER_DATE,
310 .major = DRIVER_MAJOR,
311 .minor = DRIVER_MINOR,
312 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT		 313};
314
14adc892
CK		 315#endif
316
771fe6b9
JG		 317static struct drm_driver kms_driver;
318
30238151 319static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
a56f7428
BH		 320{
321 struct apertures_struct *ap;
322 bool primary = false;
323
324 ap = alloc_apertures(1);
30238151
TR		 325 if (!ap)
326 return -ENOMEM;
327
a56f7428
BH		 328 ap->ranges[0].base = pci_resource_start(pdev, 0);
329 ap->ranges[0].size = pci_resource_len(pdev, 0);
330
331#ifdef CONFIG_X86
332 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
333#endif
334 remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
335 kfree(ap);
30238151
TR		 336
337 return 0;
a56f7428
BH		 338}
339
56550d94
GKH		 340static int radeon_pci_probe(struct pci_dev *pdev,
341 const struct pci_device_id *ent)
771fe6b9 342{
30238151
TR		 343 int ret;
344
a56f7428 345 /* Get rid of things like offb */
30238151
TR		 346 ret = radeon_kick_out_firmware_fb(pdev);
347 if (ret)
348 return ret;
a56f7428 349
dcdb1674 350 return drm_get_pci_dev(pdev, ent, &kms_driver);
771fe6b9
JG		 351}
352
353static void
354radeon_pci_remove(struct pci_dev *pdev)
355{
356 struct drm_device *dev = pci_get_drvdata(pdev);
357
358 drm_put_dev(dev);
359}
360
361static int
362radeon_pci_suspend(struct pci_dev *pdev, pm_message_t state)
363{
364 struct drm_device *dev = pci_get_drvdata(pdev);
365 return radeon_suspend_kms(dev, state);
366}
367
368static int
369radeon_pci_resume(struct pci_dev *pdev)
370{
371 struct drm_device *dev = pci_get_drvdata(pdev);
372 return radeon_resume_kms(dev);
373}
374
e08e96de
AV		 375static const struct file_operations radeon_driver_kms_fops = {
376 .owner = THIS_MODULE,
377 .open = drm_open,
378 .release = drm_release,
379 .unlocked_ioctl = drm_ioctl,
380 .mmap = radeon_mmap,
381 .poll = drm_poll,
382 .fasync = drm_fasync,
383 .read = drm_read,
384#ifdef CONFIG_COMPAT
385 .compat_ioctl = radeon_kms_compat_ioctl,
386#endif
387};
388
771fe6b9
JG		 389static struct drm_driver kms_driver = {
390 .driver_features =
391 DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG |
40f5cf99
AD		 392 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_GEM |
393 DRIVER_PRIME,
771fe6b9
JG		 394 .dev_priv_size = 0,
395 .load = radeon_driver_load_kms,
396 .firstopen = radeon_driver_firstopen_kms,
397 .open = radeon_driver_open_kms,
398 .preclose = radeon_driver_preclose_kms,
399 .postclose = radeon_driver_postclose_kms,
400 .lastclose = radeon_driver_lastclose_kms,
401 .unload = radeon_driver_unload_kms,
402 .suspend = radeon_suspend_kms,
403 .resume = radeon_resume_kms,
404 .get_vblank_counter = radeon_get_vblank_counter_kms,
405 .enable_vblank = radeon_enable_vblank_kms,
406 .disable_vblank = radeon_disable_vblank_kms,
f5a80209
MK		 407 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
408 .get_scanout_position = radeon_get_crtc_scanoutpos,
771fe6b9
JG		 409#if defined(CONFIG_DEBUG_FS)
410 .debugfs_init = radeon_debugfs_init,
411 .debugfs_cleanup = radeon_debugfs_cleanup,
412#endif
413 .irq_preinstall = radeon_driver_irq_preinstall_kms,
414 .irq_postinstall = radeon_driver_irq_postinstall_kms,
415 .irq_uninstall = radeon_driver_irq_uninstall_kms,
416 .irq_handler = radeon_driver_irq_handler_kms,
771fe6b9
JG		 417 .ioctls = radeon_ioctls_kms,
418 .gem_init_object = radeon_gem_object_init,
419 .gem_free_object = radeon_gem_object_free,
721604a1
JG		 420 .gem_open_object = radeon_gem_object_open,
421 .gem_close_object = radeon_gem_object_close,
ff72145b
DA		 422 .dumb_create = radeon_mode_dumb_create,
423 .dumb_map_offset = radeon_mode_dumb_mmap,
424 .dumb_destroy = radeon_mode_dumb_destroy,
e08e96de 425 .fops = &radeon_driver_kms_fops,
40f5cf99
AD		 426
427 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
428 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1e6d17a5
AP		 429 .gem_prime_export = drm_gem_prime_export,
430 .gem_prime_import = drm_gem_prime_import,
431 .gem_prime_pin = radeon_gem_prime_pin,
280cf211 432 .gem_prime_unpin = radeon_gem_prime_unpin,
1e6d17a5
AP		 433 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
434 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
435 .gem_prime_vmap = radeon_gem_prime_vmap,
436 .gem_prime_vunmap = radeon_gem_prime_vunmap,
40f5cf99 437
771fe6b9
JG		 438 .name = DRIVER_NAME,
439 .desc = DRIVER_DESC,
440 .date = DRIVER_DATE,
441 .major = KMS_DRIVER_MAJOR,
442 .minor = KMS_DRIVER_MINOR,
443 .patchlevel = KMS_DRIVER_PATCHLEVEL,
444};
771fe6b9
JG		 445
446static struct drm_driver *driver;
8410ea3b
DA		 447static struct pci_driver *pdriver;
448
14adc892 449#ifdef CONFIG_DRM_RADEON_UMS
8410ea3b
DA		 450static struct pci_driver radeon_pci_driver = {
451 .name = DRIVER_NAME,
452 .id_table = pciidlist,
453};
14adc892 454#endif
8410ea3b
DA		 455
456static struct pci_driver radeon_kms_pci_driver = {
457 .name = DRIVER_NAME,
458 .id_table = pciidlist,
459 .probe = radeon_pci_probe,
460 .remove = radeon_pci_remove,
461 .suspend = radeon_pci_suspend,
462 .resume = radeon_pci_resume,
463};
771fe6b9 464
1da177e4
LT		 465static int __init radeon_init(void)
466{
e9ced8e0
DA		 467#ifdef CONFIG_VGA_CONSOLE
468 if (vgacon_text_force() && radeon_modeset == -1) {
469 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
470 radeon_modeset = 0;
471 }
472#endif
473 /* set to modesetting by default if not nomodeset */
474 if (radeon_modeset == -1)
475 radeon_modeset = 1;
476
771fe6b9
JG		 477 if (radeon_modeset == 1) {
478 DRM_INFO("radeon kernel modesetting enabled.\n");
479 driver = &kms_driver;
8410ea3b 480 pdriver = &radeon_kms_pci_driver;
771fe6b9
JG		 481 driver->driver_features |= DRIVER_MODESET;
482 driver->num_ioctls = radeon_max_kms_ioctl;
6a9ee8af 483 radeon_register_atpx_handler();
14adc892
CK		 484
485 } else {
486#ifdef CONFIG_DRM_RADEON_UMS
487 DRM_INFO("radeon userspace modesetting enabled.\n");
488 driver = &driver_old;
489 pdriver = &radeon_pci_driver;
490 driver->driver_features &= ~DRIVER_MODESET;
491 driver->num_ioctls = radeon_max_ioctl;
492#else
493 DRM_ERROR("No UMS support in radeon module!\n");
494 return -EINVAL;
495#endif
771fe6b9 496 }
14adc892
CK		 497
498 /* let modprobe override vga console setting */
8410ea3b 499 return drm_pci_init(driver, pdriver);
1da177e4
LT		 500}
501
502static void __exit radeon_exit(void)
503{
8410ea3b 504 drm_pci_exit(driver, pdriver);
6a9ee8af 505 radeon_unregister_atpx_handler();
1da177e4
LT		 506}
507
176f613e 508module_init(radeon_init);
1da177e4
LT		 509module_exit(radeon_exit);
510
b5e89ed5
DA		 511MODULE_AUTHOR(DRIVER_AUTHOR);
512MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 513MODULE_LICENSE("GPL and additional rights");
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