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1da177e4 LT |
1 | /** |
2 | * \file radeon_drv.c | |
3 | * ATI Radeon driver | |
4 | * | |
5 | * \author Gareth Hughes <gareth@valinux.com> | |
6 | */ | |
7 | ||
8 | /* | |
9 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
10 | * All Rights Reserved. | |
11 | * | |
12 | * Permission is hereby granted, free of charge, to any person obtaining a | |
13 | * copy of this software and associated documentation files (the "Software"), | |
14 | * to deal in the Software without restriction, including without limitation | |
15 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
16 | * and/or sell copies of the Software, and to permit persons to whom the | |
17 | * Software is furnished to do so, subject to the following conditions: | |
18 | * | |
19 | * The above copyright notice and this permission notice (including the next | |
20 | * paragraph) shall be included in all copies or substantial portions of the | |
21 | * Software. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
24 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
25 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
26 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
27 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
28 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
29 | * OTHER DEALINGS IN THE SOFTWARE. | |
30 | */ | |
31 | ||
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/radeon_drm.h> | |
1da177e4 LT |
34 | #include "radeon_drv.h" |
35 | ||
760285e7 | 36 | #include <drm/drm_pciids.h> |
771fe6b9 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
771fe6b9 JG |
39 | |
40 | ||
771fe6b9 JG |
41 | /* |
42 | * KMS wrapper. | |
0de1a57b DA |
43 | * - 2.0.0 - initial interface |
44 | * - 2.1.0 - add square tiling interface | |
fdb43528 | 45 | * - 2.2.0 - add r6xx/r7xx const buffer support |
cae94b0a | 46 | * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs |
bc35afdb | 47 | * - 2.4.0 - add crtc id query |
148a03bc | 48 | * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen |
ab9e1f59 | 49 | * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) |
71901cc4 | 50 | * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs |
58bbf018 | 51 | * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query |
486af189 | 52 | * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query |
b8709894 AD |
53 | * 2.10.0 - fusion 2D tiling |
54 | * 2.11.0 - backend map, initial compute support for the CS checker | |
e70f224c | 55 | * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS |
dd220a00 | 56 | * 2.13.0 - virtual memory support, streamout |
285484e2 | 57 | * 2.14.0 - add evergreen tiling informations |
609c1e15 | 58 | * 2.15.0 - add max_pipes query |
d2609875 | 59 | * 2.16.0 - fix evergreen 2D tiled surface calculation |
7c77bf2a | 60 | * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx |
0f457e48 | 61 | * 2.18.0 - r600-eg: allow "invalid" DB formats |
b51ad12a | 62 | * 2.19.0 - r600-eg: MSAA textures |
6759a0a7 | 63 | * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query |
c116cc94 | 64 | * 2.21.0 - r600-r700: FMASK and CMASK |
523885de | 65 | * 2.22.0 - r600 only: RESOLVE_BOX allowed |
46fc8781 | 66 | * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 |
61051afd | 67 | * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures |
71bfe916 | 68 | * 2.25.0 - eg+: new info request for num SE and num SH |
4ac0533a | 69 | * 2.26.0 - r600-eg: fix htile size computation |
8696e33f | 70 | * 2.27.0 - r600-SI: Add CS ioctl support for async DMA |
4613ca14 | 71 | * 2.28.0 - r600-eg: Add MEM_WRITE packet support |
c18b1170 | 72 | * 2.29.0 - R500 FP16 color clear registers |
774c389f | 73 | * 2.30.0 - fix for FMASK texturing |
771fe6b9 JG |
74 | */ |
75 | #define KMS_DRIVER_MAJOR 2 | |
774c389f | 76 | #define KMS_DRIVER_MINOR 30 |
771fe6b9 JG |
77 | #define KMS_DRIVER_PATCHLEVEL 0 |
78 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); | |
79 | int radeon_driver_unload_kms(struct drm_device *dev); | |
80 | int radeon_driver_firstopen_kms(struct drm_device *dev); | |
81 | void radeon_driver_lastclose_kms(struct drm_device *dev); | |
82 | int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); | |
83 | void radeon_driver_postclose_kms(struct drm_device *dev, | |
84 | struct drm_file *file_priv); | |
85 | void radeon_driver_preclose_kms(struct drm_device *dev, | |
86 | struct drm_file *file_priv); | |
87 | int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); | |
88 | int radeon_resume_kms(struct drm_device *dev); | |
89 | u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc); | |
90 | int radeon_enable_vblank_kms(struct drm_device *dev, int crtc); | |
91 | void radeon_disable_vblank_kms(struct drm_device *dev, int crtc); | |
f5a80209 MK |
92 | int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, |
93 | int *max_error, | |
94 | struct timeval *vblank_time, | |
95 | unsigned flags); | |
771fe6b9 JG |
96 | void radeon_driver_irq_preinstall_kms(struct drm_device *dev); |
97 | int radeon_driver_irq_postinstall_kms(struct drm_device *dev); | |
98 | void radeon_driver_irq_uninstall_kms(struct drm_device *dev); | |
99 | irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS); | |
771fe6b9 JG |
100 | int radeon_dma_ioctl_kms(struct drm_device *dev, void *data, |
101 | struct drm_file *file_priv); | |
102 | int radeon_gem_object_init(struct drm_gem_object *obj); | |
103 | void radeon_gem_object_free(struct drm_gem_object *obj); | |
721604a1 JG |
104 | int radeon_gem_object_open(struct drm_gem_object *obj, |
105 | struct drm_file *file_priv); | |
106 | void radeon_gem_object_close(struct drm_gem_object *obj, | |
107 | struct drm_file *file_priv); | |
f5a80209 MK |
108 | extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, |
109 | int *vpos, int *hpos); | |
771fe6b9 JG |
110 | extern struct drm_ioctl_desc radeon_ioctls_kms[]; |
111 | extern int radeon_max_kms_ioctl; | |
112 | int radeon_mmap(struct file *filp, struct vm_area_struct *vma); | |
ff72145b DA |
113 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
114 | struct drm_device *dev, | |
115 | uint32_t handle, uint64_t *offset_p); | |
116 | int radeon_mode_dumb_create(struct drm_file *file_priv, | |
117 | struct drm_device *dev, | |
118 | struct drm_mode_create_dumb *args); | |
119 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, | |
120 | struct drm_device *dev, | |
121 | uint32_t handle); | |
1e6d17a5 AP |
122 | struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); |
123 | struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, | |
124 | size_t size, | |
125 | struct sg_table *sg); | |
126 | int radeon_gem_prime_pin(struct drm_gem_object *obj); | |
127 | void *radeon_gem_prime_vmap(struct drm_gem_object *obj); | |
128 | void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); | |
14adc892 CK |
129 | extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, |
130 | unsigned long arg); | |
ff72145b | 131 | |
771fe6b9 JG |
132 | #if defined(CONFIG_DEBUG_FS) |
133 | int radeon_debugfs_init(struct drm_minor *minor); | |
134 | void radeon_debugfs_cleanup(struct drm_minor *minor); | |
135 | #endif | |
771fe6b9 | 136 | |
14adc892 CK |
137 | /* atpx handler */ |
138 | #if defined(CONFIG_VGA_SWITCHEROO) | |
139 | void radeon_register_atpx_handler(void); | |
140 | void radeon_unregister_atpx_handler(void); | |
141 | #else | |
142 | static inline void radeon_register_atpx_handler(void) {} | |
143 | static inline void radeon_unregister_atpx_handler(void) {} | |
144 | #endif | |
1da177e4 | 145 | |
689b9d74 | 146 | int radeon_no_wb; |
14adc892 | 147 | int radeon_modeset = 1; |
771fe6b9 JG |
148 | int radeon_dynclks = -1; |
149 | int radeon_r4xx_atom = 0; | |
150 | int radeon_agpmode = 0; | |
151 | int radeon_vram_limit = 0; | |
152 | int radeon_gart_size = 512; /* default gart size */ | |
153 | int radeon_benchmarking = 0; | |
ecc0b326 | 154 | int radeon_testing = 0; |
771fe6b9 | 155 | int radeon_connector_table = 0; |
4ce001ab | 156 | int radeon_tv = 1; |
805c2216 | 157 | int radeon_audio = 0; |
f46c0120 | 158 | int radeon_disp_priority = 0; |
e2b0a8e1 | 159 | int radeon_hw_i2c = 0; |
197bbb3d | 160 | int radeon_pcie_gen2 = -1; |
a18cee15 | 161 | int radeon_msi = -1; |
3368ff0c | 162 | int radeon_lockup_timeout = 10000; |
689b9d74 | 163 | |
61a2d07d | 164 | MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); |
689b9d74 DA |
165 | module_param_named(no_wb, radeon_no_wb, int, 0444); |
166 | ||
771fe6b9 JG |
167 | MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); |
168 | module_param_named(modeset, radeon_modeset, int, 0400); | |
169 | ||
170 | MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); | |
171 | module_param_named(dynclks, radeon_dynclks, int, 0444); | |
172 | ||
173 | MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); | |
174 | module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); | |
175 | ||
176 | MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing"); | |
177 | module_param_named(vramlimit, radeon_vram_limit, int, 0600); | |
178 | ||
179 | MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); | |
180 | module_param_named(agpmode, radeon_agpmode, int, 0444); | |
181 | ||
27d4d052 | 182 | MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc)"); |
771fe6b9 JG |
183 | module_param_named(gartsize, radeon_gart_size, int, 0600); |
184 | ||
185 | MODULE_PARM_DESC(benchmark, "Run benchmark"); | |
186 | module_param_named(benchmark, radeon_benchmarking, int, 0444); | |
187 | ||
ecc0b326 MD |
188 | MODULE_PARM_DESC(test, "Run tests"); |
189 | module_param_named(test, radeon_testing, int, 0444); | |
190 | ||
771fe6b9 JG |
191 | MODULE_PARM_DESC(connector_table, "Force connector table"); |
192 | module_param_named(connector_table, radeon_connector_table, int, 0444); | |
4ce001ab DA |
193 | |
194 | MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); | |
195 | module_param_named(tv, radeon_tv, int, 0444); | |
771fe6b9 | 196 | |
805c2216 | 197 | MODULE_PARM_DESC(audio, "Audio enable (1 = enable)"); |
dafc3bd5 CK |
198 | module_param_named(audio, radeon_audio, int, 0444); |
199 | ||
f46c0120 AD |
200 | MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); |
201 | module_param_named(disp_priority, radeon_disp_priority, int, 0444); | |
202 | ||
e2b0a8e1 AD |
203 | MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); |
204 | module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); | |
205 | ||
197bbb3d | 206 | MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); |
d42dd579 AD |
207 | module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); |
208 | ||
a18cee15 AD |
209 | MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); |
210 | module_param_named(msi, radeon_msi, int, 0444); | |
211 | ||
3368ff0c CK |
212 | MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)"); |
213 | module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); | |
214 | ||
14adc892 CK |
215 | static struct pci_device_id pciidlist[] = { |
216 | radeon_PCI_IDS | |
217 | }; | |
218 | ||
219 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
220 | ||
221 | #ifdef CONFIG_DRM_RADEON_UMS | |
222 | ||
0a3e67a4 JB |
223 | static int radeon_suspend(struct drm_device *dev, pm_message_t state) |
224 | { | |
225 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
226 | ||
03efb885 DA |
227 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
228 | return 0; | |
229 | ||
0a3e67a4 | 230 | /* Disable *all* interrupts */ |
800b6995 | 231 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) |
0a3e67a4 JB |
232 | RADEON_WRITE(R500_DxMODE_INT_MASK, 0); |
233 | RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); | |
234 | return 0; | |
235 | } | |
236 | ||
237 | static int radeon_resume(struct drm_device *dev) | |
238 | { | |
239 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
240 | ||
03efb885 DA |
241 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
242 | return 0; | |
243 | ||
0a3e67a4 | 244 | /* Restore interrupt registers */ |
800b6995 | 245 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) |
0a3e67a4 JB |
246 | RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); |
247 | RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); | |
248 | return 0; | |
249 | } | |
250 | ||
e08e96de AV |
251 | static const struct file_operations radeon_driver_old_fops = { |
252 | .owner = THIS_MODULE, | |
253 | .open = drm_open, | |
254 | .release = drm_release, | |
255 | .unlocked_ioctl = drm_ioctl, | |
256 | .mmap = drm_mmap, | |
257 | .poll = drm_poll, | |
258 | .fasync = drm_fasync, | |
259 | .read = drm_read, | |
260 | #ifdef CONFIG_COMPAT | |
261 | .compat_ioctl = radeon_compat_ioctl, | |
262 | #endif | |
263 | .llseek = noop_llseek, | |
264 | }; | |
265 | ||
771fe6b9 | 266 | static struct drm_driver driver_old = { |
b5e89ed5 DA |
267 | .driver_features = |
268 | DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | | |
0a3e67a4 | 269 | DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED, |
1da177e4 | 270 | .dev_priv_size = sizeof(drm_radeon_buf_priv_t), |
22eae947 DA |
271 | .load = radeon_driver_load, |
272 | .firstopen = radeon_driver_firstopen, | |
273 | .open = radeon_driver_open, | |
274 | .preclose = radeon_driver_preclose, | |
275 | .postclose = radeon_driver_postclose, | |
276 | .lastclose = radeon_driver_lastclose, | |
277 | .unload = radeon_driver_unload, | |
0a3e67a4 JB |
278 | .suspend = radeon_suspend, |
279 | .resume = radeon_resume, | |
280 | .get_vblank_counter = radeon_get_vblank_counter, | |
281 | .enable_vblank = radeon_enable_vblank, | |
282 | .disable_vblank = radeon_disable_vblank, | |
60f2ee0b DA |
283 | .master_create = radeon_master_create, |
284 | .master_destroy = radeon_master_destroy, | |
1da177e4 LT |
285 | .irq_preinstall = radeon_driver_irq_preinstall, |
286 | .irq_postinstall = radeon_driver_irq_postinstall, | |
287 | .irq_uninstall = radeon_driver_irq_uninstall, | |
288 | .irq_handler = radeon_driver_irq_handler, | |
1da177e4 LT |
289 | .ioctls = radeon_ioctls, |
290 | .dma_ioctl = radeon_cp_buffers, | |
e08e96de | 291 | .fops = &radeon_driver_old_fops, |
22eae947 DA |
292 | .name = DRIVER_NAME, |
293 | .desc = DRIVER_DESC, | |
294 | .date = DRIVER_DATE, | |
295 | .major = DRIVER_MAJOR, | |
296 | .minor = DRIVER_MINOR, | |
297 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
298 | }; |
299 | ||
14adc892 CK |
300 | #endif |
301 | ||
771fe6b9 JG |
302 | static struct drm_driver kms_driver; |
303 | ||
30238151 | 304 | static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) |
a56f7428 BH |
305 | { |
306 | struct apertures_struct *ap; | |
307 | bool primary = false; | |
308 | ||
309 | ap = alloc_apertures(1); | |
30238151 TR |
310 | if (!ap) |
311 | return -ENOMEM; | |
312 | ||
a56f7428 BH |
313 | ap->ranges[0].base = pci_resource_start(pdev, 0); |
314 | ap->ranges[0].size = pci_resource_len(pdev, 0); | |
315 | ||
316 | #ifdef CONFIG_X86 | |
317 | primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
318 | #endif | |
319 | remove_conflicting_framebuffers(ap, "radeondrmfb", primary); | |
320 | kfree(ap); | |
30238151 TR |
321 | |
322 | return 0; | |
a56f7428 BH |
323 | } |
324 | ||
56550d94 GKH |
325 | static int radeon_pci_probe(struct pci_dev *pdev, |
326 | const struct pci_device_id *ent) | |
771fe6b9 | 327 | { |
30238151 TR |
328 | int ret; |
329 | ||
a56f7428 | 330 | /* Get rid of things like offb */ |
30238151 TR |
331 | ret = radeon_kick_out_firmware_fb(pdev); |
332 | if (ret) | |
333 | return ret; | |
a56f7428 | 334 | |
dcdb1674 | 335 | return drm_get_pci_dev(pdev, ent, &kms_driver); |
771fe6b9 JG |
336 | } |
337 | ||
338 | static void | |
339 | radeon_pci_remove(struct pci_dev *pdev) | |
340 | { | |
341 | struct drm_device *dev = pci_get_drvdata(pdev); | |
342 | ||
343 | drm_put_dev(dev); | |
344 | } | |
345 | ||
346 | static int | |
347 | radeon_pci_suspend(struct pci_dev *pdev, pm_message_t state) | |
348 | { | |
349 | struct drm_device *dev = pci_get_drvdata(pdev); | |
350 | return radeon_suspend_kms(dev, state); | |
351 | } | |
352 | ||
353 | static int | |
354 | radeon_pci_resume(struct pci_dev *pdev) | |
355 | { | |
356 | struct drm_device *dev = pci_get_drvdata(pdev); | |
357 | return radeon_resume_kms(dev); | |
358 | } | |
359 | ||
e08e96de AV |
360 | static const struct file_operations radeon_driver_kms_fops = { |
361 | .owner = THIS_MODULE, | |
362 | .open = drm_open, | |
363 | .release = drm_release, | |
364 | .unlocked_ioctl = drm_ioctl, | |
365 | .mmap = radeon_mmap, | |
366 | .poll = drm_poll, | |
367 | .fasync = drm_fasync, | |
368 | .read = drm_read, | |
369 | #ifdef CONFIG_COMPAT | |
370 | .compat_ioctl = radeon_kms_compat_ioctl, | |
371 | #endif | |
372 | }; | |
373 | ||
771fe6b9 JG |
374 | static struct drm_driver kms_driver = { |
375 | .driver_features = | |
376 | DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | | |
40f5cf99 AD |
377 | DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_GEM | |
378 | DRIVER_PRIME, | |
771fe6b9 JG |
379 | .dev_priv_size = 0, |
380 | .load = radeon_driver_load_kms, | |
381 | .firstopen = radeon_driver_firstopen_kms, | |
382 | .open = radeon_driver_open_kms, | |
383 | .preclose = radeon_driver_preclose_kms, | |
384 | .postclose = radeon_driver_postclose_kms, | |
385 | .lastclose = radeon_driver_lastclose_kms, | |
386 | .unload = radeon_driver_unload_kms, | |
387 | .suspend = radeon_suspend_kms, | |
388 | .resume = radeon_resume_kms, | |
389 | .get_vblank_counter = radeon_get_vblank_counter_kms, | |
390 | .enable_vblank = radeon_enable_vblank_kms, | |
391 | .disable_vblank = radeon_disable_vblank_kms, | |
f5a80209 MK |
392 | .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, |
393 | .get_scanout_position = radeon_get_crtc_scanoutpos, | |
771fe6b9 JG |
394 | #if defined(CONFIG_DEBUG_FS) |
395 | .debugfs_init = radeon_debugfs_init, | |
396 | .debugfs_cleanup = radeon_debugfs_cleanup, | |
397 | #endif | |
398 | .irq_preinstall = radeon_driver_irq_preinstall_kms, | |
399 | .irq_postinstall = radeon_driver_irq_postinstall_kms, | |
400 | .irq_uninstall = radeon_driver_irq_uninstall_kms, | |
401 | .irq_handler = radeon_driver_irq_handler_kms, | |
771fe6b9 JG |
402 | .ioctls = radeon_ioctls_kms, |
403 | .gem_init_object = radeon_gem_object_init, | |
404 | .gem_free_object = radeon_gem_object_free, | |
721604a1 JG |
405 | .gem_open_object = radeon_gem_object_open, |
406 | .gem_close_object = radeon_gem_object_close, | |
771fe6b9 | 407 | .dma_ioctl = radeon_dma_ioctl_kms, |
ff72145b DA |
408 | .dumb_create = radeon_mode_dumb_create, |
409 | .dumb_map_offset = radeon_mode_dumb_mmap, | |
410 | .dumb_destroy = radeon_mode_dumb_destroy, | |
e08e96de | 411 | .fops = &radeon_driver_kms_fops, |
40f5cf99 AD |
412 | |
413 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
414 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
1e6d17a5 AP |
415 | .gem_prime_export = drm_gem_prime_export, |
416 | .gem_prime_import = drm_gem_prime_import, | |
417 | .gem_prime_pin = radeon_gem_prime_pin, | |
418 | .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, | |
419 | .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, | |
420 | .gem_prime_vmap = radeon_gem_prime_vmap, | |
421 | .gem_prime_vunmap = radeon_gem_prime_vunmap, | |
40f5cf99 | 422 | |
771fe6b9 JG |
423 | .name = DRIVER_NAME, |
424 | .desc = DRIVER_DESC, | |
425 | .date = DRIVER_DATE, | |
426 | .major = KMS_DRIVER_MAJOR, | |
427 | .minor = KMS_DRIVER_MINOR, | |
428 | .patchlevel = KMS_DRIVER_PATCHLEVEL, | |
429 | }; | |
771fe6b9 JG |
430 | |
431 | static struct drm_driver *driver; | |
8410ea3b DA |
432 | static struct pci_driver *pdriver; |
433 | ||
14adc892 | 434 | #ifdef CONFIG_DRM_RADEON_UMS |
8410ea3b DA |
435 | static struct pci_driver radeon_pci_driver = { |
436 | .name = DRIVER_NAME, | |
437 | .id_table = pciidlist, | |
438 | }; | |
14adc892 | 439 | #endif |
8410ea3b DA |
440 | |
441 | static struct pci_driver radeon_kms_pci_driver = { | |
442 | .name = DRIVER_NAME, | |
443 | .id_table = pciidlist, | |
444 | .probe = radeon_pci_probe, | |
445 | .remove = radeon_pci_remove, | |
446 | .suspend = radeon_pci_suspend, | |
447 | .resume = radeon_pci_resume, | |
448 | }; | |
771fe6b9 | 449 | |
1da177e4 LT |
450 | static int __init radeon_init(void) |
451 | { | |
771fe6b9 JG |
452 | if (radeon_modeset == 1) { |
453 | DRM_INFO("radeon kernel modesetting enabled.\n"); | |
454 | driver = &kms_driver; | |
8410ea3b | 455 | pdriver = &radeon_kms_pci_driver; |
771fe6b9 JG |
456 | driver->driver_features |= DRIVER_MODESET; |
457 | driver->num_ioctls = radeon_max_kms_ioctl; | |
6a9ee8af | 458 | radeon_register_atpx_handler(); |
14adc892 CK |
459 | |
460 | } else { | |
461 | #ifdef CONFIG_DRM_RADEON_UMS | |
462 | DRM_INFO("radeon userspace modesetting enabled.\n"); | |
463 | driver = &driver_old; | |
464 | pdriver = &radeon_pci_driver; | |
465 | driver->driver_features &= ~DRIVER_MODESET; | |
466 | driver->num_ioctls = radeon_max_ioctl; | |
467 | #else | |
468 | DRM_ERROR("No UMS support in radeon module!\n"); | |
469 | return -EINVAL; | |
470 | #endif | |
771fe6b9 | 471 | } |
14adc892 CK |
472 | |
473 | /* let modprobe override vga console setting */ | |
8410ea3b | 474 | return drm_pci_init(driver, pdriver); |
1da177e4 LT |
475 | } |
476 | ||
477 | static void __exit radeon_exit(void) | |
478 | { | |
8410ea3b | 479 | drm_pci_exit(driver, pdriver); |
6a9ee8af | 480 | radeon_unregister_atpx_handler(); |
1da177e4 LT |
481 | } |
482 | ||
176f613e | 483 | module_init(radeon_init); |
1da177e4 LT |
484 | module_exit(radeon_exit); |
485 | ||
b5e89ed5 DA |
486 | MODULE_AUTHOR(DRIVER_AUTHOR); |
487 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 488 | MODULE_LICENSE("GPL and additional rights"); |