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drm: Pass 'flags' from the caller to .get_scanout_position()
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / radeon_drv.c
CommitLineData
1da177e4
LT
1/**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
760285e7
DH
32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
1da177e4
LT
34#include "radeon_drv.h"
35
760285e7 36#include <drm/drm_pciids.h>
771fe6b9 37#include <linux/console.h>
e0cd3608 38#include <linux/module.h>
10ebc0bc
DA
39#include <linux/pm_runtime.h>
40#include <linux/vga_switcheroo.h>
41#include "drm_crtc_helper.h"
771fe6b9
JG
42/*
43 * KMS wrapper.
0de1a57b
DA
44 * - 2.0.0 - initial interface
45 * - 2.1.0 - add square tiling interface
fdb43528 46 * - 2.2.0 - add r6xx/r7xx const buffer support
cae94b0a 47 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
bc35afdb 48 * - 2.4.0 - add crtc id query
148a03bc 49 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
ab9e1f59 50 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
71901cc4 51 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
58bbf018 52 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
486af189 53 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
b8709894
AD
54 * 2.10.0 - fusion 2D tiling
55 * 2.11.0 - backend map, initial compute support for the CS checker
e70f224c 56 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
dd220a00 57 * 2.13.0 - virtual memory support, streamout
285484e2 58 * 2.14.0 - add evergreen tiling informations
609c1e15 59 * 2.15.0 - add max_pipes query
d2609875 60 * 2.16.0 - fix evergreen 2D tiled surface calculation
7c77bf2a 61 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
0f457e48 62 * 2.18.0 - r600-eg: allow "invalid" DB formats
b51ad12a 63 * 2.19.0 - r600-eg: MSAA textures
6759a0a7 64 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
c116cc94 65 * 2.21.0 - r600-r700: FMASK and CMASK
523885de 66 * 2.22.0 - r600 only: RESOLVE_BOX allowed
46fc8781 67 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
61051afd 68 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
71bfe916 69 * 2.25.0 - eg+: new info request for num SE and num SH
4ac0533a 70 * 2.26.0 - r600-eg: fix htile size computation
8696e33f 71 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
4613ca14 72 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
c18b1170 73 * 2.29.0 - R500 FP16 color clear registers
774c389f 74 * 2.30.0 - fix for FMASK texturing
a0a53aa8 75 * 2.31.0 - Add fastfb support for rs690
902aaef6 76 * 2.32.0 - new info request for rings working
64d7b8be 77 * 2.33.0 - Add SI tiling mode array query
39aee490 78 * 2.34.0 - Add CIK tiling mode array query
32f79a8a 79 * 2.35.0 - Add CIK macrotile mode array query
9482d0d3 80 * 2.36.0 - Fix CIK DCE tiling setup
771fe6b9
JG
81 */
82#define KMS_DRIVER_MAJOR 2
9482d0d3 83#define KMS_DRIVER_MINOR 36
771fe6b9
JG
84#define KMS_DRIVER_PATCHLEVEL 0
85int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
86int radeon_driver_unload_kms(struct drm_device *dev);
771fe6b9
JG
87void radeon_driver_lastclose_kms(struct drm_device *dev);
88int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
89void radeon_driver_postclose_kms(struct drm_device *dev,
90 struct drm_file *file_priv);
91void radeon_driver_preclose_kms(struct drm_device *dev,
92 struct drm_file *file_priv);
10ebc0bc
DA
93int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
94int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
771fe6b9
JG
95u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc);
96int radeon_enable_vblank_kms(struct drm_device *dev, int crtc);
97void radeon_disable_vblank_kms(struct drm_device *dev, int crtc);
f5a80209
MK
98int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
99 int *max_error,
100 struct timeval *vblank_time,
101 unsigned flags);
771fe6b9
JG
102void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
103int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
104void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
e9f0d76f 105irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
771fe6b9 106void radeon_gem_object_free(struct drm_gem_object *obj);
721604a1
JG
107int radeon_gem_object_open(struct drm_gem_object *obj,
108 struct drm_file *file_priv);
109void radeon_gem_object_close(struct drm_gem_object *obj,
110 struct drm_file *file_priv);
f5a80209 111extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
abca9e45 112 unsigned int flags,
d47abc58
MK
113 int *vpos, int *hpos, ktime_t *stime,
114 ktime_t *etime);
baa70943 115extern const struct drm_ioctl_desc radeon_ioctls_kms[];
771fe6b9
JG
116extern int radeon_max_kms_ioctl;
117int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
ff72145b
DA
118int radeon_mode_dumb_mmap(struct drm_file *filp,
119 struct drm_device *dev,
120 uint32_t handle, uint64_t *offset_p);
121int radeon_mode_dumb_create(struct drm_file *file_priv,
122 struct drm_device *dev,
123 struct drm_mode_create_dumb *args);
1e6d17a5
AP
124struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
125struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
126 size_t size,
127 struct sg_table *sg);
128int radeon_gem_prime_pin(struct drm_gem_object *obj);
280cf211 129void radeon_gem_prime_unpin(struct drm_gem_object *obj);
1e6d17a5
AP
130void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
131void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
14adc892
CK
132extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
133 unsigned long arg);
ff72145b 134
771fe6b9
JG
135#if defined(CONFIG_DEBUG_FS)
136int radeon_debugfs_init(struct drm_minor *minor);
137void radeon_debugfs_cleanup(struct drm_minor *minor);
138#endif
771fe6b9 139
14adc892
CK
140/* atpx handler */
141#if defined(CONFIG_VGA_SWITCHEROO)
142void radeon_register_atpx_handler(void);
143void radeon_unregister_atpx_handler(void);
10ebc0bc 144bool radeon_is_px(void);
14adc892
CK
145#else
146static inline void radeon_register_atpx_handler(void) {}
147static inline void radeon_unregister_atpx_handler(void) {}
10ebc0bc 148static inline bool radeon_is_px(void) { return false; }
14adc892 149#endif
1da177e4 150
689b9d74 151int radeon_no_wb;
e9ced8e0 152int radeon_modeset = -1;
771fe6b9
JG
153int radeon_dynclks = -1;
154int radeon_r4xx_atom = 0;
155int radeon_agpmode = 0;
156int radeon_vram_limit = 0;
edcd26e8 157int radeon_gart_size = -1; /* auto */
771fe6b9 158int radeon_benchmarking = 0;
ecc0b326 159int radeon_testing = 0;
771fe6b9 160int radeon_connector_table = 0;
4ce001ab 161int radeon_tv = 1;
108dc8e8 162int radeon_audio = -1;
f46c0120 163int radeon_disp_priority = 0;
e2b0a8e1 164int radeon_hw_i2c = 0;
197bbb3d 165int radeon_pcie_gen2 = -1;
a18cee15 166int radeon_msi = -1;
3368ff0c 167int radeon_lockup_timeout = 10000;
a0a53aa8 168int radeon_fastfb = 0;
da321c8a 169int radeon_dpm = -1;
1294d4a3 170int radeon_aspm = -1;
10ebc0bc 171int radeon_runtime_pm = -1;
363eb0b4 172int radeon_hard_reset = 0;
689b9d74 173
61a2d07d 174MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
689b9d74
DA
175module_param_named(no_wb, radeon_no_wb, int, 0444);
176
771fe6b9
JG
177MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
178module_param_named(modeset, radeon_modeset, int, 0400);
179
180MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
181module_param_named(dynclks, radeon_dynclks, int, 0444);
182
183MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
184module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
185
186MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing");
187module_param_named(vramlimit, radeon_vram_limit, int, 0600);
188
189MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
190module_param_named(agpmode, radeon_agpmode, int, 0444);
191
edcd26e8 192MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
771fe6b9
JG
193module_param_named(gartsize, radeon_gart_size, int, 0600);
194
195MODULE_PARM_DESC(benchmark, "Run benchmark");
196module_param_named(benchmark, radeon_benchmarking, int, 0444);
197
ecc0b326
MD
198MODULE_PARM_DESC(test, "Run tests");
199module_param_named(test, radeon_testing, int, 0444);
200
771fe6b9
JG
201MODULE_PARM_DESC(connector_table, "Force connector table");
202module_param_named(connector_table, radeon_connector_table, int, 0444);
4ce001ab
DA
203
204MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
205module_param_named(tv, radeon_tv, int, 0444);
771fe6b9 206
108dc8e8 207MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
dafc3bd5
CK
208module_param_named(audio, radeon_audio, int, 0444);
209
f46c0120
AD
210MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
211module_param_named(disp_priority, radeon_disp_priority, int, 0444);
212
e2b0a8e1
AD
213MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
214module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
215
197bbb3d 216MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
d42dd579
AD
217module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
218
a18cee15
AD
219MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
220module_param_named(msi, radeon_msi, int, 0444);
221
3368ff0c
CK
222MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)");
223module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
224
a0a53aa8
SL
225MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
226module_param_named(fastfb, radeon_fastfb, int, 0444);
227
da321c8a
AD
228MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
229module_param_named(dpm, radeon_dpm, int, 0444);
230
1294d4a3
AD
231MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
232module_param_named(aspm, radeon_aspm, int, 0444);
233
10ebc0bc
DA
234MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
235module_param_named(runpm, radeon_runtime_pm, int, 0444);
236
363eb0b4
AD
237MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
238module_param_named(hard_reset, radeon_hard_reset, int, 0444);
239
14adc892
CK
240static struct pci_device_id pciidlist[] = {
241 radeon_PCI_IDS
242};
243
244MODULE_DEVICE_TABLE(pci, pciidlist);
245
246#ifdef CONFIG_DRM_RADEON_UMS
247
0a3e67a4
JB
248static int radeon_suspend(struct drm_device *dev, pm_message_t state)
249{
250 drm_radeon_private_t *dev_priv = dev->dev_private;
251
03efb885
DA
252 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
253 return 0;
254
0a3e67a4 255 /* Disable *all* interrupts */
800b6995 256 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
0a3e67a4
JB
257 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
258 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
259 return 0;
260}
261
262static int radeon_resume(struct drm_device *dev)
263{
264 drm_radeon_private_t *dev_priv = dev->dev_private;
265
03efb885
DA
266 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
267 return 0;
268
0a3e67a4 269 /* Restore interrupt registers */
800b6995 270 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
0a3e67a4
JB
271 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
272 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
273 return 0;
274}
275
10ebc0bc 276
e08e96de
AV
277static const struct file_operations radeon_driver_old_fops = {
278 .owner = THIS_MODULE,
279 .open = drm_open,
280 .release = drm_release,
281 .unlocked_ioctl = drm_ioctl,
282 .mmap = drm_mmap,
283 .poll = drm_poll,
e08e96de
AV
284 .read = drm_read,
285#ifdef CONFIG_COMPAT
286 .compat_ioctl = radeon_compat_ioctl,
287#endif
288 .llseek = noop_llseek,
289};
290
771fe6b9 291static struct drm_driver driver_old = {
b5e89ed5 292 .driver_features =
28185647 293 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
0a3e67a4 294 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED,
1da177e4 295 .dev_priv_size = sizeof(drm_radeon_buf_priv_t),
22eae947
DA
296 .load = radeon_driver_load,
297 .firstopen = radeon_driver_firstopen,
298 .open = radeon_driver_open,
299 .preclose = radeon_driver_preclose,
300 .postclose = radeon_driver_postclose,
301 .lastclose = radeon_driver_lastclose,
302 .unload = radeon_driver_unload,
0a3e67a4
JB
303 .suspend = radeon_suspend,
304 .resume = radeon_resume,
305 .get_vblank_counter = radeon_get_vblank_counter,
306 .enable_vblank = radeon_enable_vblank,
307 .disable_vblank = radeon_disable_vblank,
60f2ee0b
DA
308 .master_create = radeon_master_create,
309 .master_destroy = radeon_master_destroy,
1da177e4
LT
310 .irq_preinstall = radeon_driver_irq_preinstall,
311 .irq_postinstall = radeon_driver_irq_postinstall,
312 .irq_uninstall = radeon_driver_irq_uninstall,
313 .irq_handler = radeon_driver_irq_handler,
1da177e4
LT
314 .ioctls = radeon_ioctls,
315 .dma_ioctl = radeon_cp_buffers,
e08e96de 316 .fops = &radeon_driver_old_fops,
22eae947
DA
317 .name = DRIVER_NAME,
318 .desc = DRIVER_DESC,
319 .date = DRIVER_DATE,
320 .major = DRIVER_MAJOR,
321 .minor = DRIVER_MINOR,
322 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT
323};
324
14adc892
CK
325#endif
326
771fe6b9
JG
327static struct drm_driver kms_driver;
328
30238151 329static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
a56f7428
BH
330{
331 struct apertures_struct *ap;
332 bool primary = false;
333
334 ap = alloc_apertures(1);
30238151
TR
335 if (!ap)
336 return -ENOMEM;
337
a56f7428
BH
338 ap->ranges[0].base = pci_resource_start(pdev, 0);
339 ap->ranges[0].size = pci_resource_len(pdev, 0);
340
341#ifdef CONFIG_X86
342 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
343#endif
344 remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
345 kfree(ap);
30238151
TR
346
347 return 0;
a56f7428
BH
348}
349
56550d94
GKH
350static int radeon_pci_probe(struct pci_dev *pdev,
351 const struct pci_device_id *ent)
771fe6b9 352{
30238151
TR
353 int ret;
354
a56f7428 355 /* Get rid of things like offb */
30238151
TR
356 ret = radeon_kick_out_firmware_fb(pdev);
357 if (ret)
358 return ret;
a56f7428 359
dcdb1674 360 return drm_get_pci_dev(pdev, ent, &kms_driver);
771fe6b9
JG
361}
362
363static void
364radeon_pci_remove(struct pci_dev *pdev)
365{
366 struct drm_device *dev = pci_get_drvdata(pdev);
367
368 drm_put_dev(dev);
369}
370
7473e830 371static int radeon_pmops_suspend(struct device *dev)
771fe6b9 372{
7473e830
DA
373 struct pci_dev *pdev = to_pci_dev(dev);
374 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 375 return radeon_suspend_kms(drm_dev, true, true);
771fe6b9
JG
376}
377
7473e830 378static int radeon_pmops_resume(struct device *dev)
771fe6b9 379{
7473e830
DA
380 struct pci_dev *pdev = to_pci_dev(dev);
381 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 382 return radeon_resume_kms(drm_dev, true, true);
7473e830
DA
383}
384
385static int radeon_pmops_freeze(struct device *dev)
386{
387 struct pci_dev *pdev = to_pci_dev(dev);
388 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 389 return radeon_suspend_kms(drm_dev, false, true);
771fe6b9
JG
390}
391
7473e830
DA
392static int radeon_pmops_thaw(struct device *dev)
393{
394 struct pci_dev *pdev = to_pci_dev(dev);
395 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc
DA
396 return radeon_resume_kms(drm_dev, false, true);
397}
398
399static int radeon_pmops_runtime_suspend(struct device *dev)
400{
401 struct pci_dev *pdev = to_pci_dev(dev);
402 struct drm_device *drm_dev = pci_get_drvdata(pdev);
403 int ret;
404
405 if (radeon_runtime_pm == 0)
406 return -EINVAL;
407
408 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
409 drm_kms_helper_poll_disable(drm_dev);
410 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
411
412 ret = radeon_suspend_kms(drm_dev, false, false);
413 pci_save_state(pdev);
414 pci_disable_device(pdev);
415 pci_set_power_state(pdev, PCI_D3cold);
416 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
417
418 return 0;
419}
420
421static int radeon_pmops_runtime_resume(struct device *dev)
422{
423 struct pci_dev *pdev = to_pci_dev(dev);
424 struct drm_device *drm_dev = pci_get_drvdata(pdev);
425 int ret;
426
427 if (radeon_runtime_pm == 0)
428 return -EINVAL;
429
430 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
431
432 pci_set_power_state(pdev, PCI_D0);
433 pci_restore_state(pdev);
434 ret = pci_enable_device(pdev);
435 if (ret)
436 return ret;
437 pci_set_master(pdev);
438
439 ret = radeon_resume_kms(drm_dev, false, false);
440 drm_kms_helper_poll_enable(drm_dev);
441 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
442 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
443 return 0;
444}
445
446static int radeon_pmops_runtime_idle(struct device *dev)
447{
448 struct pci_dev *pdev = to_pci_dev(dev);
449 struct drm_device *drm_dev = pci_get_drvdata(pdev);
450 struct drm_crtc *crtc;
451
452 if (radeon_runtime_pm == 0)
453 return -EBUSY;
454
455 /* are we PX enabled? */
456 if (radeon_runtime_pm == -1 && !radeon_is_px()) {
457 DRM_DEBUG_DRIVER("failing to power off - not px\n");
458 return -EBUSY;
459 }
460
461 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
462 if (crtc->enabled) {
463 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
464 return -EBUSY;
465 }
466 }
467
468 pm_runtime_mark_last_busy(dev);
469 pm_runtime_autosuspend(dev);
470 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
471 return 1;
472}
473
474long radeon_drm_ioctl(struct file *filp,
475 unsigned int cmd, unsigned long arg)
476{
477 struct drm_file *file_priv = filp->private_data;
478 struct drm_device *dev;
479 long ret;
480 dev = file_priv->minor->dev;
481 ret = pm_runtime_get_sync(dev->dev);
482 if (ret < 0)
483 return ret;
484
485 ret = drm_ioctl(filp, cmd, arg);
486
487 pm_runtime_mark_last_busy(dev->dev);
488 pm_runtime_put_autosuspend(dev->dev);
489 return ret;
7473e830
DA
490}
491
492static const struct dev_pm_ops radeon_pm_ops = {
493 .suspend = radeon_pmops_suspend,
494 .resume = radeon_pmops_resume,
495 .freeze = radeon_pmops_freeze,
496 .thaw = radeon_pmops_thaw,
497 .poweroff = radeon_pmops_freeze,
498 .restore = radeon_pmops_resume,
10ebc0bc
DA
499 .runtime_suspend = radeon_pmops_runtime_suspend,
500 .runtime_resume = radeon_pmops_runtime_resume,
501 .runtime_idle = radeon_pmops_runtime_idle,
7473e830
DA
502};
503
e08e96de
AV
504static const struct file_operations radeon_driver_kms_fops = {
505 .owner = THIS_MODULE,
506 .open = drm_open,
507 .release = drm_release,
10ebc0bc 508 .unlocked_ioctl = radeon_drm_ioctl,
e08e96de
AV
509 .mmap = radeon_mmap,
510 .poll = drm_poll,
e08e96de
AV
511 .read = drm_read,
512#ifdef CONFIG_COMPAT
513 .compat_ioctl = radeon_kms_compat_ioctl,
514#endif
515};
516
771fe6b9
JG
517static struct drm_driver kms_driver = {
518 .driver_features =
28185647 519 DRIVER_USE_AGP |
81e95697 520 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
f33bcab9 521 DRIVER_PRIME | DRIVER_RENDER,
771fe6b9
JG
522 .dev_priv_size = 0,
523 .load = radeon_driver_load_kms,
771fe6b9
JG
524 .open = radeon_driver_open_kms,
525 .preclose = radeon_driver_preclose_kms,
526 .postclose = radeon_driver_postclose_kms,
527 .lastclose = radeon_driver_lastclose_kms,
528 .unload = radeon_driver_unload_kms,
771fe6b9
JG
529 .get_vblank_counter = radeon_get_vblank_counter_kms,
530 .enable_vblank = radeon_enable_vblank_kms,
531 .disable_vblank = radeon_disable_vblank_kms,
f5a80209
MK
532 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
533 .get_scanout_position = radeon_get_crtc_scanoutpos,
771fe6b9
JG
534#if defined(CONFIG_DEBUG_FS)
535 .debugfs_init = radeon_debugfs_init,
536 .debugfs_cleanup = radeon_debugfs_cleanup,
537#endif
538 .irq_preinstall = radeon_driver_irq_preinstall_kms,
539 .irq_postinstall = radeon_driver_irq_postinstall_kms,
540 .irq_uninstall = radeon_driver_irq_uninstall_kms,
541 .irq_handler = radeon_driver_irq_handler_kms,
771fe6b9 542 .ioctls = radeon_ioctls_kms,
771fe6b9 543 .gem_free_object = radeon_gem_object_free,
721604a1
JG
544 .gem_open_object = radeon_gem_object_open,
545 .gem_close_object = radeon_gem_object_close,
ff72145b
DA
546 .dumb_create = radeon_mode_dumb_create,
547 .dumb_map_offset = radeon_mode_dumb_mmap,
43387b37 548 .dumb_destroy = drm_gem_dumb_destroy,
e08e96de 549 .fops = &radeon_driver_kms_fops,
40f5cf99
AD
550
551 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
552 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1e6d17a5
AP
553 .gem_prime_export = drm_gem_prime_export,
554 .gem_prime_import = drm_gem_prime_import,
555 .gem_prime_pin = radeon_gem_prime_pin,
280cf211 556 .gem_prime_unpin = radeon_gem_prime_unpin,
1e6d17a5
AP
557 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
558 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
559 .gem_prime_vmap = radeon_gem_prime_vmap,
560 .gem_prime_vunmap = radeon_gem_prime_vunmap,
40f5cf99 561
771fe6b9
JG
562 .name = DRIVER_NAME,
563 .desc = DRIVER_DESC,
564 .date = DRIVER_DATE,
565 .major = KMS_DRIVER_MAJOR,
566 .minor = KMS_DRIVER_MINOR,
567 .patchlevel = KMS_DRIVER_PATCHLEVEL,
568};
771fe6b9
JG
569
570static struct drm_driver *driver;
8410ea3b
DA
571static struct pci_driver *pdriver;
572
14adc892 573#ifdef CONFIG_DRM_RADEON_UMS
8410ea3b
DA
574static struct pci_driver radeon_pci_driver = {
575 .name = DRIVER_NAME,
576 .id_table = pciidlist,
577};
14adc892 578#endif
8410ea3b
DA
579
580static struct pci_driver radeon_kms_pci_driver = {
581 .name = DRIVER_NAME,
582 .id_table = pciidlist,
583 .probe = radeon_pci_probe,
584 .remove = radeon_pci_remove,
7473e830 585 .driver.pm = &radeon_pm_ops,
8410ea3b 586};
771fe6b9 587
1da177e4
LT
588static int __init radeon_init(void)
589{
e9ced8e0
DA
590#ifdef CONFIG_VGA_CONSOLE
591 if (vgacon_text_force() && radeon_modeset == -1) {
592 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
593 radeon_modeset = 0;
594 }
595#endif
596 /* set to modesetting by default if not nomodeset */
597 if (radeon_modeset == -1)
598 radeon_modeset = 1;
599
771fe6b9
JG
600 if (radeon_modeset == 1) {
601 DRM_INFO("radeon kernel modesetting enabled.\n");
602 driver = &kms_driver;
8410ea3b 603 pdriver = &radeon_kms_pci_driver;
771fe6b9
JG
604 driver->driver_features |= DRIVER_MODESET;
605 driver->num_ioctls = radeon_max_kms_ioctl;
6a9ee8af 606 radeon_register_atpx_handler();
14adc892
CK
607
608 } else {
609#ifdef CONFIG_DRM_RADEON_UMS
610 DRM_INFO("radeon userspace modesetting enabled.\n");
611 driver = &driver_old;
612 pdriver = &radeon_pci_driver;
613 driver->driver_features &= ~DRIVER_MODESET;
614 driver->num_ioctls = radeon_max_ioctl;
615#else
616 DRM_ERROR("No UMS support in radeon module!\n");
617 return -EINVAL;
618#endif
771fe6b9 619 }
14adc892
CK
620
621 /* let modprobe override vga console setting */
8410ea3b 622 return drm_pci_init(driver, pdriver);
1da177e4
LT
623}
624
625static void __exit radeon_exit(void)
626{
8410ea3b 627 drm_pci_exit(driver, pdriver);
6a9ee8af 628 radeon_unregister_atpx_handler();
1da177e4
LT
629}
630
176f613e 631module_init(radeon_init);
1da177e4
LT
632module_exit(radeon_exit);
633
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DA
634MODULE_AUTHOR(DRIVER_AUTHOR);
635MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 636MODULE_LICENSE("GPL and additional rights");