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1da177e4 LT |
1 | /** |
2 | * \file radeon_drv.c | |
3 | * ATI Radeon driver | |
4 | * | |
5 | * \author Gareth Hughes <gareth@valinux.com> | |
6 | */ | |
7 | ||
8 | /* | |
9 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
10 | * All Rights Reserved. | |
11 | * | |
12 | * Permission is hereby granted, free of charge, to any person obtaining a | |
13 | * copy of this software and associated documentation files (the "Software"), | |
14 | * to deal in the Software without restriction, including without limitation | |
15 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
16 | * and/or sell copies of the Software, and to permit persons to whom the | |
17 | * Software is furnished to do so, subject to the following conditions: | |
18 | * | |
19 | * The above copyright notice and this permission notice (including the next | |
20 | * paragraph) shall be included in all copies or substantial portions of the | |
21 | * Software. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
24 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
25 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
26 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
27 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
28 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
29 | * OTHER DEALINGS IN THE SOFTWARE. | |
30 | */ | |
31 | ||
1da177e4 LT |
32 | #include "drmP.h" |
33 | #include "drm.h" | |
34 | #include "radeon_drm.h" | |
35 | #include "radeon_drv.h" | |
36 | ||
37 | #include "drm_pciids.h" | |
771fe6b9 | 38 | #include <linux/console.h> |
e0cd3608 | 39 | #include <linux/module.h> |
771fe6b9 JG |
40 | |
41 | ||
771fe6b9 JG |
42 | /* |
43 | * KMS wrapper. | |
0de1a57b DA |
44 | * - 2.0.0 - initial interface |
45 | * - 2.1.0 - add square tiling interface | |
fdb43528 | 46 | * - 2.2.0 - add r6xx/r7xx const buffer support |
cae94b0a | 47 | * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs |
bc35afdb | 48 | * - 2.4.0 - add crtc id query |
148a03bc | 49 | * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen |
ab9e1f59 | 50 | * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) |
71901cc4 | 51 | * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs |
58bbf018 | 52 | * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query |
486af189 | 53 | * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query |
b8709894 AD |
54 | * 2.10.0 - fusion 2D tiling |
55 | * 2.11.0 - backend map, initial compute support for the CS checker | |
e70f224c | 56 | * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS |
dd220a00 | 57 | * 2.13.0 - virtual memory support, streamout |
285484e2 | 58 | * 2.14.0 - add evergreen tiling informations |
609c1e15 | 59 | * 2.15.0 - add max_pipes query |
d2609875 | 60 | * 2.16.0 - fix evergreen 2D tiled surface calculation |
7c77bf2a | 61 | * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx |
0f457e48 | 62 | * 2.18.0 - r600-eg: allow "invalid" DB formats |
771fe6b9 JG |
63 | */ |
64 | #define KMS_DRIVER_MAJOR 2 | |
0f457e48 | 65 | #define KMS_DRIVER_MINOR 18 |
771fe6b9 JG |
66 | #define KMS_DRIVER_PATCHLEVEL 0 |
67 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); | |
68 | int radeon_driver_unload_kms(struct drm_device *dev); | |
69 | int radeon_driver_firstopen_kms(struct drm_device *dev); | |
70 | void radeon_driver_lastclose_kms(struct drm_device *dev); | |
71 | int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); | |
72 | void radeon_driver_postclose_kms(struct drm_device *dev, | |
73 | struct drm_file *file_priv); | |
74 | void radeon_driver_preclose_kms(struct drm_device *dev, | |
75 | struct drm_file *file_priv); | |
76 | int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); | |
77 | int radeon_resume_kms(struct drm_device *dev); | |
78 | u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc); | |
79 | int radeon_enable_vblank_kms(struct drm_device *dev, int crtc); | |
80 | void radeon_disable_vblank_kms(struct drm_device *dev, int crtc); | |
f5a80209 MK |
81 | int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, |
82 | int *max_error, | |
83 | struct timeval *vblank_time, | |
84 | unsigned flags); | |
771fe6b9 JG |
85 | void radeon_driver_irq_preinstall_kms(struct drm_device *dev); |
86 | int radeon_driver_irq_postinstall_kms(struct drm_device *dev); | |
87 | void radeon_driver_irq_uninstall_kms(struct drm_device *dev); | |
88 | irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS); | |
771fe6b9 JG |
89 | int radeon_dma_ioctl_kms(struct drm_device *dev, void *data, |
90 | struct drm_file *file_priv); | |
91 | int radeon_gem_object_init(struct drm_gem_object *obj); | |
92 | void radeon_gem_object_free(struct drm_gem_object *obj); | |
721604a1 JG |
93 | int radeon_gem_object_open(struct drm_gem_object *obj, |
94 | struct drm_file *file_priv); | |
95 | void radeon_gem_object_close(struct drm_gem_object *obj, | |
96 | struct drm_file *file_priv); | |
f5a80209 MK |
97 | extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, |
98 | int *vpos, int *hpos); | |
771fe6b9 JG |
99 | extern struct drm_ioctl_desc radeon_ioctls_kms[]; |
100 | extern int radeon_max_kms_ioctl; | |
101 | int radeon_mmap(struct file *filp, struct vm_area_struct *vma); | |
ff72145b DA |
102 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
103 | struct drm_device *dev, | |
104 | uint32_t handle, uint64_t *offset_p); | |
105 | int radeon_mode_dumb_create(struct drm_file *file_priv, | |
106 | struct drm_device *dev, | |
107 | struct drm_mode_create_dumb *args); | |
108 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, | |
109 | struct drm_device *dev, | |
110 | uint32_t handle); | |
40f5cf99 AD |
111 | struct dma_buf *radeon_gem_prime_export(struct drm_device *dev, |
112 | struct drm_gem_object *obj, | |
113 | int flags); | |
114 | struct drm_gem_object *radeon_gem_prime_import(struct drm_device *dev, | |
115 | struct dma_buf *dma_buf); | |
ff72145b | 116 | |
771fe6b9 JG |
117 | #if defined(CONFIG_DEBUG_FS) |
118 | int radeon_debugfs_init(struct drm_minor *minor); | |
119 | void radeon_debugfs_cleanup(struct drm_minor *minor); | |
120 | #endif | |
771fe6b9 | 121 | |
1da177e4 | 122 | |
689b9d74 | 123 | int radeon_no_wb; |
771fe6b9 JG |
124 | int radeon_modeset = -1; |
125 | int radeon_dynclks = -1; | |
126 | int radeon_r4xx_atom = 0; | |
127 | int radeon_agpmode = 0; | |
128 | int radeon_vram_limit = 0; | |
129 | int radeon_gart_size = 512; /* default gart size */ | |
130 | int radeon_benchmarking = 0; | |
ecc0b326 | 131 | int radeon_testing = 0; |
771fe6b9 | 132 | int radeon_connector_table = 0; |
4ce001ab | 133 | int radeon_tv = 1; |
805c2216 | 134 | int radeon_audio = 0; |
f46c0120 | 135 | int radeon_disp_priority = 0; |
e2b0a8e1 | 136 | int radeon_hw_i2c = 0; |
197bbb3d | 137 | int radeon_pcie_gen2 = -1; |
a18cee15 | 138 | int radeon_msi = -1; |
3368ff0c | 139 | int radeon_lockup_timeout = 10000; |
689b9d74 | 140 | |
61a2d07d | 141 | MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); |
689b9d74 DA |
142 | module_param_named(no_wb, radeon_no_wb, int, 0444); |
143 | ||
771fe6b9 JG |
144 | MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); |
145 | module_param_named(modeset, radeon_modeset, int, 0400); | |
146 | ||
147 | MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); | |
148 | module_param_named(dynclks, radeon_dynclks, int, 0444); | |
149 | ||
150 | MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); | |
151 | module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); | |
152 | ||
153 | MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing"); | |
154 | module_param_named(vramlimit, radeon_vram_limit, int, 0600); | |
155 | ||
156 | MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); | |
157 | module_param_named(agpmode, radeon_agpmode, int, 0444); | |
158 | ||
27d4d052 | 159 | MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc)"); |
771fe6b9 JG |
160 | module_param_named(gartsize, radeon_gart_size, int, 0600); |
161 | ||
162 | MODULE_PARM_DESC(benchmark, "Run benchmark"); | |
163 | module_param_named(benchmark, radeon_benchmarking, int, 0444); | |
164 | ||
ecc0b326 MD |
165 | MODULE_PARM_DESC(test, "Run tests"); |
166 | module_param_named(test, radeon_testing, int, 0444); | |
167 | ||
771fe6b9 JG |
168 | MODULE_PARM_DESC(connector_table, "Force connector table"); |
169 | module_param_named(connector_table, radeon_connector_table, int, 0444); | |
4ce001ab DA |
170 | |
171 | MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); | |
172 | module_param_named(tv, radeon_tv, int, 0444); | |
771fe6b9 | 173 | |
805c2216 | 174 | MODULE_PARM_DESC(audio, "Audio enable (1 = enable)"); |
dafc3bd5 CK |
175 | module_param_named(audio, radeon_audio, int, 0444); |
176 | ||
f46c0120 AD |
177 | MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); |
178 | module_param_named(disp_priority, radeon_disp_priority, int, 0444); | |
179 | ||
e2b0a8e1 AD |
180 | MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); |
181 | module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); | |
182 | ||
197bbb3d | 183 | MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); |
d42dd579 AD |
184 | module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); |
185 | ||
a18cee15 AD |
186 | MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); |
187 | module_param_named(msi, radeon_msi, int, 0444); | |
188 | ||
3368ff0c CK |
189 | MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)"); |
190 | module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); | |
191 | ||
0a3e67a4 JB |
192 | static int radeon_suspend(struct drm_device *dev, pm_message_t state) |
193 | { | |
194 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
195 | ||
03efb885 DA |
196 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
197 | return 0; | |
198 | ||
0a3e67a4 | 199 | /* Disable *all* interrupts */ |
800b6995 | 200 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) |
0a3e67a4 JB |
201 | RADEON_WRITE(R500_DxMODE_INT_MASK, 0); |
202 | RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); | |
203 | return 0; | |
204 | } | |
205 | ||
206 | static int radeon_resume(struct drm_device *dev) | |
207 | { | |
208 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
209 | ||
03efb885 DA |
210 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
211 | return 0; | |
212 | ||
0a3e67a4 | 213 | /* Restore interrupt registers */ |
800b6995 | 214 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) |
0a3e67a4 JB |
215 | RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); |
216 | RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); | |
217 | return 0; | |
218 | } | |
219 | ||
1da177e4 LT |
220 | static struct pci_device_id pciidlist[] = { |
221 | radeon_PCI_IDS | |
222 | }; | |
223 | ||
771fe6b9 JG |
224 | #if defined(CONFIG_DRM_RADEON_KMS) |
225 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
226 | #endif | |
227 | ||
e08e96de AV |
228 | static const struct file_operations radeon_driver_old_fops = { |
229 | .owner = THIS_MODULE, | |
230 | .open = drm_open, | |
231 | .release = drm_release, | |
232 | .unlocked_ioctl = drm_ioctl, | |
233 | .mmap = drm_mmap, | |
234 | .poll = drm_poll, | |
235 | .fasync = drm_fasync, | |
236 | .read = drm_read, | |
237 | #ifdef CONFIG_COMPAT | |
238 | .compat_ioctl = radeon_compat_ioctl, | |
239 | #endif | |
240 | .llseek = noop_llseek, | |
241 | }; | |
242 | ||
771fe6b9 | 243 | static struct drm_driver driver_old = { |
b5e89ed5 DA |
244 | .driver_features = |
245 | DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | | |
0a3e67a4 | 246 | DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED, |
1da177e4 | 247 | .dev_priv_size = sizeof(drm_radeon_buf_priv_t), |
22eae947 DA |
248 | .load = radeon_driver_load, |
249 | .firstopen = radeon_driver_firstopen, | |
250 | .open = radeon_driver_open, | |
251 | .preclose = radeon_driver_preclose, | |
252 | .postclose = radeon_driver_postclose, | |
253 | .lastclose = radeon_driver_lastclose, | |
254 | .unload = radeon_driver_unload, | |
0a3e67a4 JB |
255 | .suspend = radeon_suspend, |
256 | .resume = radeon_resume, | |
257 | .get_vblank_counter = radeon_get_vblank_counter, | |
258 | .enable_vblank = radeon_enable_vblank, | |
259 | .disable_vblank = radeon_disable_vblank, | |
60f2ee0b DA |
260 | .master_create = radeon_master_create, |
261 | .master_destroy = radeon_master_destroy, | |
1da177e4 LT |
262 | .irq_preinstall = radeon_driver_irq_preinstall, |
263 | .irq_postinstall = radeon_driver_irq_postinstall, | |
264 | .irq_uninstall = radeon_driver_irq_uninstall, | |
265 | .irq_handler = radeon_driver_irq_handler, | |
1da177e4 LT |
266 | .ioctls = radeon_ioctls, |
267 | .dma_ioctl = radeon_cp_buffers, | |
e08e96de | 268 | .fops = &radeon_driver_old_fops, |
22eae947 DA |
269 | .name = DRIVER_NAME, |
270 | .desc = DRIVER_DESC, | |
271 | .date = DRIVER_DATE, | |
272 | .major = DRIVER_MAJOR, | |
273 | .minor = DRIVER_MINOR, | |
274 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
275 | }; |
276 | ||
771fe6b9 JG |
277 | static struct drm_driver kms_driver; |
278 | ||
a56f7428 BH |
279 | static void radeon_kick_out_firmware_fb(struct pci_dev *pdev) |
280 | { | |
281 | struct apertures_struct *ap; | |
282 | bool primary = false; | |
283 | ||
284 | ap = alloc_apertures(1); | |
285 | ap->ranges[0].base = pci_resource_start(pdev, 0); | |
286 | ap->ranges[0].size = pci_resource_len(pdev, 0); | |
287 | ||
288 | #ifdef CONFIG_X86 | |
289 | primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
290 | #endif | |
291 | remove_conflicting_framebuffers(ap, "radeondrmfb", primary); | |
292 | kfree(ap); | |
293 | } | |
294 | ||
771fe6b9 JG |
295 | static int __devinit |
296 | radeon_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
297 | { | |
a56f7428 BH |
298 | /* Get rid of things like offb */ |
299 | radeon_kick_out_firmware_fb(pdev); | |
300 | ||
dcdb1674 | 301 | return drm_get_pci_dev(pdev, ent, &kms_driver); |
771fe6b9 JG |
302 | } |
303 | ||
304 | static void | |
305 | radeon_pci_remove(struct pci_dev *pdev) | |
306 | { | |
307 | struct drm_device *dev = pci_get_drvdata(pdev); | |
308 | ||
309 | drm_put_dev(dev); | |
310 | } | |
311 | ||
312 | static int | |
313 | radeon_pci_suspend(struct pci_dev *pdev, pm_message_t state) | |
314 | { | |
315 | struct drm_device *dev = pci_get_drvdata(pdev); | |
316 | return radeon_suspend_kms(dev, state); | |
317 | } | |
318 | ||
319 | static int | |
320 | radeon_pci_resume(struct pci_dev *pdev) | |
321 | { | |
322 | struct drm_device *dev = pci_get_drvdata(pdev); | |
323 | return radeon_resume_kms(dev); | |
324 | } | |
325 | ||
e08e96de AV |
326 | static const struct file_operations radeon_driver_kms_fops = { |
327 | .owner = THIS_MODULE, | |
328 | .open = drm_open, | |
329 | .release = drm_release, | |
330 | .unlocked_ioctl = drm_ioctl, | |
331 | .mmap = radeon_mmap, | |
332 | .poll = drm_poll, | |
333 | .fasync = drm_fasync, | |
334 | .read = drm_read, | |
335 | #ifdef CONFIG_COMPAT | |
336 | .compat_ioctl = radeon_kms_compat_ioctl, | |
337 | #endif | |
338 | }; | |
339 | ||
771fe6b9 JG |
340 | static struct drm_driver kms_driver = { |
341 | .driver_features = | |
342 | DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | | |
40f5cf99 AD |
343 | DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_GEM | |
344 | DRIVER_PRIME, | |
771fe6b9 JG |
345 | .dev_priv_size = 0, |
346 | .load = radeon_driver_load_kms, | |
347 | .firstopen = radeon_driver_firstopen_kms, | |
348 | .open = radeon_driver_open_kms, | |
349 | .preclose = radeon_driver_preclose_kms, | |
350 | .postclose = radeon_driver_postclose_kms, | |
351 | .lastclose = radeon_driver_lastclose_kms, | |
352 | .unload = radeon_driver_unload_kms, | |
353 | .suspend = radeon_suspend_kms, | |
354 | .resume = radeon_resume_kms, | |
355 | .get_vblank_counter = radeon_get_vblank_counter_kms, | |
356 | .enable_vblank = radeon_enable_vblank_kms, | |
357 | .disable_vblank = radeon_disable_vblank_kms, | |
f5a80209 MK |
358 | .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, |
359 | .get_scanout_position = radeon_get_crtc_scanoutpos, | |
771fe6b9 JG |
360 | #if defined(CONFIG_DEBUG_FS) |
361 | .debugfs_init = radeon_debugfs_init, | |
362 | .debugfs_cleanup = radeon_debugfs_cleanup, | |
363 | #endif | |
364 | .irq_preinstall = radeon_driver_irq_preinstall_kms, | |
365 | .irq_postinstall = radeon_driver_irq_postinstall_kms, | |
366 | .irq_uninstall = radeon_driver_irq_uninstall_kms, | |
367 | .irq_handler = radeon_driver_irq_handler_kms, | |
771fe6b9 JG |
368 | .ioctls = radeon_ioctls_kms, |
369 | .gem_init_object = radeon_gem_object_init, | |
370 | .gem_free_object = radeon_gem_object_free, | |
721604a1 JG |
371 | .gem_open_object = radeon_gem_object_open, |
372 | .gem_close_object = radeon_gem_object_close, | |
771fe6b9 | 373 | .dma_ioctl = radeon_dma_ioctl_kms, |
ff72145b DA |
374 | .dumb_create = radeon_mode_dumb_create, |
375 | .dumb_map_offset = radeon_mode_dumb_mmap, | |
376 | .dumb_destroy = radeon_mode_dumb_destroy, | |
e08e96de | 377 | .fops = &radeon_driver_kms_fops, |
40f5cf99 AD |
378 | |
379 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
380 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
381 | .gem_prime_export = radeon_gem_prime_export, | |
382 | .gem_prime_import = radeon_gem_prime_import, | |
383 | ||
771fe6b9 JG |
384 | .name = DRIVER_NAME, |
385 | .desc = DRIVER_DESC, | |
386 | .date = DRIVER_DATE, | |
387 | .major = KMS_DRIVER_MAJOR, | |
388 | .minor = KMS_DRIVER_MINOR, | |
389 | .patchlevel = KMS_DRIVER_PATCHLEVEL, | |
390 | }; | |
771fe6b9 JG |
391 | |
392 | static struct drm_driver *driver; | |
8410ea3b DA |
393 | static struct pci_driver *pdriver; |
394 | ||
395 | static struct pci_driver radeon_pci_driver = { | |
396 | .name = DRIVER_NAME, | |
397 | .id_table = pciidlist, | |
398 | }; | |
399 | ||
400 | static struct pci_driver radeon_kms_pci_driver = { | |
401 | .name = DRIVER_NAME, | |
402 | .id_table = pciidlist, | |
403 | .probe = radeon_pci_probe, | |
404 | .remove = radeon_pci_remove, | |
405 | .suspend = radeon_pci_suspend, | |
406 | .resume = radeon_pci_resume, | |
407 | }; | |
771fe6b9 | 408 | |
1da177e4 LT |
409 | static int __init radeon_init(void) |
410 | { | |
771fe6b9 | 411 | driver = &driver_old; |
8410ea3b | 412 | pdriver = &radeon_pci_driver; |
771fe6b9 | 413 | driver->num_ioctls = radeon_max_ioctl; |
de05065f DA |
414 | #ifdef CONFIG_VGA_CONSOLE |
415 | if (vgacon_text_force() && radeon_modeset == -1) { | |
416 | DRM_INFO("VGACON disable radeon kernel modesetting.\n"); | |
417 | driver = &driver_old; | |
8410ea3b | 418 | pdriver = &radeon_pci_driver; |
de05065f DA |
419 | driver->driver_features &= ~DRIVER_MODESET; |
420 | radeon_modeset = 0; | |
421 | } | |
422 | #endif | |
771fe6b9 JG |
423 | /* if enabled by default */ |
424 | if (radeon_modeset == -1) { | |
a0cdc649 DA |
425 | #ifdef CONFIG_DRM_RADEON_KMS |
426 | DRM_INFO("radeon defaulting to kernel modesetting.\n"); | |
771fe6b9 | 427 | radeon_modeset = 1; |
a0cdc649 DA |
428 | #else |
429 | DRM_INFO("radeon defaulting to userspace modesetting.\n"); | |
430 | radeon_modeset = 0; | |
431 | #endif | |
771fe6b9 JG |
432 | } |
433 | if (radeon_modeset == 1) { | |
434 | DRM_INFO("radeon kernel modesetting enabled.\n"); | |
435 | driver = &kms_driver; | |
8410ea3b | 436 | pdriver = &radeon_kms_pci_driver; |
771fe6b9 JG |
437 | driver->driver_features |= DRIVER_MODESET; |
438 | driver->num_ioctls = radeon_max_kms_ioctl; | |
6a9ee8af | 439 | radeon_register_atpx_handler(); |
771fe6b9 | 440 | } |
771fe6b9 JG |
441 | /* if the vga console setting is enabled still |
442 | * let modprobe override it */ | |
8410ea3b | 443 | return drm_pci_init(driver, pdriver); |
1da177e4 LT |
444 | } |
445 | ||
446 | static void __exit radeon_exit(void) | |
447 | { | |
8410ea3b | 448 | drm_pci_exit(driver, pdriver); |
6a9ee8af | 449 | radeon_unregister_atpx_handler(); |
1da177e4 LT |
450 | } |
451 | ||
176f613e | 452 | module_init(radeon_init); |
1da177e4 LT |
453 | module_exit(radeon_exit); |
454 | ||
b5e89ed5 DA |
455 | MODULE_AUTHOR(DRIVER_AUTHOR); |
456 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 457 | MODULE_LICENSE("GPL and additional rights"); |