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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include "drmP.h" | |
27 | #include "drm_crtc_helper.h" | |
28 | #include "radeon_drm.h" | |
29 | #include "radeon.h" | |
30 | #include "atom.h" | |
31 | ||
32 | extern int atom_debug; | |
33 | ||
5a9bcacc AD |
34 | /* evil but including atombios.h is much worse */ |
35 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, | |
36 | struct drm_display_mode *mode); | |
37 | ||
1f3b6a45 DA |
38 | static uint32_t radeon_encoder_clones(struct drm_encoder *encoder) |
39 | { | |
40 | struct drm_device *dev = encoder->dev; | |
41 | struct radeon_device *rdev = dev->dev_private; | |
42 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
43 | struct drm_encoder *clone_encoder; | |
44 | uint32_t index_mask = 0; | |
45 | int count; | |
46 | ||
47 | /* DIG routing gets problematic */ | |
48 | if (rdev->family >= CHIP_R600) | |
49 | return index_mask; | |
50 | /* LVDS/TV are too wacky */ | |
51 | if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) | |
52 | return index_mask; | |
53 | /* DVO requires 2x ppll clocks depending on tmds chip */ | |
54 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) | |
55 | return index_mask; | |
bcc1c2a1 | 56 | |
1f3b6a45 DA |
57 | count = -1; |
58 | list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) { | |
59 | struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder); | |
60 | count++; | |
61 | ||
62 | if (clone_encoder == encoder) | |
63 | continue; | |
64 | if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
65 | continue; | |
66 | if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT) | |
67 | continue; | |
68 | else | |
69 | index_mask |= (1 << count); | |
70 | } | |
71 | return index_mask; | |
72 | } | |
73 | ||
74 | void radeon_setup_encoder_clones(struct drm_device *dev) | |
75 | { | |
76 | struct drm_encoder *encoder; | |
77 | ||
78 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
79 | encoder->possible_clones = radeon_encoder_clones(encoder); | |
80 | } | |
81 | } | |
82 | ||
771fe6b9 | 83 | uint32_t |
5137ee94 | 84 | radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac) |
771fe6b9 JG |
85 | { |
86 | struct radeon_device *rdev = dev->dev_private; | |
87 | uint32_t ret = 0; | |
88 | ||
89 | switch (supported_device) { | |
90 | case ATOM_DEVICE_CRT1_SUPPORT: | |
91 | case ATOM_DEVICE_TV1_SUPPORT: | |
92 | case ATOM_DEVICE_TV2_SUPPORT: | |
93 | case ATOM_DEVICE_CRT2_SUPPORT: | |
94 | case ATOM_DEVICE_CV_SUPPORT: | |
95 | switch (dac) { | |
96 | case 1: /* dac a */ | |
97 | if ((rdev->family == CHIP_RS300) || | |
98 | (rdev->family == CHIP_RS400) || | |
99 | (rdev->family == CHIP_RS480)) | |
5137ee94 | 100 | ret = ENCODER_INTERNAL_DAC2_ENUM_ID1; |
771fe6b9 | 101 | else if (ASIC_IS_AVIVO(rdev)) |
5137ee94 | 102 | ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1; |
771fe6b9 | 103 | else |
5137ee94 | 104 | ret = ENCODER_INTERNAL_DAC1_ENUM_ID1; |
771fe6b9 JG |
105 | break; |
106 | case 2: /* dac b */ | |
107 | if (ASIC_IS_AVIVO(rdev)) | |
5137ee94 | 108 | ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1; |
771fe6b9 JG |
109 | else { |
110 | /*if (rdev->family == CHIP_R200) | |
5137ee94 | 111 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
771fe6b9 | 112 | else*/ |
5137ee94 | 113 | ret = ENCODER_INTERNAL_DAC2_ENUM_ID1; |
771fe6b9 JG |
114 | } |
115 | break; | |
116 | case 3: /* external dac */ | |
117 | if (ASIC_IS_AVIVO(rdev)) | |
5137ee94 | 118 | ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1; |
771fe6b9 | 119 | else |
5137ee94 | 120 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
771fe6b9 JG |
121 | break; |
122 | } | |
123 | break; | |
124 | case ATOM_DEVICE_LCD1_SUPPORT: | |
125 | if (ASIC_IS_AVIVO(rdev)) | |
5137ee94 | 126 | ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1; |
771fe6b9 | 127 | else |
5137ee94 | 128 | ret = ENCODER_INTERNAL_LVDS_ENUM_ID1; |
771fe6b9 JG |
129 | break; |
130 | case ATOM_DEVICE_DFP1_SUPPORT: | |
131 | if ((rdev->family == CHIP_RS300) || | |
132 | (rdev->family == CHIP_RS400) || | |
133 | (rdev->family == CHIP_RS480)) | |
5137ee94 | 134 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
771fe6b9 | 135 | else if (ASIC_IS_AVIVO(rdev)) |
5137ee94 | 136 | ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1; |
771fe6b9 | 137 | else |
5137ee94 | 138 | ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1; |
771fe6b9 JG |
139 | break; |
140 | case ATOM_DEVICE_LCD2_SUPPORT: | |
141 | case ATOM_DEVICE_DFP2_SUPPORT: | |
142 | if ((rdev->family == CHIP_RS600) || | |
143 | (rdev->family == CHIP_RS690) || | |
144 | (rdev->family == CHIP_RS740)) | |
5137ee94 | 145 | ret = ENCODER_INTERNAL_DDI_ENUM_ID1; |
771fe6b9 | 146 | else if (ASIC_IS_AVIVO(rdev)) |
5137ee94 | 147 | ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1; |
771fe6b9 | 148 | else |
5137ee94 | 149 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
771fe6b9 JG |
150 | break; |
151 | case ATOM_DEVICE_DFP3_SUPPORT: | |
5137ee94 | 152 | ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1; |
771fe6b9 JG |
153 | break; |
154 | } | |
155 | ||
156 | return ret; | |
157 | } | |
158 | ||
f28cf339 DA |
159 | static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) |
160 | { | |
161 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
162 | switch (radeon_encoder->encoder_id) { | |
163 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
164 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
165 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
166 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
167 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
168 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
169 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
170 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
171 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
172 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
173 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
174 | return true; | |
175 | default: | |
176 | return false; | |
177 | } | |
178 | } | |
771fe6b9 JG |
179 | void |
180 | radeon_link_encoder_connector(struct drm_device *dev) | |
181 | { | |
182 | struct drm_connector *connector; | |
183 | struct radeon_connector *radeon_connector; | |
184 | struct drm_encoder *encoder; | |
185 | struct radeon_encoder *radeon_encoder; | |
186 | ||
187 | /* walk the list and link encoders to connectors */ | |
188 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
189 | radeon_connector = to_radeon_connector(connector); | |
190 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
191 | radeon_encoder = to_radeon_encoder(encoder); | |
192 | if (radeon_encoder->devices & radeon_connector->devices) | |
193 | drm_mode_connector_attach_encoder(connector, encoder); | |
194 | } | |
195 | } | |
196 | } | |
197 | ||
4ce001ab DA |
198 | void radeon_encoder_set_active_device(struct drm_encoder *encoder) |
199 | { | |
200 | struct drm_device *dev = encoder->dev; | |
201 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
202 | struct drm_connector *connector; | |
203 | ||
204 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
205 | if (connector->encoder == encoder) { | |
206 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
207 | radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; | |
d9fdaafb | 208 | DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n", |
f641e51e DA |
209 | radeon_encoder->active_device, radeon_encoder->devices, |
210 | radeon_connector->devices, encoder->encoder_type); | |
4ce001ab DA |
211 | } |
212 | } | |
213 | } | |
214 | ||
5b1714d3 | 215 | struct drm_connector * |
771fe6b9 JG |
216 | radeon_get_connector_for_encoder(struct drm_encoder *encoder) |
217 | { | |
218 | struct drm_device *dev = encoder->dev; | |
219 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
220 | struct drm_connector *connector; | |
221 | struct radeon_connector *radeon_connector; | |
222 | ||
223 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
224 | radeon_connector = to_radeon_connector(connector); | |
43c33ed8 | 225 | if (radeon_encoder->active_device & radeon_connector->devices) |
771fe6b9 JG |
226 | return connector; |
227 | } | |
228 | return NULL; | |
229 | } | |
230 | ||
9ae47867 AD |
231 | static struct radeon_connector_atom_dig * |
232 | radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder) | |
233 | { | |
234 | struct drm_device *dev = encoder->dev; | |
235 | struct radeon_device *rdev = dev->dev_private; | |
236 | struct drm_connector *connector; | |
237 | struct radeon_connector *radeon_connector; | |
238 | struct radeon_connector_atom_dig *dig_connector; | |
239 | ||
240 | if (!rdev->is_atom_bios) | |
241 | return NULL; | |
242 | ||
243 | connector = radeon_get_connector_for_encoder(encoder); | |
244 | if (!connector) | |
245 | return NULL; | |
246 | ||
247 | radeon_connector = to_radeon_connector(connector); | |
248 | ||
249 | if (!radeon_connector->con_priv) | |
250 | return NULL; | |
251 | ||
252 | dig_connector = radeon_connector->con_priv; | |
253 | ||
254 | return dig_connector; | |
255 | } | |
256 | ||
3515387b AD |
257 | void radeon_panel_mode_fixup(struct drm_encoder *encoder, |
258 | struct drm_display_mode *adjusted_mode) | |
259 | { | |
260 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
261 | struct drm_device *dev = encoder->dev; | |
262 | struct radeon_device *rdev = dev->dev_private; | |
263 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; | |
264 | unsigned hblank = native_mode->htotal - native_mode->hdisplay; | |
265 | unsigned vblank = native_mode->vtotal - native_mode->vdisplay; | |
266 | unsigned hover = native_mode->hsync_start - native_mode->hdisplay; | |
267 | unsigned vover = native_mode->vsync_start - native_mode->vdisplay; | |
268 | unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start; | |
269 | unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start; | |
270 | ||
271 | adjusted_mode->clock = native_mode->clock; | |
272 | adjusted_mode->flags = native_mode->flags; | |
273 | ||
274 | if (ASIC_IS_AVIVO(rdev)) { | |
275 | adjusted_mode->hdisplay = native_mode->hdisplay; | |
276 | adjusted_mode->vdisplay = native_mode->vdisplay; | |
277 | } | |
278 | ||
279 | adjusted_mode->htotal = native_mode->hdisplay + hblank; | |
280 | adjusted_mode->hsync_start = native_mode->hdisplay + hover; | |
281 | adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width; | |
282 | ||
283 | adjusted_mode->vtotal = native_mode->vdisplay + vblank; | |
284 | adjusted_mode->vsync_start = native_mode->vdisplay + vover; | |
285 | adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width; | |
286 | ||
287 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); | |
288 | ||
289 | if (ASIC_IS_AVIVO(rdev)) { | |
290 | adjusted_mode->crtc_hdisplay = native_mode->hdisplay; | |
291 | adjusted_mode->crtc_vdisplay = native_mode->vdisplay; | |
292 | } | |
293 | ||
294 | adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank; | |
295 | adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover; | |
296 | adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width; | |
297 | ||
298 | adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank; | |
299 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover; | |
300 | adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width; | |
301 | ||
302 | } | |
303 | ||
771fe6b9 JG |
304 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
305 | struct drm_display_mode *mode, | |
306 | struct drm_display_mode *adjusted_mode) | |
307 | { | |
771fe6b9 | 308 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
5a9bcacc AD |
309 | struct drm_device *dev = encoder->dev; |
310 | struct radeon_device *rdev = dev->dev_private; | |
771fe6b9 | 311 | |
8c2a6d73 AD |
312 | /* set the active encoder to connector routing */ |
313 | radeon_encoder_set_active_device(encoder); | |
771fe6b9 JG |
314 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
315 | ||
771fe6b9 JG |
316 | /* hw bug */ |
317 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) | |
318 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) | |
319 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; | |
320 | ||
80297e87 | 321 | /* get the native mode for LVDS */ |
3515387b AD |
322 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) |
323 | radeon_panel_mode_fixup(encoder, adjusted_mode); | |
80297e87 AD |
324 | |
325 | /* get the native mode for TV */ | |
ceefedd8 | 326 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
5a9bcacc AD |
327 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
328 | if (tv_dac) { | |
329 | if (tv_dac->tv_std == TV_STD_NTSC || | |
330 | tv_dac->tv_std == TV_STD_NTSC_J || | |
331 | tv_dac->tv_std == TV_STD_PAL_M) | |
332 | radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); | |
333 | else | |
334 | radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); | |
335 | } | |
336 | } | |
337 | ||
5801ead6 | 338 | if (ASIC_IS_DCE3(rdev) && |
9f998ad7 | 339 | (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) { |
5801ead6 AD |
340 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
341 | radeon_dp_set_link_config(connector, mode); | |
342 | } | |
343 | ||
771fe6b9 JG |
344 | return true; |
345 | } | |
346 | ||
347 | static void | |
348 | atombios_dac_setup(struct drm_encoder *encoder, int action) | |
349 | { | |
350 | struct drm_device *dev = encoder->dev; | |
351 | struct radeon_device *rdev = dev->dev_private; | |
352 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
353 | DAC_ENCODER_CONTROL_PS_ALLOCATION args; | |
affd8589 | 354 | int index = 0; |
445282db | 355 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
445282db | 356 | |
771fe6b9 JG |
357 | memset(&args, 0, sizeof(args)); |
358 | ||
359 | switch (radeon_encoder->encoder_id) { | |
360 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
361 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
362 | index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); | |
771fe6b9 JG |
363 | break; |
364 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
365 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
366 | index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); | |
771fe6b9 JG |
367 | break; |
368 | } | |
369 | ||
370 | args.ucAction = action; | |
371 | ||
4ce001ab | 372 | if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) |
771fe6b9 | 373 | args.ucDacStandard = ATOM_DAC1_PS2; |
4ce001ab | 374 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
375 | args.ucDacStandard = ATOM_DAC1_CV; |
376 | else { | |
affd8589 | 377 | switch (dac_info->tv_std) { |
771fe6b9 JG |
378 | case TV_STD_PAL: |
379 | case TV_STD_PAL_M: | |
380 | case TV_STD_SCART_PAL: | |
381 | case TV_STD_SECAM: | |
382 | case TV_STD_PAL_CN: | |
383 | args.ucDacStandard = ATOM_DAC1_PAL; | |
384 | break; | |
385 | case TV_STD_NTSC: | |
386 | case TV_STD_NTSC_J: | |
387 | case TV_STD_PAL_60: | |
388 | default: | |
389 | args.ucDacStandard = ATOM_DAC1_NTSC; | |
390 | break; | |
391 | } | |
392 | } | |
393 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
394 | ||
395 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
396 | ||
397 | } | |
398 | ||
399 | static void | |
400 | atombios_tv_setup(struct drm_encoder *encoder, int action) | |
401 | { | |
402 | struct drm_device *dev = encoder->dev; | |
403 | struct radeon_device *rdev = dev->dev_private; | |
404 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
405 | TV_ENCODER_CONTROL_PS_ALLOCATION args; | |
406 | int index = 0; | |
445282db | 407 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
445282db | 408 | |
771fe6b9 JG |
409 | memset(&args, 0, sizeof(args)); |
410 | ||
411 | index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); | |
412 | ||
413 | args.sTVEncoder.ucAction = action; | |
414 | ||
4ce001ab | 415 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
416 | args.sTVEncoder.ucTvStandard = ATOM_TV_CV; |
417 | else { | |
affd8589 | 418 | switch (dac_info->tv_std) { |
771fe6b9 JG |
419 | case TV_STD_NTSC: |
420 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; | |
421 | break; | |
422 | case TV_STD_PAL: | |
423 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; | |
424 | break; | |
425 | case TV_STD_PAL_M: | |
426 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; | |
427 | break; | |
428 | case TV_STD_PAL_60: | |
429 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; | |
430 | break; | |
431 | case TV_STD_NTSC_J: | |
432 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; | |
433 | break; | |
434 | case TV_STD_SCART_PAL: | |
435 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ | |
436 | break; | |
437 | case TV_STD_SECAM: | |
438 | args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; | |
439 | break; | |
440 | case TV_STD_PAL_CN: | |
441 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; | |
442 | break; | |
443 | default: | |
444 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; | |
445 | break; | |
446 | } | |
447 | } | |
448 | ||
449 | args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
450 | ||
451 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
452 | ||
453 | } | |
454 | ||
455 | void | |
456 | atombios_external_tmds_setup(struct drm_encoder *encoder, int action) | |
457 | { | |
458 | struct drm_device *dev = encoder->dev; | |
459 | struct radeon_device *rdev = dev->dev_private; | |
460 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
461 | ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args; | |
462 | int index = 0; | |
463 | ||
464 | memset(&args, 0, sizeof(args)); | |
465 | ||
466 | index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); | |
467 | ||
468 | args.sXTmdsEncoder.ucEnable = action; | |
469 | ||
470 | if (radeon_encoder->pixel_clock > 165000) | |
471 | args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL; | |
472 | ||
473 | /*if (pScrn->rgbBits == 8)*/ | |
474 | args.sXTmdsEncoder.ucMisc |= (1 << 1); | |
475 | ||
476 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
477 | ||
478 | } | |
479 | ||
480 | static void | |
481 | atombios_ddia_setup(struct drm_encoder *encoder, int action) | |
482 | { | |
483 | struct drm_device *dev = encoder->dev; | |
484 | struct radeon_device *rdev = dev->dev_private; | |
485 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
486 | DVO_ENCODER_CONTROL_PS_ALLOCATION args; | |
487 | int index = 0; | |
488 | ||
489 | memset(&args, 0, sizeof(args)); | |
490 | ||
491 | index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); | |
492 | ||
493 | args.sDVOEncoder.ucAction = action; | |
494 | args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
495 | ||
496 | if (radeon_encoder->pixel_clock > 165000) | |
497 | args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL; | |
498 | ||
499 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
500 | ||
501 | } | |
502 | ||
503 | union lvds_encoder_control { | |
504 | LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; | |
505 | LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; | |
506 | }; | |
507 | ||
32f48ffe | 508 | void |
771fe6b9 JG |
509 | atombios_digital_setup(struct drm_encoder *encoder, int action) |
510 | { | |
511 | struct drm_device *dev = encoder->dev; | |
512 | struct radeon_device *rdev = dev->dev_private; | |
513 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
9ae47867 AD |
514 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
515 | struct radeon_connector_atom_dig *dig_connector = | |
516 | radeon_get_atom_connector_priv_from_encoder(encoder); | |
771fe6b9 JG |
517 | union lvds_encoder_control args; |
518 | int index = 0; | |
dafc3bd5 | 519 | int hdmi_detected = 0; |
771fe6b9 | 520 | uint8_t frev, crev; |
771fe6b9 | 521 | |
9ae47867 | 522 | if (!dig || !dig_connector) |
771fe6b9 JG |
523 | return; |
524 | ||
9ae47867 | 525 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) |
dafc3bd5 CK |
526 | hdmi_detected = 1; |
527 | ||
771fe6b9 JG |
528 | memset(&args, 0, sizeof(args)); |
529 | ||
530 | switch (radeon_encoder->encoder_id) { | |
531 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
532 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); | |
533 | break; | |
534 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
535 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
536 | index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); | |
537 | break; | |
538 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
539 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
540 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); | |
541 | else | |
542 | index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); | |
543 | break; | |
544 | } | |
545 | ||
a084e6ee AD |
546 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
547 | return; | |
771fe6b9 JG |
548 | |
549 | switch (frev) { | |
550 | case 1: | |
551 | case 2: | |
552 | switch (crev) { | |
553 | case 1: | |
554 | args.v1.ucMisc = 0; | |
555 | args.v1.ucAction = action; | |
dafc3bd5 | 556 | if (hdmi_detected) |
771fe6b9 JG |
557 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
558 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
559 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
edc664e3 | 560 | if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL) |
771fe6b9 | 561 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
edc664e3 | 562 | if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) |
771fe6b9 JG |
563 | args.v1.ucMisc |= (1 << 1); |
564 | } else { | |
5137ee94 | 565 | if (dig->linkb) |
771fe6b9 JG |
566 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
567 | if (radeon_encoder->pixel_clock > 165000) | |
568 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; | |
569 | /*if (pScrn->rgbBits == 8) */ | |
570 | args.v1.ucMisc |= (1 << 1); | |
571 | } | |
572 | break; | |
573 | case 2: | |
574 | case 3: | |
575 | args.v2.ucMisc = 0; | |
576 | args.v2.ucAction = action; | |
577 | if (crev == 3) { | |
578 | if (dig->coherent_mode) | |
579 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; | |
580 | } | |
dafc3bd5 | 581 | if (hdmi_detected) |
771fe6b9 JG |
582 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
583 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
584 | args.v2.ucTruncate = 0; | |
585 | args.v2.ucSpatial = 0; | |
586 | args.v2.ucTemporal = 0; | |
587 | args.v2.ucFRC = 0; | |
588 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
edc664e3 | 589 | if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL) |
771fe6b9 | 590 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
edc664e3 | 591 | if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) { |
771fe6b9 | 592 | args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; |
edc664e3 | 593 | if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) |
771fe6b9 JG |
594 | args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; |
595 | } | |
edc664e3 | 596 | if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) { |
771fe6b9 | 597 | args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; |
edc664e3 | 598 | if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) |
771fe6b9 | 599 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; |
edc664e3 | 600 | if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) |
771fe6b9 JG |
601 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; |
602 | } | |
603 | } else { | |
5137ee94 | 604 | if (dig->linkb) |
771fe6b9 JG |
605 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
606 | if (radeon_encoder->pixel_clock > 165000) | |
607 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; | |
608 | } | |
609 | break; | |
610 | default: | |
611 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
612 | break; | |
613 | } | |
614 | break; | |
615 | default: | |
616 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
617 | break; | |
618 | } | |
619 | ||
620 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
771fe6b9 JG |
621 | } |
622 | ||
623 | int | |
624 | atombios_get_encoder_mode(struct drm_encoder *encoder) | |
625 | { | |
626 | struct drm_connector *connector; | |
627 | struct radeon_connector *radeon_connector; | |
9ae47867 | 628 | struct radeon_connector_atom_dig *dig_connector; |
771fe6b9 JG |
629 | |
630 | connector = radeon_get_connector_for_encoder(encoder); | |
631 | if (!connector) | |
632 | return 0; | |
633 | ||
634 | radeon_connector = to_radeon_connector(connector); | |
635 | ||
636 | switch (connector->connector_type) { | |
637 | case DRM_MODE_CONNECTOR_DVII: | |
705af9c7 | 638 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
0294cf4f | 639 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
771fe6b9 JG |
640 | return ATOM_ENCODER_MODE_HDMI; |
641 | else if (radeon_connector->use_digital) | |
642 | return ATOM_ENCODER_MODE_DVI; | |
643 | else | |
644 | return ATOM_ENCODER_MODE_CRT; | |
645 | break; | |
646 | case DRM_MODE_CONNECTOR_DVID: | |
647 | case DRM_MODE_CONNECTOR_HDMIA: | |
771fe6b9 | 648 | default: |
0294cf4f | 649 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
771fe6b9 JG |
650 | return ATOM_ENCODER_MODE_HDMI; |
651 | else | |
652 | return ATOM_ENCODER_MODE_DVI; | |
653 | break; | |
654 | case DRM_MODE_CONNECTOR_LVDS: | |
655 | return ATOM_ENCODER_MODE_LVDS; | |
656 | break; | |
657 | case DRM_MODE_CONNECTOR_DisplayPort: | |
196c58d2 | 658 | case DRM_MODE_CONNECTOR_eDP: |
9ae47867 AD |
659 | dig_connector = radeon_connector->con_priv; |
660 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || | |
661 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) | |
f92a8b67 AD |
662 | return ATOM_ENCODER_MODE_DP; |
663 | else if (drm_detect_hdmi_monitor(radeon_connector->edid)) | |
771fe6b9 JG |
664 | return ATOM_ENCODER_MODE_HDMI; |
665 | else | |
666 | return ATOM_ENCODER_MODE_DVI; | |
667 | break; | |
a5899fcc AD |
668 | case DRM_MODE_CONNECTOR_DVIA: |
669 | case DRM_MODE_CONNECTOR_VGA: | |
771fe6b9 JG |
670 | return ATOM_ENCODER_MODE_CRT; |
671 | break; | |
a5899fcc AD |
672 | case DRM_MODE_CONNECTOR_Composite: |
673 | case DRM_MODE_CONNECTOR_SVIDEO: | |
674 | case DRM_MODE_CONNECTOR_9PinDIN: | |
771fe6b9 JG |
675 | /* fix me */ |
676 | return ATOM_ENCODER_MODE_TV; | |
677 | /*return ATOM_ENCODER_MODE_CV;*/ | |
678 | break; | |
679 | } | |
680 | } | |
681 | ||
1a66c95a AD |
682 | /* |
683 | * DIG Encoder/Transmitter Setup | |
684 | * | |
685 | * DCE 3.0/3.1 | |
686 | * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. | |
687 | * Supports up to 3 digital outputs | |
688 | * - 2 DIG encoder blocks. | |
689 | * DIG1 can drive UNIPHY link A or link B | |
690 | * DIG2 can drive UNIPHY link B or LVTMA | |
691 | * | |
692 | * DCE 3.2 | |
693 | * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). | |
694 | * Supports up to 5 digital outputs | |
695 | * - 2 DIG encoder blocks. | |
696 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B | |
697 | * | |
bcc1c2a1 AD |
698 | * DCE 4.0 |
699 | * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B). | |
700 | * Supports up to 6 digital outputs | |
701 | * - 6 DIG encoder blocks. | |
702 | * - DIG to PHY mapping is hardcoded | |
703 | * DIG1 drives UNIPHY0 link A, A+B | |
704 | * DIG2 drives UNIPHY0 link B | |
705 | * DIG3 drives UNIPHY1 link A, A+B | |
706 | * DIG4 drives UNIPHY1 link B | |
707 | * DIG5 drives UNIPHY2 link A, A+B | |
708 | * DIG6 drives UNIPHY2 link B | |
709 | * | |
1a66c95a AD |
710 | * Routing |
711 | * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) | |
712 | * Examples: | |
713 | * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI | |
714 | * crtc1 -> dig1 -> UNIPHY0 link B -> DP | |
715 | * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS | |
716 | * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI | |
717 | */ | |
bcc1c2a1 AD |
718 | |
719 | union dig_encoder_control { | |
720 | DIG_ENCODER_CONTROL_PS_ALLOCATION v1; | |
721 | DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; | |
722 | DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; | |
723 | }; | |
724 | ||
725 | void | |
771fe6b9 JG |
726 | atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) |
727 | { | |
728 | struct drm_device *dev = encoder->dev; | |
729 | struct radeon_device *rdev = dev->dev_private; | |
730 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
9ae47867 AD |
731 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
732 | struct radeon_connector_atom_dig *dig_connector = | |
733 | radeon_get_atom_connector_priv_from_encoder(encoder); | |
bcc1c2a1 | 734 | union dig_encoder_control args; |
d9c9fe36 | 735 | int index = 0; |
771fe6b9 | 736 | uint8_t frev, crev; |
771fe6b9 | 737 | |
9ae47867 | 738 | if (!dig || !dig_connector) |
771fe6b9 JG |
739 | return; |
740 | ||
771fe6b9 JG |
741 | memset(&args, 0, sizeof(args)); |
742 | ||
bcc1c2a1 AD |
743 | if (ASIC_IS_DCE4(rdev)) |
744 | index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); | |
745 | else { | |
746 | if (dig->dig_encoder) | |
747 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); | |
748 | else | |
749 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); | |
750 | } | |
771fe6b9 | 751 | |
a084e6ee AD |
752 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
753 | return; | |
771fe6b9 | 754 | |
bcc1c2a1 AD |
755 | args.v1.ucAction = action; |
756 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
757 | args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); | |
771fe6b9 | 758 | |
bcc1c2a1 AD |
759 | if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) { |
760 | if (dig_connector->dp_clock == 270000) | |
761 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; | |
762 | args.v1.ucLaneNum = dig_connector->dp_lane_count; | |
763 | } else if (radeon_encoder->pixel_clock > 165000) | |
764 | args.v1.ucLaneNum = 8; | |
765 | else | |
766 | args.v1.ucLaneNum = 4; | |
767 | ||
768 | if (ASIC_IS_DCE4(rdev)) { | |
769 | args.v3.acConfig.ucDigSel = dig->dig_encoder; | |
770 | args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; | |
771 | } else { | |
771fe6b9 JG |
772 | switch (radeon_encoder->encoder_id) { |
773 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
bcc1c2a1 | 774 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; |
771fe6b9 JG |
775 | break; |
776 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
bcc1c2a1 AD |
777 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
778 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; | |
771fe6b9 JG |
779 | break; |
780 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
bcc1c2a1 | 781 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; |
771fe6b9 JG |
782 | break; |
783 | } | |
5137ee94 | 784 | if (dig->linkb) |
bcc1c2a1 AD |
785 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; |
786 | else | |
787 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; | |
771fe6b9 JG |
788 | } |
789 | ||
771fe6b9 JG |
790 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
791 | ||
792 | } | |
793 | ||
794 | union dig_transmitter_control { | |
795 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; | |
796 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; | |
bcc1c2a1 | 797 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; |
771fe6b9 JG |
798 | }; |
799 | ||
5801ead6 | 800 | void |
1a66c95a | 801 | atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) |
771fe6b9 JG |
802 | { |
803 | struct drm_device *dev = encoder->dev; | |
804 | struct radeon_device *rdev = dev->dev_private; | |
805 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
9ae47867 AD |
806 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
807 | struct radeon_connector_atom_dig *dig_connector = | |
808 | radeon_get_atom_connector_priv_from_encoder(encoder); | |
809 | struct drm_connector *connector; | |
810 | struct radeon_connector *radeon_connector; | |
771fe6b9 | 811 | union dig_transmitter_control args; |
d9c9fe36 | 812 | int index = 0; |
771fe6b9 | 813 | uint8_t frev, crev; |
f92a8b67 | 814 | bool is_dp = false; |
bcc1c2a1 | 815 | int pll_id = 0; |
771fe6b9 | 816 | |
9ae47867 | 817 | if (!dig || !dig_connector) |
771fe6b9 JG |
818 | return; |
819 | ||
9ae47867 | 820 | connector = radeon_get_connector_for_encoder(encoder); |
771fe6b9 JG |
821 | radeon_connector = to_radeon_connector(connector); |
822 | ||
f92a8b67 AD |
823 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) |
824 | is_dp = true; | |
825 | ||
771fe6b9 JG |
826 | memset(&args, 0, sizeof(args)); |
827 | ||
bcc1c2a1 | 828 | if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev)) |
771fe6b9 JG |
829 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
830 | else { | |
831 | switch (radeon_encoder->encoder_id) { | |
832 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
833 | index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); | |
834 | break; | |
835 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
836 | index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); | |
837 | break; | |
838 | } | |
839 | } | |
840 | ||
a084e6ee AD |
841 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
842 | return; | |
771fe6b9 JG |
843 | |
844 | args.v1.ucAction = action; | |
f95a9f0b AD |
845 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
846 | args.v1.usInitInfo = radeon_connector->connector_object_id; | |
1a66c95a AD |
847 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
848 | args.v1.asMode.ucLaneSel = lane_num; | |
849 | args.v1.asMode.ucLaneSet = lane_set; | |
f95a9f0b | 850 | } else { |
f92a8b67 AD |
851 | if (is_dp) |
852 | args.v1.usPixelClock = | |
5801ead6 | 853 | cpu_to_le16(dig_connector->dp_clock / 10); |
f92a8b67 | 854 | else if (radeon_encoder->pixel_clock > 165000) |
f95a9f0b AD |
855 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
856 | else | |
857 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
858 | } | |
bcc1c2a1 AD |
859 | if (ASIC_IS_DCE4(rdev)) { |
860 | if (is_dp) | |
861 | args.v3.ucLaneNum = dig_connector->dp_lane_count; | |
862 | else if (radeon_encoder->pixel_clock > 165000) | |
863 | args.v3.ucLaneNum = 8; | |
864 | else | |
865 | args.v3.ucLaneNum = 4; | |
866 | ||
5137ee94 | 867 | if (dig->linkb) { |
bcc1c2a1 AD |
868 | args.v3.acConfig.ucLinkSel = 1; |
869 | args.v3.acConfig.ucEncoderSel = 1; | |
870 | } | |
871 | ||
872 | /* Select the PLL for the PHY | |
873 | * DP PHY should be clocked from external src if there is | |
874 | * one. | |
875 | */ | |
876 | if (encoder->crtc) { | |
877 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
878 | pll_id = radeon_crtc->pll_id; | |
879 | } | |
880 | if (is_dp && rdev->clock.dp_extclk) | |
881 | args.v3.acConfig.ucRefClkSource = 2; /* external src */ | |
882 | else | |
883 | args.v3.acConfig.ucRefClkSource = pll_id; | |
884 | ||
885 | switch (radeon_encoder->encoder_id) { | |
886 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
887 | args.v3.acConfig.ucTransmitterSel = 0; | |
bcc1c2a1 AD |
888 | break; |
889 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
890 | args.v3.acConfig.ucTransmitterSel = 1; | |
bcc1c2a1 AD |
891 | break; |
892 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
893 | args.v3.acConfig.ucTransmitterSel = 2; | |
bcc1c2a1 AD |
894 | break; |
895 | } | |
896 | ||
897 | if (is_dp) | |
898 | args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ | |
899 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
900 | if (dig->coherent_mode) | |
901 | args.v3.acConfig.fCoherentMode = 1; | |
b317a9ce AD |
902 | if (radeon_encoder->pixel_clock > 165000) |
903 | args.v3.acConfig.fDualLinkConnector = 1; | |
bcc1c2a1 AD |
904 | } |
905 | } else if (ASIC_IS_DCE32(rdev)) { | |
d9c9fe36 | 906 | args.v2.acConfig.ucEncoderSel = dig->dig_encoder; |
5137ee94 | 907 | if (dig->linkb) |
1a66c95a | 908 | args.v2.acConfig.ucLinkSel = 1; |
771fe6b9 JG |
909 | |
910 | switch (radeon_encoder->encoder_id) { | |
911 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
912 | args.v2.acConfig.ucTransmitterSel = 0; | |
771fe6b9 JG |
913 | break; |
914 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
915 | args.v2.acConfig.ucTransmitterSel = 1; | |
771fe6b9 JG |
916 | break; |
917 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
918 | args.v2.acConfig.ucTransmitterSel = 2; | |
771fe6b9 JG |
919 | break; |
920 | } | |
921 | ||
f92a8b67 AD |
922 | if (is_dp) |
923 | args.v2.acConfig.fCoherentMode = 1; | |
924 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
771fe6b9 JG |
925 | if (dig->coherent_mode) |
926 | args.v2.acConfig.fCoherentMode = 1; | |
b317a9ce AD |
927 | if (radeon_encoder->pixel_clock > 165000) |
928 | args.v2.acConfig.fDualLinkConnector = 1; | |
771fe6b9 JG |
929 | } |
930 | } else { | |
931 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; | |
771fe6b9 | 932 | |
f28cf339 DA |
933 | if (dig->dig_encoder) |
934 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; | |
935 | else | |
936 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; | |
937 | ||
d9c9fe36 AD |
938 | if ((rdev->flags & RADEON_IS_IGP) && |
939 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { | |
940 | if (is_dp || (radeon_encoder->pixel_clock <= 165000)) { | |
941 | if (dig_connector->igp_lane_info & 0x1) | |
942 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; | |
943 | else if (dig_connector->igp_lane_info & 0x2) | |
944 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; | |
945 | else if (dig_connector->igp_lane_info & 0x4) | |
946 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; | |
947 | else if (dig_connector->igp_lane_info & 0x8) | |
948 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; | |
949 | } else { | |
950 | if (dig_connector->igp_lane_info & 0x3) | |
951 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; | |
952 | else if (dig_connector->igp_lane_info & 0xc) | |
953 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; | |
771fe6b9 | 954 | } |
771fe6b9 JG |
955 | } |
956 | ||
5137ee94 | 957 | if (dig->linkb) |
1a66c95a AD |
958 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; |
959 | else | |
960 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; | |
961 | ||
f92a8b67 AD |
962 | if (is_dp) |
963 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; | |
964 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
771fe6b9 JG |
965 | if (dig->coherent_mode) |
966 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; | |
d9c9fe36 AD |
967 | if (radeon_encoder->pixel_clock > 165000) |
968 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; | |
771fe6b9 JG |
969 | } |
970 | } | |
971 | ||
972 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
771fe6b9 JG |
973 | } |
974 | ||
771fe6b9 JG |
975 | static void |
976 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) | |
977 | { | |
978 | struct drm_device *dev = encoder->dev; | |
979 | struct radeon_device *rdev = dev->dev_private; | |
980 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
981 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
982 | ENABLE_YUV_PS_ALLOCATION args; | |
983 | int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); | |
984 | uint32_t temp, reg; | |
985 | ||
986 | memset(&args, 0, sizeof(args)); | |
987 | ||
988 | if (rdev->family >= CHIP_R600) | |
989 | reg = R600_BIOS_3_SCRATCH; | |
990 | else | |
991 | reg = RADEON_BIOS_3_SCRATCH; | |
992 | ||
993 | /* XXX: fix up scratch reg handling */ | |
994 | temp = RREG32(reg); | |
4ce001ab | 995 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 JG |
996 | WREG32(reg, (ATOM_S3_TV1_ACTIVE | |
997 | (radeon_crtc->crtc_id << 18))); | |
4ce001ab | 998 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
999 | WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); |
1000 | else | |
1001 | WREG32(reg, 0); | |
1002 | ||
1003 | if (enable) | |
1004 | args.ucEnable = ATOM_ENABLE; | |
1005 | args.ucCRTC = radeon_crtc->crtc_id; | |
1006 | ||
1007 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1008 | ||
1009 | WREG32(reg, temp); | |
1010 | } | |
1011 | ||
771fe6b9 JG |
1012 | static void |
1013 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) | |
1014 | { | |
1015 | struct drm_device *dev = encoder->dev; | |
1016 | struct radeon_device *rdev = dev->dev_private; | |
1017 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1018 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; | |
1019 | int index = 0; | |
1020 | bool is_dig = false; | |
1021 | ||
1022 | memset(&args, 0, sizeof(args)); | |
1023 | ||
d9fdaafb | 1024 | DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
f641e51e DA |
1025 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
1026 | radeon_encoder->active_device); | |
771fe6b9 JG |
1027 | switch (radeon_encoder->encoder_id) { |
1028 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1029 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1030 | index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); | |
1031 | break; | |
1032 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1033 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1034 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1035 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
1036 | is_dig = true; | |
1037 | break; | |
1038 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1039 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1040 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1041 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); | |
1042 | break; | |
1043 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1044 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); | |
1045 | break; | |
1046 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1047 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
1048 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); | |
1049 | else | |
1050 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); | |
1051 | break; | |
1052 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1053 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
8c2a6d73 | 1054 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1055 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
8c2a6d73 | 1056 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1057 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
1058 | else | |
1059 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); | |
1060 | break; | |
1061 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1062 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
8c2a6d73 | 1063 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1064 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
8c2a6d73 | 1065 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1066 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
1067 | else | |
1068 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); | |
1069 | break; | |
1070 | } | |
1071 | ||
1072 | if (is_dig) { | |
1073 | switch (mode) { | |
1074 | case DRM_MODE_DPMS_ON: | |
a5f798ce AD |
1075 | if (!ASIC_IS_DCE4(rdev)) |
1076 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); | |
fb668c2f | 1077 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { |
58682f10 | 1078 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
fb668c2f | 1079 | |
58682f10 | 1080 | dp_link_train(encoder, connector); |
fb668c2f AD |
1081 | if (ASIC_IS_DCE4(rdev)) |
1082 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON); | |
58682f10 | 1083 | } |
771fe6b9 JG |
1084 | break; |
1085 | case DRM_MODE_DPMS_STANDBY: | |
1086 | case DRM_MODE_DPMS_SUSPEND: | |
1087 | case DRM_MODE_DPMS_OFF: | |
fb668c2f AD |
1088 | if (!ASIC_IS_DCE4(rdev)) |
1089 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); | |
1090 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { | |
1091 | if (ASIC_IS_DCE4(rdev)) | |
1092 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF); | |
1093 | } | |
771fe6b9 JG |
1094 | break; |
1095 | } | |
1096 | } else { | |
1097 | switch (mode) { | |
1098 | case DRM_MODE_DPMS_ON: | |
1099 | args.ucAction = ATOM_ENABLE; | |
1100 | break; | |
1101 | case DRM_MODE_DPMS_STANDBY: | |
1102 | case DRM_MODE_DPMS_SUSPEND: | |
1103 | case DRM_MODE_DPMS_OFF: | |
1104 | args.ucAction = ATOM_DISABLE; | |
1105 | break; | |
1106 | } | |
1107 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1108 | } | |
1109 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); | |
c913e23a | 1110 | |
771fe6b9 JG |
1111 | } |
1112 | ||
9ae47867 | 1113 | union crtc_source_param { |
771fe6b9 JG |
1114 | SELECT_CRTC_SOURCE_PS_ALLOCATION v1; |
1115 | SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; | |
1116 | }; | |
1117 | ||
1118 | static void | |
1119 | atombios_set_encoder_crtc_source(struct drm_encoder *encoder) | |
1120 | { | |
1121 | struct drm_device *dev = encoder->dev; | |
1122 | struct radeon_device *rdev = dev->dev_private; | |
1123 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1124 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
9ae47867 | 1125 | union crtc_source_param args; |
771fe6b9 JG |
1126 | int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); |
1127 | uint8_t frev, crev; | |
f28cf339 | 1128 | struct radeon_encoder_atom_dig *dig; |
771fe6b9 JG |
1129 | |
1130 | memset(&args, 0, sizeof(args)); | |
1131 | ||
a084e6ee AD |
1132 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1133 | return; | |
771fe6b9 JG |
1134 | |
1135 | switch (frev) { | |
1136 | case 1: | |
1137 | switch (crev) { | |
1138 | case 1: | |
1139 | default: | |
1140 | if (ASIC_IS_AVIVO(rdev)) | |
1141 | args.v1.ucCRTC = radeon_crtc->crtc_id; | |
1142 | else { | |
1143 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { | |
1144 | args.v1.ucCRTC = radeon_crtc->crtc_id; | |
1145 | } else { | |
1146 | args.v1.ucCRTC = radeon_crtc->crtc_id << 2; | |
1147 | } | |
1148 | } | |
1149 | switch (radeon_encoder->encoder_id) { | |
1150 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1151 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1152 | args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; | |
1153 | break; | |
1154 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1155 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1156 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) | |
1157 | args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; | |
1158 | else | |
1159 | args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; | |
1160 | break; | |
1161 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1162 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1163 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1164 | args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; | |
1165 | break; | |
1166 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1167 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
4ce001ab | 1168 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1169 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
4ce001ab | 1170 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1171 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1172 | else | |
1173 | args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; | |
1174 | break; | |
1175 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1176 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
4ce001ab | 1177 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1178 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
4ce001ab | 1179 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1180 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1181 | else | |
1182 | args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; | |
1183 | break; | |
1184 | } | |
1185 | break; | |
1186 | case 2: | |
1187 | args.v2.ucCRTC = radeon_crtc->crtc_id; | |
1188 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); | |
1189 | switch (radeon_encoder->encoder_id) { | |
1190 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1191 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1192 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
f28cf339 DA |
1193 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1194 | dig = radeon_encoder->enc_priv; | |
bcc1c2a1 AD |
1195 | switch (dig->dig_encoder) { |
1196 | case 0: | |
f28cf339 | 1197 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; |
bcc1c2a1 AD |
1198 | break; |
1199 | case 1: | |
1200 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; | |
1201 | break; | |
1202 | case 2: | |
1203 | args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; | |
1204 | break; | |
1205 | case 3: | |
1206 | args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; | |
1207 | break; | |
1208 | case 4: | |
1209 | args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; | |
1210 | break; | |
1211 | case 5: | |
1212 | args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; | |
1213 | break; | |
1214 | } | |
771fe6b9 JG |
1215 | break; |
1216 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1217 | args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; | |
1218 | break; | |
771fe6b9 | 1219 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
4ce001ab | 1220 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1221 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
4ce001ab | 1222 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1223 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1224 | else | |
1225 | args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; | |
1226 | break; | |
1227 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
4ce001ab | 1228 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1229 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
4ce001ab | 1230 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1231 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1232 | else | |
1233 | args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; | |
1234 | break; | |
1235 | } | |
1236 | break; | |
1237 | } | |
1238 | break; | |
1239 | default: | |
1240 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); | |
1241 | break; | |
1242 | } | |
1243 | ||
1244 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
267364ac AD |
1245 | |
1246 | /* update scratch regs with new routing */ | |
1247 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); | |
771fe6b9 JG |
1248 | } |
1249 | ||
1250 | static void | |
1251 | atombios_apply_encoder_quirks(struct drm_encoder *encoder, | |
1252 | struct drm_display_mode *mode) | |
1253 | { | |
1254 | struct drm_device *dev = encoder->dev; | |
1255 | struct radeon_device *rdev = dev->dev_private; | |
1256 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1257 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
1258 | ||
1259 | /* Funky macbooks */ | |
1260 | if ((dev->pdev->device == 0x71C5) && | |
1261 | (dev->pdev->subsystem_vendor == 0x106b) && | |
1262 | (dev->pdev->subsystem_device == 0x0080)) { | |
1263 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { | |
1264 | uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); | |
1265 | ||
1266 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; | |
1267 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; | |
1268 | ||
1269 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); | |
1270 | } | |
1271 | } | |
1272 | ||
1273 | /* set scaler clears this on some chips */ | |
bcc1c2a1 | 1274 | /* XXX check DCE4 */ |
ceefedd8 AD |
1275 | if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) { |
1276 | if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) | |
1277 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, | |
1278 | AVIVO_D1MODE_INTERLEAVE_EN); | |
1279 | } | |
771fe6b9 JG |
1280 | } |
1281 | ||
f28cf339 DA |
1282 | static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) |
1283 | { | |
1284 | struct drm_device *dev = encoder->dev; | |
1285 | struct radeon_device *rdev = dev->dev_private; | |
1286 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
1287 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1288 | struct drm_encoder *test_encoder; | |
1289 | struct radeon_encoder_atom_dig *dig; | |
1290 | uint32_t dig_enc_in_use = 0; | |
bcc1c2a1 AD |
1291 | |
1292 | if (ASIC_IS_DCE4(rdev)) { | |
5137ee94 | 1293 | dig = radeon_encoder->enc_priv; |
bcc1c2a1 AD |
1294 | switch (radeon_encoder->encoder_id) { |
1295 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
5137ee94 | 1296 | if (dig->linkb) |
bcc1c2a1 AD |
1297 | return 1; |
1298 | else | |
1299 | return 0; | |
1300 | break; | |
1301 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
5137ee94 | 1302 | if (dig->linkb) |
bcc1c2a1 AD |
1303 | return 3; |
1304 | else | |
1305 | return 2; | |
1306 | break; | |
1307 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
5137ee94 | 1308 | if (dig->linkb) |
bcc1c2a1 AD |
1309 | return 5; |
1310 | else | |
1311 | return 4; | |
1312 | break; | |
1313 | } | |
1314 | } | |
1315 | ||
f28cf339 DA |
1316 | /* on DCE32 and encoder can driver any block so just crtc id */ |
1317 | if (ASIC_IS_DCE32(rdev)) { | |
1318 | return radeon_crtc->crtc_id; | |
1319 | } | |
1320 | ||
1321 | /* on DCE3 - LVTMA can only be driven by DIGB */ | |
1322 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { | |
1323 | struct radeon_encoder *radeon_test_encoder; | |
1324 | ||
1325 | if (encoder == test_encoder) | |
1326 | continue; | |
1327 | ||
1328 | if (!radeon_encoder_is_digital(test_encoder)) | |
1329 | continue; | |
1330 | ||
1331 | radeon_test_encoder = to_radeon_encoder(test_encoder); | |
1332 | dig = radeon_test_encoder->enc_priv; | |
1333 | ||
1334 | if (dig->dig_encoder >= 0) | |
1335 | dig_enc_in_use |= (1 << dig->dig_encoder); | |
1336 | } | |
1337 | ||
1338 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { | |
1339 | if (dig_enc_in_use & 0x2) | |
1340 | DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); | |
1341 | return 1; | |
1342 | } | |
1343 | if (!(dig_enc_in_use & 1)) | |
1344 | return 0; | |
1345 | return 1; | |
1346 | } | |
1347 | ||
771fe6b9 JG |
1348 | static void |
1349 | radeon_atom_encoder_mode_set(struct drm_encoder *encoder, | |
1350 | struct drm_display_mode *mode, | |
1351 | struct drm_display_mode *adjusted_mode) | |
1352 | { | |
1353 | struct drm_device *dev = encoder->dev; | |
1354 | struct radeon_device *rdev = dev->dev_private; | |
1355 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
771fe6b9 | 1356 | |
771fe6b9 JG |
1357 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
1358 | ||
c6f8505e | 1359 | if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { |
4ce001ab | 1360 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 JG |
1361 | atombios_yuv_setup(encoder, true); |
1362 | else | |
1363 | atombios_yuv_setup(encoder, false); | |
1364 | } | |
1365 | ||
1366 | switch (radeon_encoder->encoder_id) { | |
1367 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1368 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1369 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1370 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1371 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); | |
1372 | break; | |
1373 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1374 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1375 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1376 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
bcc1c2a1 AD |
1377 | if (ASIC_IS_DCE4(rdev)) { |
1378 | /* disable the transmitter */ | |
1379 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | |
1380 | /* setup and enable the encoder */ | |
1381 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP); | |
1382 | ||
1383 | /* init and enable the transmitter */ | |
1384 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); | |
1385 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); | |
1386 | } else { | |
1387 | /* disable the encoder and transmitter */ | |
1388 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | |
1389 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE); | |
1390 | ||
1391 | /* setup and enable the encoder and transmitter */ | |
1392 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE); | |
1393 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); | |
1394 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); | |
1395 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); | |
1396 | } | |
771fe6b9 JG |
1397 | break; |
1398 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1399 | atombios_ddia_setup(encoder, ATOM_ENABLE); | |
1400 | break; | |
1401 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1402 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1403 | atombios_external_tmds_setup(encoder, ATOM_ENABLE); | |
1404 | break; | |
1405 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1406 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
1407 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1408 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
1409 | atombios_dac_setup(encoder, ATOM_ENABLE); | |
d3a67a43 AD |
1410 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { |
1411 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) | |
1412 | atombios_tv_setup(encoder, ATOM_ENABLE); | |
1413 | else | |
1414 | atombios_tv_setup(encoder, ATOM_DISABLE); | |
1415 | } | |
771fe6b9 JG |
1416 | break; |
1417 | } | |
1418 | atombios_apply_encoder_quirks(encoder, adjusted_mode); | |
dafc3bd5 | 1419 | |
2cd6218c RM |
1420 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { |
1421 | r600_hdmi_enable(encoder); | |
bcc1c2a1 | 1422 | r600_hdmi_setmode(encoder, adjusted_mode); |
2cd6218c | 1423 | } |
771fe6b9 JG |
1424 | } |
1425 | ||
1426 | static bool | |
4ce001ab | 1427 | atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
771fe6b9 JG |
1428 | { |
1429 | struct drm_device *dev = encoder->dev; | |
1430 | struct radeon_device *rdev = dev->dev_private; | |
1431 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
4ce001ab | 1432 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
771fe6b9 JG |
1433 | |
1434 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | | |
1435 | ATOM_DEVICE_CV_SUPPORT | | |
1436 | ATOM_DEVICE_CRT_SUPPORT)) { | |
1437 | DAC_LOAD_DETECTION_PS_ALLOCATION args; | |
1438 | int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); | |
1439 | uint8_t frev, crev; | |
1440 | ||
1441 | memset(&args, 0, sizeof(args)); | |
1442 | ||
a084e6ee AD |
1443 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1444 | return false; | |
771fe6b9 JG |
1445 | |
1446 | args.sDacload.ucMisc = 0; | |
1447 | ||
1448 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || | |
1449 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) | |
1450 | args.sDacload.ucDacType = ATOM_DAC_A; | |
1451 | else | |
1452 | args.sDacload.ucDacType = ATOM_DAC_B; | |
1453 | ||
4ce001ab | 1454 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) |
771fe6b9 | 1455 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); |
4ce001ab | 1456 | else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) |
771fe6b9 | 1457 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); |
4ce001ab | 1458 | else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
771fe6b9 JG |
1459 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); |
1460 | if (crev >= 3) | |
1461 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; | |
4ce001ab | 1462 | } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
771fe6b9 JG |
1463 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); |
1464 | if (crev >= 3) | |
1465 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; | |
1466 | } | |
1467 | ||
1468 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1469 | ||
1470 | return true; | |
1471 | } else | |
1472 | return false; | |
1473 | } | |
1474 | ||
1475 | static enum drm_connector_status | |
1476 | radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) | |
1477 | { | |
1478 | struct drm_device *dev = encoder->dev; | |
1479 | struct radeon_device *rdev = dev->dev_private; | |
1480 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
4ce001ab | 1481 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
771fe6b9 JG |
1482 | uint32_t bios_0_scratch; |
1483 | ||
4ce001ab | 1484 | if (!atombios_dac_load_detect(encoder, connector)) { |
d9fdaafb | 1485 | DRM_DEBUG_KMS("detect returned false \n"); |
771fe6b9 JG |
1486 | return connector_status_unknown; |
1487 | } | |
1488 | ||
1489 | if (rdev->family >= CHIP_R600) | |
1490 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); | |
1491 | else | |
1492 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); | |
1493 | ||
d9fdaafb | 1494 | DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); |
4ce001ab | 1495 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
771fe6b9 JG |
1496 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
1497 | return connector_status_connected; | |
4ce001ab DA |
1498 | } |
1499 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { | |
771fe6b9 JG |
1500 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
1501 | return connector_status_connected; | |
4ce001ab DA |
1502 | } |
1503 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { | |
771fe6b9 JG |
1504 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
1505 | return connector_status_connected; | |
4ce001ab DA |
1506 | } |
1507 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { | |
771fe6b9 JG |
1508 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
1509 | return connector_status_connected; /* CTV */ | |
1510 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) | |
1511 | return connector_status_connected; /* STV */ | |
1512 | } | |
1513 | return connector_status_disconnected; | |
1514 | } | |
1515 | ||
1516 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) | |
1517 | { | |
267364ac AD |
1518 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1519 | ||
1520 | if (radeon_encoder->active_device & | |
1521 | (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) { | |
1522 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
1523 | if (dig) | |
1524 | dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); | |
1525 | } | |
1526 | ||
771fe6b9 JG |
1527 | radeon_atom_output_lock(encoder, true); |
1528 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); | |
267364ac AD |
1529 | |
1530 | /* this is needed for the pll/ss setup to work correctly in some cases */ | |
1531 | atombios_set_encoder_crtc_source(encoder); | |
771fe6b9 JG |
1532 | } |
1533 | ||
1534 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) | |
1535 | { | |
1536 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); | |
1537 | radeon_atom_output_lock(encoder, false); | |
1538 | } | |
1539 | ||
4ce001ab DA |
1540 | static void radeon_atom_encoder_disable(struct drm_encoder *encoder) |
1541 | { | |
aa961391 AD |
1542 | struct drm_device *dev = encoder->dev; |
1543 | struct radeon_device *rdev = dev->dev_private; | |
4ce001ab | 1544 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
f28cf339 | 1545 | struct radeon_encoder_atom_dig *dig; |
4ce001ab | 1546 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
f28cf339 | 1547 | |
aa961391 AD |
1548 | switch (radeon_encoder->encoder_id) { |
1549 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1550 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1551 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1552 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1553 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); | |
1554 | break; | |
1555 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1556 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1557 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1558 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
1559 | if (ASIC_IS_DCE4(rdev)) | |
1560 | /* disable the transmitter */ | |
1561 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | |
1562 | else { | |
1563 | /* disable the encoder and transmitter */ | |
1564 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | |
1565 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE); | |
1566 | } | |
1567 | break; | |
1568 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1569 | atombios_ddia_setup(encoder, ATOM_DISABLE); | |
1570 | break; | |
1571 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1572 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1573 | atombios_external_tmds_setup(encoder, ATOM_DISABLE); | |
1574 | break; | |
1575 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1576 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
1577 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1578 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
1579 | atombios_dac_setup(encoder, ATOM_DISABLE); | |
8bf3aae6 | 1580 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
aa961391 AD |
1581 | atombios_tv_setup(encoder, ATOM_DISABLE); |
1582 | break; | |
1583 | } | |
1584 | ||
f28cf339 | 1585 | if (radeon_encoder_is_digital(encoder)) { |
2cd6218c RM |
1586 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) |
1587 | r600_hdmi_disable(encoder); | |
f28cf339 DA |
1588 | dig = radeon_encoder->enc_priv; |
1589 | dig->dig_encoder = -1; | |
1590 | } | |
4ce001ab DA |
1591 | radeon_encoder->active_device = 0; |
1592 | } | |
1593 | ||
771fe6b9 JG |
1594 | static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { |
1595 | .dpms = radeon_atom_encoder_dpms, | |
1596 | .mode_fixup = radeon_atom_mode_fixup, | |
1597 | .prepare = radeon_atom_encoder_prepare, | |
1598 | .mode_set = radeon_atom_encoder_mode_set, | |
1599 | .commit = radeon_atom_encoder_commit, | |
4ce001ab | 1600 | .disable = radeon_atom_encoder_disable, |
771fe6b9 JG |
1601 | /* no detect for TMDS/LVDS yet */ |
1602 | }; | |
1603 | ||
1604 | static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { | |
1605 | .dpms = radeon_atom_encoder_dpms, | |
1606 | .mode_fixup = radeon_atom_mode_fixup, | |
1607 | .prepare = radeon_atom_encoder_prepare, | |
1608 | .mode_set = radeon_atom_encoder_mode_set, | |
1609 | .commit = radeon_atom_encoder_commit, | |
1610 | .detect = radeon_atom_dac_detect, | |
1611 | }; | |
1612 | ||
1613 | void radeon_enc_destroy(struct drm_encoder *encoder) | |
1614 | { | |
1615 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1616 | kfree(radeon_encoder->enc_priv); | |
1617 | drm_encoder_cleanup(encoder); | |
1618 | kfree(radeon_encoder); | |
1619 | } | |
1620 | ||
1621 | static const struct drm_encoder_funcs radeon_atom_enc_funcs = { | |
1622 | .destroy = radeon_enc_destroy, | |
1623 | }; | |
1624 | ||
4ce001ab DA |
1625 | struct radeon_encoder_atom_dac * |
1626 | radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) | |
1627 | { | |
affd8589 AD |
1628 | struct drm_device *dev = radeon_encoder->base.dev; |
1629 | struct radeon_device *rdev = dev->dev_private; | |
4ce001ab DA |
1630 | struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); |
1631 | ||
1632 | if (!dac) | |
1633 | return NULL; | |
1634 | ||
affd8589 | 1635 | dac->tv_std = radeon_atombios_get_tv_info(rdev); |
4ce001ab DA |
1636 | return dac; |
1637 | } | |
1638 | ||
771fe6b9 JG |
1639 | struct radeon_encoder_atom_dig * |
1640 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) | |
1641 | { | |
5137ee94 | 1642 | int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
771fe6b9 JG |
1643 | struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
1644 | ||
1645 | if (!dig) | |
1646 | return NULL; | |
1647 | ||
1648 | /* coherent mode by default */ | |
1649 | dig->coherent_mode = true; | |
f28cf339 | 1650 | dig->dig_encoder = -1; |
771fe6b9 | 1651 | |
5137ee94 AD |
1652 | if (encoder_enum == 2) |
1653 | dig->linkb = true; | |
1654 | else | |
1655 | dig->linkb = false; | |
1656 | ||
771fe6b9 JG |
1657 | return dig; |
1658 | } | |
1659 | ||
1660 | void | |
5137ee94 | 1661 | radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device) |
771fe6b9 | 1662 | { |
dfee5614 | 1663 | struct radeon_device *rdev = dev->dev_private; |
771fe6b9 JG |
1664 | struct drm_encoder *encoder; |
1665 | struct radeon_encoder *radeon_encoder; | |
1666 | ||
1667 | /* see if we already added it */ | |
1668 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1669 | radeon_encoder = to_radeon_encoder(encoder); | |
5137ee94 | 1670 | if (radeon_encoder->encoder_enum == encoder_enum) { |
771fe6b9 JG |
1671 | radeon_encoder->devices |= supported_device; |
1672 | return; | |
1673 | } | |
1674 | ||
1675 | } | |
1676 | ||
1677 | /* add a new one */ | |
1678 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); | |
1679 | if (!radeon_encoder) | |
1680 | return; | |
1681 | ||
1682 | encoder = &radeon_encoder->base; | |
bcc1c2a1 AD |
1683 | switch (rdev->num_crtc) { |
1684 | case 1: | |
dfee5614 | 1685 | encoder->possible_crtcs = 0x1; |
bcc1c2a1 AD |
1686 | break; |
1687 | case 2: | |
1688 | default: | |
dfee5614 | 1689 | encoder->possible_crtcs = 0x3; |
bcc1c2a1 AD |
1690 | break; |
1691 | case 6: | |
1692 | encoder->possible_crtcs = 0x3f; | |
1693 | break; | |
1694 | } | |
771fe6b9 JG |
1695 | |
1696 | radeon_encoder->enc_priv = NULL; | |
1697 | ||
5137ee94 AD |
1698 | radeon_encoder->encoder_enum = encoder_enum; |
1699 | radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | |
771fe6b9 | 1700 | radeon_encoder->devices = supported_device; |
c93bb85b | 1701 | radeon_encoder->rmx_type = RMX_OFF; |
5b1714d3 | 1702 | radeon_encoder->underscan_type = UNDERSCAN_OFF; |
771fe6b9 JG |
1703 | |
1704 | switch (radeon_encoder->encoder_id) { | |
1705 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1706 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1707 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1708 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1709 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
1710 | radeon_encoder->rmx_type = RMX_FULL; | |
1711 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); | |
1712 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); | |
1713 | } else { | |
1714 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); | |
1715 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); | |
430f70d5 AD |
1716 | if (ASIC_IS_AVIVO(rdev)) |
1717 | radeon_encoder->underscan_type = UNDERSCAN_AUTO; | |
771fe6b9 JG |
1718 | } |
1719 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); | |
1720 | break; | |
1721 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1722 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); | |
affd8589 | 1723 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
771fe6b9 JG |
1724 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
1725 | break; | |
1726 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1727 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
1728 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
1729 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); | |
4ce001ab | 1730 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
771fe6b9 JG |
1731 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
1732 | break; | |
1733 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1734 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1735 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1736 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1737 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
1738 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1739 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
60d15f55 AD |
1740 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1741 | radeon_encoder->rmx_type = RMX_FULL; | |
1742 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); | |
1743 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); | |
1744 | } else { | |
1745 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); | |
1746 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); | |
430f70d5 AD |
1747 | if (ASIC_IS_AVIVO(rdev)) |
1748 | radeon_encoder->underscan_type = UNDERSCAN_AUTO; | |
60d15f55 | 1749 | } |
771fe6b9 JG |
1750 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
1751 | break; | |
1752 | } | |
1753 | } |