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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include "drmP.h" | |
27 | #include "drm_crtc_helper.h" | |
28 | #include "radeon_drm.h" | |
29 | #include "radeon.h" | |
30 | #include "atom.h" | |
31 | ||
32 | extern int atom_debug; | |
33 | ||
5a9bcacc AD |
34 | /* evil but including atombios.h is much worse */ |
35 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, | |
36 | struct drm_display_mode *mode); | |
37 | ||
1f3b6a45 DA |
38 | static uint32_t radeon_encoder_clones(struct drm_encoder *encoder) |
39 | { | |
40 | struct drm_device *dev = encoder->dev; | |
41 | struct radeon_device *rdev = dev->dev_private; | |
42 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
43 | struct drm_encoder *clone_encoder; | |
44 | uint32_t index_mask = 0; | |
45 | int count; | |
46 | ||
47 | /* DIG routing gets problematic */ | |
48 | if (rdev->family >= CHIP_R600) | |
49 | return index_mask; | |
50 | /* LVDS/TV are too wacky */ | |
51 | if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) | |
52 | return index_mask; | |
53 | /* DVO requires 2x ppll clocks depending on tmds chip */ | |
54 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) | |
55 | return index_mask; | |
56 | ||
57 | count = -1; | |
58 | list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) { | |
59 | struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder); | |
60 | count++; | |
61 | ||
62 | if (clone_encoder == encoder) | |
63 | continue; | |
64 | if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
65 | continue; | |
66 | if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT) | |
67 | continue; | |
68 | else | |
69 | index_mask |= (1 << count); | |
70 | } | |
71 | return index_mask; | |
72 | } | |
73 | ||
74 | void radeon_setup_encoder_clones(struct drm_device *dev) | |
75 | { | |
76 | struct drm_encoder *encoder; | |
77 | ||
78 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
79 | encoder->possible_clones = radeon_encoder_clones(encoder); | |
80 | } | |
81 | } | |
82 | ||
771fe6b9 JG |
83 | uint32_t |
84 | radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac) | |
85 | { | |
86 | struct radeon_device *rdev = dev->dev_private; | |
87 | uint32_t ret = 0; | |
88 | ||
89 | switch (supported_device) { | |
90 | case ATOM_DEVICE_CRT1_SUPPORT: | |
91 | case ATOM_DEVICE_TV1_SUPPORT: | |
92 | case ATOM_DEVICE_TV2_SUPPORT: | |
93 | case ATOM_DEVICE_CRT2_SUPPORT: | |
94 | case ATOM_DEVICE_CV_SUPPORT: | |
95 | switch (dac) { | |
96 | case 1: /* dac a */ | |
97 | if ((rdev->family == CHIP_RS300) || | |
98 | (rdev->family == CHIP_RS400) || | |
99 | (rdev->family == CHIP_RS480)) | |
100 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; | |
101 | else if (ASIC_IS_AVIVO(rdev)) | |
102 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; | |
103 | else | |
104 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC1; | |
105 | break; | |
106 | case 2: /* dac b */ | |
107 | if (ASIC_IS_AVIVO(rdev)) | |
108 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; | |
109 | else { | |
110 | /*if (rdev->family == CHIP_R200) | |
111 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; | |
112 | else*/ | |
113 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; | |
114 | } | |
115 | break; | |
116 | case 3: /* external dac */ | |
117 | if (ASIC_IS_AVIVO(rdev)) | |
118 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; | |
119 | else | |
120 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; | |
121 | break; | |
122 | } | |
123 | break; | |
124 | case ATOM_DEVICE_LCD1_SUPPORT: | |
125 | if (ASIC_IS_AVIVO(rdev)) | |
126 | ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; | |
127 | else | |
128 | ret = ENCODER_OBJECT_ID_INTERNAL_LVDS; | |
129 | break; | |
130 | case ATOM_DEVICE_DFP1_SUPPORT: | |
131 | if ((rdev->family == CHIP_RS300) || | |
132 | (rdev->family == CHIP_RS400) || | |
133 | (rdev->family == CHIP_RS480)) | |
134 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; | |
135 | else if (ASIC_IS_AVIVO(rdev)) | |
136 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; | |
137 | else | |
138 | ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1; | |
139 | break; | |
140 | case ATOM_DEVICE_LCD2_SUPPORT: | |
141 | case ATOM_DEVICE_DFP2_SUPPORT: | |
142 | if ((rdev->family == CHIP_RS600) || | |
143 | (rdev->family == CHIP_RS690) || | |
144 | (rdev->family == CHIP_RS740)) | |
145 | ret = ENCODER_OBJECT_ID_INTERNAL_DDI; | |
146 | else if (ASIC_IS_AVIVO(rdev)) | |
147 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; | |
148 | else | |
149 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; | |
150 | break; | |
151 | case ATOM_DEVICE_DFP3_SUPPORT: | |
152 | ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; | |
153 | break; | |
154 | } | |
155 | ||
156 | return ret; | |
157 | } | |
158 | ||
159 | void | |
160 | radeon_link_encoder_connector(struct drm_device *dev) | |
161 | { | |
162 | struct drm_connector *connector; | |
163 | struct radeon_connector *radeon_connector; | |
164 | struct drm_encoder *encoder; | |
165 | struct radeon_encoder *radeon_encoder; | |
166 | ||
167 | /* walk the list and link encoders to connectors */ | |
168 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
169 | radeon_connector = to_radeon_connector(connector); | |
170 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
171 | radeon_encoder = to_radeon_encoder(encoder); | |
172 | if (radeon_encoder->devices & radeon_connector->devices) | |
173 | drm_mode_connector_attach_encoder(connector, encoder); | |
174 | } | |
175 | } | |
176 | } | |
177 | ||
4ce001ab DA |
178 | void radeon_encoder_set_active_device(struct drm_encoder *encoder) |
179 | { | |
180 | struct drm_device *dev = encoder->dev; | |
181 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
182 | struct drm_connector *connector; | |
183 | ||
184 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
185 | if (connector->encoder == encoder) { | |
186 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
187 | radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; | |
f641e51e DA |
188 | DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n", |
189 | radeon_encoder->active_device, radeon_encoder->devices, | |
190 | radeon_connector->devices, encoder->encoder_type); | |
4ce001ab DA |
191 | } |
192 | } | |
193 | } | |
194 | ||
771fe6b9 JG |
195 | static struct drm_connector * |
196 | radeon_get_connector_for_encoder(struct drm_encoder *encoder) | |
197 | { | |
198 | struct drm_device *dev = encoder->dev; | |
199 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
200 | struct drm_connector *connector; | |
201 | struct radeon_connector *radeon_connector; | |
202 | ||
203 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
204 | radeon_connector = to_radeon_connector(connector); | |
205 | if (radeon_encoder->devices & radeon_connector->devices) | |
206 | return connector; | |
207 | } | |
208 | return NULL; | |
209 | } | |
210 | ||
771fe6b9 JG |
211 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
212 | struct drm_display_mode *mode, | |
213 | struct drm_display_mode *adjusted_mode) | |
214 | { | |
771fe6b9 | 215 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
5a9bcacc AD |
216 | struct drm_device *dev = encoder->dev; |
217 | struct radeon_device *rdev = dev->dev_private; | |
771fe6b9 | 218 | |
8c2a6d73 AD |
219 | /* set the active encoder to connector routing */ |
220 | radeon_encoder_set_active_device(encoder); | |
771fe6b9 JG |
221 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
222 | ||
771fe6b9 JG |
223 | /* hw bug */ |
224 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) | |
225 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) | |
226 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; | |
227 | ||
80297e87 AD |
228 | /* get the native mode for LVDS */ |
229 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { | |
230 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; | |
231 | int mode_id = adjusted_mode->base.id; | |
232 | *adjusted_mode = *native_mode; | |
233 | if (!ASIC_IS_AVIVO(rdev)) { | |
234 | adjusted_mode->hdisplay = mode->hdisplay; | |
235 | adjusted_mode->vdisplay = mode->vdisplay; | |
236 | } | |
237 | adjusted_mode->base.id = mode_id; | |
238 | } | |
239 | ||
240 | /* get the native mode for TV */ | |
ceefedd8 | 241 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
5a9bcacc AD |
242 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
243 | if (tv_dac) { | |
244 | if (tv_dac->tv_std == TV_STD_NTSC || | |
245 | tv_dac->tv_std == TV_STD_NTSC_J || | |
246 | tv_dac->tv_std == TV_STD_PAL_M) | |
247 | radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); | |
248 | else | |
249 | radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); | |
250 | } | |
251 | } | |
252 | ||
771fe6b9 JG |
253 | return true; |
254 | } | |
255 | ||
256 | static void | |
257 | atombios_dac_setup(struct drm_encoder *encoder, int action) | |
258 | { | |
259 | struct drm_device *dev = encoder->dev; | |
260 | struct radeon_device *rdev = dev->dev_private; | |
261 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
262 | DAC_ENCODER_CONTROL_PS_ALLOCATION args; | |
263 | int index = 0, num = 0; | |
445282db | 264 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
771fe6b9 JG |
265 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
266 | ||
445282db DA |
267 | if (dac_info->tv_std) |
268 | tv_std = dac_info->tv_std; | |
269 | ||
771fe6b9 JG |
270 | memset(&args, 0, sizeof(args)); |
271 | ||
272 | switch (radeon_encoder->encoder_id) { | |
273 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
274 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
275 | index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); | |
276 | num = 1; | |
277 | break; | |
278 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
279 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
280 | index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); | |
281 | num = 2; | |
282 | break; | |
283 | } | |
284 | ||
285 | args.ucAction = action; | |
286 | ||
4ce001ab | 287 | if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) |
771fe6b9 | 288 | args.ucDacStandard = ATOM_DAC1_PS2; |
4ce001ab | 289 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
290 | args.ucDacStandard = ATOM_DAC1_CV; |
291 | else { | |
292 | switch (tv_std) { | |
293 | case TV_STD_PAL: | |
294 | case TV_STD_PAL_M: | |
295 | case TV_STD_SCART_PAL: | |
296 | case TV_STD_SECAM: | |
297 | case TV_STD_PAL_CN: | |
298 | args.ucDacStandard = ATOM_DAC1_PAL; | |
299 | break; | |
300 | case TV_STD_NTSC: | |
301 | case TV_STD_NTSC_J: | |
302 | case TV_STD_PAL_60: | |
303 | default: | |
304 | args.ucDacStandard = ATOM_DAC1_NTSC; | |
305 | break; | |
306 | } | |
307 | } | |
308 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
309 | ||
310 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
311 | ||
312 | } | |
313 | ||
314 | static void | |
315 | atombios_tv_setup(struct drm_encoder *encoder, int action) | |
316 | { | |
317 | struct drm_device *dev = encoder->dev; | |
318 | struct radeon_device *rdev = dev->dev_private; | |
319 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
320 | TV_ENCODER_CONTROL_PS_ALLOCATION args; | |
321 | int index = 0; | |
445282db | 322 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
771fe6b9 JG |
323 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
324 | ||
445282db DA |
325 | if (dac_info->tv_std) |
326 | tv_std = dac_info->tv_std; | |
327 | ||
771fe6b9 JG |
328 | memset(&args, 0, sizeof(args)); |
329 | ||
330 | index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); | |
331 | ||
332 | args.sTVEncoder.ucAction = action; | |
333 | ||
4ce001ab | 334 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
335 | args.sTVEncoder.ucTvStandard = ATOM_TV_CV; |
336 | else { | |
337 | switch (tv_std) { | |
338 | case TV_STD_NTSC: | |
339 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; | |
340 | break; | |
341 | case TV_STD_PAL: | |
342 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; | |
343 | break; | |
344 | case TV_STD_PAL_M: | |
345 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; | |
346 | break; | |
347 | case TV_STD_PAL_60: | |
348 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; | |
349 | break; | |
350 | case TV_STD_NTSC_J: | |
351 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; | |
352 | break; | |
353 | case TV_STD_SCART_PAL: | |
354 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ | |
355 | break; | |
356 | case TV_STD_SECAM: | |
357 | args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; | |
358 | break; | |
359 | case TV_STD_PAL_CN: | |
360 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; | |
361 | break; | |
362 | default: | |
363 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; | |
364 | break; | |
365 | } | |
366 | } | |
367 | ||
368 | args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
369 | ||
370 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
371 | ||
372 | } | |
373 | ||
374 | void | |
375 | atombios_external_tmds_setup(struct drm_encoder *encoder, int action) | |
376 | { | |
377 | struct drm_device *dev = encoder->dev; | |
378 | struct radeon_device *rdev = dev->dev_private; | |
379 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
380 | ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args; | |
381 | int index = 0; | |
382 | ||
383 | memset(&args, 0, sizeof(args)); | |
384 | ||
385 | index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); | |
386 | ||
387 | args.sXTmdsEncoder.ucEnable = action; | |
388 | ||
389 | if (radeon_encoder->pixel_clock > 165000) | |
390 | args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL; | |
391 | ||
392 | /*if (pScrn->rgbBits == 8)*/ | |
393 | args.sXTmdsEncoder.ucMisc |= (1 << 1); | |
394 | ||
395 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
396 | ||
397 | } | |
398 | ||
399 | static void | |
400 | atombios_ddia_setup(struct drm_encoder *encoder, int action) | |
401 | { | |
402 | struct drm_device *dev = encoder->dev; | |
403 | struct radeon_device *rdev = dev->dev_private; | |
404 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
405 | DVO_ENCODER_CONTROL_PS_ALLOCATION args; | |
406 | int index = 0; | |
407 | ||
408 | memset(&args, 0, sizeof(args)); | |
409 | ||
410 | index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); | |
411 | ||
412 | args.sDVOEncoder.ucAction = action; | |
413 | args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
414 | ||
415 | if (radeon_encoder->pixel_clock > 165000) | |
416 | args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL; | |
417 | ||
418 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
419 | ||
420 | } | |
421 | ||
422 | union lvds_encoder_control { | |
423 | LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; | |
424 | LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; | |
425 | }; | |
426 | ||
32f48ffe | 427 | void |
771fe6b9 JG |
428 | atombios_digital_setup(struct drm_encoder *encoder, int action) |
429 | { | |
430 | struct drm_device *dev = encoder->dev; | |
431 | struct radeon_device *rdev = dev->dev_private; | |
432 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
433 | union lvds_encoder_control args; | |
434 | int index = 0; | |
435 | uint8_t frev, crev; | |
436 | struct radeon_encoder_atom_dig *dig; | |
437 | struct drm_connector *connector; | |
438 | struct radeon_connector *radeon_connector; | |
439 | struct radeon_connector_atom_dig *dig_connector; | |
440 | ||
441 | connector = radeon_get_connector_for_encoder(encoder); | |
442 | if (!connector) | |
443 | return; | |
444 | ||
445 | radeon_connector = to_radeon_connector(connector); | |
446 | ||
447 | if (!radeon_encoder->enc_priv) | |
448 | return; | |
449 | ||
450 | dig = radeon_encoder->enc_priv; | |
451 | ||
452 | if (!radeon_connector->con_priv) | |
453 | return; | |
454 | ||
455 | dig_connector = radeon_connector->con_priv; | |
456 | ||
457 | memset(&args, 0, sizeof(args)); | |
458 | ||
459 | switch (radeon_encoder->encoder_id) { | |
460 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
461 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); | |
462 | break; | |
463 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
464 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
465 | index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); | |
466 | break; | |
467 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
468 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
469 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); | |
470 | else | |
471 | index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); | |
472 | break; | |
473 | } | |
474 | ||
475 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); | |
476 | ||
477 | switch (frev) { | |
478 | case 1: | |
479 | case 2: | |
480 | switch (crev) { | |
481 | case 1: | |
482 | args.v1.ucMisc = 0; | |
483 | args.v1.ucAction = action; | |
0294cf4f | 484 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
771fe6b9 JG |
485 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
486 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
487 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
488 | if (dig->lvds_misc & (1 << 0)) | |
489 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; | |
490 | if (dig->lvds_misc & (1 << 1)) | |
491 | args.v1.ucMisc |= (1 << 1); | |
492 | } else { | |
493 | if (dig_connector->linkb) | |
494 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; | |
495 | if (radeon_encoder->pixel_clock > 165000) | |
496 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; | |
497 | /*if (pScrn->rgbBits == 8) */ | |
498 | args.v1.ucMisc |= (1 << 1); | |
499 | } | |
500 | break; | |
501 | case 2: | |
502 | case 3: | |
503 | args.v2.ucMisc = 0; | |
504 | args.v2.ucAction = action; | |
505 | if (crev == 3) { | |
506 | if (dig->coherent_mode) | |
507 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; | |
508 | } | |
0294cf4f | 509 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
771fe6b9 JG |
510 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
511 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
512 | args.v2.ucTruncate = 0; | |
513 | args.v2.ucSpatial = 0; | |
514 | args.v2.ucTemporal = 0; | |
515 | args.v2.ucFRC = 0; | |
516 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
517 | if (dig->lvds_misc & (1 << 0)) | |
518 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; | |
519 | if (dig->lvds_misc & (1 << 5)) { | |
520 | args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; | |
521 | if (dig->lvds_misc & (1 << 1)) | |
522 | args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; | |
523 | } | |
524 | if (dig->lvds_misc & (1 << 6)) { | |
525 | args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; | |
526 | if (dig->lvds_misc & (1 << 1)) | |
527 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; | |
528 | if (((dig->lvds_misc >> 2) & 0x3) == 2) | |
529 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; | |
530 | } | |
531 | } else { | |
532 | if (dig_connector->linkb) | |
533 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; | |
534 | if (radeon_encoder->pixel_clock > 165000) | |
535 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; | |
536 | } | |
537 | break; | |
538 | default: | |
539 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
540 | break; | |
541 | } | |
542 | break; | |
543 | default: | |
544 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
545 | break; | |
546 | } | |
547 | ||
548 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
549 | ||
550 | } | |
551 | ||
552 | int | |
553 | atombios_get_encoder_mode(struct drm_encoder *encoder) | |
554 | { | |
555 | struct drm_connector *connector; | |
556 | struct radeon_connector *radeon_connector; | |
f92a8b67 | 557 | struct radeon_connector_atom_dig *radeon_dig_connector; |
771fe6b9 JG |
558 | |
559 | connector = radeon_get_connector_for_encoder(encoder); | |
560 | if (!connector) | |
561 | return 0; | |
562 | ||
563 | radeon_connector = to_radeon_connector(connector); | |
564 | ||
565 | switch (connector->connector_type) { | |
566 | case DRM_MODE_CONNECTOR_DVII: | |
705af9c7 | 567 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
0294cf4f | 568 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
771fe6b9 JG |
569 | return ATOM_ENCODER_MODE_HDMI; |
570 | else if (radeon_connector->use_digital) | |
571 | return ATOM_ENCODER_MODE_DVI; | |
572 | else | |
573 | return ATOM_ENCODER_MODE_CRT; | |
574 | break; | |
575 | case DRM_MODE_CONNECTOR_DVID: | |
576 | case DRM_MODE_CONNECTOR_HDMIA: | |
771fe6b9 | 577 | default: |
0294cf4f | 578 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
771fe6b9 JG |
579 | return ATOM_ENCODER_MODE_HDMI; |
580 | else | |
581 | return ATOM_ENCODER_MODE_DVI; | |
582 | break; | |
583 | case DRM_MODE_CONNECTOR_LVDS: | |
584 | return ATOM_ENCODER_MODE_LVDS; | |
585 | break; | |
586 | case DRM_MODE_CONNECTOR_DisplayPort: | |
f92a8b67 AD |
587 | radeon_dig_connector = radeon_connector->con_priv; |
588 | if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) | |
589 | return ATOM_ENCODER_MODE_DP; | |
590 | else if (drm_detect_hdmi_monitor(radeon_connector->edid)) | |
771fe6b9 JG |
591 | return ATOM_ENCODER_MODE_HDMI; |
592 | else | |
593 | return ATOM_ENCODER_MODE_DVI; | |
594 | break; | |
595 | case CONNECTOR_DVI_A: | |
596 | case CONNECTOR_VGA: | |
597 | return ATOM_ENCODER_MODE_CRT; | |
598 | break; | |
599 | case CONNECTOR_STV: | |
600 | case CONNECTOR_CTV: | |
601 | case CONNECTOR_DIN: | |
602 | /* fix me */ | |
603 | return ATOM_ENCODER_MODE_TV; | |
604 | /*return ATOM_ENCODER_MODE_CV;*/ | |
605 | break; | |
606 | } | |
607 | } | |
608 | ||
1a66c95a AD |
609 | /* |
610 | * DIG Encoder/Transmitter Setup | |
611 | * | |
612 | * DCE 3.0/3.1 | |
613 | * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. | |
614 | * Supports up to 3 digital outputs | |
615 | * - 2 DIG encoder blocks. | |
616 | * DIG1 can drive UNIPHY link A or link B | |
617 | * DIG2 can drive UNIPHY link B or LVTMA | |
618 | * | |
619 | * DCE 3.2 | |
620 | * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). | |
621 | * Supports up to 5 digital outputs | |
622 | * - 2 DIG encoder blocks. | |
623 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B | |
624 | * | |
625 | * Routing | |
626 | * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) | |
627 | * Examples: | |
628 | * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI | |
629 | * crtc1 -> dig1 -> UNIPHY0 link B -> DP | |
630 | * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS | |
631 | * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI | |
632 | */ | |
771fe6b9 JG |
633 | static void |
634 | atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) | |
635 | { | |
636 | struct drm_device *dev = encoder->dev; | |
637 | struct radeon_device *rdev = dev->dev_private; | |
638 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
639 | DIG_ENCODER_CONTROL_PS_ALLOCATION args; | |
640 | int index = 0, num = 0; | |
641 | uint8_t frev, crev; | |
642 | struct radeon_encoder_atom_dig *dig; | |
643 | struct drm_connector *connector; | |
644 | struct radeon_connector *radeon_connector; | |
645 | struct radeon_connector_atom_dig *dig_connector; | |
646 | ||
647 | connector = radeon_get_connector_for_encoder(encoder); | |
648 | if (!connector) | |
649 | return; | |
650 | ||
651 | radeon_connector = to_radeon_connector(connector); | |
652 | ||
653 | if (!radeon_connector->con_priv) | |
654 | return; | |
655 | ||
656 | dig_connector = radeon_connector->con_priv; | |
657 | ||
658 | if (!radeon_encoder->enc_priv) | |
659 | return; | |
660 | ||
661 | dig = radeon_encoder->enc_priv; | |
662 | ||
663 | memset(&args, 0, sizeof(args)); | |
664 | ||
665 | if (ASIC_IS_DCE32(rdev)) { | |
666 | if (dig->dig_block) | |
667 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); | |
668 | else | |
669 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); | |
670 | num = dig->dig_block + 1; | |
671 | } else { | |
672 | switch (radeon_encoder->encoder_id) { | |
673 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1a66c95a AD |
674 | /* XXX doesn't really matter which dig encoder we pick as long as it's |
675 | * not already in use | |
676 | */ | |
677 | if (dig_connector->linkb) | |
678 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); | |
679 | else | |
680 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); | |
771fe6b9 JG |
681 | num = 1; |
682 | break; | |
683 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
1a66c95a | 684 | /* Only dig2 encoder can drive LVTMA */ |
771fe6b9 JG |
685 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); |
686 | num = 2; | |
687 | break; | |
688 | } | |
689 | } | |
690 | ||
691 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); | |
692 | ||
693 | args.ucAction = action; | |
694 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
695 | ||
696 | if (ASIC_IS_DCE32(rdev)) { | |
697 | switch (radeon_encoder->encoder_id) { | |
698 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
699 | args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; | |
700 | break; | |
701 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
702 | args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; | |
703 | break; | |
704 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
705 | args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; | |
706 | break; | |
707 | } | |
708 | } else { | |
709 | switch (radeon_encoder->encoder_id) { | |
710 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
711 | args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1; | |
712 | break; | |
713 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
714 | args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2; | |
715 | break; | |
716 | } | |
717 | } | |
718 | ||
f92a8b67 AD |
719 | args.ucEncoderMode = atombios_get_encoder_mode(encoder); |
720 | ||
721 | if (args.ucEncoderMode == ATOM_ENCODER_MODE_DP) { | |
722 | if (dp_link_clock_for_mode_clock(dig_connector->dpcd[1], | |
723 | radeon_encoder->pixel_clock) == 270000) | |
724 | args.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; | |
725 | args.ucLaneNum = dp_lanes_for_mode_clock(dig_connector->dpcd[1], | |
726 | radeon_encoder->pixel_clock); | |
727 | } else if (radeon_encoder->pixel_clock > 165000) | |
771fe6b9 | 728 | args.ucLaneNum = 8; |
1a66c95a | 729 | else |
771fe6b9 | 730 | args.ucLaneNum = 4; |
1a66c95a AD |
731 | |
732 | if (dig_connector->linkb) | |
733 | args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; | |
734 | else | |
735 | args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; | |
771fe6b9 | 736 | |
771fe6b9 JG |
737 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
738 | ||
739 | } | |
740 | ||
741 | union dig_transmitter_control { | |
742 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; | |
743 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; | |
744 | }; | |
745 | ||
746 | static void | |
1a66c95a | 747 | atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) |
771fe6b9 JG |
748 | { |
749 | struct drm_device *dev = encoder->dev; | |
750 | struct radeon_device *rdev = dev->dev_private; | |
751 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
752 | union dig_transmitter_control args; | |
753 | int index = 0, num = 0; | |
754 | uint8_t frev, crev; | |
755 | struct radeon_encoder_atom_dig *dig; | |
756 | struct drm_connector *connector; | |
757 | struct radeon_connector *radeon_connector; | |
758 | struct radeon_connector_atom_dig *dig_connector; | |
f92a8b67 | 759 | bool is_dp = false; |
771fe6b9 JG |
760 | |
761 | connector = radeon_get_connector_for_encoder(encoder); | |
762 | if (!connector) | |
763 | return; | |
764 | ||
765 | radeon_connector = to_radeon_connector(connector); | |
766 | ||
767 | if (!radeon_encoder->enc_priv) | |
768 | return; | |
769 | ||
770 | dig = radeon_encoder->enc_priv; | |
771 | ||
772 | if (!radeon_connector->con_priv) | |
773 | return; | |
774 | ||
775 | dig_connector = radeon_connector->con_priv; | |
776 | ||
f92a8b67 AD |
777 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) |
778 | is_dp = true; | |
779 | ||
771fe6b9 JG |
780 | memset(&args, 0, sizeof(args)); |
781 | ||
782 | if (ASIC_IS_DCE32(rdev)) | |
783 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); | |
784 | else { | |
785 | switch (radeon_encoder->encoder_id) { | |
786 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
787 | index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); | |
788 | break; | |
789 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
790 | index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); | |
791 | break; | |
792 | } | |
793 | } | |
794 | ||
795 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); | |
796 | ||
797 | args.v1.ucAction = action; | |
f95a9f0b AD |
798 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
799 | args.v1.usInitInfo = radeon_connector->connector_object_id; | |
1a66c95a AD |
800 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
801 | args.v1.asMode.ucLaneSel = lane_num; | |
802 | args.v1.asMode.ucLaneSet = lane_set; | |
f95a9f0b | 803 | } else { |
f92a8b67 AD |
804 | if (is_dp) |
805 | args.v1.usPixelClock = | |
806 | cpu_to_le16(dp_link_clock_for_mode_clock(dig_connector->dpcd[1], | |
807 | radeon_encoder->pixel_clock) / 10); | |
808 | else if (radeon_encoder->pixel_clock > 165000) | |
f95a9f0b AD |
809 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
810 | else | |
811 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
812 | } | |
771fe6b9 | 813 | if (ASIC_IS_DCE32(rdev)) { |
771fe6b9 JG |
814 | if (dig->dig_block) |
815 | args.v2.acConfig.ucEncoderSel = 1; | |
1a66c95a AD |
816 | if (dig_connector->linkb) |
817 | args.v2.acConfig.ucLinkSel = 1; | |
771fe6b9 JG |
818 | |
819 | switch (radeon_encoder->encoder_id) { | |
820 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
821 | args.v2.acConfig.ucTransmitterSel = 0; | |
822 | num = 0; | |
823 | break; | |
824 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
825 | args.v2.acConfig.ucTransmitterSel = 1; | |
826 | num = 1; | |
827 | break; | |
828 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
829 | args.v2.acConfig.ucTransmitterSel = 2; | |
830 | num = 2; | |
831 | break; | |
832 | } | |
833 | ||
f92a8b67 AD |
834 | if (is_dp) |
835 | args.v2.acConfig.fCoherentMode = 1; | |
836 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
771fe6b9 JG |
837 | if (dig->coherent_mode) |
838 | args.v2.acConfig.fCoherentMode = 1; | |
839 | } | |
840 | } else { | |
841 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; | |
771fe6b9 JG |
842 | |
843 | switch (radeon_encoder->encoder_id) { | |
844 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1a66c95a AD |
845 | /* XXX doesn't really matter which dig encoder we pick as long as it's |
846 | * not already in use | |
847 | */ | |
848 | if (dig_connector->linkb) | |
849 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; | |
850 | else | |
851 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; | |
771fe6b9 JG |
852 | if (rdev->flags & RADEON_IS_IGP) { |
853 | if (radeon_encoder->pixel_clock > 165000) { | |
771fe6b9 JG |
854 | if (dig_connector->igp_lane_info & 0x3) |
855 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; | |
856 | else if (dig_connector->igp_lane_info & 0xc) | |
857 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; | |
858 | } else { | |
771fe6b9 JG |
859 | if (dig_connector->igp_lane_info & 0x1) |
860 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; | |
861 | else if (dig_connector->igp_lane_info & 0x2) | |
862 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; | |
863 | else if (dig_connector->igp_lane_info & 0x4) | |
864 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; | |
865 | else if (dig_connector->igp_lane_info & 0x8) | |
866 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; | |
867 | } | |
771fe6b9 JG |
868 | } |
869 | break; | |
870 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
1a66c95a | 871 | /* Only dig2 encoder can drive LVTMA */ |
771fe6b9 | 872 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; |
771fe6b9 JG |
873 | break; |
874 | } | |
875 | ||
1a66c95a AD |
876 | if (radeon_encoder->pixel_clock > 165000) |
877 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; | |
878 | ||
879 | if (dig_connector->linkb) | |
880 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; | |
881 | else | |
882 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; | |
883 | ||
f92a8b67 AD |
884 | if (is_dp) |
885 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; | |
886 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
771fe6b9 JG |
887 | if (dig->coherent_mode) |
888 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; | |
889 | } | |
890 | } | |
891 | ||
892 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
893 | ||
894 | } | |
895 | ||
771fe6b9 JG |
896 | static void |
897 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) | |
898 | { | |
899 | struct drm_device *dev = encoder->dev; | |
900 | struct radeon_device *rdev = dev->dev_private; | |
901 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
902 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
903 | ENABLE_YUV_PS_ALLOCATION args; | |
904 | int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); | |
905 | uint32_t temp, reg; | |
906 | ||
907 | memset(&args, 0, sizeof(args)); | |
908 | ||
909 | if (rdev->family >= CHIP_R600) | |
910 | reg = R600_BIOS_3_SCRATCH; | |
911 | else | |
912 | reg = RADEON_BIOS_3_SCRATCH; | |
913 | ||
914 | /* XXX: fix up scratch reg handling */ | |
915 | temp = RREG32(reg); | |
4ce001ab | 916 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 JG |
917 | WREG32(reg, (ATOM_S3_TV1_ACTIVE | |
918 | (radeon_crtc->crtc_id << 18))); | |
4ce001ab | 919 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
920 | WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); |
921 | else | |
922 | WREG32(reg, 0); | |
923 | ||
924 | if (enable) | |
925 | args.ucEnable = ATOM_ENABLE; | |
926 | args.ucCRTC = radeon_crtc->crtc_id; | |
927 | ||
928 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
929 | ||
930 | WREG32(reg, temp); | |
931 | } | |
932 | ||
771fe6b9 JG |
933 | static void |
934 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) | |
935 | { | |
936 | struct drm_device *dev = encoder->dev; | |
937 | struct radeon_device *rdev = dev->dev_private; | |
938 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
939 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; | |
940 | int index = 0; | |
941 | bool is_dig = false; | |
942 | ||
943 | memset(&args, 0, sizeof(args)); | |
944 | ||
f641e51e DA |
945 | DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
946 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, | |
947 | radeon_encoder->active_device); | |
771fe6b9 JG |
948 | switch (radeon_encoder->encoder_id) { |
949 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
950 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
951 | index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); | |
952 | break; | |
953 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
954 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
955 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
956 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
957 | is_dig = true; | |
958 | break; | |
959 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
960 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
961 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
962 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); | |
963 | break; | |
964 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
965 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); | |
966 | break; | |
967 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
968 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
969 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); | |
970 | else | |
971 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); | |
972 | break; | |
973 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
974 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
8c2a6d73 | 975 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 976 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
8c2a6d73 | 977 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
978 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
979 | else | |
980 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); | |
981 | break; | |
982 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
983 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
8c2a6d73 | 984 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 985 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
8c2a6d73 | 986 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
987 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
988 | else | |
989 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); | |
990 | break; | |
991 | } | |
992 | ||
993 | if (is_dig) { | |
994 | switch (mode) { | |
995 | case DRM_MODE_DPMS_ON: | |
50dafba6 | 996 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT); |
771fe6b9 JG |
997 | break; |
998 | case DRM_MODE_DPMS_STANDBY: | |
999 | case DRM_MODE_DPMS_SUSPEND: | |
1000 | case DRM_MODE_DPMS_OFF: | |
50dafba6 | 1001 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT); |
771fe6b9 JG |
1002 | break; |
1003 | } | |
1004 | } else { | |
1005 | switch (mode) { | |
1006 | case DRM_MODE_DPMS_ON: | |
1007 | args.ucAction = ATOM_ENABLE; | |
1008 | break; | |
1009 | case DRM_MODE_DPMS_STANDBY: | |
1010 | case DRM_MODE_DPMS_SUSPEND: | |
1011 | case DRM_MODE_DPMS_OFF: | |
1012 | args.ucAction = ATOM_DISABLE; | |
1013 | break; | |
1014 | } | |
1015 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1016 | } | |
1017 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); | |
1018 | } | |
1019 | ||
1020 | union crtc_sourc_param { | |
1021 | SELECT_CRTC_SOURCE_PS_ALLOCATION v1; | |
1022 | SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; | |
1023 | }; | |
1024 | ||
1025 | static void | |
1026 | atombios_set_encoder_crtc_source(struct drm_encoder *encoder) | |
1027 | { | |
1028 | struct drm_device *dev = encoder->dev; | |
1029 | struct radeon_device *rdev = dev->dev_private; | |
1030 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1031 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
1032 | union crtc_sourc_param args; | |
1033 | int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); | |
1034 | uint8_t frev, crev; | |
1035 | ||
1036 | memset(&args, 0, sizeof(args)); | |
1037 | ||
1038 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); | |
1039 | ||
1040 | switch (frev) { | |
1041 | case 1: | |
1042 | switch (crev) { | |
1043 | case 1: | |
1044 | default: | |
1045 | if (ASIC_IS_AVIVO(rdev)) | |
1046 | args.v1.ucCRTC = radeon_crtc->crtc_id; | |
1047 | else { | |
1048 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { | |
1049 | args.v1.ucCRTC = radeon_crtc->crtc_id; | |
1050 | } else { | |
1051 | args.v1.ucCRTC = radeon_crtc->crtc_id << 2; | |
1052 | } | |
1053 | } | |
1054 | switch (radeon_encoder->encoder_id) { | |
1055 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1056 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1057 | args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; | |
1058 | break; | |
1059 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1060 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1061 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) | |
1062 | args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; | |
1063 | else | |
1064 | args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; | |
1065 | break; | |
1066 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1067 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1068 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1069 | args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; | |
1070 | break; | |
1071 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1072 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
4ce001ab | 1073 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1074 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
4ce001ab | 1075 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1076 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1077 | else | |
1078 | args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; | |
1079 | break; | |
1080 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1081 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
4ce001ab | 1082 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1083 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
4ce001ab | 1084 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1085 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1086 | else | |
1087 | args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; | |
1088 | break; | |
1089 | } | |
1090 | break; | |
1091 | case 2: | |
1092 | args.v2.ucCRTC = radeon_crtc->crtc_id; | |
1093 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); | |
1094 | switch (radeon_encoder->encoder_id) { | |
1095 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1096 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1097 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1098 | if (ASIC_IS_DCE32(rdev)) { | |
1099 | if (radeon_crtc->crtc_id) | |
1100 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; | |
1101 | else | |
1102 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; | |
1a66c95a AD |
1103 | } else { |
1104 | struct drm_connector *connector; | |
1105 | struct radeon_connector *radeon_connector; | |
1106 | struct radeon_connector_atom_dig *dig_connector; | |
1107 | ||
1108 | connector = radeon_get_connector_for_encoder(encoder); | |
1109 | if (!connector) | |
1110 | return; | |
1111 | radeon_connector = to_radeon_connector(connector); | |
1112 | if (!radeon_connector->con_priv) | |
1113 | return; | |
1114 | dig_connector = radeon_connector->con_priv; | |
1115 | ||
1116 | /* XXX doesn't really matter which dig encoder we pick as long as it's | |
1117 | * not already in use | |
1118 | */ | |
1119 | if (dig_connector->linkb) | |
1120 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; | |
1121 | else | |
1122 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; | |
1123 | } | |
771fe6b9 JG |
1124 | break; |
1125 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1126 | args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; | |
1127 | break; | |
1128 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
1a66c95a | 1129 | /* Only dig2 encoder can drive LVTMA */ |
771fe6b9 JG |
1130 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; |
1131 | break; | |
1132 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
4ce001ab | 1133 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1134 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
4ce001ab | 1135 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1136 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1137 | else | |
1138 | args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; | |
1139 | break; | |
1140 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
4ce001ab | 1141 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1142 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
4ce001ab | 1143 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1144 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1145 | else | |
1146 | args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; | |
1147 | break; | |
1148 | } | |
1149 | break; | |
1150 | } | |
1151 | break; | |
1152 | default: | |
1153 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); | |
1154 | break; | |
1155 | } | |
1156 | ||
1157 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1158 | ||
1159 | } | |
1160 | ||
1161 | static void | |
1162 | atombios_apply_encoder_quirks(struct drm_encoder *encoder, | |
1163 | struct drm_display_mode *mode) | |
1164 | { | |
1165 | struct drm_device *dev = encoder->dev; | |
1166 | struct radeon_device *rdev = dev->dev_private; | |
1167 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1168 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
1169 | ||
1170 | /* Funky macbooks */ | |
1171 | if ((dev->pdev->device == 0x71C5) && | |
1172 | (dev->pdev->subsystem_vendor == 0x106b) && | |
1173 | (dev->pdev->subsystem_device == 0x0080)) { | |
1174 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { | |
1175 | uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); | |
1176 | ||
1177 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; | |
1178 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; | |
1179 | ||
1180 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); | |
1181 | } | |
1182 | } | |
1183 | ||
1184 | /* set scaler clears this on some chips */ | |
ceefedd8 AD |
1185 | if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) { |
1186 | if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) | |
1187 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, | |
1188 | AVIVO_D1MODE_INTERLEAVE_EN); | |
1189 | } | |
771fe6b9 JG |
1190 | } |
1191 | ||
1192 | static void | |
1193 | radeon_atom_encoder_mode_set(struct drm_encoder *encoder, | |
1194 | struct drm_display_mode *mode, | |
1195 | struct drm_display_mode *adjusted_mode) | |
1196 | { | |
1197 | struct drm_device *dev = encoder->dev; | |
1198 | struct radeon_device *rdev = dev->dev_private; | |
1199 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1200 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
1201 | ||
1202 | if (radeon_encoder->enc_priv) { | |
1203 | struct radeon_encoder_atom_dig *dig; | |
1204 | ||
1205 | dig = radeon_encoder->enc_priv; | |
1206 | dig->dig_block = radeon_crtc->crtc_id; | |
1207 | } | |
1208 | radeon_encoder->pixel_clock = adjusted_mode->clock; | |
1209 | ||
1210 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); | |
771fe6b9 JG |
1211 | atombios_set_encoder_crtc_source(encoder); |
1212 | ||
1213 | if (ASIC_IS_AVIVO(rdev)) { | |
4ce001ab | 1214 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 JG |
1215 | atombios_yuv_setup(encoder, true); |
1216 | else | |
1217 | atombios_yuv_setup(encoder, false); | |
1218 | } | |
1219 | ||
1220 | switch (radeon_encoder->encoder_id) { | |
1221 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1222 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1223 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1224 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1225 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); | |
1226 | break; | |
1227 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1228 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1229 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1230 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
1231 | /* disable the encoder and transmitter */ | |
1a66c95a | 1232 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
771fe6b9 JG |
1233 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE); |
1234 | ||
1235 | /* setup and enable the encoder and transmitter */ | |
1236 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE); | |
1a66c95a AD |
1237 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); |
1238 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); | |
1239 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); | |
771fe6b9 JG |
1240 | break; |
1241 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1242 | atombios_ddia_setup(encoder, ATOM_ENABLE); | |
1243 | break; | |
1244 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1245 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1246 | atombios_external_tmds_setup(encoder, ATOM_ENABLE); | |
1247 | break; | |
1248 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1249 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
1250 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1251 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
1252 | atombios_dac_setup(encoder, ATOM_ENABLE); | |
4ce001ab | 1253 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1254 | atombios_tv_setup(encoder, ATOM_ENABLE); |
1255 | break; | |
1256 | } | |
1257 | atombios_apply_encoder_quirks(encoder, adjusted_mode); | |
1258 | } | |
1259 | ||
1260 | static bool | |
4ce001ab | 1261 | atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
771fe6b9 JG |
1262 | { |
1263 | struct drm_device *dev = encoder->dev; | |
1264 | struct radeon_device *rdev = dev->dev_private; | |
1265 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
4ce001ab | 1266 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
771fe6b9 JG |
1267 | |
1268 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | | |
1269 | ATOM_DEVICE_CV_SUPPORT | | |
1270 | ATOM_DEVICE_CRT_SUPPORT)) { | |
1271 | DAC_LOAD_DETECTION_PS_ALLOCATION args; | |
1272 | int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); | |
1273 | uint8_t frev, crev; | |
1274 | ||
1275 | memset(&args, 0, sizeof(args)); | |
1276 | ||
1277 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); | |
1278 | ||
1279 | args.sDacload.ucMisc = 0; | |
1280 | ||
1281 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || | |
1282 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) | |
1283 | args.sDacload.ucDacType = ATOM_DAC_A; | |
1284 | else | |
1285 | args.sDacload.ucDacType = ATOM_DAC_B; | |
1286 | ||
4ce001ab | 1287 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) |
771fe6b9 | 1288 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); |
4ce001ab | 1289 | else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) |
771fe6b9 | 1290 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); |
4ce001ab | 1291 | else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
771fe6b9 JG |
1292 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); |
1293 | if (crev >= 3) | |
1294 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; | |
4ce001ab | 1295 | } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
771fe6b9 JG |
1296 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); |
1297 | if (crev >= 3) | |
1298 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; | |
1299 | } | |
1300 | ||
1301 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1302 | ||
1303 | return true; | |
1304 | } else | |
1305 | return false; | |
1306 | } | |
1307 | ||
1308 | static enum drm_connector_status | |
1309 | radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) | |
1310 | { | |
1311 | struct drm_device *dev = encoder->dev; | |
1312 | struct radeon_device *rdev = dev->dev_private; | |
1313 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
4ce001ab | 1314 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
771fe6b9 JG |
1315 | uint32_t bios_0_scratch; |
1316 | ||
4ce001ab | 1317 | if (!atombios_dac_load_detect(encoder, connector)) { |
771fe6b9 JG |
1318 | DRM_DEBUG("detect returned false \n"); |
1319 | return connector_status_unknown; | |
1320 | } | |
1321 | ||
1322 | if (rdev->family >= CHIP_R600) | |
1323 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); | |
1324 | else | |
1325 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); | |
1326 | ||
4ce001ab DA |
1327 | DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); |
1328 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { | |
771fe6b9 JG |
1329 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
1330 | return connector_status_connected; | |
4ce001ab DA |
1331 | } |
1332 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { | |
771fe6b9 JG |
1333 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
1334 | return connector_status_connected; | |
4ce001ab DA |
1335 | } |
1336 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { | |
771fe6b9 JG |
1337 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
1338 | return connector_status_connected; | |
4ce001ab DA |
1339 | } |
1340 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { | |
771fe6b9 JG |
1341 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
1342 | return connector_status_connected; /* CTV */ | |
1343 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) | |
1344 | return connector_status_connected; /* STV */ | |
1345 | } | |
1346 | return connector_status_disconnected; | |
1347 | } | |
1348 | ||
1349 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) | |
1350 | { | |
1351 | radeon_atom_output_lock(encoder, true); | |
1352 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); | |
1353 | } | |
1354 | ||
1355 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) | |
1356 | { | |
1357 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); | |
1358 | radeon_atom_output_lock(encoder, false); | |
1359 | } | |
1360 | ||
4ce001ab DA |
1361 | static void radeon_atom_encoder_disable(struct drm_encoder *encoder) |
1362 | { | |
1363 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1364 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); | |
4ce001ab DA |
1365 | radeon_encoder->active_device = 0; |
1366 | } | |
1367 | ||
771fe6b9 JG |
1368 | static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { |
1369 | .dpms = radeon_atom_encoder_dpms, | |
1370 | .mode_fixup = radeon_atom_mode_fixup, | |
1371 | .prepare = radeon_atom_encoder_prepare, | |
1372 | .mode_set = radeon_atom_encoder_mode_set, | |
1373 | .commit = radeon_atom_encoder_commit, | |
4ce001ab | 1374 | .disable = radeon_atom_encoder_disable, |
771fe6b9 JG |
1375 | /* no detect for TMDS/LVDS yet */ |
1376 | }; | |
1377 | ||
1378 | static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { | |
1379 | .dpms = radeon_atom_encoder_dpms, | |
1380 | .mode_fixup = radeon_atom_mode_fixup, | |
1381 | .prepare = radeon_atom_encoder_prepare, | |
1382 | .mode_set = radeon_atom_encoder_mode_set, | |
1383 | .commit = radeon_atom_encoder_commit, | |
1384 | .detect = radeon_atom_dac_detect, | |
1385 | }; | |
1386 | ||
1387 | void radeon_enc_destroy(struct drm_encoder *encoder) | |
1388 | { | |
1389 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1390 | kfree(radeon_encoder->enc_priv); | |
1391 | drm_encoder_cleanup(encoder); | |
1392 | kfree(radeon_encoder); | |
1393 | } | |
1394 | ||
1395 | static const struct drm_encoder_funcs radeon_atom_enc_funcs = { | |
1396 | .destroy = radeon_enc_destroy, | |
1397 | }; | |
1398 | ||
4ce001ab DA |
1399 | struct radeon_encoder_atom_dac * |
1400 | radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) | |
1401 | { | |
1402 | struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); | |
1403 | ||
1404 | if (!dac) | |
1405 | return NULL; | |
1406 | ||
1407 | dac->tv_std = TV_STD_NTSC; | |
1408 | return dac; | |
1409 | } | |
1410 | ||
771fe6b9 JG |
1411 | struct radeon_encoder_atom_dig * |
1412 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) | |
1413 | { | |
1414 | struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); | |
1415 | ||
1416 | if (!dig) | |
1417 | return NULL; | |
1418 | ||
1419 | /* coherent mode by default */ | |
1420 | dig->coherent_mode = true; | |
1421 | ||
1422 | return dig; | |
1423 | } | |
1424 | ||
1425 | void | |
1426 | radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) | |
1427 | { | |
dfee5614 | 1428 | struct radeon_device *rdev = dev->dev_private; |
771fe6b9 JG |
1429 | struct drm_encoder *encoder; |
1430 | struct radeon_encoder *radeon_encoder; | |
1431 | ||
1432 | /* see if we already added it */ | |
1433 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1434 | radeon_encoder = to_radeon_encoder(encoder); | |
1435 | if (radeon_encoder->encoder_id == encoder_id) { | |
1436 | radeon_encoder->devices |= supported_device; | |
1437 | return; | |
1438 | } | |
1439 | ||
1440 | } | |
1441 | ||
1442 | /* add a new one */ | |
1443 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); | |
1444 | if (!radeon_encoder) | |
1445 | return; | |
1446 | ||
1447 | encoder = &radeon_encoder->base; | |
dfee5614 DA |
1448 | if (rdev->flags & RADEON_SINGLE_CRTC) |
1449 | encoder->possible_crtcs = 0x1; | |
1450 | else | |
1451 | encoder->possible_crtcs = 0x3; | |
771fe6b9 JG |
1452 | |
1453 | radeon_encoder->enc_priv = NULL; | |
1454 | ||
1455 | radeon_encoder->encoder_id = encoder_id; | |
1456 | radeon_encoder->devices = supported_device; | |
c93bb85b | 1457 | radeon_encoder->rmx_type = RMX_OFF; |
771fe6b9 JG |
1458 | |
1459 | switch (radeon_encoder->encoder_id) { | |
1460 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1461 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1462 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1463 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1464 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
1465 | radeon_encoder->rmx_type = RMX_FULL; | |
1466 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); | |
1467 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); | |
1468 | } else { | |
1469 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); | |
1470 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); | |
1471 | } | |
1472 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); | |
1473 | break; | |
1474 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1475 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); | |
1476 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); | |
1477 | break; | |
1478 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1479 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
1480 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
1481 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); | |
4ce001ab | 1482 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
771fe6b9 JG |
1483 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
1484 | break; | |
1485 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1486 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1487 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1488 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1489 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
1490 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1491 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
60d15f55 AD |
1492 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1493 | radeon_encoder->rmx_type = RMX_FULL; | |
1494 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); | |
1495 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); | |
1496 | } else { | |
1497 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); | |
1498 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); | |
1499 | } | |
771fe6b9 JG |
1500 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
1501 | break; | |
1502 | } | |
1503 | } |