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drm/radeon/kms: properly handle mode id with native mode changes
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / radeon_encoders.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "drm_crtc_helper.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32extern int atom_debug;
33
5a9bcacc
AD		 34/* evil but including atombios.h is much worse */
35bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
771fe6b9
JG		 38uint32_t
39radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
40{
41 struct radeon_device *rdev = dev->dev_private;
42 uint32_t ret = 0;
43
44 switch (supported_device) {
45 case ATOM_DEVICE_CRT1_SUPPORT:
46 case ATOM_DEVICE_TV1_SUPPORT:
47 case ATOM_DEVICE_TV2_SUPPORT:
48 case ATOM_DEVICE_CRT2_SUPPORT:
49 case ATOM_DEVICE_CV_SUPPORT:
50 switch (dac) {
51 case 1: /* dac a */
52 if ((rdev->family == CHIP_RS300) ||
53 (rdev->family == CHIP_RS400) ||
54 (rdev->family == CHIP_RS480))
55 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
56 else if (ASIC_IS_AVIVO(rdev))
57 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
58 else
59 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
60 break;
61 case 2: /* dac b */
62 if (ASIC_IS_AVIVO(rdev))
63 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
64 else {
65 /*if (rdev->family == CHIP_R200)
66 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
67 else*/
68 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
69 }
70 break;
71 case 3: /* external dac */
72 if (ASIC_IS_AVIVO(rdev))
73 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
74 else
75 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
76 break;
77 }
78 break;
79 case ATOM_DEVICE_LCD1_SUPPORT:
80 if (ASIC_IS_AVIVO(rdev))
81 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
82 else
83 ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
84 break;
85 case ATOM_DEVICE_DFP1_SUPPORT:
86 if ((rdev->family == CHIP_RS300) ||
87 (rdev->family == CHIP_RS400) ||
88 (rdev->family == CHIP_RS480))
89 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
90 else if (ASIC_IS_AVIVO(rdev))
91 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
92 else
93 ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
94 break;
95 case ATOM_DEVICE_LCD2_SUPPORT:
96 case ATOM_DEVICE_DFP2_SUPPORT:
97 if ((rdev->family == CHIP_RS600) ||
98 (rdev->family == CHIP_RS690) ||
99 (rdev->family == CHIP_RS740))
100 ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
103 else
104 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
105 break;
106 case ATOM_DEVICE_DFP3_SUPPORT:
107 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
108 break;
109 }
110
111 return ret;
112}
113
114void
115radeon_link_encoder_connector(struct drm_device *dev)
116{
117 struct drm_connector *connector;
118 struct radeon_connector *radeon_connector;
119 struct drm_encoder *encoder;
120 struct radeon_encoder *radeon_encoder;
121
122 /* walk the list and link encoders to connectors */
123 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
124 radeon_connector = to_radeon_connector(connector);
125 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
126 radeon_encoder = to_radeon_encoder(encoder);
127 if (radeon_encoder->devices & radeon_connector->devices)
128 drm_mode_connector_attach_encoder(connector, encoder);
129 }
130 }
131}
132
4ce001ab
DA		 133void radeon_encoder_set_active_device(struct drm_encoder *encoder)
134{
135 struct drm_device *dev = encoder->dev;
136 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
137 struct drm_connector *connector;
138
139 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
140 if (connector->encoder == encoder) {
141 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
142 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
f641e51e
DA		 143 DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
144 radeon_encoder->active_device, radeon_encoder->devices,
145 radeon_connector->devices, encoder->encoder_type);
4ce001ab
DA		 146 }
147 }
148}
149
771fe6b9
JG		 150static struct drm_connector *
151radeon_get_connector_for_encoder(struct drm_encoder *encoder)
152{
153 struct drm_device *dev = encoder->dev;
154 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
155 struct drm_connector *connector;
156 struct radeon_connector *radeon_connector;
157
158 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
159 radeon_connector = to_radeon_connector(connector);
160 if (radeon_encoder->devices & radeon_connector->devices)
161 return connector;
162 }
163 return NULL;
164}
165
166/* used for both atom and legacy */
167void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
168 struct drm_display_mode *mode,
169 struct drm_display_mode *adjusted_mode)
170{
171 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
172 struct drm_device *dev = encoder->dev;
173 struct radeon_device *rdev = dev->dev_private;
de2103e4 174 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
771fe6b9 175
de2103e4
AD		 176 if (mode->hdisplay < native_mode->hdisplay ||
177 mode->vdisplay < native_mode->vdisplay) {
fb06ca8f 178 int mode_id = adjusted_mode->base.id;
de2103e4
AD		 179 *adjusted_mode = *native_mode;
180 if (!ASIC_IS_AVIVO(rdev)) {
181 adjusted_mode->hdisplay = mode->hdisplay;
182 adjusted_mode->vdisplay = mode->vdisplay;
771fe6b9 183 }
fb06ca8f 184 adjusted_mode->base.id = mode_id;
771fe6b9
JG		 185 }
186}
187
c93bb85b 188
771fe6b9
JG		 189static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
190 struct drm_display_mode *mode,
191 struct drm_display_mode *adjusted_mode)
192{
771fe6b9 193 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
5a9bcacc
AD		 194 struct drm_device *dev = encoder->dev;
195 struct radeon_device *rdev = dev->dev_private;
771fe6b9 196
771fe6b9
JG		 197 drm_mode_set_crtcinfo(adjusted_mode, 0);
198
199 if (radeon_encoder->rmx_type != RMX_OFF)
200 radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
201
202 /* hw bug */
203 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
204 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
205 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
206
5a9bcacc
AD		 207 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
208 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
209 if (tv_dac) {
210 if (tv_dac->tv_std == TV_STD_NTSC ||
211 tv_dac->tv_std == TV_STD_NTSC_J ||
212 tv_dac->tv_std == TV_STD_PAL_M)
213 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
214 else
215 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
216 }
217 }
218
771fe6b9
JG		 219 return true;
220}
221
222static void
223atombios_dac_setup(struct drm_encoder *encoder, int action)
224{
225 struct drm_device *dev = encoder->dev;
226 struct radeon_device *rdev = dev->dev_private;
227 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
228 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
229 int index = 0, num = 0;
445282db 230 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
771fe6b9
JG		 231 enum radeon_tv_std tv_std = TV_STD_NTSC;
232
445282db
DA		 233 if (dac_info->tv_std)
234 tv_std = dac_info->tv_std;
235
771fe6b9
JG		 236 memset(&args, 0, sizeof(args));
237
238 switch (radeon_encoder->encoder_id) {
239 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
240 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
241 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
242 num = 1;
243 break;
244 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
245 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
246 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
247 num = 2;
248 break;
249 }
250
251 args.ucAction = action;
252
4ce001ab 253 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
771fe6b9 254 args.ucDacStandard = ATOM_DAC1_PS2;
4ce001ab 255 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 256 args.ucDacStandard = ATOM_DAC1_CV;
257 else {
258 switch (tv_std) {
259 case TV_STD_PAL:
260 case TV_STD_PAL_M:
261 case TV_STD_SCART_PAL:
262 case TV_STD_SECAM:
263 case TV_STD_PAL_CN:
264 args.ucDacStandard = ATOM_DAC1_PAL;
265 break;
266 case TV_STD_NTSC:
267 case TV_STD_NTSC_J:
268 case TV_STD_PAL_60:
269 default:
270 args.ucDacStandard = ATOM_DAC1_NTSC;
271 break;
272 }
273 }
274 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
275
276 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
277
278}
279
280static void
281atombios_tv_setup(struct drm_encoder *encoder, int action)
282{
283 struct drm_device *dev = encoder->dev;
284 struct radeon_device *rdev = dev->dev_private;
285 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
286 TV_ENCODER_CONTROL_PS_ALLOCATION args;
287 int index = 0;
445282db 288 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
771fe6b9
JG		 289 enum radeon_tv_std tv_std = TV_STD_NTSC;
290
445282db
DA		 291 if (dac_info->tv_std)
292 tv_std = dac_info->tv_std;
293
771fe6b9
JG		 294 memset(&args, 0, sizeof(args));
295
296 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
297
298 args.sTVEncoder.ucAction = action;
299
4ce001ab 300 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 301 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
302 else {
303 switch (tv_std) {
304 case TV_STD_NTSC:
305 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
306 break;
307 case TV_STD_PAL:
308 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
309 break;
310 case TV_STD_PAL_M:
311 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
312 break;
313 case TV_STD_PAL_60:
314 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
315 break;
316 case TV_STD_NTSC_J:
317 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
318 break;
319 case TV_STD_SCART_PAL:
320 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
321 break;
322 case TV_STD_SECAM:
323 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
324 break;
325 case TV_STD_PAL_CN:
326 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
327 break;
328 default:
329 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
330 break;
331 }
332 }
333
334 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
335
336 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
337
338}
339
340void
341atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
342{
343 struct drm_device *dev = encoder->dev;
344 struct radeon_device *rdev = dev->dev_private;
345 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
346 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
347 int index = 0;
348
349 memset(&args, 0, sizeof(args));
350
351 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
352
353 args.sXTmdsEncoder.ucEnable = action;
354
355 if (radeon_encoder->pixel_clock > 165000)
356 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
357
358 /*if (pScrn->rgbBits == 8)*/
359 args.sXTmdsEncoder.ucMisc |= (1 << 1);
360
361 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
362
363}
364
365static void
366atombios_ddia_setup(struct drm_encoder *encoder, int action)
367{
368 struct drm_device *dev = encoder->dev;
369 struct radeon_device *rdev = dev->dev_private;
370 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
371 DVO_ENCODER_CONTROL_PS_ALLOCATION args;
372 int index = 0;
373
374 memset(&args, 0, sizeof(args));
375
376 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
377
378 args.sDVOEncoder.ucAction = action;
379 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
380
381 if (radeon_encoder->pixel_clock > 165000)
382 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
383
384 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
385
386}
387
388union lvds_encoder_control {
389 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
390 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
391};
392
393static void
394atombios_digital_setup(struct drm_encoder *encoder, int action)
395{
396 struct drm_device *dev = encoder->dev;
397 struct radeon_device *rdev = dev->dev_private;
398 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
399 union lvds_encoder_control args;
400 int index = 0;
401 uint8_t frev, crev;
402 struct radeon_encoder_atom_dig *dig;
403 struct drm_connector *connector;
404 struct radeon_connector *radeon_connector;
405 struct radeon_connector_atom_dig *dig_connector;
406
407 connector = radeon_get_connector_for_encoder(encoder);
408 if (!connector)
409 return;
410
411 radeon_connector = to_radeon_connector(connector);
412
413 if (!radeon_encoder->enc_priv)
414 return;
415
416 dig = radeon_encoder->enc_priv;
417
418 if (!radeon_connector->con_priv)
419 return;
420
421 dig_connector = radeon_connector->con_priv;
422
423 memset(&args, 0, sizeof(args));
424
425 switch (radeon_encoder->encoder_id) {
426 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
427 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
428 break;
429 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
430 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
431 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
432 break;
433 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
434 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
435 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
436 else
437 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
438 break;
439 }
440
441 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
442
443 switch (frev) {
444 case 1:
445 case 2:
446 switch (crev) {
447 case 1:
448 args.v1.ucMisc = 0;
449 args.v1.ucAction = action;
450 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
451 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
452 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
453 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
454 if (dig->lvds_misc & (1 << 0))
455 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
456 if (dig->lvds_misc & (1 << 1))
457 args.v1.ucMisc |= (1 << 1);
458 } else {
459 if (dig_connector->linkb)
460 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
461 if (radeon_encoder->pixel_clock > 165000)
462 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
463 /*if (pScrn->rgbBits == 8) */
464 args.v1.ucMisc |= (1 << 1);
465 }
466 break;
467 case 2:
468 case 3:
469 args.v2.ucMisc = 0;
470 args.v2.ucAction = action;
471 if (crev == 3) {
472 if (dig->coherent_mode)
473 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
474 }
475 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
476 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
477 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
478 args.v2.ucTruncate = 0;
479 args.v2.ucSpatial = 0;
480 args.v2.ucTemporal = 0;
481 args.v2.ucFRC = 0;
482 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
483 if (dig->lvds_misc & (1 << 0))
484 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
485 if (dig->lvds_misc & (1 << 5)) {
486 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
487 if (dig->lvds_misc & (1 << 1))
488 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
489 }
490 if (dig->lvds_misc & (1 << 6)) {
491 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
492 if (dig->lvds_misc & (1 << 1))
493 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
494 if (((dig->lvds_misc >> 2) & 0x3) == 2)
495 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
496 }
497 } else {
498 if (dig_connector->linkb)
499 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
500 if (radeon_encoder->pixel_clock > 165000)
501 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
502 }
503 break;
504 default:
505 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
506 break;
507 }
508 break;
509 default:
510 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
511 break;
512 }
513
514 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
515
516}
517
518int
519atombios_get_encoder_mode(struct drm_encoder *encoder)
520{
521 struct drm_connector *connector;
522 struct radeon_connector *radeon_connector;
523
524 connector = radeon_get_connector_for_encoder(encoder);
525 if (!connector)
526 return 0;
527
528 radeon_connector = to_radeon_connector(connector);
529
530 switch (connector->connector_type) {
531 case DRM_MODE_CONNECTOR_DVII:
705af9c7 532 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
771fe6b9
JG		 533 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
534 return ATOM_ENCODER_MODE_HDMI;
535 else if (radeon_connector->use_digital)
536 return ATOM_ENCODER_MODE_DVI;
537 else
538 return ATOM_ENCODER_MODE_CRT;
539 break;
540 case DRM_MODE_CONNECTOR_DVID:
541 case DRM_MODE_CONNECTOR_HDMIA:
771fe6b9
JG		 542 default:
543 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
544 return ATOM_ENCODER_MODE_HDMI;
545 else
546 return ATOM_ENCODER_MODE_DVI;
547 break;
548 case DRM_MODE_CONNECTOR_LVDS:
549 return ATOM_ENCODER_MODE_LVDS;
550 break;
551 case DRM_MODE_CONNECTOR_DisplayPort:
552 /*if (radeon_output->MonType == MT_DP)
553 return ATOM_ENCODER_MODE_DP;
554 else*/
555 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
556 return ATOM_ENCODER_MODE_HDMI;
557 else
558 return ATOM_ENCODER_MODE_DVI;
559 break;
560 case CONNECTOR_DVI_A:
561 case CONNECTOR_VGA:
562 return ATOM_ENCODER_MODE_CRT;
563 break;
564 case CONNECTOR_STV:
565 case CONNECTOR_CTV:
566 case CONNECTOR_DIN:
567 /* fix me */
568 return ATOM_ENCODER_MODE_TV;
569 /*return ATOM_ENCODER_MODE_CV;*/
570 break;
571 }
572}
573
574static void
575atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
576{
577 struct drm_device *dev = encoder->dev;
578 struct radeon_device *rdev = dev->dev_private;
579 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
580 DIG_ENCODER_CONTROL_PS_ALLOCATION args;
581 int index = 0, num = 0;
582 uint8_t frev, crev;
583 struct radeon_encoder_atom_dig *dig;
584 struct drm_connector *connector;
585 struct radeon_connector *radeon_connector;
586 struct radeon_connector_atom_dig *dig_connector;
587
588 connector = radeon_get_connector_for_encoder(encoder);
589 if (!connector)
590 return;
591
592 radeon_connector = to_radeon_connector(connector);
593
594 if (!radeon_connector->con_priv)
595 return;
596
597 dig_connector = radeon_connector->con_priv;
598
599 if (!radeon_encoder->enc_priv)
600 return;
601
602 dig = radeon_encoder->enc_priv;
603
604 memset(&args, 0, sizeof(args));
605
606 if (ASIC_IS_DCE32(rdev)) {
607 if (dig->dig_block)
608 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
609 else
610 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
611 num = dig->dig_block + 1;
612 } else {
613 switch (radeon_encoder->encoder_id) {
614 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
615 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
616 num = 1;
617 break;
618 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
619 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
620 num = 2;
621 break;
622 }
623 }
624
625 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
626
627 args.ucAction = action;
628 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
629
630 if (ASIC_IS_DCE32(rdev)) {
631 switch (radeon_encoder->encoder_id) {
632 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
633 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
634 break;
635 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
636 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
637 break;
638 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
639 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
640 break;
641 }
642 } else {
643 switch (radeon_encoder->encoder_id) {
644 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
645 args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
646 break;
647 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
648 args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
649 break;
650 }
651 }
652
653 if (radeon_encoder->pixel_clock > 165000) {
654 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B;
655 args.ucLaneNum = 8;
656 } else {
657 if (dig_connector->linkb)
658 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
659 else
660 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
661 args.ucLaneNum = 4;
662 }
663
664 args.ucEncoderMode = atombios_get_encoder_mode(encoder);
665
666 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
667
668}
669
670union dig_transmitter_control {
671 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
672 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
673};
674
675static void
676atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
677{
678 struct drm_device *dev = encoder->dev;
679 struct radeon_device *rdev = dev->dev_private;
680 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
681 union dig_transmitter_control args;
682 int index = 0, num = 0;
683 uint8_t frev, crev;
684 struct radeon_encoder_atom_dig *dig;
685 struct drm_connector *connector;
686 struct radeon_connector *radeon_connector;
687 struct radeon_connector_atom_dig *dig_connector;
688
689 connector = radeon_get_connector_for_encoder(encoder);
690 if (!connector)
691 return;
692
693 radeon_connector = to_radeon_connector(connector);
694
695 if (!radeon_encoder->enc_priv)
696 return;
697
698 dig = radeon_encoder->enc_priv;
699
700 if (!radeon_connector->con_priv)
701 return;
702
703 dig_connector = radeon_connector->con_priv;
704
705 memset(&args, 0, sizeof(args));
706
707 if (ASIC_IS_DCE32(rdev))
708 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
709 else {
710 switch (radeon_encoder->encoder_id) {
711 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
712 index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
713 break;
714 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
715 index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
716 break;
717 }
718 }
719
720 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
721
722 args.v1.ucAction = action;
723
724 if (ASIC_IS_DCE32(rdev)) {
725 if (radeon_encoder->pixel_clock > 165000) {
726 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 2) / 100);
727 args.v2.acConfig.fDualLinkConnector = 1;
728 } else {
729 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 4) / 100);
730 }
731 if (dig->dig_block)
732 args.v2.acConfig.ucEncoderSel = 1;
733
734 switch (radeon_encoder->encoder_id) {
735 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
736 args.v2.acConfig.ucTransmitterSel = 0;
737 num = 0;
738 break;
739 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
740 args.v2.acConfig.ucTransmitterSel = 1;
741 num = 1;
742 break;
743 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
744 args.v2.acConfig.ucTransmitterSel = 2;
745 num = 2;
746 break;
747 }
748
749 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
750 if (dig->coherent_mode)
751 args.v2.acConfig.fCoherentMode = 1;
752 }
753 } else {
754 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
755 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock) / 10);
756
757 switch (radeon_encoder->encoder_id) {
758 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
759 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
760 if (rdev->flags & RADEON_IS_IGP) {
761 if (radeon_encoder->pixel_clock > 165000) {
762 args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
763 ATOM_TRANSMITTER_CONFIG_LINKA_B);
764 if (dig_connector->igp_lane_info & 0x3)
765 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
766 else if (dig_connector->igp_lane_info & 0xc)
767 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
768 } else {
769 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
770 if (dig_connector->igp_lane_info & 0x1)
771 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
772 else if (dig_connector->igp_lane_info & 0x2)
773 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
774 else if (dig_connector->igp_lane_info & 0x4)
775 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
776 else if (dig_connector->igp_lane_info & 0x8)
777 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
778 }
779 } else {
780 if (radeon_encoder->pixel_clock > 165000)
781 args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
782 ATOM_TRANSMITTER_CONFIG_LINKA_B |
783 ATOM_TRANSMITTER_CONFIG_LANE_0_7);
784 else {
785 if (dig_connector->linkb)
786 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
787 else
788 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
789 }
790 }
791 break;
792 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
793 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
794 if (radeon_encoder->pixel_clock > 165000)
795 args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
796 ATOM_TRANSMITTER_CONFIG_LINKA_B |
797 ATOM_TRANSMITTER_CONFIG_LANE_0_7);
798 else {
799 if (dig_connector->linkb)
800 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
801 else
802 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
803 }
804 break;
805 }
806
807 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
808 if (dig->coherent_mode)
809 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
810 }
811 }
812
813 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
814
815}
816
771fe6b9
JG		 817static void
818atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
819{
820 struct drm_device *dev = encoder->dev;
821 struct radeon_device *rdev = dev->dev_private;
822 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
823 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
824 ENABLE_YUV_PS_ALLOCATION args;
825 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
826 uint32_t temp, reg;
827
828 memset(&args, 0, sizeof(args));
829
830 if (rdev->family >= CHIP_R600)
831 reg = R600_BIOS_3_SCRATCH;
832 else
833 reg = RADEON_BIOS_3_SCRATCH;
834
835 /* XXX: fix up scratch reg handling */
836 temp = RREG32(reg);
4ce001ab 837 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9
JG		 838 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
839 (radeon_crtc->crtc_id << 18)));
4ce001ab 840 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 841 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
842 else
843 WREG32(reg, 0);
844
845 if (enable)
846 args.ucEnable = ATOM_ENABLE;
847 args.ucCRTC = radeon_crtc->crtc_id;
848
849 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
850
851 WREG32(reg, temp);
852}
853
771fe6b9
JG		 854static void
855radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
856{
857 struct drm_device *dev = encoder->dev;
858 struct radeon_device *rdev = dev->dev_private;
859 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
860 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
861 int index = 0;
862 bool is_dig = false;
4ce001ab 863 int devices;
771fe6b9
JG		 864
865 memset(&args, 0, sizeof(args));
866
4ce001ab
DA		 867 /* on DPMS off we have no idea if active device is meaningful */
868 if (mode != DRM_MODE_DPMS_ON && !radeon_encoder->active_device)
869 devices = radeon_encoder->devices;
870 else
871 devices = radeon_encoder->active_device;
872
f641e51e
DA		 873 DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
874 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
875 radeon_encoder->active_device);
771fe6b9
JG		 876 switch (radeon_encoder->encoder_id) {
877 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
878 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
879 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
880 break;
881 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
882 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
883 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
884 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
885 is_dig = true;
886 break;
887 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
888 case ENCODER_OBJECT_ID_INTERNAL_DDI:
889 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
890 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
891 break;
892 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
893 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
894 break;
895 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
896 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
897 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
898 else
899 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
900 break;
901 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
902 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
4ce001ab 903 if (devices & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 904 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
4ce001ab 905 else if (devices & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 906 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
907 else
908 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
909 break;
910 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
911 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
4ce001ab 912 if (devices & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 913 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
4ce001ab 914 else if (devices & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 915 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
916 else
917 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
918 break;
919 }
920
921 if (is_dig) {
922 switch (mode) {
923 case DRM_MODE_DPMS_ON:
924 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE);
925 break;
926 case DRM_MODE_DPMS_STANDBY:
927 case DRM_MODE_DPMS_SUSPEND:
928 case DRM_MODE_DPMS_OFF:
929 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE);
930 break;
931 }
932 } else {
933 switch (mode) {
934 case DRM_MODE_DPMS_ON:
935 args.ucAction = ATOM_ENABLE;
936 break;
937 case DRM_MODE_DPMS_STANDBY:
938 case DRM_MODE_DPMS_SUSPEND:
939 case DRM_MODE_DPMS_OFF:
940 args.ucAction = ATOM_DISABLE;
941 break;
942 }
943 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
944 }
945 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
946}
947
948union crtc_sourc_param {
949 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
950 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
951};
952
953static void
954atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
955{
956 struct drm_device *dev = encoder->dev;
957 struct radeon_device *rdev = dev->dev_private;
958 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
959 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
960 union crtc_sourc_param args;
961 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
962 uint8_t frev, crev;
963
964 memset(&args, 0, sizeof(args));
965
966 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
967
968 switch (frev) {
969 case 1:
970 switch (crev) {
971 case 1:
972 default:
973 if (ASIC_IS_AVIVO(rdev))
974 args.v1.ucCRTC = radeon_crtc->crtc_id;
975 else {
976 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
977 args.v1.ucCRTC = radeon_crtc->crtc_id;
978 } else {
979 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
980 }
981 }
982 switch (radeon_encoder->encoder_id) {
983 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
984 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
985 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
986 break;
987 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
988 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
989 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
990 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
991 else
992 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
993 break;
994 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
995 case ENCODER_OBJECT_ID_INTERNAL_DDI:
996 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
997 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
998 break;
999 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1000 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
4ce001ab 1001 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1002 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
4ce001ab 1003 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1004 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1005 else
1006 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1007 break;
1008 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1009 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
4ce001ab 1010 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1011 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
4ce001ab 1012 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1013 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1014 else
1015 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1016 break;
1017 }
1018 break;
1019 case 2:
1020 args.v2.ucCRTC = radeon_crtc->crtc_id;
1021 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1022 switch (radeon_encoder->encoder_id) {
1023 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1024 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1025 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1026 if (ASIC_IS_DCE32(rdev)) {
1027 if (radeon_crtc->crtc_id)
1028 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1029 else
1030 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1031 } else
1032 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1033 break;
1034 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1035 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1036 break;
1037 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1038 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1039 break;
1040 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
4ce001ab 1041 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1042 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
4ce001ab 1043 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1044 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1045 else
1046 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1047 break;
1048 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
4ce001ab 1049 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1050 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
4ce001ab 1051 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1052 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1053 else
1054 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1055 break;
1056 }
1057 break;
1058 }
1059 break;
1060 default:
1061 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1062 break;
1063 }
1064
1065 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1066
1067}
1068
1069static void
1070atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1071 struct drm_display_mode *mode)
1072{
1073 struct drm_device *dev = encoder->dev;
1074 struct radeon_device *rdev = dev->dev_private;
1075 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1076 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1077
1078 /* Funky macbooks */
1079 if ((dev->pdev->device == 0x71C5) &&
1080 (dev->pdev->subsystem_vendor == 0x106b) &&
1081 (dev->pdev->subsystem_device == 0x0080)) {
1082 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1083 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1084
1085 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1086 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1087
1088 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1089 }
1090 }
1091
1092 /* set scaler clears this on some chips */
1093 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1094 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, AVIVO_D1MODE_INTERLEAVE_EN);
1095}
1096
1097static void
1098radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1099 struct drm_display_mode *mode,
1100 struct drm_display_mode *adjusted_mode)
1101{
1102 struct drm_device *dev = encoder->dev;
1103 struct radeon_device *rdev = dev->dev_private;
1104 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1105 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1106
1107 if (radeon_encoder->enc_priv) {
1108 struct radeon_encoder_atom_dig *dig;
1109
1110 dig = radeon_encoder->enc_priv;
1111 dig->dig_block = radeon_crtc->crtc_id;
1112 }
1113 radeon_encoder->pixel_clock = adjusted_mode->clock;
1114
1115 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
771fe6b9
JG		 1116 atombios_set_encoder_crtc_source(encoder);
1117
1118 if (ASIC_IS_AVIVO(rdev)) {
4ce001ab 1119 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
771fe6b9
JG		 1120 atombios_yuv_setup(encoder, true);
1121 else
1122 atombios_yuv_setup(encoder, false);
1123 }
1124
1125 switch (radeon_encoder->encoder_id) {
1126 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1127 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1128 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1129 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1130 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1131 break;
1132 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1133 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1134 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1135 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1136 /* disable the encoder and transmitter */
1137 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE);
1138 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1139
1140 /* setup and enable the encoder and transmitter */
1141 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1142 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP);
1143 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE);
1144 break;
1145 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1146 atombios_ddia_setup(encoder, ATOM_ENABLE);
1147 break;
1148 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1149 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1150 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1151 break;
1152 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1153 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1154 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1155 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1156 atombios_dac_setup(encoder, ATOM_ENABLE);
4ce001ab 1157 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1158 atombios_tv_setup(encoder, ATOM_ENABLE);
1159 break;
1160 }
1161 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1162}
1163
1164static bool
4ce001ab 1165atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
771fe6b9
JG		 1166{
1167 struct drm_device *dev = encoder->dev;
1168 struct radeon_device *rdev = dev->dev_private;
1169 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4ce001ab 1170 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
771fe6b9
JG		 1171
1172 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1173 ATOM_DEVICE_CV_SUPPORT |
1174 ATOM_DEVICE_CRT_SUPPORT)) {
1175 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1176 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1177 uint8_t frev, crev;
1178
1179 memset(&args, 0, sizeof(args));
1180
1181 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1182
1183 args.sDacload.ucMisc = 0;
1184
1185 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1186 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1187 args.sDacload.ucDacType = ATOM_DAC_A;
1188 else
1189 args.sDacload.ucDacType = ATOM_DAC_B;
1190
4ce001ab 1191 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
771fe6b9 1192 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
4ce001ab 1193 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
771fe6b9 1194 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
4ce001ab 1195 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
771fe6b9
JG		 1196 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1197 if (crev >= 3)
1198 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
4ce001ab 1199 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
771fe6b9
JG		 1200 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1201 if (crev >= 3)
1202 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1203 }
1204
1205 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1206
1207 return true;
1208 } else
1209 return false;
1210}
1211
1212static enum drm_connector_status
1213radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1214{
1215 struct drm_device *dev = encoder->dev;
1216 struct radeon_device *rdev = dev->dev_private;
1217 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4ce001ab 1218 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
771fe6b9
JG		 1219 uint32_t bios_0_scratch;
1220
4ce001ab 1221 if (!atombios_dac_load_detect(encoder, connector)) {
771fe6b9
JG		 1222 DRM_DEBUG("detect returned false \n");
1223 return connector_status_unknown;
1224 }
1225
1226 if (rdev->family >= CHIP_R600)
1227 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1228 else
1229 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1230
4ce001ab
DA		 1231 DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1232 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
771fe6b9
JG		 1233 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1234 return connector_status_connected;
4ce001ab
DA		 1235 }
1236 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
771fe6b9
JG		 1237 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1238 return connector_status_connected;
4ce001ab
DA		 1239 }
1240 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
771fe6b9
JG		 1241 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1242 return connector_status_connected;
4ce001ab
DA		 1243 }
1244 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
771fe6b9
JG		 1245 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1246 return connector_status_connected; /* CTV */
1247 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1248 return connector_status_connected; /* STV */
1249 }
1250 return connector_status_disconnected;
1251}
1252
1253static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1254{
1255 radeon_atom_output_lock(encoder, true);
1256 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
4ce001ab
DA		 1257
1258 radeon_encoder_set_active_device(encoder);
771fe6b9
JG		 1259}
1260
1261static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1262{
1263 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1264 radeon_atom_output_lock(encoder, false);
1265}
1266
4ce001ab
DA		 1267static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1268{
1269 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1270 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
4ce001ab
DA		 1271 radeon_encoder->active_device = 0;
1272}
1273
771fe6b9
JG		 1274static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1275 .dpms = radeon_atom_encoder_dpms,
1276 .mode_fixup = radeon_atom_mode_fixup,
1277 .prepare = radeon_atom_encoder_prepare,
1278 .mode_set = radeon_atom_encoder_mode_set,
1279 .commit = radeon_atom_encoder_commit,
4ce001ab 1280 .disable = radeon_atom_encoder_disable,
771fe6b9
JG		 1281 /* no detect for TMDS/LVDS yet */
1282};
1283
1284static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1285 .dpms = radeon_atom_encoder_dpms,
1286 .mode_fixup = radeon_atom_mode_fixup,
1287 .prepare = radeon_atom_encoder_prepare,
1288 .mode_set = radeon_atom_encoder_mode_set,
1289 .commit = radeon_atom_encoder_commit,
1290 .detect = radeon_atom_dac_detect,
1291};
1292
1293void radeon_enc_destroy(struct drm_encoder *encoder)
1294{
1295 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1296 kfree(radeon_encoder->enc_priv);
1297 drm_encoder_cleanup(encoder);
1298 kfree(radeon_encoder);
1299}
1300
1301static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1302 .destroy = radeon_enc_destroy,
1303};
1304
4ce001ab
DA		 1305struct radeon_encoder_atom_dac *
1306radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1307{
1308 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1309
1310 if (!dac)
1311 return NULL;
1312
1313 dac->tv_std = TV_STD_NTSC;
1314 return dac;
1315}
1316
771fe6b9
JG		 1317struct radeon_encoder_atom_dig *
1318radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1319{
1320 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1321
1322 if (!dig)
1323 return NULL;
1324
1325 /* coherent mode by default */
1326 dig->coherent_mode = true;
1327
1328 return dig;
1329}
1330
1331void
1332radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1333{
dfee5614 1334 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 1335 struct drm_encoder *encoder;
1336 struct radeon_encoder *radeon_encoder;
1337
1338 /* see if we already added it */
1339 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1340 radeon_encoder = to_radeon_encoder(encoder);
1341 if (radeon_encoder->encoder_id == encoder_id) {
1342 radeon_encoder->devices |= supported_device;
1343 return;
1344 }
1345
1346 }
1347
1348 /* add a new one */
1349 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1350 if (!radeon_encoder)
1351 return;
1352
1353 encoder = &radeon_encoder->base;
dfee5614
DA		 1354 if (rdev->flags & RADEON_SINGLE_CRTC)
1355 encoder->possible_crtcs = 0x1;
1356 else
1357 encoder->possible_crtcs = 0x3;
771fe6b9
JG		 1358 encoder->possible_clones = 0;
1359
1360 radeon_encoder->enc_priv = NULL;
1361
1362 radeon_encoder->encoder_id = encoder_id;
1363 radeon_encoder->devices = supported_device;
c93bb85b 1364 radeon_encoder->rmx_type = RMX_OFF;
771fe6b9
JG		 1365
1366 switch (radeon_encoder->encoder_id) {
1367 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1368 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1369 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1370 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1371 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1372 radeon_encoder->rmx_type = RMX_FULL;
1373 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1374 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1375 } else {
1376 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1377 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1378 }
1379 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1380 break;
1381 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1382 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1383 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1384 break;
1385 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1386 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1387 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1388 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
4ce001ab 1389 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
771fe6b9
JG		 1390 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1391 break;
1392 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1393 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1394 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1395 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1396 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1397 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1398 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
60d15f55
AD		 1399 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1400 radeon_encoder->rmx_type = RMX_FULL;
1401 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1402 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1403 } else {
1404 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1405 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1406 }
771fe6b9
JG		 1407 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1408 break;
1409 }
1410}
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