[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / radeon / radeon_fb.c

/*
 * Copyright © 2007 David Airlie
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *     David Airlie
 */
    /*
     *  Modularization
     */

#include <linux/module.h>
#include <linux/fb.h>

#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "radeon_drm.h"
#include "radeon.h"

#include "drm_fb_helper.h"

struct radeon_fb_device {
	struct drm_fb_helper helper;
	struct radeon_framebuffer	*rfb;
	struct radeon_device		*rdev;
};

static struct fb_ops radeonfb_ops = {
	.owner = THIS_MODULE,
	.fb_check_var = drm_fb_helper_check_var,
	.fb_set_par = drm_fb_helper_set_par,
	.fb_setcolreg = drm_fb_helper_setcolreg,
	.fb_fillrect = cfb_fillrect,
	.fb_copyarea = cfb_copyarea,
	.fb_imageblit = cfb_imageblit,
	.fb_pan_display = drm_fb_helper_pan_display,
	.fb_blank = drm_fb_helper_blank,
	.fb_setcmap = drm_fb_helper_setcmap,
};

/**
 * Currently it is assumed that the old framebuffer is reused.
 *
 * LOCKING
 * caller should hold the mode config lock.
 *
 */
int radeonfb_resize(struct drm_device *dev, struct drm_crtc *crtc)
{
	struct fb_info *info;
	struct drm_framebuffer *fb;
	struct drm_display_mode *mode = crtc->desired_mode;

	fb = crtc->fb;
	if (fb == NULL) {
		return 1;
	}
	info = fb->fbdev;
	if (info == NULL) {
		return 1;
	}
	if (mode == NULL) {
		return 1;
	}
	info->var.xres = mode->hdisplay;
	info->var.right_margin = mode->hsync_start - mode->hdisplay;
	info->var.hsync_len = mode->hsync_end - mode->hsync_start;
	info->var.left_margin = mode->htotal - mode->hsync_end;
	info->var.yres = mode->vdisplay;
	info->var.lower_margin = mode->vsync_start - mode->vdisplay;
	info->var.vsync_len = mode->vsync_end - mode->vsync_start;
	info->var.upper_margin = mode->vtotal - mode->vsync_end;
	info->var.pixclock = 10000000 / mode->htotal * 1000 / mode->vtotal * 100;
	/* avoid overflow */
	info->var.pixclock = info->var.pixclock * 1000 / mode->vrefresh;

	return 0;
}
EXPORT_SYMBOL(radeonfb_resize);

static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
{
	int aligned = width;
	int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
	int pitch_mask = 0;

	switch (bpp / 8) {
	case 1:
		pitch_mask = align_large ? 255 : 127;
		break;
	case 2:
		pitch_mask = align_large ? 127 : 31;
		break;
	case 3:
	case 4:
		pitch_mask = align_large ? 63 : 15;
		break;
	}

	aligned += pitch_mask;
	aligned &= ~pitch_mask;
	return aligned;
}

static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
	.gamma_set = radeon_crtc_fb_gamma_set,
	.gamma_get = radeon_crtc_fb_gamma_get,
};

int radeonfb_create(struct drm_device *dev,
		    uint32_t fb_width, uint32_t fb_height,
		    uint32_t surface_width, uint32_t surface_height,
		    uint32_t surface_depth, uint32_t surface_bpp,
		    struct drm_framebuffer **fb_p)
{
	struct radeon_device *rdev = dev->dev_private;
	struct fb_info *info;
	struct radeon_fb_device *rfbdev;
	struct drm_framebuffer *fb = NULL;
	struct radeon_framebuffer *rfb;
	struct drm_mode_fb_cmd mode_cmd;
	struct drm_gem_object *gobj = NULL;
	struct radeon_object *robj = NULL;
	struct device *device = &rdev->pdev->dev;
	int size, aligned_size, ret;
	u64 fb_gpuaddr;
	void *fbptr = NULL;
	unsigned long tmp;
	bool fb_tiled = false; /* useful for testing */
	u32 tiling_flags = 0;
	int crtc_count;

	mode_cmd.width = surface_width;
	mode_cmd.height = surface_height;

	/* avivo can't scanout real 24bpp */
	if ((surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
		surface_bpp = 32;

	mode_cmd.bpp = surface_bpp;
	/* need to align pitch with crtc limits */
	mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp, fb_tiled) * ((mode_cmd.bpp + 1) / 8);
	mode_cmd.depth = surface_depth;

	size = mode_cmd.pitch * mode_cmd.height;
	aligned_size = ALIGN(size, PAGE_SIZE);

	ret = radeon_gem_object_create(rdev, aligned_size, 0,
			RADEON_GEM_DOMAIN_VRAM,
			false, ttm_bo_type_kernel,
			false, &gobj);
	if (ret) {
		printk(KERN_ERR "failed to allocate framebuffer (%d %d)\n",
		       surface_width, surface_height);
		ret = -ENOMEM;
		goto out;
	}
	robj = gobj->driver_private;

	if (fb_tiled)
		tiling_flags = RADEON_TILING_MACRO;

#ifdef __BIG_ENDIAN
	switch (mode_cmd.bpp) {
	case 32:
		tiling_flags |= RADEON_TILING_SWAP_32BIT;
		break;
	case 16:
		tiling_flags |= RADEON_TILING_SWAP_16BIT;
	default:
		break;
	}
#endif

	if (tiling_flags)
		radeon_object_set_tiling_flags(robj, tiling_flags | RADEON_TILING_SURFACE, mode_cmd.pitch);
	mutex_lock(&rdev->ddev->struct_mutex);
	fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj);
	if (fb == NULL) {
		DRM_ERROR("failed to allocate fb.\n");
		ret = -ENOMEM;
		goto out_unref;
	}
	ret = radeon_object_pin(robj, RADEON_GEM_DOMAIN_VRAM, &fb_gpuaddr);
	if (ret) {
		printk(KERN_ERR "failed to pin framebuffer\n");
		ret = -ENOMEM;
		goto out_unref;
	}

	list_add(&fb->filp_head, &rdev->ddev->mode_config.fb_kernel_list);

	*fb_p = fb;
	rfb = to_radeon_framebuffer(fb);
	rdev->fbdev_rfb = rfb;
	rdev->fbdev_robj = robj;

	info = framebuffer_alloc(sizeof(struct radeon_fb_device), device);
	if (info == NULL) {
		ret = -ENOMEM;
		goto out_unref;
	}

	rdev->fbdev_info = info;
	rfbdev = info->par;
	rfbdev->helper.funcs = &radeon_fb_helper_funcs;
	rfbdev->helper.dev = dev;
	if (rdev->flags & RADEON_SINGLE_CRTC)
		crtc_count = 1;
	else
		crtc_count = 2;
	ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, crtc_count,
					    RADEONFB_CONN_LIMIT);
	if (ret)
		goto out_unref;

	if (fb_tiled)
		radeon_object_check_tiling(robj, 0, 0);

	ret = radeon_object_kmap(robj, &fbptr);
	if (ret) {
		goto out_unref;
	}

	memset_io(fbptr, 0, aligned_size);

	strcpy(info->fix.id, "radeondrmfb");

	drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);

	info->flags = FBINFO_DEFAULT;
	info->fbops = &radeonfb_ops;

	tmp = fb_gpuaddr - rdev->mc.vram_location;
	info->fix.smem_start = rdev->mc.aper_base + tmp;
	info->fix.smem_len = size;
	info->screen_base = fbptr;
	info->screen_size = size;

	drm_fb_helper_fill_var(info, fb, fb_width, fb_height);

	/* setup aperture base/size for vesafb takeover */
	info->aperture_base = rdev->ddev->mode_config.fb_base;
	info->aperture_size = rdev->mc.real_vram_size;

	info->fix.mmio_start = 0;
	info->fix.mmio_len = 0;
	info->pixmap.size = 64*1024;
	info->pixmap.buf_align = 8;
	info->pixmap.access_align = 32;
	info->pixmap.flags = FB_PIXMAP_SYSTEM;
	info->pixmap.scan_align = 1;
	if (info->screen_base == NULL) {
		ret = -ENOSPC;
		goto out_unref;
	}
	DRM_INFO("fb mappable at 0x%lX\n",  info->fix.smem_start);
	DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)rdev->mc.aper_base);
	DRM_INFO("size %lu\n", (unsigned long)size);
	DRM_INFO("fb depth is %d\n", fb->depth);
	DRM_INFO("   pitch is %d\n", fb->pitch);

	fb->fbdev = info;
	rfbdev->rfb = rfb;
	rfbdev->rdev = rdev;

	mutex_unlock(&rdev->ddev->struct_mutex);
	return 0;

out_unref:
	if (robj) {
		radeon_object_kunmap(robj);
	}
	if (fb && ret) {
		list_del(&fb->filp_head);
		drm_gem_object_unreference(gobj);
		drm_framebuffer_cleanup(fb);
		kfree(fb);
	}
	drm_gem_object_unreference(gobj);
	mutex_unlock(&rdev->ddev->struct_mutex);
out:
	return ret;
}

static char *mode_option;
int radeon_parse_options(char *options)
{
	char *this_opt;

	if (!options || !*options)
		return 0;

	while ((this_opt = strsep(&options, ",")) != NULL) {
		if (!*this_opt)
			continue;
		mode_option = this_opt;
	}
	return 0;
}

int radeonfb_probe(struct drm_device *dev)
{
	return drm_fb_helper_single_fb_probe(dev, 32, &radeonfb_create);
}

int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb)
{
	struct fb_info *info;
	struct radeon_framebuffer *rfb = to_radeon_framebuffer(fb);
	struct radeon_object *robj;

	if (!fb) {
		return -EINVAL;
	}
	info = fb->fbdev;
	if (info) {
		struct radeon_fb_device *rfbdev = info->par;
		robj = rfb->obj->driver_private;
		unregister_framebuffer(info);
		radeon_object_kunmap(robj);
		radeon_object_unpin(robj);
		drm_fb_helper_free(&rfbdev->helper);
		framebuffer_release(info);
	}

	printk(KERN_INFO "unregistered panic notifier\n");

	return 0;
}
EXPORT_SYMBOL(radeonfb_remove);
MODULE_LICENSE("GPL");
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright © 2007 David Airlie
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* David Airlie
	25	*/
	26	/*
	27	* Modularization
	28	*/
	29
	30	#include <linux/module.h>
771fe6b9	31	#include <linux/fb.h>
771fe6b9 JG	32
	33	#include "drmP.h"
	34	#include "drm.h"
	35	#include "drm_crtc.h"
	36	#include "drm_crtc_helper.h"
	37	#include "radeon_drm.h"
	38	#include "radeon.h"
	39
785b93ef DA	40	#include "drm_fb_helper.h"
785b93ef DA	41
771fe6b9	42	struct radeon_fb_device {
785b93ef	43	struct drm_fb_helper helper;
771fe6b9	44	struct radeon_framebuffer *rfb;
785b93ef	45	struct radeon_device *rdev;
771fe6b9 JG	46	};
771fe6b9 JG	47
771fe6b9 JG	48	static struct fb_ops radeonfb_ops = {
771fe6b9 JG	49	.owner = THIS_MODULE,
c88f9f0c	50	.fb_check_var = drm_fb_helper_check_var,
785b93ef DA	51	.fb_set_par = drm_fb_helper_set_par,
785b93ef DA	52	.fb_setcolreg = drm_fb_helper_setcolreg,
771fe6b9 JG	53	.fb_fillrect = cfb_fillrect,
	54	.fb_copyarea = cfb_copyarea,
	55	.fb_imageblit = cfb_imageblit,
785b93ef DA	56	.fb_pan_display = drm_fb_helper_pan_display,
785b93ef DA	57	.fb_blank = drm_fb_helper_blank,
068143d3	58	.fb_setcmap = drm_fb_helper_setcmap,
771fe6b9 JG	59	};
	60
	61	/**
af901ca1	62	* Currently it is assumed that the old framebuffer is reused.
771fe6b9 JG	63	*
	64	* LOCKING
	65	* caller should hold the mode config lock.
	66	*
	67	*/
	68	int radeonfb_resize(struct drm_device dev, struct drm_crtc crtc)
	69	{
	70	struct fb_info *info;
	71	struct drm_framebuffer *fb;
	72	struct drm_display_mode *mode = crtc->desired_mode;
	73
	74	fb = crtc->fb;
	75	if (fb == NULL) {
	76	return 1;
	77	}
	78	info = fb->fbdev;
	79	if (info == NULL) {
	80	return 1;
	81	}
	82	if (mode == NULL) {
	83	return 1;
	84	}
	85	info->var.xres = mode->hdisplay;
	86	info->var.right_margin = mode->hsync_start - mode->hdisplay;
	87	info->var.hsync_len = mode->hsync_end - mode->hsync_start;
	88	info->var.left_margin = mode->htotal - mode->hsync_end;
	89	info->var.yres = mode->vdisplay;
	90	info->var.lower_margin = mode->vsync_start - mode->vdisplay;
	91	info->var.vsync_len = mode->vsync_end - mode->vsync_start;
	92	info->var.upper_margin = mode->vtotal - mode->vsync_end;
	93	info->var.pixclock = 10000000 / mode->htotal * 1000 / mode->vtotal * 100;
	94	/* avoid overflow */
	95	info->var.pixclock = info->var.pixclock * 1000 / mode->vrefresh;
	96
	97	return 0;
	98	}
	99	EXPORT_SYMBOL(radeonfb_resize);
	100
e024e110	101	static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
771fe6b9 JG	102	{
771fe6b9 JG	103	int aligned = width;
e024e110	104	int align_large = (ASIC_IS_AVIVO(rdev)) \|\| tiled;
771fe6b9 JG	105	int pitch_mask = 0;
	106
	107	switch (bpp / 8) {
	108	case 1:
	109	pitch_mask = align_large ? 255 : 127;
	110	break;
	111	case 2:
	112	pitch_mask = align_large ? 127 : 31;
	113	break;
	114	case 3:
	115	case 4:
	116	pitch_mask = align_large ? 63 : 15;
	117	break;
	118	}
	119
	120	aligned += pitch_mask;
	121	aligned &= ~pitch_mask;
	122	return aligned;
	123	}
	124
785b93ef DA	125	static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
785b93ef DA	126	.gamma_set = radeon_crtc_fb_gamma_set,
b8c00ac5	127	.gamma_get = radeon_crtc_fb_gamma_get,
785b93ef DA	128	};
	129
	130	int radeonfb_create(struct drm_device *dev,
771fe6b9 JG	131	uint32_t fb_width, uint32_t fb_height,
771fe6b9 JG	132	uint32_t surface_width, uint32_t surface_height,
d50ba256	133	uint32_t surface_depth, uint32_t surface_bpp,
785b93ef	134	struct drm_framebuffer **fb_p)
771fe6b9	135	{
785b93ef	136	struct radeon_device *rdev = dev->dev_private;
771fe6b9 JG	137	struct fb_info *info;
771fe6b9 JG	138	struct radeon_fb_device *rfbdev;
f92e93eb	139	struct drm_framebuffer *fb = NULL;
771fe6b9 JG	140	struct radeon_framebuffer *rfb;
	141	struct drm_mode_fb_cmd mode_cmd;
	142	struct drm_gem_object *gobj = NULL;
	143	struct radeon_object *robj = NULL;
	144	struct device *device = &rdev->pdev->dev;
	145	int size, aligned_size, ret;
f92e93eb	146	u64 fb_gpuaddr;
771fe6b9	147	void *fbptr = NULL;
f92e93eb	148	unsigned long tmp;
e024e110	149	bool fb_tiled = false; /* useful for testing */
c88f9f0c	150	u32 tiling_flags = 0;
dfee5614	151	int crtc_count;
771fe6b9 JG	152
	153	mode_cmd.width = surface_width;
	154	mode_cmd.height = surface_height;
b8c00ac5 DA	155
	156	/* avivo can't scanout real 24bpp */
	157	if ((surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
	158	surface_bpp = 32;
	159
d50ba256	160	mode_cmd.bpp = surface_bpp;
771fe6b9	161	/* need to align pitch with crtc limits */
e024e110	162	mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp, fb_tiled) * ((mode_cmd.bpp + 1) / 8);
d50ba256	163	mode_cmd.depth = surface_depth;
771fe6b9 JG	164
	165	size = mode_cmd.pitch * mode_cmd.height;
	166	aligned_size = ALIGN(size, PAGE_SIZE);
	167
	168	ret = radeon_gem_object_create(rdev, aligned_size, 0,
f92e93eb JG	169	RADEON_GEM_DOMAIN_VRAM,
	170	false, ttm_bo_type_kernel,
	171	false, &gobj);
771fe6b9	172	if (ret) {
f92e93eb JG	173	printk(KERN_ERR "failed to allocate framebuffer (%d %d)\n",
f92e93eb JG	174	surface_width, surface_height);
771fe6b9 JG	175	ret = -ENOMEM;
	176	goto out;
	177	}
	178	robj = gobj->driver_private;
	179
e024e110	180	if (fb_tiled)
c88f9f0c MD	181	tiling_flags = RADEON_TILING_MACRO;
	182
	183	#ifdef __BIG_ENDIAN
	184	switch (mode_cmd.bpp) {
	185	case 32:
	186	tiling_flags \|= RADEON_TILING_SWAP_32BIT;
	187	break;
	188	case 16:
	189	tiling_flags \|= RADEON_TILING_SWAP_16BIT;
	190	default:
	191	break;
	192	}
	193	#endif
	194
	195	if (tiling_flags)
	196	radeon_object_set_tiling_flags(robj, tiling_flags \| RADEON_TILING_SURFACE, mode_cmd.pitch);
771fe6b9 JG	197	mutex_lock(&rdev->ddev->struct_mutex);
	198	fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj);
	199	if (fb == NULL) {
	200	DRM_ERROR("failed to allocate fb.\n");
	201	ret = -ENOMEM;
	202	goto out_unref;
	203	}
f92e93eb JG	204	ret = radeon_object_pin(robj, RADEON_GEM_DOMAIN_VRAM, &fb_gpuaddr);
	205	if (ret) {
	206	printk(KERN_ERR "failed to pin framebuffer\n");
	207	ret = -ENOMEM;
	208	goto out_unref;
	209	}
771fe6b9 JG	210
	211	list_add(&fb->filp_head, &rdev->ddev->mode_config.fb_kernel_list);
	212
785b93ef	213	*fb_p = fb;
771fe6b9	214	rfb = to_radeon_framebuffer(fb);
771fe6b9	215	rdev->fbdev_rfb = rfb;
f92e93eb	216	rdev->fbdev_robj = robj;
771fe6b9 JG	217
	218	info = framebuffer_alloc(sizeof(struct radeon_fb_device), device);
	219	if (info == NULL) {
	220	ret = -ENOMEM;
	221	goto out_unref;
	222	}
785b93ef	223
2f9a60d7	224	rdev->fbdev_info = info;
771fe6b9	225	rfbdev = info->par;
785b93ef DA	226	rfbdev->helper.funcs = &radeon_fb_helper_funcs;
785b93ef DA	227	rfbdev->helper.dev = dev;
dfee5614 DA	228	if (rdev->flags & RADEON_SINGLE_CRTC)
	229	crtc_count = 1;
	230	else
	231	crtc_count = 2;
	232	ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, crtc_count,
785b93ef DA	233	RADEONFB_CONN_LIMIT);
	234	if (ret)
	235	goto out_unref;
771fe6b9	236
e024e110 DA	237	if (fb_tiled)
	238	radeon_object_check_tiling(robj, 0, 0);
	239
771fe6b9 JG	240	ret = radeon_object_kmap(robj, &fbptr);
	241	if (ret) {
	242	goto out_unref;
	243	}
	244
bf8e828b DA	245	memset_io(fbptr, 0, aligned_size);
bf8e828b DA	246
771fe6b9	247	strcpy(info->fix.id, "radeondrmfb");
785b93ef	248
068143d3	249	drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);
785b93ef	250
771fe6b9 JG	251	info->flags = FBINFO_DEFAULT;
771fe6b9 JG	252	info->fbops = &radeonfb_ops;
785b93ef	253
f92e93eb JG	254	tmp = fb_gpuaddr - rdev->mc.vram_location;
f92e93eb JG	255	info->fix.smem_start = rdev->mc.aper_base + tmp;
771fe6b9 JG	256	info->fix.smem_len = size;
	257	info->screen_base = fbptr;
	258	info->screen_size = size;
785b93ef DA	259
785b93ef DA	260	drm_fb_helper_fill_var(info, fb, fb_width, fb_height);
ed8f0d9e DA	261
	262	/* setup aperture base/size for vesafb takeover */
	263	info->aperture_base = rdev->ddev->mode_config.fb_base;
	264	info->aperture_size = rdev->mc.real_vram_size;
	265
696d4df1 MD	266	info->fix.mmio_start = 0;
696d4df1 MD	267	info->fix.mmio_len = 0;
771fe6b9 JG	268	info->pixmap.size = 64*1024;
	269	info->pixmap.buf_align = 8;
	270	info->pixmap.access_align = 32;
	271	info->pixmap.flags = FB_PIXMAP_SYSTEM;
	272	info->pixmap.scan_align = 1;
	273	if (info->screen_base == NULL) {
	274	ret = -ENOSPC;
	275	goto out_unref;
	276	}
	277	DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
	278	DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base);
	279	DRM_INFO("size %lu\n", (unsigned long)size);
	280	DRM_INFO("fb depth is %d\n", fb->depth);
	281	DRM_INFO(" pitch is %d\n", fb->pitch);
	282
771fe6b9 JG	283	fb->fbdev = info;
	284	rfbdev->rfb = rfb;
	285	rfbdev->rdev = rdev;
	286
	287	mutex_unlock(&rdev->ddev->struct_mutex);
	288	return 0;
	289
	290	out_unref:
	291	if (robj) {
	292	radeon_object_kunmap(robj);
	293	}
f92e93eb	294	if (fb && ret) {
771fe6b9 JG	295	list_del(&fb->filp_head);
	296	drm_gem_object_unreference(gobj);
	297	drm_framebuffer_cleanup(fb);
	298	kfree(fb);
	299	}
	300	drm_gem_object_unreference(gobj);
	301	mutex_unlock(&rdev->ddev->struct_mutex);
	302	out:
	303	return ret;
	304	}
	305
d50ba256 DA	306	static char *mode_option;
	307	int radeon_parse_options(char *options)
	308	{
	309	char *this_opt;
	310
	311	if (!options \|\| !*options)
	312	return 0;
	313
	314	while ((this_opt = strsep(&options, ",")) != NULL) {
	315	if (!*this_opt)
	316	continue;
	317	mode_option = this_opt;
	318	}
	319	return 0;
	320	}
	321
771fe6b9 JG	322	int radeonfb_probe(struct drm_device *dev)
771fe6b9 JG	323	{
b8c00ac5	324	return drm_fb_helper_single_fb_probe(dev, 32, &radeonfb_create);
771fe6b9	325	}
771fe6b9 JG	326
	327	int radeonfb_remove(struct drm_device dev, struct drm_framebuffer fb)
	328	{
	329	struct fb_info *info;
	330	struct radeon_framebuffer *rfb = to_radeon_framebuffer(fb);
	331	struct radeon_object *robj;
	332
	333	if (!fb) {
	334	return -EINVAL;
	335	}
	336	info = fb->fbdev;
	337	if (info) {
785b93ef	338	struct radeon_fb_device *rfbdev = info->par;
771fe6b9 JG	339	robj = rfb->obj->driver_private;
	340	unregister_framebuffer(info);
	341	radeon_object_kunmap(robj);
f92e93eb	342	radeon_object_unpin(robj);
785b93ef	343	drm_fb_helper_free(&rfbdev->helper);
771fe6b9 JG	344	framebuffer_release(info);
	345	}
	346
	347	printk(KERN_INFO "unregistered panic notifier\n");
785b93ef	348
771fe6b9 JG	349	return 0;
	350	}
	351	EXPORT_SYMBOL(radeonfb_remove);
	352	MODULE_LICENSE("GPL");