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Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/radeon_drm.h> | |
771fe6b9 JG |
30 | #include "radeon.h" |
31 | ||
771fe6b9 JG |
32 | void radeon_gem_object_free(struct drm_gem_object *gobj) |
33 | { | |
7e4d15d9 | 34 | struct radeon_bo *robj = gem_to_radeon_bo(gobj); |
771fe6b9 | 35 | |
771fe6b9 | 36 | if (robj) { |
12f1384d | 37 | radeon_mn_unregister(robj); |
4c788679 | 38 | radeon_bo_unref(&robj); |
771fe6b9 JG |
39 | } |
40 | } | |
41 | ||
391bfec3 | 42 | int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, |
4c788679 | 43 | int alignment, int initial_domain, |
ed5cb43f | 44 | u32 flags, bool kernel, |
4c788679 | 45 | struct drm_gem_object **obj) |
771fe6b9 | 46 | { |
4c788679 | 47 | struct radeon_bo *robj; |
6c0d112f | 48 | unsigned long max_size; |
771fe6b9 JG |
49 | int r; |
50 | ||
51 | *obj = NULL; | |
771fe6b9 JG |
52 | /* At least align on page size */ |
53 | if (alignment < PAGE_SIZE) { | |
54 | alignment = PAGE_SIZE; | |
55 | } | |
6c0d112f | 56 | |
391bfec3 AD |
57 | /* Maximum bo size is the unpinned gtt size since we use the gtt to |
58 | * handle vram to system pool migrations. | |
59 | */ | |
60 | max_size = rdev->mc.gtt_size - rdev->gart_pin_size; | |
6c0d112f | 61 | if (size > max_size) { |
391bfec3 | 62 | DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n", |
380670ae | 63 | size >> 20, max_size >> 20); |
6c0d112f CK |
64 | return -ENOMEM; |
65 | } | |
66 | ||
0fe7158c | 67 | retry: |
02376d82 | 68 | r = radeon_bo_create(rdev, size, alignment, kernel, initial_domain, |
831b6966 | 69 | flags, NULL, NULL, &robj); |
771fe6b9 | 70 | if (r) { |
0fe7158c CK |
71 | if (r != -ERESTARTSYS) { |
72 | if (initial_domain == RADEON_GEM_DOMAIN_VRAM) { | |
73 | initial_domain |= RADEON_GEM_DOMAIN_GTT; | |
74 | goto retry; | |
75 | } | |
391bfec3 | 76 | DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n", |
ecabd32a | 77 | size, initial_domain, alignment, r); |
0fe7158c | 78 | } |
771fe6b9 JG |
79 | return r; |
80 | } | |
441921d5 | 81 | *obj = &robj->gem_base; |
409851f4 | 82 | robj->pid = task_pid_nr(current); |
441921d5 DV |
83 | |
84 | mutex_lock(&rdev->gem.mutex); | |
85 | list_add_tail(&robj->list, &rdev->gem.objects); | |
86 | mutex_unlock(&rdev->gem.mutex); | |
87 | ||
771fe6b9 JG |
88 | return 0; |
89 | } | |
90 | ||
248a6c4a | 91 | static int radeon_gem_set_domain(struct drm_gem_object *gobj, |
771fe6b9 JG |
92 | uint32_t rdomain, uint32_t wdomain) |
93 | { | |
4c788679 | 94 | struct radeon_bo *robj; |
771fe6b9 | 95 | uint32_t domain; |
39e7f6f8 | 96 | long r; |
771fe6b9 JG |
97 | |
98 | /* FIXME: reeimplement */ | |
7e4d15d9 | 99 | robj = gem_to_radeon_bo(gobj); |
771fe6b9 JG |
100 | /* work out where to validate the buffer to */ |
101 | domain = wdomain; | |
102 | if (!domain) { | |
103 | domain = rdomain; | |
104 | } | |
105 | if (!domain) { | |
106 | /* Do nothings */ | |
7ca85295 | 107 | pr_warn("Set domain without domain !\n"); |
771fe6b9 JG |
108 | return 0; |
109 | } | |
110 | if (domain == RADEON_GEM_DOMAIN_CPU) { | |
111 | /* Asking for cpu access wait for object idle */ | |
39e7f6f8 ML |
112 | r = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 30 * HZ); |
113 | if (!r) | |
114 | r = -EBUSY; | |
115 | ||
116 | if (r < 0 && r != -EINTR) { | |
7ca85295 | 117 | pr_err("Failed to wait for object: %li\n", r); |
771fe6b9 JG |
118 | return r; |
119 | } | |
120 | } | |
ede2e019 CJHR |
121 | if (domain == RADEON_GEM_DOMAIN_VRAM && robj->prime_shared_count) { |
122 | /* A BO that is associated with a dma-buf cannot be sensibly migrated to VRAM */ | |
123 | return -EINVAL; | |
124 | } | |
771fe6b9 JG |
125 | return 0; |
126 | } | |
127 | ||
128 | int radeon_gem_init(struct radeon_device *rdev) | |
129 | { | |
130 | INIT_LIST_HEAD(&rdev->gem.objects); | |
131 | return 0; | |
132 | } | |
133 | ||
134 | void radeon_gem_fini(struct radeon_device *rdev) | |
135 | { | |
4c788679 | 136 | radeon_bo_force_delete(rdev); |
771fe6b9 JG |
137 | } |
138 | ||
721604a1 JG |
139 | /* |
140 | * Call from drm_gem_handle_create which appear in both new and open ioctl | |
141 | * case. | |
142 | */ | |
143 | int radeon_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) | |
144 | { | |
e971bd5e CK |
145 | struct radeon_bo *rbo = gem_to_radeon_bo(obj); |
146 | struct radeon_device *rdev = rbo->rdev; | |
147 | struct radeon_fpriv *fpriv = file_priv->driver_priv; | |
148 | struct radeon_vm *vm = &fpriv->vm; | |
149 | struct radeon_bo_va *bo_va; | |
150 | int r; | |
151 | ||
544143f9 AD |
152 | if ((rdev->family < CHIP_CAYMAN) || |
153 | (!rdev->accel_working)) { | |
e971bd5e CK |
154 | return 0; |
155 | } | |
156 | ||
157 | r = radeon_bo_reserve(rbo, false); | |
158 | if (r) { | |
159 | return r; | |
160 | } | |
161 | ||
162 | bo_va = radeon_vm_bo_find(vm, rbo); | |
163 | if (!bo_va) { | |
164 | bo_va = radeon_vm_bo_add(rdev, vm, rbo); | |
165 | } else { | |
166 | ++bo_va->ref_count; | |
167 | } | |
168 | radeon_bo_unreserve(rbo); | |
169 | ||
721604a1 JG |
170 | return 0; |
171 | } | |
172 | ||
173 | void radeon_gem_object_close(struct drm_gem_object *obj, | |
174 | struct drm_file *file_priv) | |
175 | { | |
176 | struct radeon_bo *rbo = gem_to_radeon_bo(obj); | |
177 | struct radeon_device *rdev = rbo->rdev; | |
178 | struct radeon_fpriv *fpriv = file_priv->driver_priv; | |
179 | struct radeon_vm *vm = &fpriv->vm; | |
e971bd5e | 180 | struct radeon_bo_va *bo_va; |
d59f7021 | 181 | int r; |
721604a1 | 182 | |
544143f9 AD |
183 | if ((rdev->family < CHIP_CAYMAN) || |
184 | (!rdev->accel_working)) { | |
721604a1 JG |
185 | return; |
186 | } | |
187 | ||
d59f7021 CK |
188 | r = radeon_bo_reserve(rbo, true); |
189 | if (r) { | |
190 | dev_err(rdev->dev, "leaking bo va because " | |
191 | "we fail to reserve bo (%d)\n", r); | |
721604a1 JG |
192 | return; |
193 | } | |
e971bd5e CK |
194 | bo_va = radeon_vm_bo_find(vm, rbo); |
195 | if (bo_va) { | |
196 | if (--bo_va->ref_count == 0) { | |
197 | radeon_vm_bo_rmv(rdev, bo_va); | |
198 | } | |
199 | } | |
721604a1 JG |
200 | radeon_bo_unreserve(rbo); |
201 | } | |
202 | ||
6c6f4783 CK |
203 | static int radeon_gem_handle_lockup(struct radeon_device *rdev, int r) |
204 | { | |
205 | if (r == -EDEADLK) { | |
6c6f4783 CK |
206 | r = radeon_gpu_reset(rdev); |
207 | if (!r) | |
208 | r = -EAGAIN; | |
6c6f4783 CK |
209 | } |
210 | return r; | |
211 | } | |
771fe6b9 JG |
212 | |
213 | /* | |
214 | * GEM ioctls. | |
215 | */ | |
216 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |
217 | struct drm_file *filp) | |
218 | { | |
219 | struct radeon_device *rdev = dev->dev_private; | |
220 | struct drm_radeon_gem_info *args = data; | |
53595338 DA |
221 | struct ttm_mem_type_manager *man; |
222 | ||
223 | man = &rdev->mman.bdev.man[TTM_PL_VRAM]; | |
771fe6b9 | 224 | |
51964e9e MD |
225 | args->vram_size = (u64)man->size << PAGE_SHIFT; |
226 | args->vram_visible = rdev->mc.visible_vram_size; | |
ccbe0060 AD |
227 | args->vram_visible -= rdev->vram_pin_size; |
228 | args->gart_size = rdev->mc.gtt_size; | |
229 | args->gart_size -= rdev->gart_pin_size; | |
230 | ||
771fe6b9 JG |
231 | return 0; |
232 | } | |
233 | ||
234 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, | |
235 | struct drm_file *filp) | |
236 | { | |
237 | /* TODO: implement */ | |
238 | DRM_ERROR("unimplemented %s\n", __func__); | |
239 | return -ENOSYS; | |
240 | } | |
241 | ||
242 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
243 | struct drm_file *filp) | |
244 | { | |
245 | /* TODO: implement */ | |
246 | DRM_ERROR("unimplemented %s\n", __func__); | |
247 | return -ENOSYS; | |
248 | } | |
249 | ||
250 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, | |
251 | struct drm_file *filp) | |
252 | { | |
253 | struct radeon_device *rdev = dev->dev_private; | |
254 | struct drm_radeon_gem_create *args = data; | |
255 | struct drm_gem_object *gobj; | |
256 | uint32_t handle; | |
257 | int r; | |
258 | ||
dee53e7f | 259 | down_read(&rdev->exclusive_lock); |
771fe6b9 JG |
260 | /* create a gem object to contain this object in */ |
261 | args->size = roundup(args->size, PAGE_SIZE); | |
262 | r = radeon_gem_object_create(rdev, args->size, args->alignment, | |
02376d82 | 263 | args->initial_domain, args->flags, |
ed5cb43f | 264 | false, &gobj); |
771fe6b9 | 265 | if (r) { |
dee53e7f | 266 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 267 | r = radeon_gem_handle_lockup(rdev, r); |
771fe6b9 JG |
268 | return r; |
269 | } | |
270 | r = drm_gem_handle_create(filp, gobj, &handle); | |
29d08b3e | 271 | /* drop reference from allocate - handle holds it now */ |
07f65bb2 | 272 | drm_gem_object_put_unlocked(gobj); |
771fe6b9 | 273 | if (r) { |
dee53e7f | 274 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 275 | r = radeon_gem_handle_lockup(rdev, r); |
771fe6b9 JG |
276 | return r; |
277 | } | |
771fe6b9 | 278 | args->handle = handle; |
dee53e7f | 279 | up_read(&rdev->exclusive_lock); |
771fe6b9 JG |
280 | return 0; |
281 | } | |
282 | ||
f72a113a CK |
283 | int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, |
284 | struct drm_file *filp) | |
285 | { | |
286 | struct radeon_device *rdev = dev->dev_private; | |
287 | struct drm_radeon_gem_userptr *args = data; | |
288 | struct drm_gem_object *gobj; | |
289 | struct radeon_bo *bo; | |
290 | uint32_t handle; | |
291 | int r; | |
292 | ||
293 | if (offset_in_page(args->addr | args->size)) | |
294 | return -EINVAL; | |
295 | ||
f72a113a | 296 | /* reject unknown flag values */ |
ddd00e33 | 297 | if (args->flags & ~(RADEON_GEM_USERPTR_READONLY | |
341cb9e4 CK |
298 | RADEON_GEM_USERPTR_ANONONLY | RADEON_GEM_USERPTR_VALIDATE | |
299 | RADEON_GEM_USERPTR_REGISTER)) | |
f72a113a CK |
300 | return -EINVAL; |
301 | ||
bd645e43 CK |
302 | if (args->flags & RADEON_GEM_USERPTR_READONLY) { |
303 | /* readonly pages not tested on older hardware */ | |
304 | if (rdev->family < CHIP_R600) | |
305 | return -EINVAL; | |
306 | ||
307 | } else if (!(args->flags & RADEON_GEM_USERPTR_ANONONLY) || | |
308 | !(args->flags & RADEON_GEM_USERPTR_REGISTER)) { | |
309 | ||
310 | /* if we want to write to it we must require anonymous | |
311 | memory and install a MMU notifier */ | |
312 | return -EACCES; | |
313 | } | |
f72a113a CK |
314 | |
315 | down_read(&rdev->exclusive_lock); | |
316 | ||
317 | /* create a gem object to contain this object in */ | |
318 | r = radeon_gem_object_create(rdev, args->size, 0, | |
319 | RADEON_GEM_DOMAIN_CPU, 0, | |
320 | false, &gobj); | |
321 | if (r) | |
322 | goto handle_lockup; | |
323 | ||
324 | bo = gem_to_radeon_bo(gobj); | |
325 | r = radeon_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); | |
326 | if (r) | |
327 | goto release_object; | |
328 | ||
341cb9e4 CK |
329 | if (args->flags & RADEON_GEM_USERPTR_REGISTER) { |
330 | r = radeon_mn_register(bo, args->addr); | |
331 | if (r) | |
332 | goto release_object; | |
333 | } | |
334 | ||
2a84a447 CK |
335 | if (args->flags & RADEON_GEM_USERPTR_VALIDATE) { |
336 | down_read(¤t->mm->mmap_sem); | |
337 | r = radeon_bo_reserve(bo, true); | |
338 | if (r) { | |
339 | up_read(¤t->mm->mmap_sem); | |
340 | goto release_object; | |
341 | } | |
342 | ||
343 | radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_GTT); | |
344 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
345 | radeon_bo_unreserve(bo); | |
346 | up_read(¤t->mm->mmap_sem); | |
347 | if (r) | |
348 | goto release_object; | |
349 | } | |
350 | ||
f72a113a CK |
351 | r = drm_gem_handle_create(filp, gobj, &handle); |
352 | /* drop reference from allocate - handle holds it now */ | |
07f65bb2 | 353 | drm_gem_object_put_unlocked(gobj); |
f72a113a CK |
354 | if (r) |
355 | goto handle_lockup; | |
356 | ||
357 | args->handle = handle; | |
358 | up_read(&rdev->exclusive_lock); | |
359 | return 0; | |
360 | ||
361 | release_object: | |
07f65bb2 | 362 | drm_gem_object_put_unlocked(gobj); |
f72a113a CK |
363 | |
364 | handle_lockup: | |
365 | up_read(&rdev->exclusive_lock); | |
366 | r = radeon_gem_handle_lockup(rdev, r); | |
367 | ||
368 | return r; | |
369 | } | |
370 | ||
771fe6b9 JG |
371 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
372 | struct drm_file *filp) | |
373 | { | |
374 | /* transition the BO to a domain - | |
375 | * just validate the BO into a certain domain */ | |
dee53e7f | 376 | struct radeon_device *rdev = dev->dev_private; |
771fe6b9 JG |
377 | struct drm_radeon_gem_set_domain *args = data; |
378 | struct drm_gem_object *gobj; | |
4c788679 | 379 | struct radeon_bo *robj; |
771fe6b9 JG |
380 | int r; |
381 | ||
382 | /* for now if someone requests domain CPU - | |
383 | * just make sure the buffer is finished with */ | |
dee53e7f | 384 | down_read(&rdev->exclusive_lock); |
771fe6b9 JG |
385 | |
386 | /* just do a BO wait for now */ | |
a8ad0bd8 | 387 | gobj = drm_gem_object_lookup(filp, args->handle); |
771fe6b9 | 388 | if (gobj == NULL) { |
dee53e7f | 389 | up_read(&rdev->exclusive_lock); |
bf79cb91 | 390 | return -ENOENT; |
771fe6b9 | 391 | } |
7e4d15d9 | 392 | robj = gem_to_radeon_bo(gobj); |
771fe6b9 JG |
393 | |
394 | r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain); | |
395 | ||
07f65bb2 | 396 | drm_gem_object_put_unlocked(gobj); |
dee53e7f | 397 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 398 | r = radeon_gem_handle_lockup(robj->rdev, r); |
771fe6b9 JG |
399 | return r; |
400 | } | |
401 | ||
da6b51d0 DA |
402 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
403 | struct drm_device *dev, | |
404 | uint32_t handle, uint64_t *offset_p) | |
771fe6b9 | 405 | { |
771fe6b9 | 406 | struct drm_gem_object *gobj; |
4c788679 | 407 | struct radeon_bo *robj; |
771fe6b9 | 408 | |
a8ad0bd8 | 409 | gobj = drm_gem_object_lookup(filp, handle); |
771fe6b9 | 410 | if (gobj == NULL) { |
bf79cb91 | 411 | return -ENOENT; |
771fe6b9 | 412 | } |
7e4d15d9 | 413 | robj = gem_to_radeon_bo(gobj); |
f72a113a | 414 | if (radeon_ttm_tt_has_userptr(robj->tbo.ttm)) { |
07f65bb2 | 415 | drm_gem_object_put_unlocked(gobj); |
f72a113a CK |
416 | return -EPERM; |
417 | } | |
ff72145b | 418 | *offset_p = radeon_bo_mmap_offset(robj); |
07f65bb2 | 419 | drm_gem_object_put_unlocked(gobj); |
4c788679 | 420 | return 0; |
771fe6b9 JG |
421 | } |
422 | ||
ff72145b DA |
423 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, |
424 | struct drm_file *filp) | |
425 | { | |
426 | struct drm_radeon_gem_mmap *args = data; | |
427 | ||
da6b51d0 | 428 | return radeon_mode_dumb_mmap(filp, dev, args->handle, &args->addr_ptr); |
ff72145b DA |
429 | } |
430 | ||
771fe6b9 JG |
431 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, |
432 | struct drm_file *filp) | |
433 | { | |
cefb87ef DA |
434 | struct drm_radeon_gem_busy *args = data; |
435 | struct drm_gem_object *gobj; | |
4c788679 | 436 | struct radeon_bo *robj; |
cefb87ef | 437 | int r; |
4361e52a | 438 | uint32_t cur_placement = 0; |
cefb87ef | 439 | |
a8ad0bd8 | 440 | gobj = drm_gem_object_lookup(filp, args->handle); |
cefb87ef | 441 | if (gobj == NULL) { |
bf79cb91 | 442 | return -ENOENT; |
cefb87ef | 443 | } |
7e4d15d9 | 444 | robj = gem_to_radeon_bo(gobj); |
828202a3 GG |
445 | |
446 | r = reservation_object_test_signaled_rcu(robj->tbo.resv, true); | |
447 | if (r == 0) | |
448 | r = -EBUSY; | |
449 | else | |
450 | r = 0; | |
451 | ||
6aa7de05 | 452 | cur_placement = READ_ONCE(robj->tbo.mem.mem_type); |
0bc490a8 | 453 | args->domain = radeon_mem_type_to_domain(cur_placement); |
07f65bb2 | 454 | drm_gem_object_put_unlocked(gobj); |
e3b2415e | 455 | return r; |
771fe6b9 JG |
456 | } |
457 | ||
458 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
459 | struct drm_file *filp) | |
460 | { | |
1ef5325b | 461 | struct radeon_device *rdev = dev->dev_private; |
771fe6b9 JG |
462 | struct drm_radeon_gem_wait_idle *args = data; |
463 | struct drm_gem_object *gobj; | |
4c788679 | 464 | struct radeon_bo *robj; |
39e7f6f8 | 465 | int r = 0; |
404a6a51 | 466 | uint32_t cur_placement = 0; |
39e7f6f8 | 467 | long ret; |
771fe6b9 | 468 | |
a8ad0bd8 | 469 | gobj = drm_gem_object_lookup(filp, args->handle); |
771fe6b9 | 470 | if (gobj == NULL) { |
bf79cb91 | 471 | return -ENOENT; |
771fe6b9 | 472 | } |
7e4d15d9 | 473 | robj = gem_to_radeon_bo(gobj); |
39e7f6f8 ML |
474 | |
475 | ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 30 * HZ); | |
476 | if (ret == 0) | |
477 | r = -EBUSY; | |
478 | else if (ret < 0) | |
479 | r = ret; | |
480 | ||
124764f1 | 481 | /* Flush HDP cache via MMIO if necessary */ |
6aa7de05 | 482 | cur_placement = READ_ONCE(robj->tbo.mem.mem_type); |
404a6a51 MD |
483 | if (rdev->asic->mmio_hdp_flush && |
484 | radeon_mem_type_to_domain(cur_placement) == RADEON_GEM_DOMAIN_VRAM) | |
124764f1 | 485 | robj->rdev->asic->mmio_hdp_flush(rdev); |
07f65bb2 | 486 | drm_gem_object_put_unlocked(gobj); |
1ef5325b | 487 | r = radeon_gem_handle_lockup(rdev, r); |
771fe6b9 JG |
488 | return r; |
489 | } | |
e024e110 DA |
490 | |
491 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, | |
492 | struct drm_file *filp) | |
493 | { | |
494 | struct drm_radeon_gem_set_tiling *args = data; | |
495 | struct drm_gem_object *gobj; | |
4c788679 | 496 | struct radeon_bo *robj; |
e024e110 DA |
497 | int r = 0; |
498 | ||
499 | DRM_DEBUG("%d \n", args->handle); | |
a8ad0bd8 | 500 | gobj = drm_gem_object_lookup(filp, args->handle); |
e024e110 | 501 | if (gobj == NULL) |
bf79cb91 | 502 | return -ENOENT; |
7e4d15d9 | 503 | robj = gem_to_radeon_bo(gobj); |
4c788679 | 504 | r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); |
07f65bb2 | 505 | drm_gem_object_put_unlocked(gobj); |
e024e110 DA |
506 | return r; |
507 | } | |
508 | ||
509 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
510 | struct drm_file *filp) | |
511 | { | |
512 | struct drm_radeon_gem_get_tiling *args = data; | |
513 | struct drm_gem_object *gobj; | |
4c788679 | 514 | struct radeon_bo *rbo; |
e024e110 DA |
515 | int r = 0; |
516 | ||
517 | DRM_DEBUG("\n"); | |
a8ad0bd8 | 518 | gobj = drm_gem_object_lookup(filp, args->handle); |
e024e110 | 519 | if (gobj == NULL) |
bf79cb91 | 520 | return -ENOENT; |
7e4d15d9 | 521 | rbo = gem_to_radeon_bo(gobj); |
4c788679 JG |
522 | r = radeon_bo_reserve(rbo, false); |
523 | if (unlikely(r != 0)) | |
51f07b7e | 524 | goto out; |
4c788679 JG |
525 | radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); |
526 | radeon_bo_unreserve(rbo); | |
51f07b7e | 527 | out: |
07f65bb2 | 528 | drm_gem_object_put_unlocked(gobj); |
721604a1 JG |
529 | return r; |
530 | } | |
531 | ||
2f2624c2 CK |
532 | /** |
533 | * radeon_gem_va_update_vm -update the bo_va in its VM | |
534 | * | |
535 | * @rdev: radeon_device pointer | |
536 | * @bo_va: bo_va to update | |
537 | * | |
538 | * Update the bo_va directly after setting it's address. Errors are not | |
539 | * vital here, so they are not reported back to userspace. | |
540 | */ | |
541 | static void radeon_gem_va_update_vm(struct radeon_device *rdev, | |
542 | struct radeon_bo_va *bo_va) | |
543 | { | |
544 | struct ttm_validate_buffer tv, *entry; | |
1d0c0942 | 545 | struct radeon_bo_list *vm_bos; |
2f2624c2 CK |
546 | struct ww_acquire_ctx ticket; |
547 | struct list_head list; | |
548 | unsigned domain; | |
549 | int r; | |
550 | ||
551 | INIT_LIST_HEAD(&list); | |
552 | ||
553 | tv.bo = &bo_va->bo->tbo; | |
554 | tv.shared = true; | |
555 | list_add(&tv.head, &list); | |
556 | ||
557 | vm_bos = radeon_vm_get_bos(rdev, bo_va->vm, &list); | |
558 | if (!vm_bos) | |
559 | return; | |
560 | ||
aa35071c | 561 | r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL); |
2f2624c2 CK |
562 | if (r) |
563 | goto error_free; | |
564 | ||
565 | list_for_each_entry(entry, &list, head) { | |
566 | domain = radeon_mem_type_to_domain(entry->bo->mem.mem_type); | |
567 | /* if anything is swapped out don't swap it in here, | |
568 | just abort and wait for the next CS */ | |
569 | if (domain == RADEON_GEM_DOMAIN_CPU) | |
570 | goto error_unreserve; | |
571 | } | |
572 | ||
573 | mutex_lock(&bo_va->vm->mutex); | |
574 | r = radeon_vm_clear_freed(rdev, bo_va->vm); | |
575 | if (r) | |
576 | goto error_unlock; | |
577 | ||
578 | if (bo_va->it.start) | |
579 | r = radeon_vm_bo_update(rdev, bo_va, &bo_va->bo->tbo.mem); | |
580 | ||
581 | error_unlock: | |
582 | mutex_unlock(&bo_va->vm->mutex); | |
583 | ||
584 | error_unreserve: | |
585 | ttm_eu_backoff_reservation(&ticket, &list); | |
586 | ||
587 | error_free: | |
2098105e | 588 | kvfree(vm_bos); |
2f2624c2 | 589 | |
ad1a6222 | 590 | if (r && r != -ERESTARTSYS) |
2f2624c2 CK |
591 | DRM_ERROR("Couldn't update BO_VA (%d)\n", r); |
592 | } | |
593 | ||
721604a1 JG |
594 | int radeon_gem_va_ioctl(struct drm_device *dev, void *data, |
595 | struct drm_file *filp) | |
596 | { | |
597 | struct drm_radeon_gem_va *args = data; | |
598 | struct drm_gem_object *gobj; | |
599 | struct radeon_device *rdev = dev->dev_private; | |
600 | struct radeon_fpriv *fpriv = filp->driver_priv; | |
601 | struct radeon_bo *rbo; | |
602 | struct radeon_bo_va *bo_va; | |
603 | u32 invalid_flags; | |
604 | int r = 0; | |
605 | ||
67e915e4 AD |
606 | if (!rdev->vm_manager.enabled) { |
607 | args->operation = RADEON_VA_RESULT_ERROR; | |
608 | return -ENOTTY; | |
609 | } | |
610 | ||
721604a1 JG |
611 | /* !! DONT REMOVE !! |
612 | * We don't support vm_id yet, to be sure we don't have have broken | |
613 | * userspace, reject anyone trying to use non 0 value thus moving | |
614 | * forward we can use those fields without breaking existant userspace | |
615 | */ | |
616 | if (args->vm_id) { | |
617 | args->operation = RADEON_VA_RESULT_ERROR; | |
618 | return -EINVAL; | |
619 | } | |
620 | ||
621 | if (args->offset < RADEON_VA_RESERVED_SIZE) { | |
622 | dev_err(&dev->pdev->dev, | |
623 | "offset 0x%lX is in reserved area 0x%X\n", | |
624 | (unsigned long)args->offset, | |
625 | RADEON_VA_RESERVED_SIZE); | |
626 | args->operation = RADEON_VA_RESULT_ERROR; | |
627 | return -EINVAL; | |
628 | } | |
629 | ||
630 | /* don't remove, we need to enforce userspace to set the snooped flag | |
631 | * otherwise we will endup with broken userspace and we won't be able | |
632 | * to enable this feature without adding new interface | |
633 | */ | |
634 | invalid_flags = RADEON_VM_PAGE_VALID | RADEON_VM_PAGE_SYSTEM; | |
635 | if ((args->flags & invalid_flags)) { | |
636 | dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n", | |
637 | args->flags, invalid_flags); | |
638 | args->operation = RADEON_VA_RESULT_ERROR; | |
639 | return -EINVAL; | |
640 | } | |
721604a1 JG |
641 | |
642 | switch (args->operation) { | |
643 | case RADEON_VA_MAP: | |
644 | case RADEON_VA_UNMAP: | |
645 | break; | |
646 | default: | |
647 | dev_err(&dev->pdev->dev, "unsupported operation %d\n", | |
648 | args->operation); | |
649 | args->operation = RADEON_VA_RESULT_ERROR; | |
650 | return -EINVAL; | |
651 | } | |
652 | ||
a8ad0bd8 | 653 | gobj = drm_gem_object_lookup(filp, args->handle); |
721604a1 JG |
654 | if (gobj == NULL) { |
655 | args->operation = RADEON_VA_RESULT_ERROR; | |
656 | return -ENOENT; | |
657 | } | |
658 | rbo = gem_to_radeon_bo(gobj); | |
659 | r = radeon_bo_reserve(rbo, false); | |
660 | if (r) { | |
661 | args->operation = RADEON_VA_RESULT_ERROR; | |
07f65bb2 | 662 | drm_gem_object_put_unlocked(gobj); |
721604a1 JG |
663 | return r; |
664 | } | |
e971bd5e CK |
665 | bo_va = radeon_vm_bo_find(&fpriv->vm, rbo); |
666 | if (!bo_va) { | |
667 | args->operation = RADEON_VA_RESULT_ERROR; | |
186bac81 | 668 | radeon_bo_unreserve(rbo); |
07f65bb2 | 669 | drm_gem_object_put_unlocked(gobj); |
e971bd5e CK |
670 | return -ENOENT; |
671 | } | |
672 | ||
721604a1 JG |
673 | switch (args->operation) { |
674 | case RADEON_VA_MAP: | |
0aea5e4a | 675 | if (bo_va->it.start) { |
721604a1 | 676 | args->operation = RADEON_VA_RESULT_VA_EXIST; |
0aea5e4a | 677 | args->offset = bo_va->it.start * RADEON_GPU_PAGE_SIZE; |
85761f60 | 678 | radeon_bo_unreserve(rbo); |
721604a1 JG |
679 | goto out; |
680 | } | |
e971bd5e | 681 | r = radeon_vm_bo_set_addr(rdev, bo_va, args->offset, args->flags); |
721604a1 JG |
682 | break; |
683 | case RADEON_VA_UNMAP: | |
e971bd5e | 684 | r = radeon_vm_bo_set_addr(rdev, bo_va, 0, 0); |
721604a1 JG |
685 | break; |
686 | default: | |
687 | break; | |
688 | } | |
2f2624c2 CK |
689 | if (!r) |
690 | radeon_gem_va_update_vm(rdev, bo_va); | |
721604a1 JG |
691 | args->operation = RADEON_VA_RESULT_OK; |
692 | if (r) { | |
693 | args->operation = RADEON_VA_RESULT_ERROR; | |
694 | } | |
695 | out: | |
07f65bb2 | 696 | drm_gem_object_put_unlocked(gobj); |
e024e110 | 697 | return r; |
bda72d58 MO |
698 | } |
699 | ||
700 | int radeon_gem_op_ioctl(struct drm_device *dev, void *data, | |
701 | struct drm_file *filp) | |
702 | { | |
703 | struct drm_radeon_gem_op *args = data; | |
704 | struct drm_gem_object *gobj; | |
705 | struct radeon_bo *robj; | |
706 | int r; | |
707 | ||
a8ad0bd8 | 708 | gobj = drm_gem_object_lookup(filp, args->handle); |
bda72d58 MO |
709 | if (gobj == NULL) { |
710 | return -ENOENT; | |
711 | } | |
712 | robj = gem_to_radeon_bo(gobj); | |
f72a113a CK |
713 | |
714 | r = -EPERM; | |
715 | if (radeon_ttm_tt_has_userptr(robj->tbo.ttm)) | |
716 | goto out; | |
717 | ||
bda72d58 MO |
718 | r = radeon_bo_reserve(robj, false); |
719 | if (unlikely(r)) | |
720 | goto out; | |
721 | ||
722 | switch (args->op) { | |
723 | case RADEON_GEM_OP_GET_INITIAL_DOMAIN: | |
724 | args->value = robj->initial_domain; | |
725 | break; | |
726 | case RADEON_GEM_OP_SET_INITIAL_DOMAIN: | |
727 | robj->initial_domain = args->value & (RADEON_GEM_DOMAIN_VRAM | | |
728 | RADEON_GEM_DOMAIN_GTT | | |
729 | RADEON_GEM_DOMAIN_CPU); | |
730 | break; | |
731 | default: | |
732 | r = -EINVAL; | |
733 | } | |
734 | ||
735 | radeon_bo_unreserve(robj); | |
736 | out: | |
07f65bb2 | 737 | drm_gem_object_put_unlocked(gobj); |
bda72d58 | 738 | return r; |
e024e110 | 739 | } |
ff72145b DA |
740 | |
741 | int radeon_mode_dumb_create(struct drm_file *file_priv, | |
742 | struct drm_device *dev, | |
743 | struct drm_mode_create_dumb *args) | |
744 | { | |
745 | struct radeon_device *rdev = dev->dev_private; | |
746 | struct drm_gem_object *gobj; | |
c87a8d8d | 747 | uint32_t handle; |
ff72145b DA |
748 | int r; |
749 | ||
802aaf76 LP |
750 | args->pitch = radeon_align_pitch(rdev, args->width, |
751 | DIV_ROUND_UP(args->bpp, 8), 0); | |
ff72145b DA |
752 | args->size = args->pitch * args->height; |
753 | args->size = ALIGN(args->size, PAGE_SIZE); | |
754 | ||
755 | r = radeon_gem_object_create(rdev, args->size, 0, | |
02376d82 | 756 | RADEON_GEM_DOMAIN_VRAM, 0, |
ed5cb43f | 757 | false, &gobj); |
ff72145b DA |
758 | if (r) |
759 | return -ENOMEM; | |
760 | ||
c87a8d8d DA |
761 | r = drm_gem_handle_create(file_priv, gobj, &handle); |
762 | /* drop reference from allocate - handle holds it now */ | |
07f65bb2 | 763 | drm_gem_object_put_unlocked(gobj); |
ff72145b | 764 | if (r) { |
ff72145b DA |
765 | return r; |
766 | } | |
c87a8d8d | 767 | args->handle = handle; |
ff72145b DA |
768 | return 0; |
769 | } | |
770 | ||
409851f4 JG |
771 | #if defined(CONFIG_DEBUG_FS) |
772 | static int radeon_debugfs_gem_info(struct seq_file *m, void *data) | |
773 | { | |
774 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
775 | struct drm_device *dev = node->minor->dev; | |
776 | struct radeon_device *rdev = dev->dev_private; | |
777 | struct radeon_bo *rbo; | |
778 | unsigned i = 0; | |
779 | ||
780 | mutex_lock(&rdev->gem.mutex); | |
781 | list_for_each_entry(rbo, &rdev->gem.objects, list) { | |
782 | unsigned domain; | |
783 | const char *placement; | |
784 | ||
785 | domain = radeon_mem_type_to_domain(rbo->tbo.mem.mem_type); | |
786 | switch (domain) { | |
787 | case RADEON_GEM_DOMAIN_VRAM: | |
788 | placement = "VRAM"; | |
789 | break; | |
790 | case RADEON_GEM_DOMAIN_GTT: | |
791 | placement = " GTT"; | |
792 | break; | |
793 | case RADEON_GEM_DOMAIN_CPU: | |
794 | default: | |
795 | placement = " CPU"; | |
796 | break; | |
797 | } | |
798 | seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n", | |
799 | i, radeon_bo_size(rbo) >> 10, radeon_bo_size(rbo) >> 20, | |
800 | placement, (unsigned long)rbo->pid); | |
801 | i++; | |
802 | } | |
803 | mutex_unlock(&rdev->gem.mutex); | |
804 | return 0; | |
805 | } | |
806 | ||
807 | static struct drm_info_list radeon_debugfs_gem_list[] = { | |
808 | {"radeon_gem_info", &radeon_debugfs_gem_info, 0, NULL}, | |
809 | }; | |
810 | #endif | |
811 | ||
812 | int radeon_gem_debugfs_init(struct radeon_device *rdev) | |
813 | { | |
814 | #if defined(CONFIG_DEBUG_FS) | |
815 | return radeon_debugfs_add_files(rdev, radeon_debugfs_gem_list, 1); | |
816 | #endif | |
817 | return 0; | |
818 | } |