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gpu: Add export.h as required to drivers/gpu files.
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / radeon / radeon_i2c.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
2d1a8a48
PG		 26#include <linux/export.h>
27
771fe6b9
JG		 28#include "drmP.h"
29#include "radeon_drm.h"
30#include "radeon.h"
40bacf16 31#include "atom.h"
771fe6b9
JG		 32
33/**
34 * radeon_ddc_probe
35 *
36 */
e384fab8 37bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool requires_extended_probe)
771fe6b9 38{
e384fab8
TR		 39 u8 out = 0x0;
40 u8 buf[8];
771fe6b9
JG		 41 int ret;
42 struct i2c_msg msgs[] = {
43 {
44 .addr = 0x50,
45 .flags = 0,
46 .len = 1,
e384fab8 47 .buf = &out,
771fe6b9
JG		 48 },
49 {
50 .addr = 0x50,
51 .flags = I2C_M_RD,
52 .len = 1,
53 .buf = buf,
54 }
55 };
56
e384fab8
TR		 57 /* Read 8 bytes from i2c for extended probe of EDID header */
58 if (requires_extended_probe)
59 msgs[1].len = 8;
60
26b5bc98 61 /* on hw with routers, select right port */
fb939dfc
AD		 62 if (radeon_connector->router.ddc_valid)
63 radeon_router_select_ddc_port(radeon_connector);
26b5bc98 64
771fe6b9 65 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
e384fab8
TR		 66 if (ret != 2)
67 /* Couldn't find an accessible DDC on this connector */
68 return false;
69 if (requires_extended_probe) {
70 /* Probe also for valid EDID header
71 * EDID header starts with:
72 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
73 * Only the first 6 bytes must be valid as
74 * drm_edid_block_valid() can fix the last 2 bytes */
75 if (drm_edid_header_is_valid(buf) < 6) {
76 /* Couldn't find an accessible EDID on this
77 * connector */
78 return false;
79 }
80 }
81 return true;
771fe6b9
JG		 82}
83
ac1aade6 84/* bit banging i2c */
771fe6b9 85
43e5f612 86static int pre_xfer(struct i2c_adapter *i2c_adap)
771fe6b9 87{
43e5f612 88 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
ab1e9ea0
AD		 89 struct radeon_device *rdev = i2c->dev->dev_private;
90 struct radeon_i2c_bus_rec *rec = &i2c->rec;
771fe6b9 91 uint32_t temp;
771fe6b9
JG		 92
93 /* RV410 appears to have a bug where the hw i2c in reset
94 * holds the i2c port in a bad state - switch hw i2c away before
95 * doing DDC - do this for all r200s/r300s/r400s for safety sake
96 */
6a93cb25
AD		 97 if (rec->hw_capable) {
98 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
40bacf16
AD		 99 u32 reg;
100
101 if (rdev->family >= CHIP_RV350)
102 reg = RADEON_GPIO_MONID;
103 else if ((rdev->family == CHIP_R300) ||
104 (rdev->family == CHIP_R350))
105 reg = RADEON_GPIO_DVI_DDC;
106 else
107 reg = RADEON_GPIO_CRT2_DDC;
108
109 mutex_lock(&rdev->dc_hw_i2c_mutex);
110 if (rec->a_clk_reg == reg) {
6a93cb25
AD		 111 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
112 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
113 } else {
114 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
115 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
116 }
40bacf16 117 mutex_unlock(&rdev->dc_hw_i2c_mutex);
771fe6b9
JG		 118 }
119 }
771fe6b9 120
5786e2c5
AD		 121 /* switch the pads to ddc mode */
122 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
123 temp = RREG32(rec->mask_clk_reg);
124 temp &= ~(1 << 16);
125 WREG32(rec->mask_clk_reg, temp);
126 }
127
9b9fe724
AD		 128 /* clear the output pin values */
129 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
130 WREG32(rec->a_clk_reg, temp);
131
132 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
133 WREG32(rec->a_data_reg, temp);
134
6a93cb25
AD		 135 /* set the pins to input */
136 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
137 WREG32(rec->en_clk_reg, temp);
138
139 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
140 WREG32(rec->en_data_reg, temp);
9b9fe724
AD		 141
142 /* mask the gpio pins for software use */
43e5f612 143 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
771fe6b9
JG		 144 WREG32(rec->mask_clk_reg, temp);
145 temp = RREG32(rec->mask_clk_reg);
146
43e5f612
JD		 147 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
148 WREG32(rec->mask_data_reg, temp);
771fe6b9 149 temp = RREG32(rec->mask_data_reg);
43e5f612
JD		 150
151 return 0;
152}
153
154static void post_xfer(struct i2c_adapter *i2c_adap)
155{
156 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
157 struct radeon_device *rdev = i2c->dev->dev_private;
158 struct radeon_i2c_bus_rec *rec = &i2c->rec;
159 uint32_t temp;
160
161 /* unmask the gpio pins for software use */
162 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
163 WREG32(rec->mask_clk_reg, temp);
164 temp = RREG32(rec->mask_clk_reg);
165
166 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
771fe6b9
JG		 167 WREG32(rec->mask_data_reg, temp);
168 temp = RREG32(rec->mask_data_reg);
169}
170
171static int get_clock(void *i2c_priv)
172{
173 struct radeon_i2c_chan *i2c = i2c_priv;
174 struct radeon_device *rdev = i2c->dev->dev_private;
175 struct radeon_i2c_bus_rec *rec = &i2c->rec;
176 uint32_t val;
177
9b9fe724
AD		 178 /* read the value off the pin */
179 val = RREG32(rec->y_clk_reg);
180 val &= rec->y_clk_mask;
771fe6b9
JG		 181
182 return (val != 0);
183}
184
185
186static int get_data(void *i2c_priv)
187{
188 struct radeon_i2c_chan *i2c = i2c_priv;
189 struct radeon_device *rdev = i2c->dev->dev_private;
190 struct radeon_i2c_bus_rec *rec = &i2c->rec;
191 uint32_t val;
192
9b9fe724
AD		 193 /* read the value off the pin */
194 val = RREG32(rec->y_data_reg);
195 val &= rec->y_data_mask;
196
771fe6b9
JG		 197 return (val != 0);
198}
199
200static void set_clock(void *i2c_priv, int clock)
201{
202 struct radeon_i2c_chan *i2c = i2c_priv;
203 struct radeon_device *rdev = i2c->dev->dev_private;
204 struct radeon_i2c_bus_rec *rec = &i2c->rec;
205 uint32_t val;
206
9b9fe724
AD		 207 /* set pin direction */
208 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
209 val |= clock ? 0 : rec->en_clk_mask;
210 WREG32(rec->en_clk_reg, val);
771fe6b9
JG		 211}
212
213static void set_data(void *i2c_priv, int data)
214{
215 struct radeon_i2c_chan *i2c = i2c_priv;
216 struct radeon_device *rdev = i2c->dev->dev_private;
217 struct radeon_i2c_bus_rec *rec = &i2c->rec;
218 uint32_t val;
219
9b9fe724
AD		 220 /* set pin direction */
221 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
222 val |= data ? 0 : rec->en_data_mask;
223 WREG32(rec->en_data_reg, val);
771fe6b9
JG		 224}
225
ac1aade6
AD		 226/* hw i2c */
227
9dad76e8
AD		 228static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
229{
8807286e 230 u32 sclk = rdev->pm.current_sclk;
9dad76e8 231 u32 prescale = 0;
96a4c8d5
AD		 232 u32 nm;
233 u8 n, m, loop;
9dad76e8
AD		 234 int i2c_clock;
235
236 switch (rdev->family) {
237 case CHIP_R100:
238 case CHIP_RV100:
239 case CHIP_RS100:
240 case CHIP_RV200:
241 case CHIP_RS200:
242 case CHIP_R200:
243 case CHIP_RV250:
244 case CHIP_RS300:
245 case CHIP_RV280:
246 case CHIP_R300:
247 case CHIP_R350:
248 case CHIP_RV350:
96a4c8d5
AD		 249 i2c_clock = 60;
250 nm = (sclk * 10) / (i2c_clock * 4);
9dad76e8 251 for (loop = 1; loop < 255; loop++) {
96a4c8d5 252 if ((nm / loop) < loop)
9dad76e8
AD		 253 break;
254 }
96a4c8d5
AD		 255 n = loop - 1;
256 m = loop - 2;
257 prescale = m | (n << 8);
9dad76e8
AD		 258 break;
259 case CHIP_RV380:
260 case CHIP_RS400:
261 case CHIP_RS480:
262 case CHIP_R420:
263 case CHIP_R423:
264 case CHIP_RV410:
9dad76e8
AD		 265 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
266 break;
267 case CHIP_RS600:
268 case CHIP_RS690:
269 case CHIP_RS740:
270 /* todo */
271 break;
272 case CHIP_RV515:
273 case CHIP_R520:
274 case CHIP_RV530:
275 case CHIP_RV560:
276 case CHIP_RV570:
277 case CHIP_R580:
278 i2c_clock = 50;
9dad76e8
AD		 279 if (rdev->family == CHIP_R520)
280 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
281 else
282 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
283 break;
284 case CHIP_R600:
285 case CHIP_RV610:
286 case CHIP_RV630:
287 case CHIP_RV670:
288 /* todo */
289 break;
290 case CHIP_RV620:
291 case CHIP_RV635:
292 case CHIP_RS780:
293 case CHIP_RS880:
294 case CHIP_RV770:
295 case CHIP_RV730:
296 case CHIP_RV710:
297 case CHIP_RV740:
298 /* todo */
299 break;
4c36b678
AD		 300 case CHIP_CEDAR:
301 case CHIP_REDWOOD:
302 case CHIP_JUNIPER:
303 case CHIP_CYPRESS:
304 case CHIP_HEMLOCK:
305 /* todo */
306 break;
9dad76e8
AD		 307 default:
308 DRM_ERROR("i2c: unhandled radeon chip\n");
309 break;
310 }
311 return prescale;
312}
313
314
40bacf16
AD		 315/* hw i2c engine for r1xx-4xx hardware
316 * hw can buffer up to 15 bytes
317 */
318static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
319 struct i2c_msg *msgs, int num)
320{
321 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
322 struct radeon_device *rdev = i2c->dev->dev_private;
323 struct radeon_i2c_bus_rec *rec = &i2c->rec;
324 struct i2c_msg *p;
325 int i, j, k, ret = num;
9dad76e8 326 u32 prescale;
40bacf16
AD		 327 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
328 u32 tmp, reg;
329
330 mutex_lock(&rdev->dc_hw_i2c_mutex);
57fcab62
AD		 331 /* take the pm lock since we need a constant sclk */
332 mutex_lock(&rdev->pm.mutex);
333
9dad76e8 334 prescale = radeon_get_i2c_prescale(rdev);
40bacf16
AD		 335
336 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
ae08819c 337 RADEON_I2C_DRIVE_EN |
40bacf16
AD		 338 RADEON_I2C_START |
339 RADEON_I2C_STOP |
340 RADEON_I2C_GO);
341
342 if (rdev->is_atom_bios) {
343 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
344 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
345 }
346
347 if (rec->mm_i2c) {
348 i2c_cntl_0 = RADEON_I2C_CNTL_0;
349 i2c_cntl_1 = RADEON_I2C_CNTL_1;
350 i2c_data = RADEON_I2C_DATA;
351 } else {
352 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
353 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
354 i2c_data = RADEON_DVI_I2C_DATA;
355
356 switch (rdev->family) {
357 case CHIP_R100:
358 case CHIP_RV100:
359 case CHIP_RS100:
360 case CHIP_RV200:
361 case CHIP_RS200:
362 case CHIP_RS300:
363 switch (rec->mask_clk_reg) {
364 case RADEON_GPIO_DVI_DDC:
365 /* no gpio select bit */
366 break;
367 default:
368 DRM_ERROR("gpio not supported with hw i2c\n");
369 ret = -EINVAL;
370 goto done;
371 }
372 break;
373 case CHIP_R200:
374 /* only bit 4 on r200 */
375 switch (rec->mask_clk_reg) {
376 case RADEON_GPIO_DVI_DDC:
377 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
378 break;
379 case RADEON_GPIO_MONID:
380 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
381 break;
382 default:
383 DRM_ERROR("gpio not supported with hw i2c\n");
384 ret = -EINVAL;
385 goto done;
386 }
387 break;
388 case CHIP_RV250:
389 case CHIP_RV280:
390 /* bits 3 and 4 */
391 switch (rec->mask_clk_reg) {
392 case RADEON_GPIO_DVI_DDC:
393 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
394 break;
395 case RADEON_GPIO_VGA_DDC:
396 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
397 break;
398 case RADEON_GPIO_CRT2_DDC:
399 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
400 break;
401 default:
402 DRM_ERROR("gpio not supported with hw i2c\n");
403 ret = -EINVAL;
404 goto done;
405 }
406 break;
407 case CHIP_R300:
408 case CHIP_R350:
409 /* only bit 4 on r300/r350 */
410 switch (rec->mask_clk_reg) {
411 case RADEON_GPIO_VGA_DDC:
412 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
413 break;
414 case RADEON_GPIO_DVI_DDC:
415 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
416 break;
417 default:
418 DRM_ERROR("gpio not supported with hw i2c\n");
419 ret = -EINVAL;
420 goto done;
421 }
422 break;
423 case CHIP_RV350:
424 case CHIP_RV380:
425 case CHIP_R420:
426 case CHIP_R423:
427 case CHIP_RV410:
428 case CHIP_RS400:
429 case CHIP_RS480:
430 /* bits 3 and 4 */
431 switch (rec->mask_clk_reg) {
432 case RADEON_GPIO_VGA_DDC:
433 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
434 break;
435 case RADEON_GPIO_DVI_DDC:
436 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
437 break;
438 case RADEON_GPIO_MONID:
439 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
440 break;
441 default:
442 DRM_ERROR("gpio not supported with hw i2c\n");
443 ret = -EINVAL;
444 goto done;
445 }
446 break;
447 default:
448 DRM_ERROR("unsupported asic\n");
449 ret = -EINVAL;
450 goto done;
451 break;
452 }
453 }
454
455 /* check for bus probe */
456 p = &msgs[0];
457 if ((num == 1) && (p->len == 0)) {
458 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
459 RADEON_I2C_NACK |
460 RADEON_I2C_HALT |
461 RADEON_I2C_SOFT_RST));
462 WREG32(i2c_data, (p->addr << 1) & 0xff);
463 WREG32(i2c_data, 0);
464 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
465 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
466 RADEON_I2C_EN |
467 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
468 WREG32(i2c_cntl_0, reg);
469 for (k = 0; k < 32; k++) {
470 udelay(10);
471 tmp = RREG32(i2c_cntl_0);
472 if (tmp & RADEON_I2C_GO)
473 continue;
474 tmp = RREG32(i2c_cntl_0);
475 if (tmp & RADEON_I2C_DONE)
476 break;
477 else {
478 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
479 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
480 ret = -EIO;
481 goto done;
482 }
483 }
484 goto done;
485 }
486
487 for (i = 0; i < num; i++) {
488 p = &msgs[i];
489 for (j = 0; j < p->len; j++) {
490 if (p->flags & I2C_M_RD) {
491 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
492 RADEON_I2C_NACK |
493 RADEON_I2C_HALT |
494 RADEON_I2C_SOFT_RST));
495 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
496 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
497 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
498 RADEON_I2C_EN |
499 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
500 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
501 for (k = 0; k < 32; k++) {
502 udelay(10);
503 tmp = RREG32(i2c_cntl_0);
504 if (tmp & RADEON_I2C_GO)
505 continue;
506 tmp = RREG32(i2c_cntl_0);
507 if (tmp & RADEON_I2C_DONE)
508 break;
509 else {
510 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
511 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
512 ret = -EIO;
513 goto done;
514 }
515 }
516 p->buf[j] = RREG32(i2c_data) & 0xff;
517 } else {
518 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
519 RADEON_I2C_NACK |
520 RADEON_I2C_HALT |
521 RADEON_I2C_SOFT_RST));
522 WREG32(i2c_data, (p->addr << 1) & 0xff);
523 WREG32(i2c_data, p->buf[j]);
524 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
525 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
526 RADEON_I2C_EN |
527 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
528 WREG32(i2c_cntl_0, reg);
529 for (k = 0; k < 32; k++) {
530 udelay(10);
531 tmp = RREG32(i2c_cntl_0);
532 if (tmp & RADEON_I2C_GO)
533 continue;
534 tmp = RREG32(i2c_cntl_0);
535 if (tmp & RADEON_I2C_DONE)
536 break;
537 else {
538 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
539 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
540 ret = -EIO;
541 goto done;
542 }
543 }
544 }
545 }
546 }
547
548done:
549 WREG32(i2c_cntl_0, 0);
550 WREG32(i2c_cntl_1, 0);
551 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
552 RADEON_I2C_NACK |
553 RADEON_I2C_HALT |
554 RADEON_I2C_SOFT_RST));
555
556 if (rdev->is_atom_bios) {
557 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
558 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
559 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
560 }
561
57fcab62 562 mutex_unlock(&rdev->pm.mutex);
40bacf16
AD		 563 mutex_unlock(&rdev->dc_hw_i2c_mutex);
564
565 return ret;
566}
567
568/* hw i2c engine for r5xx hardware
569 * hw can buffer up to 15 bytes
570 */
571static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
572 struct i2c_msg *msgs, int num)
573{
574 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
575 struct radeon_device *rdev = i2c->dev->dev_private;
576 struct radeon_i2c_bus_rec *rec = &i2c->rec;
577 struct i2c_msg *p;
40bacf16 578 int i, j, remaining, current_count, buffer_offset, ret = num;
9dad76e8 579 u32 prescale;
40bacf16
AD		 580 u32 tmp, reg;
581 u32 saved1, saved2;
582
583 mutex_lock(&rdev->dc_hw_i2c_mutex);
57fcab62
AD		 584 /* take the pm lock since we need a constant sclk */
585 mutex_lock(&rdev->pm.mutex);
586
9dad76e8 587 prescale = radeon_get_i2c_prescale(rdev);
40bacf16
AD		 588
589 /* clear gpio mask bits */
590 tmp = RREG32(rec->mask_clk_reg);
591 tmp &= ~rec->mask_clk_mask;
592 WREG32(rec->mask_clk_reg, tmp);
593 tmp = RREG32(rec->mask_clk_reg);
594
595 tmp = RREG32(rec->mask_data_reg);
596 tmp &= ~rec->mask_data_mask;
597 WREG32(rec->mask_data_reg, tmp);
598 tmp = RREG32(rec->mask_data_reg);
599
600 /* clear pin values */
601 tmp = RREG32(rec->a_clk_reg);
602 tmp &= ~rec->a_clk_mask;
603 WREG32(rec->a_clk_reg, tmp);
604 tmp = RREG32(rec->a_clk_reg);
605
606 tmp = RREG32(rec->a_data_reg);
607 tmp &= ~rec->a_data_mask;
608 WREG32(rec->a_data_reg, tmp);
609 tmp = RREG32(rec->a_data_reg);
610
611 /* set the pins to input */
612 tmp = RREG32(rec->en_clk_reg);
613 tmp &= ~rec->en_clk_mask;
614 WREG32(rec->en_clk_reg, tmp);
615 tmp = RREG32(rec->en_clk_reg);
616
617 tmp = RREG32(rec->en_data_reg);
618 tmp &= ~rec->en_data_mask;
619 WREG32(rec->en_data_reg, tmp);
620 tmp = RREG32(rec->en_data_reg);
621
622 /* */
623 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
624 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
625 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
626 saved2 = RREG32(0x494);
627 WREG32(0x494, saved2 | 0x1);
628
629 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
630 for (i = 0; i < 50; i++) {
631 udelay(1);
632 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
633 break;
634 }
635 if (i == 50) {
636 DRM_ERROR("failed to get i2c bus\n");
637 ret = -EBUSY;
638 goto done;
639 }
640
40bacf16
AD		 641 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
642 switch (rec->mask_clk_reg) {
643 case AVIVO_DC_GPIO_DDC1_MASK:
644 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
645 break;
646 case AVIVO_DC_GPIO_DDC2_MASK:
647 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
648 break;
649 case AVIVO_DC_GPIO_DDC3_MASK:
650 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
651 break;
652 default:
653 DRM_ERROR("gpio not supported with hw i2c\n");
654 ret = -EINVAL;
655 goto done;
656 }
657
658 /* check for bus probe */
659 p = &msgs[0];
660 if ((num == 1) && (p->len == 0)) {
661 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
662 AVIVO_DC_I2C_NACK |
663 AVIVO_DC_I2C_HALT));
664 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
665 udelay(1);
666 WREG32(AVIVO_DC_I2C_RESET, 0);
667
668 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
669 WREG32(AVIVO_DC_I2C_DATA, 0);
670
671 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
672 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
673 AVIVO_DC_I2C_DATA_COUNT(1) |
674 (prescale << 16)));
675 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
676 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
677 for (j = 0; j < 200; j++) {
678 udelay(50);
679 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
680 if (tmp & AVIVO_DC_I2C_GO)
681 continue;
682 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
683 if (tmp & AVIVO_DC_I2C_DONE)
684 break;
685 else {
686 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
687 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
688 ret = -EIO;
689 goto done;
690 }
691 }
692 goto done;
693 }
694
695 for (i = 0; i < num; i++) {
696 p = &msgs[i];
697 remaining = p->len;
698 buffer_offset = 0;
699 if (p->flags & I2C_M_RD) {
700 while (remaining) {
701 if (remaining > 15)
702 current_count = 15;
703 else
704 current_count = remaining;
705 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
706 AVIVO_DC_I2C_NACK |
707 AVIVO_DC_I2C_HALT));
708 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
709 udelay(1);
710 WREG32(AVIVO_DC_I2C_RESET, 0);
711
712 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
713 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
714 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
715 AVIVO_DC_I2C_DATA_COUNT(current_count) |
716 (prescale << 16)));
717 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
718 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
719 for (j = 0; j < 200; j++) {
720 udelay(50);
721 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
722 if (tmp & AVIVO_DC_I2C_GO)
723 continue;
724 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
725 if (tmp & AVIVO_DC_I2C_DONE)
726 break;
727 else {
728 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
729 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
730 ret = -EIO;
731 goto done;
732 }
733 }
734 for (j = 0; j < current_count; j++)
735 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
736 remaining -= current_count;
737 buffer_offset += current_count;
738 }
739 } else {
740 while (remaining) {
741 if (remaining > 15)
742 current_count = 15;
743 else
744 current_count = remaining;
745 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
746 AVIVO_DC_I2C_NACK |
747 AVIVO_DC_I2C_HALT));
748 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
749 udelay(1);
750 WREG32(AVIVO_DC_I2C_RESET, 0);
751
752 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
753 for (j = 0; j < current_count; j++)
754 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
755
756 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
757 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
758 AVIVO_DC_I2C_DATA_COUNT(current_count) |
759 (prescale << 16)));
760 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
761 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
762 for (j = 0; j < 200; j++) {
763 udelay(50);
764 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
765 if (tmp & AVIVO_DC_I2C_GO)
766 continue;
767 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
768 if (tmp & AVIVO_DC_I2C_DONE)
769 break;
770 else {
771 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
772 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
773 ret = -EIO;
774 goto done;
775 }
776 }
777 remaining -= current_count;
778 buffer_offset += current_count;
779 }
780 }
781 }
782
783done:
784 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
785 AVIVO_DC_I2C_NACK |
786 AVIVO_DC_I2C_HALT));
787 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
788 udelay(1);
789 WREG32(AVIVO_DC_I2C_RESET, 0);
790
791 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
792 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
793 WREG32(0x494, saved2);
794 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
795 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
796 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
797
57fcab62 798 mutex_unlock(&rdev->pm.mutex);
40bacf16
AD		 799 mutex_unlock(&rdev->dc_hw_i2c_mutex);
800
801 return ret;
802}
803
ac1aade6 804static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
40bacf16 805 struct i2c_msg *msgs, int num)
40bacf16
AD		 806{
807 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
808 struct radeon_device *rdev = i2c->dev->dev_private;
809 struct radeon_i2c_bus_rec *rec = &i2c->rec;
ac1aade6 810 int ret = 0;
40bacf16
AD		 811
812 switch (rdev->family) {
813 case CHIP_R100:
814 case CHIP_RV100:
815 case CHIP_RS100:
816 case CHIP_RV200:
817 case CHIP_RS200:
818 case CHIP_R200:
819 case CHIP_RV250:
820 case CHIP_RS300:
821 case CHIP_RV280:
822 case CHIP_R300:
823 case CHIP_R350:
824 case CHIP_RV350:
825 case CHIP_RV380:
826 case CHIP_R420:
827 case CHIP_R423:
828 case CHIP_RV410:
829 case CHIP_RS400:
830 case CHIP_RS480:
ac1aade6 831 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
40bacf16
AD		 832 break;
833 case CHIP_RS600:
834 case CHIP_RS690:
835 case CHIP_RS740:
836 /* XXX fill in hw i2c implementation */
40bacf16
AD		 837 break;
838 case CHIP_RV515:
839 case CHIP_R520:
840 case CHIP_RV530:
841 case CHIP_RV560:
842 case CHIP_RV570:
843 case CHIP_R580:
ac1aade6
AD		 844 if (rec->mm_i2c)
845 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
846 else
847 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
40bacf16
AD		 848 break;
849 case CHIP_R600:
850 case CHIP_RV610:
851 case CHIP_RV630:
852 case CHIP_RV670:
853 /* XXX fill in hw i2c implementation */
40bacf16
AD		 854 break;
855 case CHIP_RV620:
856 case CHIP_RV635:
857 case CHIP_RS780:
858 case CHIP_RS880:
859 case CHIP_RV770:
860 case CHIP_RV730:
861 case CHIP_RV710:
862 case CHIP_RV740:
863 /* XXX fill in hw i2c implementation */
40bacf16 864 break;
4c36b678
AD		 865 case CHIP_CEDAR:
866 case CHIP_REDWOOD:
867 case CHIP_JUNIPER:
868 case CHIP_CYPRESS:
869 case CHIP_HEMLOCK:
870 /* XXX fill in hw i2c implementation */
4c36b678 871 break;
40bacf16
AD		 872 default:
873 DRM_ERROR("i2c: unhandled radeon chip\n");
874 ret = -EIO;
875 break;
876 }
877
878 return ret;
879}
880
ac1aade6 881static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
5a6f98f5
AD		 882{
883 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
884}
885
886static const struct i2c_algorithm radeon_i2c_algo = {
ac1aade6
AD		 887 .master_xfer = radeon_hw_i2c_xfer,
888 .functionality = radeon_hw_i2c_func,
5a6f98f5
AD		 889};
890
771fe6b9 891struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
ab1e9ea0
AD		 892 struct radeon_i2c_bus_rec *rec,
893 const char *name)
771fe6b9 894{
ac1aade6 895 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 896 struct radeon_i2c_chan *i2c;
897 int ret;
898
9a298b2a 899 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
771fe6b9
JG		 900 if (i2c == NULL)
901 return NULL;
902
40bacf16 903 i2c->rec = *rec;
5a6f98f5 904 i2c->adapter.owner = THIS_MODULE;
87d7a1f9 905 i2c->adapter.class = I2C_CLASS_DDC;
ac1aade6 906 i2c->dev = dev;
5a6f98f5 907 i2c_set_adapdata(&i2c->adapter, i2c);
e2b0a8e1
AD		 908 if (rec->mm_i2c ||
909 (rec->hw_capable &&
910 radeon_hw_i2c &&
911 ((rdev->family <= CHIP_RS480) ||
912 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
ac1aade6 913 /* set the radeon hw i2c adapter */
164bcb94
AD		 914 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
915 "Radeon i2c hw bus %s", name);
ac1aade6
AD		 916 i2c->adapter.algo = &radeon_i2c_algo;
917 ret = i2c_add_adapter(&i2c->adapter);
918 if (ret) {
919 DRM_ERROR("Failed to register hw i2c %s\n", name);
920 goto out_free;
921 }
922 } else {
923 /* set the radeon bit adapter */
164bcb94
AD		 924 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
925 "Radeon i2c bit bus %s", name);
ac1aade6
AD		 926 i2c->adapter.algo_data = &i2c->algo.bit;
927 i2c->algo.bit.pre_xfer = pre_xfer;
928 i2c->algo.bit.post_xfer = post_xfer;
929 i2c->algo.bit.setsda = set_data;
930 i2c->algo.bit.setscl = set_clock;
931 i2c->algo.bit.getsda = get_data;
932 i2c->algo.bit.getscl = get_clock;
933 i2c->algo.bit.udelay = 20;
934 /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
935 * make this, 2 jiffies is a lot more reliable */
936 i2c->algo.bit.timeout = 2;
937 i2c->algo.bit.data = i2c;
938 ret = i2c_bit_add_bus(&i2c->adapter);
939 if (ret) {
940 DRM_ERROR("Failed to register bit i2c %s\n", name);
941 goto out_free;
942 }
771fe6b9
JG		 943 }
944
945 return i2c;
946out_free:
9a298b2a 947 kfree(i2c);
771fe6b9
JG		 948 return NULL;
949
950}
951
746c1aa4 952struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
6a93cb25
AD		 953 struct radeon_i2c_bus_rec *rec,
954 const char *name)
746c1aa4
DA		 955{
956 struct radeon_i2c_chan *i2c;
957 int ret;
958
959 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
960 if (i2c == NULL)
961 return NULL;
962
6a93cb25 963 i2c->rec = *rec;
746c1aa4 964 i2c->adapter.owner = THIS_MODULE;
87d7a1f9 965 i2c->adapter.class = I2C_CLASS_DDC;
746c1aa4 966 i2c->dev = dev;
164bcb94
AD		 967 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
968 "Radeon aux bus %s", name);
746c1aa4
DA		 969 i2c_set_adapdata(&i2c->adapter, i2c);
970 i2c->adapter.algo_data = &i2c->algo.dp;
971 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
972 i2c->algo.dp.address = 0;
973 ret = i2c_dp_aux_add_bus(&i2c->adapter);
974 if (ret) {
975 DRM_INFO("Failed to register i2c %s\n", name);
976 goto out_free;
977 }
978
979 return i2c;
980out_free:
981 kfree(i2c);
982 return NULL;
983
984}
985
771fe6b9 986void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
5a6f98f5
AD		 987{
988 if (!i2c)
989 return;
771fe6b9 990 i2c_del_adapter(&i2c->adapter);
9a298b2a 991 kfree(i2c);
771fe6b9
JG		 992}
993
f376b94f
AD		 994/* Add the default buses */
995void radeon_i2c_init(struct radeon_device *rdev)
996{
997 if (rdev->is_atom_bios)
998 radeon_atombios_i2c_init(rdev);
999 else
1000 radeon_combios_i2c_init(rdev);
1001}
1002
1003/* remove all the buses */
1004void radeon_i2c_fini(struct radeon_device *rdev)
1005{
1006 int i;
1007
1008 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1009 if (rdev->i2c_bus[i]) {
1010 radeon_i2c_destroy(rdev->i2c_bus[i]);
1011 rdev->i2c_bus[i] = NULL;
1012 }
1013 }
1014}
1015
1016/* Add additional buses */
1017void radeon_i2c_add(struct radeon_device *rdev,
1018 struct radeon_i2c_bus_rec *rec,
1019 const char *name)
1020{
1021 struct drm_device *dev = rdev->ddev;
1022 int i;
1023
1024 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1025 if (!rdev->i2c_bus[i]) {
1026 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1027 return;
1028 }
1029 }
1030}
1031
1032/* looks up bus based on id */
1033struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1034 struct radeon_i2c_bus_rec *i2c_bus)
1035{
1036 int i;
1037
1038 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1039 if (rdev->i2c_bus[i] &&
1040 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1041 return rdev->i2c_bus[i];
1042 }
1043 }
1044 return NULL;
1045}
1046
771fe6b9
JG		 1047struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
1048{
1049 return NULL;
1050}
fcec570b 1051
5a6f98f5
AD		 1052void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1053 u8 slave_addr,
1054 u8 addr,
1055 u8 *val)
fcec570b
AD		 1056{
1057 u8 out_buf[2];
1058 u8 in_buf[2];
1059 struct i2c_msg msgs[] = {
1060 {
1061 .addr = slave_addr,
1062 .flags = 0,
1063 .len = 1,
1064 .buf = out_buf,
1065 },
1066 {
1067 .addr = slave_addr,
1068 .flags = I2C_M_RD,
1069 .len = 1,
1070 .buf = in_buf,
1071 }
1072 };
1073
1074 out_buf[0] = addr;
1075 out_buf[1] = 0;
1076
1077 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
1078 *val = in_buf[0];
1079 DRM_DEBUG("val = 0x%02x\n", *val);
1080 } else {
d4864d60 1081 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
fcec570b
AD		 1082 addr, *val);
1083 }
1084}
1085
5a6f98f5
AD		 1086void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1087 u8 slave_addr,
1088 u8 addr,
1089 u8 val)
fcec570b
AD		 1090{
1091 uint8_t out_buf[2];
1092 struct i2c_msg msg = {
1093 .addr = slave_addr,
1094 .flags = 0,
1095 .len = 2,
1096 .buf = out_buf,
1097 };
1098
1099 out_buf[0] = addr;
1100 out_buf[1] = val;
1101
1102 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
d4864d60 1103 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
fcec570b
AD		 1104 addr, val);
1105}
1106
fb939dfc
AD		 1107/* ddc router switching */
1108void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
26b5bc98
AD		 1109{
1110 u8 val;
1111
fb939dfc 1112 if (!radeon_connector->router.ddc_valid)
26b5bc98
AD		 1113 return;
1114
a70882aa
AD		 1115 if (!radeon_connector->router_bus)
1116 return;
1117
26b5bc98
AD		 1118 radeon_i2c_get_byte(radeon_connector->router_bus,
1119 radeon_connector->router.i2c_addr,
1120 0x3, &val);
bdd91b2b 1121 val &= ~radeon_connector->router.ddc_mux_control_pin;
26b5bc98
AD		 1122 radeon_i2c_put_byte(radeon_connector->router_bus,
1123 radeon_connector->router.i2c_addr,
1124 0x3, val);
1125 radeon_i2c_get_byte(radeon_connector->router_bus,
1126 radeon_connector->router.i2c_addr,
1127 0x1, &val);
bdd91b2b 1128 val &= ~radeon_connector->router.ddc_mux_control_pin;
fb939dfc
AD		 1129 val |= radeon_connector->router.ddc_mux_state;
1130 radeon_i2c_put_byte(radeon_connector->router_bus,
1131 radeon_connector->router.i2c_addr,
1132 0x1, val);
1133}
1134
1135/* clock/data router switching */
1136void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
1137{
1138 u8 val;
1139
1140 if (!radeon_connector->router.cd_valid)
1141 return;
1142
a70882aa
AD		 1143 if (!radeon_connector->router_bus)
1144 return;
1145
fb939dfc
AD		 1146 radeon_i2c_get_byte(radeon_connector->router_bus,
1147 radeon_connector->router.i2c_addr,
1148 0x3, &val);
bdd91b2b 1149 val &= ~radeon_connector->router.cd_mux_control_pin;
fb939dfc
AD		 1150 radeon_i2c_put_byte(radeon_connector->router_bus,
1151 radeon_connector->router.i2c_addr,
1152 0x3, val);
1153 radeon_i2c_get_byte(radeon_connector->router_bus,
1154 radeon_connector->router.i2c_addr,
1155 0x1, &val);
bdd91b2b 1156 val &= ~radeon_connector->router.cd_mux_control_pin;
fb939dfc 1157 val |= radeon_connector->router.cd_mux_state;
26b5bc98
AD		 1158 radeon_i2c_put_byte(radeon_connector->router_bus,
1159 radeon_connector->router.i2c_addr,
1160 0x1, val);
1161}
1162
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