]>
Commit | Line | Data |
---|---|---|
771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/drm_crtc_helper.h> | |
30 | #include <drm/radeon_drm.h> | |
771fe6b9 | 31 | #include "radeon_reg.h" |
771fe6b9 JG |
32 | #include "radeon.h" |
33 | #include "atom.h" | |
34 | ||
fb98257a CK |
35 | #define RADEON_WAIT_IDLE_TIMEOUT 200 |
36 | ||
b73ba98d AD |
37 | /** |
38 | * radeon_driver_irq_handler_kms - irq handler for KMS | |
39 | * | |
40 | * @DRM_IRQ_ARGS: args | |
41 | * | |
42 | * This is the irq handler for the radeon KMS driver (all asics). | |
43 | * radeon_irq_process is a macro that points to the per-asic | |
44 | * irq handler callback. | |
45 | */ | |
771fe6b9 JG |
46 | irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS) |
47 | { | |
48 | struct drm_device *dev = (struct drm_device *) arg; | |
49 | struct radeon_device *rdev = dev->dev_private; | |
50 | ||
51 | return radeon_irq_process(rdev); | |
52 | } | |
53 | ||
d4877cf2 AD |
54 | /* |
55 | * Handle hotplug events outside the interrupt handler proper. | |
56 | */ | |
b73ba98d AD |
57 | /** |
58 | * radeon_hotplug_work_func - display hotplug work handler | |
59 | * | |
60 | * @work: work struct | |
61 | * | |
62 | * This is the hot plug event work handler (all asics). | |
63 | * The work gets scheduled from the irq handler if there | |
64 | * was a hot plug interrupt. It walks the connector table | |
65 | * and calls the hotplug handler for each one, then sends | |
66 | * a drm hotplug event to alert userspace. | |
67 | */ | |
d4877cf2 AD |
68 | static void radeon_hotplug_work_func(struct work_struct *work) |
69 | { | |
70 | struct radeon_device *rdev = container_of(work, struct radeon_device, | |
71 | hotplug_work); | |
72 | struct drm_device *dev = rdev->ddev; | |
73 | struct drm_mode_config *mode_config = &dev->mode_config; | |
74 | struct drm_connector *connector; | |
75 | ||
76 | if (mode_config->num_connector) { | |
77 | list_for_each_entry(connector, &mode_config->connector_list, head) | |
78 | radeon_connector_hotplug(connector); | |
79 | } | |
80 | /* Just fire off a uevent and let userspace tell us what to do */ | |
eb1f8e4f | 81 | drm_helper_hpd_irq_event(dev); |
d4877cf2 AD |
82 | } |
83 | ||
b73ba98d AD |
84 | /** |
85 | * radeon_driver_irq_preinstall_kms - drm irq preinstall callback | |
86 | * | |
87 | * @dev: drm dev pointer | |
88 | * | |
89 | * Gets the hw ready to enable irqs (all asics). | |
90 | * This function disables all interrupt sources on the GPU. | |
91 | */ | |
771fe6b9 JG |
92 | void radeon_driver_irq_preinstall_kms(struct drm_device *dev) |
93 | { | |
94 | struct radeon_device *rdev = dev->dev_private; | |
fb98257a | 95 | unsigned long irqflags; |
771fe6b9 JG |
96 | unsigned i; |
97 | ||
fb98257a | 98 | spin_lock_irqsave(&rdev->irq.lock, irqflags); |
771fe6b9 | 99 | /* Disable *all* interrupts */ |
1b37078b | 100 | for (i = 0; i < RADEON_NUM_RINGS; i++) |
736fc37f | 101 | atomic_set(&rdev->irq.ring_int[i], 0); |
54bd5206 | 102 | for (i = 0; i < RADEON_MAX_HPD_PINS; i++) |
9e7b414e | 103 | rdev->irq.hpd[i] = false; |
54bd5206 IH |
104 | for (i = 0; i < RADEON_MAX_CRTCS; i++) { |
105 | rdev->irq.crtc_vblank_int[i] = false; | |
736fc37f | 106 | atomic_set(&rdev->irq.pflip[i], 0); |
f122c610 | 107 | rdev->irq.afmt[i] = false; |
6f34be50 | 108 | } |
771fe6b9 | 109 | radeon_irq_set(rdev); |
fb98257a | 110 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); |
771fe6b9 JG |
111 | /* Clear bits */ |
112 | radeon_irq_process(rdev); | |
113 | } | |
114 | ||
b73ba98d AD |
115 | /** |
116 | * radeon_driver_irq_postinstall_kms - drm irq preinstall callback | |
117 | * | |
118 | * @dev: drm dev pointer | |
119 | * | |
120 | * Handles stuff to be done after enabling irqs (all asics). | |
121 | * Returns 0 on success. | |
122 | */ | |
771fe6b9 JG |
123 | int radeon_driver_irq_postinstall_kms(struct drm_device *dev) |
124 | { | |
771fe6b9 | 125 | dev->max_vblank_count = 0x001fffff; |
771fe6b9 JG |
126 | return 0; |
127 | } | |
128 | ||
b73ba98d AD |
129 | /** |
130 | * radeon_driver_irq_uninstall_kms - drm irq uninstall callback | |
131 | * | |
132 | * @dev: drm dev pointer | |
133 | * | |
134 | * This function disables all interrupt sources on the GPU (all asics). | |
135 | */ | |
771fe6b9 JG |
136 | void radeon_driver_irq_uninstall_kms(struct drm_device *dev) |
137 | { | |
138 | struct radeon_device *rdev = dev->dev_private; | |
fb98257a | 139 | unsigned long irqflags; |
771fe6b9 JG |
140 | unsigned i; |
141 | ||
142 | if (rdev == NULL) { | |
143 | return; | |
144 | } | |
fb98257a | 145 | spin_lock_irqsave(&rdev->irq.lock, irqflags); |
771fe6b9 | 146 | /* Disable *all* interrupts */ |
1b37078b | 147 | for (i = 0; i < RADEON_NUM_RINGS; i++) |
736fc37f | 148 | atomic_set(&rdev->irq.ring_int[i], 0); |
54bd5206 | 149 | for (i = 0; i < RADEON_MAX_HPD_PINS; i++) |
003e69f9 | 150 | rdev->irq.hpd[i] = false; |
54bd5206 IH |
151 | for (i = 0; i < RADEON_MAX_CRTCS; i++) { |
152 | rdev->irq.crtc_vblank_int[i] = false; | |
736fc37f | 153 | atomic_set(&rdev->irq.pflip[i], 0); |
f122c610 | 154 | rdev->irq.afmt[i] = false; |
6f34be50 | 155 | } |
771fe6b9 | 156 | radeon_irq_set(rdev); |
fb98257a | 157 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); |
771fe6b9 JG |
158 | } |
159 | ||
b73ba98d AD |
160 | /** |
161 | * radeon_msi_ok - asic specific msi checks | |
162 | * | |
163 | * @rdev: radeon device pointer | |
164 | * | |
165 | * Handles asic specific MSI checks to determine if | |
166 | * MSIs should be enabled on a particular chip (all asics). | |
167 | * Returns true if MSIs should be enabled, false if MSIs | |
168 | * should not be enabled. | |
169 | */ | |
8f6c25c5 AD |
170 | static bool radeon_msi_ok(struct radeon_device *rdev) |
171 | { | |
172 | /* RV370/RV380 was first asic with MSI support */ | |
173 | if (rdev->family < CHIP_RV380) | |
174 | return false; | |
175 | ||
176 | /* MSIs don't work on AGP */ | |
177 | if (rdev->flags & RADEON_IS_AGP) | |
178 | return false; | |
179 | ||
a18cee15 AD |
180 | /* force MSI on */ |
181 | if (radeon_msi == 1) | |
182 | return true; | |
183 | else if (radeon_msi == 0) | |
184 | return false; | |
185 | ||
b362105f AD |
186 | /* Quirks */ |
187 | /* HP RS690 only seems to work with MSIs. */ | |
188 | if ((rdev->pdev->device == 0x791f) && | |
189 | (rdev->pdev->subsystem_vendor == 0x103c) && | |
190 | (rdev->pdev->subsystem_device == 0x30c2)) | |
191 | return true; | |
192 | ||
44517c44 AD |
193 | /* Dell RS690 only seems to work with MSIs. */ |
194 | if ((rdev->pdev->device == 0x791f) && | |
195 | (rdev->pdev->subsystem_vendor == 0x1028) && | |
196 | (rdev->pdev->subsystem_device == 0x01fc)) | |
197 | return true; | |
198 | ||
01e718ec AD |
199 | /* Dell RS690 only seems to work with MSIs. */ |
200 | if ((rdev->pdev->device == 0x791f) && | |
201 | (rdev->pdev->subsystem_vendor == 0x1028) && | |
202 | (rdev->pdev->subsystem_device == 0x01fd)) | |
203 | return true; | |
204 | ||
3a6d59df AD |
205 | /* Gateway RS690 only seems to work with MSIs. */ |
206 | if ((rdev->pdev->device == 0x791f) && | |
207 | (rdev->pdev->subsystem_vendor == 0x107b) && | |
208 | (rdev->pdev->subsystem_device == 0x0185)) | |
209 | return true; | |
210 | ||
fb6ca6d1 AD |
211 | /* try and enable MSIs by default on all RS690s */ |
212 | if (rdev->family == CHIP_RS690) | |
213 | return true; | |
214 | ||
16a5e32b DA |
215 | /* RV515 seems to have MSI issues where it loses |
216 | * MSI rearms occasionally. This leads to lockups and freezes. | |
217 | * disable it by default. | |
218 | */ | |
219 | if (rdev->family == CHIP_RV515) | |
220 | return false; | |
8f6c25c5 AD |
221 | if (rdev->flags & RADEON_IS_IGP) { |
222 | /* APUs work fine with MSIs */ | |
223 | if (rdev->family >= CHIP_PALM) | |
224 | return true; | |
225 | /* lots of IGPs have problems with MSIs */ | |
226 | return false; | |
227 | } | |
228 | ||
229 | return true; | |
230 | } | |
231 | ||
b73ba98d AD |
232 | /** |
233 | * radeon_irq_kms_init - init driver interrupt info | |
234 | * | |
235 | * @rdev: radeon device pointer | |
236 | * | |
237 | * Sets up the work irq handlers, vblank init, MSIs, etc. (all asics). | |
238 | * Returns 0 for success, error for failure. | |
239 | */ | |
771fe6b9 JG |
240 | int radeon_irq_kms_init(struct radeon_device *rdev) |
241 | { | |
242 | int r = 0; | |
243 | ||
32c87fca | 244 | INIT_WORK(&rdev->hotplug_work, radeon_hotplug_work_func); |
f122c610 | 245 | INIT_WORK(&rdev->audio_work, r600_audio_update_hdmi); |
32c87fca | 246 | |
fb98257a | 247 | spin_lock_init(&rdev->irq.lock); |
9e7b414e | 248 | r = drm_vblank_init(rdev->ddev, rdev->num_crtc); |
771fe6b9 JG |
249 | if (r) { |
250 | return r; | |
251 | } | |
3e5cb98d AD |
252 | /* enable msi */ |
253 | rdev->msi_enabled = 0; | |
8f6c25c5 AD |
254 | |
255 | if (radeon_msi_ok(rdev)) { | |
3e5cb98d | 256 | int ret = pci_enable_msi(rdev->pdev); |
d8f60cfc | 257 | if (!ret) { |
3e5cb98d | 258 | rdev->msi_enabled = 1; |
da7be684 | 259 | dev_info(rdev->dev, "radeon: using MSI.\n"); |
d8f60cfc | 260 | } |
3e5cb98d | 261 | } |
771fe6b9 | 262 | rdev->irq.installed = true; |
003e69f9 JG |
263 | r = drm_irq_install(rdev->ddev); |
264 | if (r) { | |
265 | rdev->irq.installed = false; | |
266 | return r; | |
267 | } | |
771fe6b9 JG |
268 | DRM_INFO("radeon: irq initialized.\n"); |
269 | return 0; | |
270 | } | |
271 | ||
b73ba98d AD |
272 | /** |
273 | * radeon_irq_kms_fini - tear down driver interrrupt info | |
274 | * | |
275 | * @rdev: radeon device pointer | |
276 | * | |
277 | * Tears down the work irq handlers, vblank handlers, MSIs, etc. (all asics). | |
278 | */ | |
771fe6b9 JG |
279 | void radeon_irq_kms_fini(struct radeon_device *rdev) |
280 | { | |
003e69f9 | 281 | drm_vblank_cleanup(rdev->ddev); |
771fe6b9 | 282 | if (rdev->irq.installed) { |
771fe6b9 | 283 | drm_irq_uninstall(rdev->ddev); |
003e69f9 | 284 | rdev->irq.installed = false; |
3e5cb98d AD |
285 | if (rdev->msi_enabled) |
286 | pci_disable_msi(rdev->pdev); | |
771fe6b9 | 287 | } |
43829731 | 288 | flush_work(&rdev->hotplug_work); |
771fe6b9 | 289 | } |
1614f8b1 | 290 | |
b73ba98d AD |
291 | /** |
292 | * radeon_irq_kms_sw_irq_get - enable software interrupt | |
293 | * | |
294 | * @rdev: radeon device pointer | |
295 | * @ring: ring whose interrupt you want to enable | |
296 | * | |
297 | * Enables the software interrupt for a specific ring (all asics). | |
298 | * The software interrupt is generally used to signal a fence on | |
299 | * a particular ring. | |
300 | */ | |
1b37078b | 301 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring) |
1614f8b1 DA |
302 | { |
303 | unsigned long irqflags; | |
304 | ||
736fc37f CK |
305 | if (!rdev->ddev->irq_enabled) |
306 | return; | |
307 | ||
308 | if (atomic_inc_return(&rdev->irq.ring_int[ring]) == 1) { | |
309 | spin_lock_irqsave(&rdev->irq.lock, irqflags); | |
1614f8b1 | 310 | radeon_irq_set(rdev); |
736fc37f | 311 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); |
1614f8b1 | 312 | } |
1614f8b1 DA |
313 | } |
314 | ||
b73ba98d AD |
315 | /** |
316 | * radeon_irq_kms_sw_irq_put - disable software interrupt | |
317 | * | |
318 | * @rdev: radeon device pointer | |
319 | * @ring: ring whose interrupt you want to disable | |
320 | * | |
321 | * Disables the software interrupt for a specific ring (all asics). | |
322 | * The software interrupt is generally used to signal a fence on | |
323 | * a particular ring. | |
324 | */ | |
1b37078b | 325 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring) |
1614f8b1 DA |
326 | { |
327 | unsigned long irqflags; | |
328 | ||
736fc37f CK |
329 | if (!rdev->ddev->irq_enabled) |
330 | return; | |
331 | ||
332 | if (atomic_dec_and_test(&rdev->irq.ring_int[ring])) { | |
333 | spin_lock_irqsave(&rdev->irq.lock, irqflags); | |
1614f8b1 | 334 | radeon_irq_set(rdev); |
736fc37f | 335 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); |
1614f8b1 | 336 | } |
1614f8b1 DA |
337 | } |
338 | ||
b73ba98d AD |
339 | /** |
340 | * radeon_irq_kms_pflip_irq_get - enable pageflip interrupt | |
341 | * | |
342 | * @rdev: radeon device pointer | |
343 | * @crtc: crtc whose interrupt you want to enable | |
344 | * | |
345 | * Enables the pageflip interrupt for a specific crtc (all asics). | |
346 | * For pageflips we use the vblank interrupt source. | |
347 | */ | |
6f34be50 AD |
348 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc) |
349 | { | |
350 | unsigned long irqflags; | |
351 | ||
352 | if (crtc < 0 || crtc >= rdev->num_crtc) | |
353 | return; | |
354 | ||
736fc37f CK |
355 | if (!rdev->ddev->irq_enabled) |
356 | return; | |
357 | ||
358 | if (atomic_inc_return(&rdev->irq.pflip[crtc]) == 1) { | |
359 | spin_lock_irqsave(&rdev->irq.lock, irqflags); | |
6f34be50 | 360 | radeon_irq_set(rdev); |
736fc37f | 361 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); |
6f34be50 | 362 | } |
6f34be50 AD |
363 | } |
364 | ||
b73ba98d AD |
365 | /** |
366 | * radeon_irq_kms_pflip_irq_put - disable pageflip interrupt | |
367 | * | |
368 | * @rdev: radeon device pointer | |
369 | * @crtc: crtc whose interrupt you want to disable | |
370 | * | |
371 | * Disables the pageflip interrupt for a specific crtc (all asics). | |
372 | * For pageflips we use the vblank interrupt source. | |
373 | */ | |
6f34be50 AD |
374 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc) |
375 | { | |
376 | unsigned long irqflags; | |
377 | ||
378 | if (crtc < 0 || crtc >= rdev->num_crtc) | |
379 | return; | |
380 | ||
736fc37f CK |
381 | if (!rdev->ddev->irq_enabled) |
382 | return; | |
383 | ||
384 | if (atomic_dec_and_test(&rdev->irq.pflip[crtc])) { | |
385 | spin_lock_irqsave(&rdev->irq.lock, irqflags); | |
6f34be50 | 386 | radeon_irq_set(rdev); |
736fc37f | 387 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); |
6f34be50 | 388 | } |
6f34be50 AD |
389 | } |
390 | ||
b73ba98d AD |
391 | /** |
392 | * radeon_irq_kms_enable_afmt - enable audio format change interrupt | |
393 | * | |
394 | * @rdev: radeon device pointer | |
395 | * @block: afmt block whose interrupt you want to enable | |
396 | * | |
397 | * Enables the afmt change interrupt for a specific afmt block (all asics). | |
398 | */ | |
fb98257a CK |
399 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block) |
400 | { | |
401 | unsigned long irqflags; | |
402 | ||
cc9945bf AD |
403 | if (!rdev->ddev->irq_enabled) |
404 | return; | |
405 | ||
fb98257a CK |
406 | spin_lock_irqsave(&rdev->irq.lock, irqflags); |
407 | rdev->irq.afmt[block] = true; | |
408 | radeon_irq_set(rdev); | |
409 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); | |
410 | ||
411 | } | |
412 | ||
b73ba98d AD |
413 | /** |
414 | * radeon_irq_kms_disable_afmt - disable audio format change interrupt | |
415 | * | |
416 | * @rdev: radeon device pointer | |
417 | * @block: afmt block whose interrupt you want to disable | |
418 | * | |
419 | * Disables the afmt change interrupt for a specific afmt block (all asics). | |
420 | */ | |
fb98257a CK |
421 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block) |
422 | { | |
423 | unsigned long irqflags; | |
424 | ||
cc9945bf AD |
425 | if (!rdev->ddev->irq_enabled) |
426 | return; | |
427 | ||
fb98257a CK |
428 | spin_lock_irqsave(&rdev->irq.lock, irqflags); |
429 | rdev->irq.afmt[block] = false; | |
430 | radeon_irq_set(rdev); | |
431 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); | |
432 | } | |
433 | ||
b73ba98d AD |
434 | /** |
435 | * radeon_irq_kms_enable_hpd - enable hotplug detect interrupt | |
436 | * | |
437 | * @rdev: radeon device pointer | |
438 | * @hpd_mask: mask of hpd pins you want to enable. | |
439 | * | |
440 | * Enables the hotplug detect interrupt for a specific hpd pin (all asics). | |
441 | */ | |
fb98257a CK |
442 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask) |
443 | { | |
444 | unsigned long irqflags; | |
445 | int i; | |
446 | ||
cc9945bf AD |
447 | if (!rdev->ddev->irq_enabled) |
448 | return; | |
449 | ||
fb98257a CK |
450 | spin_lock_irqsave(&rdev->irq.lock, irqflags); |
451 | for (i = 0; i < RADEON_MAX_HPD_PINS; ++i) | |
452 | rdev->irq.hpd[i] |= !!(hpd_mask & (1 << i)); | |
453 | radeon_irq_set(rdev); | |
454 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); | |
455 | } | |
456 | ||
b73ba98d AD |
457 | /** |
458 | * radeon_irq_kms_disable_hpd - disable hotplug detect interrupt | |
459 | * | |
460 | * @rdev: radeon device pointer | |
461 | * @hpd_mask: mask of hpd pins you want to disable. | |
462 | * | |
463 | * Disables the hotplug detect interrupt for a specific hpd pin (all asics). | |
464 | */ | |
fb98257a CK |
465 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask) |
466 | { | |
467 | unsigned long irqflags; | |
468 | int i; | |
469 | ||
cc9945bf AD |
470 | if (!rdev->ddev->irq_enabled) |
471 | return; | |
472 | ||
fb98257a CK |
473 | spin_lock_irqsave(&rdev->irq.lock, irqflags); |
474 | for (i = 0; i < RADEON_MAX_HPD_PINS; ++i) | |
475 | rdev->irq.hpd[i] &= !(hpd_mask & (1 << i)); | |
476 | radeon_irq_set(rdev); | |
477 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); | |
478 | } | |
479 |