[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / radeon_kfd.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#include <linux/module.h>
#include <linux/fdtable.h>
#include <linux/uaccess.h>
#include <drm/drmP.h>
#include "radeon.h"
#include "cikd.h"
#include "cik_reg.h"
#include "radeon_kfd.h"
#include "radeon_ucode.h"
#include <linux/firmware.h>

#define CIK_PIPE_PER_MEC	(4)

struct kgd_mem {
	struct radeon_bo *bo;
	uint64_t gpu_addr;
	void *cpu_ptr;
};


static int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
			void **mem_obj, uint64_t *gpu_addr,
			void **cpu_ptr);

static void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj);

static uint64_t get_vmem_size(struct kgd_dev *kgd);
static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd);

static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);

/*
 * Register access functions
 */

static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
		uint32_t sh_mem_config,	uint32_t sh_mem_ape1_base,
		uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);

static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
					unsigned int vmid);

static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
				uint32_t hpd_size, uint64_t hpd_gpu_addr);

static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
			uint32_t queue_id, uint32_t __user *wptr);
static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd);
static bool kgd_hqd_is_occupies(struct kgd_dev *kgd, uint64_t queue_address,
				uint32_t pipe_id, uint32_t queue_id);

static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
				unsigned int timeout, uint32_t pipe_id,
				uint32_t queue_id);
static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
				unsigned int timeout);

static const struct kfd2kgd_calls kfd2kgd = {
	.init_gtt_mem_allocation = alloc_gtt_mem,
	.free_gtt_mem = free_gtt_mem,
	.get_vmem_size = get_vmem_size,
	.get_gpu_clock_counter = get_gpu_clock_counter,
	.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
	.program_sh_mem_settings = kgd_program_sh_mem_settings,
	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
	.init_pipeline = kgd_init_pipeline,
	.hqd_load = kgd_hqd_load,
	.hqd_sdma_load = kgd_hqd_sdma_load,
	.hqd_is_occupies = kgd_hqd_is_occupies,
	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
	.hqd_destroy = kgd_hqd_destroy,
	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
	.get_fw_version = get_fw_version
};

static const struct kgd2kfd_calls *kgd2kfd;

bool radeon_kfd_init(void)
{
	bool (*kgd2kfd_init_p)(unsigned, const struct kfd2kgd_calls*,
				const struct kgd2kfd_calls**);

	kgd2kfd_init_p = symbol_request(kgd2kfd_init);

	if (kgd2kfd_init_p == NULL)
		return false;

	if (!kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kfd2kgd, &kgd2kfd)) {
		symbol_put(kgd2kfd_init);
		kgd2kfd = NULL;

		return false;
	}

	return true;
}

void radeon_kfd_fini(void)
{
	if (kgd2kfd) {
		kgd2kfd->exit();
		symbol_put(kgd2kfd_init);
	}
}

void radeon_kfd_device_probe(struct radeon_device *rdev)
{
	if (kgd2kfd)
		rdev->kfd = kgd2kfd->probe((struct kgd_dev *)rdev, rdev->pdev);
}

void radeon_kfd_device_init(struct radeon_device *rdev)
{
	if (rdev->kfd) {
		struct kgd2kfd_shared_resources gpu_resources = {
			.compute_vmid_bitmap = 0xFF00,

			.first_compute_pipe = 1,
			.compute_pipe_count = 8 - 1,
		};

		radeon_doorbell_get_kfd_info(rdev,
				&gpu_resources.doorbell_physical_address,
				&gpu_resources.doorbell_aperture_size,
				&gpu_resources.doorbell_start_offset);

		kgd2kfd->device_init(rdev->kfd, &gpu_resources);
	}
}

void radeon_kfd_device_fini(struct radeon_device *rdev)
{
	if (rdev->kfd) {
		kgd2kfd->device_exit(rdev->kfd);
		rdev->kfd = NULL;
	}
}

void radeon_kfd_interrupt(struct radeon_device *rdev, const void *ih_ring_entry)
{
	if (rdev->kfd)
		kgd2kfd->interrupt(rdev->kfd, ih_ring_entry);
}

void radeon_kfd_suspend(struct radeon_device *rdev)
{
	if (rdev->kfd)
		kgd2kfd->suspend(rdev->kfd);
}

int radeon_kfd_resume(struct radeon_device *rdev)
{
	int r = 0;

	if (rdev->kfd)
		r = kgd2kfd->resume(rdev->kfd);

	return r;
}

static int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
			void **mem_obj, uint64_t *gpu_addr,
			void **cpu_ptr)
{
	struct radeon_device *rdev = (struct radeon_device *)kgd;
	struct kgd_mem **mem = (struct kgd_mem **) mem_obj;
	int r;

	BUG_ON(kgd == NULL);
	BUG_ON(gpu_addr == NULL);
	BUG_ON(cpu_ptr == NULL);

	*mem = kmalloc(sizeof(struct kgd_mem), GFP_KERNEL);
	if ((*mem) == NULL)
		return -ENOMEM;

	r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_GTT,
				RADEON_GEM_GTT_WC, NULL, NULL, &(*mem)->bo);
	if (r) {
		dev_err(rdev->dev,
			"failed to allocate BO for amdkfd (%d)\n", r);
		return r;
	}

	/* map the buffer */
	r = radeon_bo_reserve((*mem)->bo, true);
	if (r) {
		dev_err(rdev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
		goto allocate_mem_reserve_bo_failed;
	}

	r = radeon_bo_pin((*mem)->bo, RADEON_GEM_DOMAIN_GTT,
				&(*mem)->gpu_addr);
	if (r) {
		dev_err(rdev->dev, "(%d) failed to pin bo for amdkfd\n", r);
		goto allocate_mem_pin_bo_failed;
	}
	*gpu_addr = (*mem)->gpu_addr;

	r = radeon_bo_kmap((*mem)->bo, &(*mem)->cpu_ptr);
	if (r) {
		dev_err(rdev->dev,
			"(%d) failed to map bo to kernel for amdkfd\n", r);
		goto allocate_mem_kmap_bo_failed;
	}
	*cpu_ptr = (*mem)->cpu_ptr;

	radeon_bo_unreserve((*mem)->bo);

	return 0;

allocate_mem_kmap_bo_failed:
	radeon_bo_unpin((*mem)->bo);
allocate_mem_pin_bo_failed:
	radeon_bo_unreserve((*mem)->bo);
allocate_mem_reserve_bo_failed:
	radeon_bo_unref(&(*mem)->bo);

	return r;
}

static void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
{
	struct kgd_mem *mem = (struct kgd_mem *) mem_obj;

	BUG_ON(mem == NULL);

	radeon_bo_reserve(mem->bo, true);
	radeon_bo_kunmap(mem->bo);
	radeon_bo_unpin(mem->bo);
	radeon_bo_unreserve(mem->bo);
	radeon_bo_unref(&(mem->bo));
	kfree(mem);
}

static uint64_t get_vmem_size(struct kgd_dev *kgd)
{
	struct radeon_device *rdev = (struct radeon_device *)kgd;

	BUG_ON(kgd == NULL);

	return rdev->mc.real_vram_size;
}

static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
{
	struct radeon_device *rdev = (struct radeon_device *)kgd;

	return rdev->asic->get_gpu_clock_counter(rdev);
}

static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
{
	struct radeon_device *rdev = (struct radeon_device *)kgd;

	/* The sclk is in quantas of 10kHz */
	return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100;
}

static inline struct radeon_device *get_radeon_device(struct kgd_dev *kgd)
{
	return (struct radeon_device *)kgd;
}

static void write_register(struct kgd_dev *kgd, uint32_t offset, uint32_t value)
{
	struct radeon_device *rdev = get_radeon_device(kgd);

	writel(value, (void __iomem *)(rdev->rmmio + offset));
}

static uint32_t read_register(struct kgd_dev *kgd, uint32_t offset)
{
	struct radeon_device *rdev = get_radeon_device(kgd);

	return readl((void __iomem *)(rdev->rmmio + offset));
}

static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
			uint32_t queue, uint32_t vmid)
{
	struct radeon_device *rdev = get_radeon_device(kgd);
	uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);

	mutex_lock(&rdev->srbm_mutex);
	write_register(kgd, SRBM_GFX_CNTL, value);
}

static void unlock_srbm(struct kgd_dev *kgd)
{
	struct radeon_device *rdev = get_radeon_device(kgd);

	write_register(kgd, SRBM_GFX_CNTL, 0);
	mutex_unlock(&rdev->srbm_mutex);
}

static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
				uint32_t queue_id)
{
	uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
	uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);

	lock_srbm(kgd, mec, pipe, queue_id, 0);
}

static void release_queue(struct kgd_dev *kgd)
{
	unlock_srbm(kgd);
}

static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
					uint32_t sh_mem_config,
					uint32_t sh_mem_ape1_base,
					uint32_t sh_mem_ape1_limit,
					uint32_t sh_mem_bases)
{
	lock_srbm(kgd, 0, 0, 0, vmid);

	write_register(kgd, SH_MEM_CONFIG, sh_mem_config);
	write_register(kgd, SH_MEM_APE1_BASE, sh_mem_ape1_base);
	write_register(kgd, SH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
	write_register(kgd, SH_MEM_BASES, sh_mem_bases);

	unlock_srbm(kgd);
}

static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
					unsigned int vmid)
{
	/*
	 * We have to assume that there is no outstanding mapping.
	 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0
	 * because a mapping is in progress or because a mapping finished and
	 * the SW cleared it.
	 * So the protocol is to always wait & clear.
	 */
	uint32_t pasid_mapping = (pasid == 0) ? 0 :
				(uint32_t)pasid | ATC_VMID_PASID_MAPPING_VALID;

	write_register(kgd, ATC_VMID0_PASID_MAPPING + vmid*sizeof(uint32_t),
			pasid_mapping);

	while (!(read_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS) &
								(1U << vmid)))
		cpu_relax();
	write_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);

	return 0;
}

static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
				uint32_t hpd_size, uint64_t hpd_gpu_addr)
{
	uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
	uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);

	lock_srbm(kgd, mec, pipe, 0, 0);
	write_register(kgd, CP_HPD_EOP_BASE_ADDR,
			lower_32_bits(hpd_gpu_addr >> 8));
	write_register(kgd, CP_HPD_EOP_BASE_ADDR_HI,
			upper_32_bits(hpd_gpu_addr >> 8));
	write_register(kgd, CP_HPD_EOP_VMID, 0);
	write_register(kgd, CP_HPD_EOP_CONTROL, hpd_size);
	unlock_srbm(kgd);

	return 0;
}

static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
{
	uint32_t retval;

	retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
			m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;

	pr_debug("kfd: sdma base address: 0x%x\n", retval);

	return retval;
}

static inline struct cik_mqd *get_mqd(void *mqd)
{
	return (struct cik_mqd *)mqd;
}

static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
{
	return (struct cik_sdma_rlc_registers *)mqd;
}

static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
			uint32_t queue_id, uint32_t __user *wptr)
{
	uint32_t wptr_shadow, is_wptr_shadow_valid;
	struct cik_mqd *m;

	m = get_mqd(mqd);

	is_wptr_shadow_valid = !get_user(wptr_shadow, wptr);

	acquire_queue(kgd, pipe_id, queue_id);
	write_register(kgd, CP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo);
	write_register(kgd, CP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi);
	write_register(kgd, CP_MQD_CONTROL, m->cp_mqd_control);

	write_register(kgd, CP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo);
	write_register(kgd, CP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi);
	write_register(kgd, CP_HQD_PQ_CONTROL, m->cp_hqd_pq_control);

	write_register(kgd, CP_HQD_IB_CONTROL, m->cp_hqd_ib_control);
	write_register(kgd, CP_HQD_IB_BASE_ADDR, m->cp_hqd_ib_base_addr_lo);
	write_register(kgd, CP_HQD_IB_BASE_ADDR_HI, m->cp_hqd_ib_base_addr_hi);

	write_register(kgd, CP_HQD_IB_RPTR, m->cp_hqd_ib_rptr);

	write_register(kgd, CP_HQD_PERSISTENT_STATE,
			m->cp_hqd_persistent_state);
	write_register(kgd, CP_HQD_SEMA_CMD, m->cp_hqd_sema_cmd);
	write_register(kgd, CP_HQD_MSG_TYPE, m->cp_hqd_msg_type);

	write_register(kgd, CP_HQD_ATOMIC0_PREOP_LO,
			m->cp_hqd_atomic0_preop_lo);

	write_register(kgd, CP_HQD_ATOMIC0_PREOP_HI,
			m->cp_hqd_atomic0_preop_hi);

	write_register(kgd, CP_HQD_ATOMIC1_PREOP_LO,
			m->cp_hqd_atomic1_preop_lo);

	write_register(kgd, CP_HQD_ATOMIC1_PREOP_HI,
			m->cp_hqd_atomic1_preop_hi);

	write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR,
			m->cp_hqd_pq_rptr_report_addr_lo);

	write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR_HI,
			m->cp_hqd_pq_rptr_report_addr_hi);

	write_register(kgd, CP_HQD_PQ_RPTR, m->cp_hqd_pq_rptr);

	write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR,
			m->cp_hqd_pq_wptr_poll_addr_lo);

	write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR_HI,
			m->cp_hqd_pq_wptr_poll_addr_hi);

	write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL,
			m->cp_hqd_pq_doorbell_control);

	write_register(kgd, CP_HQD_VMID, m->cp_hqd_vmid);

	write_register(kgd, CP_HQD_QUANTUM, m->cp_hqd_quantum);

	write_register(kgd, CP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority);
	write_register(kgd, CP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority);

	write_register(kgd, CP_HQD_IQ_RPTR, m->cp_hqd_iq_rptr);

	if (is_wptr_shadow_valid)
		write_register(kgd, CP_HQD_PQ_WPTR, wptr_shadow);

	write_register(kgd, CP_HQD_ACTIVE, m->cp_hqd_active);
	release_queue(kgd);

	return 0;
}

static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
{
	struct cik_sdma_rlc_registers *m;
	uint32_t sdma_base_addr;

	m = get_sdma_mqd(mqd);
	sdma_base_addr = get_sdma_base_addr(m);

	write_register(kgd,
			sdma_base_addr + SDMA0_RLC0_VIRTUAL_ADDR,
			m->sdma_rlc_virtual_addr);

	write_register(kgd,
			sdma_base_addr + SDMA0_RLC0_RB_BASE,
			m->sdma_rlc_rb_base);

	write_register(kgd,
			sdma_base_addr + SDMA0_RLC0_RB_BASE_HI,
			m->sdma_rlc_rb_base_hi);

	write_register(kgd,
			sdma_base_addr + SDMA0_RLC0_RB_RPTR_ADDR_LO,
			m->sdma_rlc_rb_rptr_addr_lo);

	write_register(kgd,
			sdma_base_addr + SDMA0_RLC0_RB_RPTR_ADDR_HI,
			m->sdma_rlc_rb_rptr_addr_hi);

	write_register(kgd,
			sdma_base_addr + SDMA0_RLC0_DOORBELL,
			m->sdma_rlc_doorbell);

	write_register(kgd,
			sdma_base_addr + SDMA0_RLC0_RB_CNTL,
			m->sdma_rlc_rb_cntl);

	return 0;
}

static bool kgd_hqd_is_occupies(struct kgd_dev *kgd, uint64_t queue_address,
				uint32_t pipe_id, uint32_t queue_id)
{
	uint32_t act;
	bool retval = false;
	uint32_t low, high;

	acquire_queue(kgd, pipe_id, queue_id);
	act = read_register(kgd, CP_HQD_ACTIVE);
	if (act) {
		low = lower_32_bits(queue_address >> 8);
		high = upper_32_bits(queue_address >> 8);

		if (low == read_register(kgd, CP_HQD_PQ_BASE) &&
				high == read_register(kgd, CP_HQD_PQ_BASE_HI))
			retval = true;
	}
	release_queue(kgd);
	return retval;
}

static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
{
	struct cik_sdma_rlc_registers *m;
	uint32_t sdma_base_addr;
	uint32_t sdma_rlc_rb_cntl;

	m = get_sdma_mqd(mqd);
	sdma_base_addr = get_sdma_base_addr(m);

	sdma_rlc_rb_cntl = read_register(kgd,
					sdma_base_addr + SDMA0_RLC0_RB_CNTL);

	if (sdma_rlc_rb_cntl & SDMA_RB_ENABLE)
		return true;

	return false;
}

static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
				unsigned int timeout, uint32_t pipe_id,
				uint32_t queue_id)
{
	uint32_t temp;

	acquire_queue(kgd, pipe_id, queue_id);
	write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL, 0);

	write_register(kgd, CP_HQD_DEQUEUE_REQUEST, reset_type);

	while (true) {
		temp = read_register(kgd, CP_HQD_ACTIVE);
		if (temp & 0x1)
			break;
		if (timeout == 0) {
			pr_err("kfd: cp queue preemption time out (%dms)\n",
				temp);
			return -ETIME;
		}
		msleep(20);
		timeout -= 20;
	}

	release_queue(kgd);
	return 0;
}

static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
				unsigned int timeout)
{
	struct cik_sdma_rlc_registers *m;
	uint32_t sdma_base_addr;
	uint32_t temp;

	m = get_sdma_mqd(mqd);
	sdma_base_addr = get_sdma_base_addr(m);

	temp = read_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_CNTL);
	temp = temp & ~SDMA_RB_ENABLE;
	write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_CNTL, temp);

	while (true) {
		temp = read_register(kgd, sdma_base_addr +
						SDMA0_RLC0_CONTEXT_STATUS);
		if (temp & SDMA_RLC_IDLE)
			break;
		if (timeout == 0)
			return -ETIME;
		msleep(20);
		timeout -= 20;
	}

	write_register(kgd, sdma_base_addr + SDMA0_RLC0_DOORBELL, 0);
	write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_RPTR, 0);
	write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_WPTR, 0);
	write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_BASE, 0);

	return 0;
}

static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
{
	struct radeon_device *rdev = (struct radeon_device *) kgd;
	const union radeon_firmware_header *hdr;

	BUG_ON(kgd == NULL || rdev->mec_fw == NULL);

	switch (type) {
	case KGD_ENGINE_PFP:
		hdr = (const union radeon_firmware_header *) rdev->pfp_fw->data;
		break;

	case KGD_ENGINE_ME:
		hdr = (const union radeon_firmware_header *) rdev->me_fw->data;
		break;

	case KGD_ENGINE_CE:
		hdr = (const union radeon_firmware_header *) rdev->ce_fw->data;
		break;

	case KGD_ENGINE_MEC1:
		hdr = (const union radeon_firmware_header *) rdev->mec_fw->data;
		break;

	case KGD_ENGINE_MEC2:
		hdr = (const union radeon_firmware_header *)
							rdev->mec2_fw->data;
		break;

	case KGD_ENGINE_RLC:
		hdr = (const union radeon_firmware_header *) rdev->rlc_fw->data;
		break;

	case KGD_ENGINE_SDMA:
		hdr = (const union radeon_firmware_header *)
							rdev->sdma_fw->data;
		break;

	default:
		return 0;
	}

	if (hdr == NULL)
		return 0;

	/* Only 12 bit in use*/
	return hdr->common.ucode_version;
}
Commit	Line	Data
e28740ec OG	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22
	23	#include <linux/module.h>
	24	#include <linux/fdtable.h>
	25	#include <linux/uaccess.h>
	26	#include <drm/drmP.h>
	27	#include "radeon.h"
	28	#include "cikd.h"
	29	#include "cik_reg.h"
	30	#include "radeon_kfd.h"
f7694323 OG	31	#include "radeon_ucode.h"
f7694323 OG	32	#include <linux/firmware.h>
e28740ec OG	33
	34	#define CIK_PIPE_PER_MEC (4)
	35
	36	struct kgd_mem {
ceae881b	37	struct radeon_bo *bo;
632aa2cb	38	uint64_t gpu_addr;
ceae881b	39	void *cpu_ptr;
e28740ec OG	40	};
e28740ec OG	41
e28740ec	42
ceae881b OG	43	static int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
	44	void *mem_obj, uint64_t gpu_addr,
	45	void **cpu_ptr);
	46
	47	static void free_gtt_mem(struct kgd_dev kgd, void mem_obj);
	48
e28740ec OG	49	static uint64_t get_vmem_size(struct kgd_dev *kgd);
	50	static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd);
	51
	52	static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
f7694323	53	static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
e28740ec OG	54
	55	/*
	56	* Register access functions
	57	*/
	58
	59	static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
	60	uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
	61	uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
	62
	63	static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
	64	unsigned int vmid);
	65
e28740ec OG	66	static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
	67	uint32_t hpd_size, uint64_t hpd_gpu_addr);
	68
	69	static int kgd_hqd_load(struct kgd_dev kgd, void mqd, uint32_t pipe_id,
	70	uint32_t queue_id, uint32_t __user *wptr);
a84a9903	71	static int kgd_hqd_sdma_load(struct kgd_dev kgd, void mqd);
e28740ec OG	72	static bool kgd_hqd_is_occupies(struct kgd_dev *kgd, uint64_t queue_address,
	73	uint32_t pipe_id, uint32_t queue_id);
	74
	75	static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
	76	unsigned int timeout, uint32_t pipe_id,
	77	uint32_t queue_id);
a84a9903 BG	78	static bool kgd_hqd_sdma_is_occupied(struct kgd_dev kgd, void mqd);
	79	static int kgd_hqd_sdma_destroy(struct kgd_dev kgd, void mqd,
	80	unsigned int timeout);
e28740ec OG	81
e28740ec OG	82	static const struct kfd2kgd_calls kfd2kgd = {
ceae881b OG	83	.init_gtt_mem_allocation = alloc_gtt_mem,
ceae881b OG	84	.free_gtt_mem = free_gtt_mem,
e28740ec OG	85	.get_vmem_size = get_vmem_size,
	86	.get_gpu_clock_counter = get_gpu_clock_counter,
	87	.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
	88	.program_sh_mem_settings = kgd_program_sh_mem_settings,
	89	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
e28740ec OG	90	.init_pipeline = kgd_init_pipeline,
e28740ec OG	91	.hqd_load = kgd_hqd_load,
a84a9903	92	.hqd_sdma_load = kgd_hqd_sdma_load,
e28740ec	93	.hqd_is_occupies = kgd_hqd_is_occupies,
a84a9903	94	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
e28740ec	95	.hqd_destroy = kgd_hqd_destroy,
a84a9903	96	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
f7694323	97	.get_fw_version = get_fw_version
e28740ec OG	98	};
	99
	100	static const struct kgd2kfd_calls *kgd2kfd;
	101
	102	bool radeon_kfd_init(void)
	103	{
	104	bool (kgd2kfd_init_p)(unsigned, const struct kfd2kgd_calls,
	105	const struct kgd2kfd_calls**);
	106
	107	kgd2kfd_init_p = symbol_request(kgd2kfd_init);
	108
	109	if (kgd2kfd_init_p == NULL)
	110	return false;
	111
	112	if (!kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kfd2kgd, &kgd2kfd)) {
	113	symbol_put(kgd2kfd_init);
	114	kgd2kfd = NULL;
	115
	116	return false;
	117	}
	118
	119	return true;
	120	}
	121
	122	void radeon_kfd_fini(void)
	123	{
	124	if (kgd2kfd) {
	125	kgd2kfd->exit();
	126	symbol_put(kgd2kfd_init);
	127	}
	128	}
	129
	130	void radeon_kfd_device_probe(struct radeon_device *rdev)
	131	{
	132	if (kgd2kfd)
	133	rdev->kfd = kgd2kfd->probe((struct kgd_dev *)rdev, rdev->pdev);
	134	}
	135
	136	void radeon_kfd_device_init(struct radeon_device *rdev)
	137	{
	138	if (rdev->kfd) {
	139	struct kgd2kfd_shared_resources gpu_resources = {
	140	.compute_vmid_bitmap = 0xFF00,
	141
	142	.first_compute_pipe = 1,
	143	.compute_pipe_count = 8 - 1,
	144	};
	145
	146	radeon_doorbell_get_kfd_info(rdev,
	147	&gpu_resources.doorbell_physical_address,
	148	&gpu_resources.doorbell_aperture_size,
	149	&gpu_resources.doorbell_start_offset);
	150
	151	kgd2kfd->device_init(rdev->kfd, &gpu_resources);
	152	}
	153	}
	154
	155	void radeon_kfd_device_fini(struct radeon_device *rdev)
	156	{
	157	if (rdev->kfd) {
	158	kgd2kfd->device_exit(rdev->kfd);
	159	rdev->kfd = NULL;
	160	}
	161	}
162
163	void radeon_kfd_interrupt(struct radeon_device rdev, const void ih_ring_entry)
164	{
165	if (rdev->kfd)
166	kgd2kfd->interrupt(rdev->kfd, ih_ring_entry);
167	}
168
169	void radeon_kfd_suspend(struct radeon_device *rdev)
170	{
171	if (rdev->kfd)
172	kgd2kfd->suspend(rdev->kfd);
173	}
174
175	int radeon_kfd_resume(struct radeon_device *rdev)
176	{
177	int r = 0;
178
179	if (rdev->kfd)
180	r = kgd2kfd->resume(rdev->kfd);
181
182	return r;
183	}
184
ceae881b OG	185	static int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
	186	void *mem_obj, uint64_t gpu_addr,
	187	void **cpu_ptr)
	188	{
	189	struct radeon_device rdev = (struct radeon_device )kgd;
	190	struct kgd_mem mem = (struct kgd_mem ) mem_obj;
	191	int r;
	192
	193	BUG_ON(kgd == NULL);
	194	BUG_ON(gpu_addr == NULL);
	195	BUG_ON(cpu_ptr == NULL);
	196
	197	*mem = kmalloc(sizeof(struct kgd_mem), GFP_KERNEL);
	198	if ((*mem) == NULL)
	199	return -ENOMEM;
	200
	201	r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_GTT,
	202	RADEON_GEM_GTT_WC, NULL, NULL, &(*mem)->bo);
	203	if (r) {
	204	dev_err(rdev->dev,
	205	"failed to allocate BO for amdkfd (%d)\n", r);
	206	return r;
	207	}
	208
	209	/* map the buffer */
	210	r = radeon_bo_reserve((*mem)->bo, true);
	211	if (r) {
	212	dev_err(rdev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
	213	goto allocate_mem_reserve_bo_failed;
	214	}
	215
	216	r = radeon_bo_pin((*mem)->bo, RADEON_GEM_DOMAIN_GTT,
	217	&(*mem)->gpu_addr);
	218	if (r) {
	219	dev_err(rdev->dev, "(%d) failed to pin bo for amdkfd\n", r);
	220	goto allocate_mem_pin_bo_failed;
	221	}
	222	gpu_addr = (mem)->gpu_addr;
	223
	224	r = radeon_bo_kmap((mem)->bo, &(mem)->cpu_ptr);
	225	if (r) {
	226	dev_err(rdev->dev,
	227	"(%d) failed to map bo to kernel for amdkfd\n", r);
	228	goto allocate_mem_kmap_bo_failed;
	229	}
	230	cpu_ptr = (mem)->cpu_ptr;
	231
	232	radeon_bo_unreserve((*mem)->bo);
	233
	234	return 0;
	235
	236	allocate_mem_kmap_bo_failed:
	237	radeon_bo_unpin((*mem)->bo);
	238	allocate_mem_pin_bo_failed:
	239	radeon_bo_unreserve((*mem)->bo);
	240	allocate_mem_reserve_bo_failed:
	241	radeon_bo_unref(&(*mem)->bo);
	242
	243	return r;
	244	}
	245
	246	static void free_gtt_mem(struct kgd_dev kgd, void mem_obj)
	247	{
	248	struct kgd_mem mem = (struct kgd_mem ) mem_obj;
249
250	BUG_ON(mem == NULL);
251
252	radeon_bo_reserve(mem->bo, true);
253	radeon_bo_kunmap(mem->bo);
254	radeon_bo_unpin(mem->bo);
255	radeon_bo_unreserve(mem->bo);
256	radeon_bo_unref(&(mem->bo));
257	kfree(mem);
258	}
259
e28740ec OG	260	static uint64_t get_vmem_size(struct kgd_dev *kgd)
	261	{
	262	struct radeon_device rdev = (struct radeon_device )kgd;
	263
	264	BUG_ON(kgd == NULL);
	265
	266	return rdev->mc.real_vram_size;
	267	}
	268
	269	static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
	270	{
	271	struct radeon_device rdev = (struct radeon_device )kgd;
	272
	273	return rdev->asic->get_gpu_clock_counter(rdev);
	274	}
	275
	276	static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
	277	{
	278	struct radeon_device rdev = (struct radeon_device )kgd;
	279
	280	/* The sclk is in quantas of 10kHz */
	281	return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100;
	282	}
	283
	284	static inline struct radeon_device get_radeon_device(struct kgd_dev kgd)
	285	{
	286	return (struct radeon_device *)kgd;
	287	}
	288
	289	static void write_register(struct kgd_dev *kgd, uint32_t offset, uint32_t value)
	290	{
	291	struct radeon_device *rdev = get_radeon_device(kgd);
	292
	293	writel(value, (void __iomem *)(rdev->rmmio + offset));
	294	}
	295
	296	static uint32_t read_register(struct kgd_dev *kgd, uint32_t offset)
	297	{
	298	struct radeon_device *rdev = get_radeon_device(kgd);
	299
	300	return readl((void __iomem *)(rdev->rmmio + offset));
	301	}
	302
	303	static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
	304	uint32_t queue, uint32_t vmid)
	305	{
	306	struct radeon_device *rdev = get_radeon_device(kgd);
	307	uint32_t value = PIPEID(pipe) \| MEID(mec) \| VMID(vmid) \| QUEUEID(queue);
	308
	309	mutex_lock(&rdev->srbm_mutex);
	310	write_register(kgd, SRBM_GFX_CNTL, value);
	311	}
	312
	313	static void unlock_srbm(struct kgd_dev *kgd)
	314	{
	315	struct radeon_device *rdev = get_radeon_device(kgd);
	316
	317	write_register(kgd, SRBM_GFX_CNTL, 0);
	318	mutex_unlock(&rdev->srbm_mutex);
	319	}
	320
	321	static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
	322	uint32_t queue_id)
	323	{
324	uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
325	uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
326
327	lock_srbm(kgd, mec, pipe, queue_id, 0);
328	}
329
330	static void release_queue(struct kgd_dev *kgd)
331	{
332	unlock_srbm(kgd);
333	}
334
335	static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
336	uint32_t sh_mem_config,
337	uint32_t sh_mem_ape1_base,
338	uint32_t sh_mem_ape1_limit,
339	uint32_t sh_mem_bases)
340	{
341	lock_srbm(kgd, 0, 0, 0, vmid);
342
343	write_register(kgd, SH_MEM_CONFIG, sh_mem_config);
344	write_register(kgd, SH_MEM_APE1_BASE, sh_mem_ape1_base);
345	write_register(kgd, SH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
346	write_register(kgd, SH_MEM_BASES, sh_mem_bases);
347
348	unlock_srbm(kgd);
349	}
350
351	static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
352	unsigned int vmid)
353	{
354	/*
355	* We have to assume that there is no outstanding mapping.
356	* The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0
357	* because a mapping is in progress or because a mapping finished and
358	* the SW cleared it.
359	* So the protocol is to always wait & clear.
360	*/
361	uint32_t pasid_mapping = (pasid == 0) ? 0 :
362	(uint32_t)pasid \| ATC_VMID_PASID_MAPPING_VALID;
363
364	write_register(kgd, ATC_VMID0_PASID_MAPPING + vmid*sizeof(uint32_t),
365	pasid_mapping);
366
367	while (!(read_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS) &
368	(1U << vmid)))
369	cpu_relax();
370	write_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
371
372	return 0;
373	}
374
e28740ec OG	375	static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
	376	uint32_t hpd_size, uint64_t hpd_gpu_addr)
	377	{
	378	uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
	379	uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
	380
	381	lock_srbm(kgd, mec, pipe, 0, 0);
	382	write_register(kgd, CP_HPD_EOP_BASE_ADDR,
	383	lower_32_bits(hpd_gpu_addr >> 8));
	384	write_register(kgd, CP_HPD_EOP_BASE_ADDR_HI,
	385	upper_32_bits(hpd_gpu_addr >> 8));
	386	write_register(kgd, CP_HPD_EOP_VMID, 0);
	387	write_register(kgd, CP_HPD_EOP_CONTROL, hpd_size);
	388	unlock_srbm(kgd);
	389
	390	return 0;
	391	}
	392
a84a9903 BG	393	static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
	394	{
	395	uint32_t retval;
	396
	397	retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
	398	m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
	399
	400	pr_debug("kfd: sdma base address: 0x%x\n", retval);
	401
	402	return retval;
	403	}
	404
e28740ec OG	405	static inline struct cik_mqd get_mqd(void mqd)
	406	{
	407	return (struct cik_mqd *)mqd;
	408	}
	409
a84a9903 BG	410	static inline struct cik_sdma_rlc_registers get_sdma_mqd(void mqd)
	411	{
	412	return (struct cik_sdma_rlc_registers *)mqd;
	413	}
	414
e28740ec OG	415	static int kgd_hqd_load(struct kgd_dev kgd, void mqd, uint32_t pipe_id,
	416	uint32_t queue_id, uint32_t __user *wptr)
	417	{
	418	uint32_t wptr_shadow, is_wptr_shadow_valid;
	419	struct cik_mqd *m;
	420
	421	m = get_mqd(mqd);
	422
	423	is_wptr_shadow_valid = !get_user(wptr_shadow, wptr);
	424
	425	acquire_queue(kgd, pipe_id, queue_id);
	426	write_register(kgd, CP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo);
	427	write_register(kgd, CP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi);
	428	write_register(kgd, CP_MQD_CONTROL, m->cp_mqd_control);
	429
	430	write_register(kgd, CP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo);
	431	write_register(kgd, CP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi);
	432	write_register(kgd, CP_HQD_PQ_CONTROL, m->cp_hqd_pq_control);
	433
	434	write_register(kgd, CP_HQD_IB_CONTROL, m->cp_hqd_ib_control);
	435	write_register(kgd, CP_HQD_IB_BASE_ADDR, m->cp_hqd_ib_base_addr_lo);
	436	write_register(kgd, CP_HQD_IB_BASE_ADDR_HI, m->cp_hqd_ib_base_addr_hi);
	437
	438	write_register(kgd, CP_HQD_IB_RPTR, m->cp_hqd_ib_rptr);
	439
	440	write_register(kgd, CP_HQD_PERSISTENT_STATE,
	441	m->cp_hqd_persistent_state);
	442	write_register(kgd, CP_HQD_SEMA_CMD, m->cp_hqd_sema_cmd);
	443	write_register(kgd, CP_HQD_MSG_TYPE, m->cp_hqd_msg_type);
	444
	445	write_register(kgd, CP_HQD_ATOMIC0_PREOP_LO,
	446	m->cp_hqd_atomic0_preop_lo);
	447
	448	write_register(kgd, CP_HQD_ATOMIC0_PREOP_HI,
	449	m->cp_hqd_atomic0_preop_hi);
	450
	451	write_register(kgd, CP_HQD_ATOMIC1_PREOP_LO,
	452	m->cp_hqd_atomic1_preop_lo);
	453
	454	write_register(kgd, CP_HQD_ATOMIC1_PREOP_HI,
	455	m->cp_hqd_atomic1_preop_hi);
	456
	457	write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR,
	458	m->cp_hqd_pq_rptr_report_addr_lo);
	459
	460	write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR_HI,
	461	m->cp_hqd_pq_rptr_report_addr_hi);
	462
	463	write_register(kgd, CP_HQD_PQ_RPTR, m->cp_hqd_pq_rptr);
	464
	465	write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR,
	466	m->cp_hqd_pq_wptr_poll_addr_lo);
	467
	468	write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR_HI,
	469	m->cp_hqd_pq_wptr_poll_addr_hi);
	470
	471	write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL,
	472	m->cp_hqd_pq_doorbell_control);
	473
	474	write_register(kgd, CP_HQD_VMID, m->cp_hqd_vmid);
	475
	476	write_register(kgd, CP_HQD_QUANTUM, m->cp_hqd_quantum);
	477
	478	write_register(kgd, CP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority);
479	write_register(kgd, CP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority);
480
481	write_register(kgd, CP_HQD_IQ_RPTR, m->cp_hqd_iq_rptr);
482
483	if (is_wptr_shadow_valid)
484	write_register(kgd, CP_HQD_PQ_WPTR, wptr_shadow);
485
486	write_register(kgd, CP_HQD_ACTIVE, m->cp_hqd_active);
487	release_queue(kgd);
488
489	return 0;
490	}
491
a84a9903 BG	492	static int kgd_hqd_sdma_load(struct kgd_dev kgd, void mqd)
	493	{
	494	struct cik_sdma_rlc_registers *m;
	495	uint32_t sdma_base_addr;
	496
	497	m = get_sdma_mqd(mqd);
	498	sdma_base_addr = get_sdma_base_addr(m);
	499
	500	write_register(kgd,
	501	sdma_base_addr + SDMA0_RLC0_VIRTUAL_ADDR,
	502	m->sdma_rlc_virtual_addr);
	503
	504	write_register(kgd,
	505	sdma_base_addr + SDMA0_RLC0_RB_BASE,
	506	m->sdma_rlc_rb_base);
	507
	508	write_register(kgd,
	509	sdma_base_addr + SDMA0_RLC0_RB_BASE_HI,
	510	m->sdma_rlc_rb_base_hi);
	511
	512	write_register(kgd,
	513	sdma_base_addr + SDMA0_RLC0_RB_RPTR_ADDR_LO,
	514	m->sdma_rlc_rb_rptr_addr_lo);
	515
	516	write_register(kgd,
	517	sdma_base_addr + SDMA0_RLC0_RB_RPTR_ADDR_HI,
	518	m->sdma_rlc_rb_rptr_addr_hi);
	519
	520	write_register(kgd,
	521	sdma_base_addr + SDMA0_RLC0_DOORBELL,
	522	m->sdma_rlc_doorbell);
	523
	524	write_register(kgd,
	525	sdma_base_addr + SDMA0_RLC0_RB_CNTL,
	526	m->sdma_rlc_rb_cntl);
	527
	528	return 0;
	529	}
	530
e28740ec OG	531	static bool kgd_hqd_is_occupies(struct kgd_dev *kgd, uint64_t queue_address,
	532	uint32_t pipe_id, uint32_t queue_id)
	533	{
	534	uint32_t act;
	535	bool retval = false;
	536	uint32_t low, high;
	537
	538	acquire_queue(kgd, pipe_id, queue_id);
	539	act = read_register(kgd, CP_HQD_ACTIVE);
	540	if (act) {
	541	low = lower_32_bits(queue_address >> 8);
	542	high = upper_32_bits(queue_address >> 8);
	543
	544	if (low == read_register(kgd, CP_HQD_PQ_BASE) &&
	545	high == read_register(kgd, CP_HQD_PQ_BASE_HI))
	546	retval = true;
	547	}
	548	release_queue(kgd);
	549	return retval;
	550	}
	551
a84a9903 BG	552	static bool kgd_hqd_sdma_is_occupied(struct kgd_dev kgd, void mqd)
	553	{
	554	struct cik_sdma_rlc_registers *m;
	555	uint32_t sdma_base_addr;
	556	uint32_t sdma_rlc_rb_cntl;
	557
	558	m = get_sdma_mqd(mqd);
	559	sdma_base_addr = get_sdma_base_addr(m);
	560
	561	sdma_rlc_rb_cntl = read_register(kgd,
	562	sdma_base_addr + SDMA0_RLC0_RB_CNTL);
	563
	564	if (sdma_rlc_rb_cntl & SDMA_RB_ENABLE)
	565	return true;
	566
	567	return false;
	568	}
	569
e28740ec OG	570	static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
	571	unsigned int timeout, uint32_t pipe_id,
	572	uint32_t queue_id)
	573	{
	574	uint32_t temp;
	575
	576	acquire_queue(kgd, pipe_id, queue_id);
	577	write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL, 0);
	578
	579	write_register(kgd, CP_HQD_DEQUEUE_REQUEST, reset_type);
	580
	581	while (true) {
	582	temp = read_register(kgd, CP_HQD_ACTIVE);
	583	if (temp & 0x1)
	584	break;
	585	if (timeout == 0) {
	586	pr_err("kfd: cp queue preemption time out (%dms)\n",
	587	temp);
	588	return -ETIME;
	589	}
	590	msleep(20);
	591	timeout -= 20;
	592	}
	593
	594	release_queue(kgd);
	595	return 0;
	596	}
f7694323	597
a84a9903 BG	598	static int kgd_hqd_sdma_destroy(struct kgd_dev kgd, void mqd,
	599	unsigned int timeout)
	600	{
	601	struct cik_sdma_rlc_registers *m;
	602	uint32_t sdma_base_addr;
	603	uint32_t temp;
	604
	605	m = get_sdma_mqd(mqd);
	606	sdma_base_addr = get_sdma_base_addr(m);
	607
	608	temp = read_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_CNTL);
	609	temp = temp & ~SDMA_RB_ENABLE;
	610	write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_CNTL, temp);
	611
	612	while (true) {
	613	temp = read_register(kgd, sdma_base_addr +
	614	SDMA0_RLC0_CONTEXT_STATUS);
	615	if (temp & SDMA_RLC_IDLE)
	616	break;
	617	if (timeout == 0)
	618	return -ETIME;
	619	msleep(20);
	620	timeout -= 20;
	621	}
	622
	623	write_register(kgd, sdma_base_addr + SDMA0_RLC0_DOORBELL, 0);
	624	write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_RPTR, 0);
	625	write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_WPTR, 0);
	626	write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_BASE, 0);
	627
	628	return 0;
	629	}
	630
f7694323 OG	631	static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
	632	{
	633	struct radeon_device rdev = (struct radeon_device ) kgd;
	634	const union radeon_firmware_header *hdr;
	635
	636	BUG_ON(kgd == NULL \|\| rdev->mec_fw == NULL);
	637
	638	switch (type) {
	639	case KGD_ENGINE_PFP:
	640	hdr = (const union radeon_firmware_header *) rdev->pfp_fw->data;
	641	break;
	642
	643	case KGD_ENGINE_ME:
	644	hdr = (const union radeon_firmware_header *) rdev->me_fw->data;
	645	break;
	646
	647	case KGD_ENGINE_CE:
	648	hdr = (const union radeon_firmware_header *) rdev->ce_fw->data;
	649	break;
	650
	651	case KGD_ENGINE_MEC1:
	652	hdr = (const union radeon_firmware_header *) rdev->mec_fw->data;
	653	break;
	654
	655	case KGD_ENGINE_MEC2:
	656	hdr = (const union radeon_firmware_header *)
	657	rdev->mec2_fw->data;
	658	break;
	659
	660	case KGD_ENGINE_RLC:
	661	hdr = (const union radeon_firmware_header *) rdev->rlc_fw->data;
	662	break;
	663
	664	case KGD_ENGINE_SDMA:
	665	hdr = (const union radeon_firmware_header *)
	666	rdev->sdma_fw->data;
	667	break;
	668
	669	default:
	670	return 0;
	671	}
	672
	673	if (hdr == NULL)
	674	return 0;
	675
	676	/* Only 12 bit in use*/
	677	return hdr->common.ucode_version;
	678	}