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Merge tag 'for-linus-20170825' of git://git.infradead.org/linux-mtd
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / radeon_kfd.c
CommitLineData
e28740ec
OG		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/module.h>
24#include <linux/fdtable.h>
25#include <linux/uaccess.h>
26#include <drm/drmP.h>
27#include "radeon.h"
28#include "cikd.h"
29#include "cik_reg.h"
30#include "radeon_kfd.h"
f7694323
OG		 31#include "radeon_ucode.h"
32#include <linux/firmware.h>
836aabc0 33#include "cik_structs.h"
e28740ec
OG		 34
35#define CIK_PIPE_PER_MEC (4)
36
a6186f4d
YS		 37static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = {
38 TCP_WATCH0_ADDR_H, TCP_WATCH0_ADDR_L, TCP_WATCH0_CNTL,
39 TCP_WATCH1_ADDR_H, TCP_WATCH1_ADDR_L, TCP_WATCH1_CNTL,
40 TCP_WATCH2_ADDR_H, TCP_WATCH2_ADDR_L, TCP_WATCH2_CNTL,
41 TCP_WATCH3_ADDR_H, TCP_WATCH3_ADDR_L, TCP_WATCH3_CNTL
42};
43
e28740ec 44struct kgd_mem {
ceae881b 45 struct radeon_bo *bo;
632aa2cb 46 uint64_t gpu_addr;
ceae881b 47 void *cpu_ptr;
e28740ec
OG		 48};
49
e28740ec 50
ceae881b
OG		 51static int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
52 void **mem_obj, uint64_t *gpu_addr,
53 void **cpu_ptr);
54
55static void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj);
56
e28740ec
OG		 57static uint64_t get_vmem_size(struct kgd_dev *kgd);
58static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd);
59
60static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
f7694323 61static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
e28740ec
OG		 62
63/*
64 * Register access functions
65 */
66
67static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
68 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
69 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
70
71static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
72 unsigned int vmid);
73
e28740ec
OG		 74static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
75 uint32_t hpd_size, uint64_t hpd_gpu_addr);
d36b94fc 76static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
e28740ec
OG		 77static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
78 uint32_t queue_id, uint32_t __user *wptr);
a84a9903 79static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd);
b64b8afc 80static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
e28740ec
OG		 81 uint32_t pipe_id, uint32_t queue_id);
82
83static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
84 unsigned int timeout, uint32_t pipe_id,
85 uint32_t queue_id);
a84a9903
BG		 86static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
87static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
88 unsigned int timeout);
a6186f4d
YS		 89static int kgd_address_watch_disable(struct kgd_dev *kgd);
90static int kgd_address_watch_execute(struct kgd_dev *kgd,
91 unsigned int watch_point_id,
92 uint32_t cntl_val,
93 uint32_t addr_hi,
94 uint32_t addr_lo);
95static int kgd_wave_control_execute(struct kgd_dev *kgd,
96 uint32_t gfx_index_val,
97 uint32_t sq_cmd);
98static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
99 unsigned int watch_point_id,
100 unsigned int reg_offset);
e28740ec 101
edad4023
AS		 102static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid);
103static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
104 uint8_t vmid);
105static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid);
106
e28740ec 107static const struct kfd2kgd_calls kfd2kgd = {
ceae881b
OG		 108 .init_gtt_mem_allocation = alloc_gtt_mem,
109 .free_gtt_mem = free_gtt_mem,
e28740ec
OG		 110 .get_vmem_size = get_vmem_size,
111 .get_gpu_clock_counter = get_gpu_clock_counter,
112 .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
113 .program_sh_mem_settings = kgd_program_sh_mem_settings,
114 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
e28740ec 115 .init_pipeline = kgd_init_pipeline,
d36b94fc 116 .init_interrupts = kgd_init_interrupts,
e28740ec 117 .hqd_load = kgd_hqd_load,
a84a9903 118 .hqd_sdma_load = kgd_hqd_sdma_load,
b64b8afc 119 .hqd_is_occupied = kgd_hqd_is_occupied,
a84a9903 120 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
e28740ec 121 .hqd_destroy = kgd_hqd_destroy,
a84a9903 122 .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
a6186f4d
YS		 123 .address_watch_disable = kgd_address_watch_disable,
124 .address_watch_execute = kgd_address_watch_execute,
125 .wave_control_execute = kgd_wave_control_execute,
126 .address_watch_get_offset = kgd_address_watch_get_offset,
edad4023
AS		 127 .get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid,
128 .get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid,
129 .write_vmid_invalidate_request = write_vmid_invalidate_request,
f7694323 130 .get_fw_version = get_fw_version
e28740ec
OG		 131};
132
133static const struct kgd2kfd_calls *kgd2kfd;
134
412c8f7d 135int radeon_kfd_init(void)
e28740ec 136{
412c8f7d
OG		 137 int ret;
138
38c2adfb 139#if defined(CONFIG_HSA_AMD_MODULE)
412c8f7d 140 int (*kgd2kfd_init_p)(unsigned, const struct kgd2kfd_calls**);
e28740ec
OG		 141
142 kgd2kfd_init_p = symbol_request(kgd2kfd_init);
143
144 if (kgd2kfd_init_p == NULL)
412c8f7d 145 return -ENOENT;
e28740ec 146
412c8f7d
OG		 147 ret = kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kgd2kfd);
148 if (ret) {
e28740ec
OG		 149 symbol_put(kgd2kfd_init);
150 kgd2kfd = NULL;
e28740ec
OG		 151 }
152
38c2adfb 153#elif defined(CONFIG_HSA_AMD)
412c8f7d
OG		 154 ret = kgd2kfd_init(KFD_INTERFACE_VERSION, &kgd2kfd);
155 if (ret)
38c2adfb
OG		 156 kgd2kfd = NULL;
157
38c2adfb 158#else
412c8f7d 159 ret = -ENOENT;
38c2adfb 160#endif
412c8f7d
OG		 161
162 return ret;
e28740ec
OG		 163}
164
165void radeon_kfd_fini(void)
166{
167 if (kgd2kfd) {
168 kgd2kfd->exit();
169 symbol_put(kgd2kfd_init);
170 }
171}
172
173void radeon_kfd_device_probe(struct radeon_device *rdev)
174{
175 if (kgd2kfd)
cea405b1
XZ		 176 rdev->kfd = kgd2kfd->probe((struct kgd_dev *)rdev,
177 rdev->pdev, &kfd2kgd);
e28740ec
OG		 178}
179
180void radeon_kfd_device_init(struct radeon_device *rdev)
181{
d0b63bb3
AR		 182 int i, queue, pipe, mec;
183
e28740ec
OG		 184 if (rdev->kfd) {
185 struct kgd2kfd_shared_resources gpu_resources = {
186 .compute_vmid_bitmap = 0xFF00,
d0b63bb3
AR		 187 .num_pipe_per_mec = 4,
188 .num_queue_per_pipe = 8
e28740ec
OG		 189 };
190
d0b63bb3
AR		 191 bitmap_zero(gpu_resources.queue_bitmap, KGD_MAX_QUEUES);
192
193 for (i = 0; i < KGD_MAX_QUEUES; ++i) {
194 queue = i % gpu_resources.num_queue_per_pipe;
195 pipe = (i / gpu_resources.num_queue_per_pipe)
196 % gpu_resources.num_pipe_per_mec;
197 mec = (i / gpu_resources.num_queue_per_pipe)
198 / gpu_resources.num_pipe_per_mec;
199
200 if (mec == 0 && pipe > 0)
201 set_bit(i, gpu_resources.queue_bitmap);
202 }
203
e28740ec
OG		 204 radeon_doorbell_get_kfd_info(rdev,
205 &gpu_resources.doorbell_physical_address,
206 &gpu_resources.doorbell_aperture_size,
207 &gpu_resources.doorbell_start_offset);
208
209 kgd2kfd->device_init(rdev->kfd, &gpu_resources);
210 }
211}
212
213void radeon_kfd_device_fini(struct radeon_device *rdev)
214{
215 if (rdev->kfd) {
216 kgd2kfd->device_exit(rdev->kfd);
217 rdev->kfd = NULL;
218 }
219}
220
221void radeon_kfd_interrupt(struct radeon_device *rdev, const void *ih_ring_entry)
222{
223 if (rdev->kfd)
224 kgd2kfd->interrupt(rdev->kfd, ih_ring_entry);
225}
226
227void radeon_kfd_suspend(struct radeon_device *rdev)
228{
229 if (rdev->kfd)
230 kgd2kfd->suspend(rdev->kfd);
231}
232
233int radeon_kfd_resume(struct radeon_device *rdev)
234{
235 int r = 0;
236
237 if (rdev->kfd)
238 r = kgd2kfd->resume(rdev->kfd);
239
240 return r;
241}
242
ceae881b
OG		 243static int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
244 void **mem_obj, uint64_t *gpu_addr,
245 void **cpu_ptr)
246{
247 struct radeon_device *rdev = (struct radeon_device *)kgd;
248 struct kgd_mem **mem = (struct kgd_mem **) mem_obj;
249 int r;
250
251 BUG_ON(kgd == NULL);
252 BUG_ON(gpu_addr == NULL);
253 BUG_ON(cpu_ptr == NULL);
254
255 *mem = kmalloc(sizeof(struct kgd_mem), GFP_KERNEL);
256 if ((*mem) == NULL)
257 return -ENOMEM;
258
259 r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_GTT,
260 RADEON_GEM_GTT_WC, NULL, NULL, &(*mem)->bo);
261 if (r) {
262 dev_err(rdev->dev,
263 "failed to allocate BO for amdkfd (%d)\n", r);
264 return r;
265 }
266
267 /* map the buffer */
268 r = radeon_bo_reserve((*mem)->bo, true);
269 if (r) {
270 dev_err(rdev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
271 goto allocate_mem_reserve_bo_failed;
272 }
273
274 r = radeon_bo_pin((*mem)->bo, RADEON_GEM_DOMAIN_GTT,
275 &(*mem)->gpu_addr);
276 if (r) {
277 dev_err(rdev->dev, "(%d) failed to pin bo for amdkfd\n", r);
278 goto allocate_mem_pin_bo_failed;
279 }
280 *gpu_addr = (*mem)->gpu_addr;
281
282 r = radeon_bo_kmap((*mem)->bo, &(*mem)->cpu_ptr);
283 if (r) {
284 dev_err(rdev->dev,
285 "(%d) failed to map bo to kernel for amdkfd\n", r);
286 goto allocate_mem_kmap_bo_failed;
287 }
288 *cpu_ptr = (*mem)->cpu_ptr;
289
290 radeon_bo_unreserve((*mem)->bo);
291
292 return 0;
293
294allocate_mem_kmap_bo_failed:
295 radeon_bo_unpin((*mem)->bo);
296allocate_mem_pin_bo_failed:
297 radeon_bo_unreserve((*mem)->bo);
298allocate_mem_reserve_bo_failed:
299 radeon_bo_unref(&(*mem)->bo);
300
301 return r;
302}
303
304static void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
305{
306 struct kgd_mem *mem = (struct kgd_mem *) mem_obj;
307
308 BUG_ON(mem == NULL);
309
310 radeon_bo_reserve(mem->bo, true);
311 radeon_bo_kunmap(mem->bo);
312 radeon_bo_unpin(mem->bo);
313 radeon_bo_unreserve(mem->bo);
314 radeon_bo_unref(&(mem->bo));
315 kfree(mem);
316}
317
e28740ec
OG		 318static uint64_t get_vmem_size(struct kgd_dev *kgd)
319{
320 struct radeon_device *rdev = (struct radeon_device *)kgd;
321
322 BUG_ON(kgd == NULL);
323
324 return rdev->mc.real_vram_size;
325}
326
327static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
328{
329 struct radeon_device *rdev = (struct radeon_device *)kgd;
330
331 return rdev->asic->get_gpu_clock_counter(rdev);
332}
333
334static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
335{
336 struct radeon_device *rdev = (struct radeon_device *)kgd;
337
338 /* The sclk is in quantas of 10kHz */
339 return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100;
340}
341
342static inline struct radeon_device *get_radeon_device(struct kgd_dev *kgd)
343{
344 return (struct radeon_device *)kgd;
345}
346
347static void write_register(struct kgd_dev *kgd, uint32_t offset, uint32_t value)
348{
349 struct radeon_device *rdev = get_radeon_device(kgd);
350
351 writel(value, (void __iomem *)(rdev->rmmio + offset));
352}
353
354static uint32_t read_register(struct kgd_dev *kgd, uint32_t offset)
355{
356 struct radeon_device *rdev = get_radeon_device(kgd);
357
358 return readl((void __iomem *)(rdev->rmmio + offset));
359}
360
361static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
362 uint32_t queue, uint32_t vmid)
363{
364 struct radeon_device *rdev = get_radeon_device(kgd);
365 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
366
367 mutex_lock(&rdev->srbm_mutex);
368 write_register(kgd, SRBM_GFX_CNTL, value);
369}
370
371static void unlock_srbm(struct kgd_dev *kgd)
372{
373 struct radeon_device *rdev = get_radeon_device(kgd);
374
375 write_register(kgd, SRBM_GFX_CNTL, 0);
376 mutex_unlock(&rdev->srbm_mutex);
377}
378
379static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
380 uint32_t queue_id)
381{
382 uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
383 uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
384
385 lock_srbm(kgd, mec, pipe, queue_id, 0);
386}
387
388static void release_queue(struct kgd_dev *kgd)
389{
390 unlock_srbm(kgd);
391}
392
393static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
394 uint32_t sh_mem_config,
395 uint32_t sh_mem_ape1_base,
396 uint32_t sh_mem_ape1_limit,
397 uint32_t sh_mem_bases)
398{
399 lock_srbm(kgd, 0, 0, 0, vmid);
400
401 write_register(kgd, SH_MEM_CONFIG, sh_mem_config);
402 write_register(kgd, SH_MEM_APE1_BASE, sh_mem_ape1_base);
403 write_register(kgd, SH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
404 write_register(kgd, SH_MEM_BASES, sh_mem_bases);
405
406 unlock_srbm(kgd);
407}
408
409static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
410 unsigned int vmid)
411{
412 /*
413 * We have to assume that there is no outstanding mapping.
414 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0
415 * because a mapping is in progress or because a mapping finished and
416 * the SW cleared it.
417 * So the protocol is to always wait & clear.
418 */
edad4023
AS		 419 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
420 ATC_VMID_PASID_MAPPING_VALID_MASK;
e28740ec
OG		 421
422 write_register(kgd, ATC_VMID0_PASID_MAPPING + vmid*sizeof(uint32_t),
423 pasid_mapping);
424
425 while (!(read_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS) &
426 (1U << vmid)))
427 cpu_relax();
428 write_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
429
fec77bb5
BG		 430 /* Mapping vmid to pasid also for IH block */
431 write_register(kgd, IH_VMID_0_LUT + vmid * sizeof(uint32_t),
432 pasid_mapping);
433
e28740ec
OG		 434 return 0;
435}
436
e28740ec
OG		 437static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
438 uint32_t hpd_size, uint64_t hpd_gpu_addr)
439{
d59095f7 440 /* nothing to do here */
e28740ec
OG		 441 return 0;
442}
443
d36b94fc
OG		 444static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
445{
446 uint32_t mec;
447 uint32_t pipe;
448
449 mec = (pipe_id / CIK_PIPE_PER_MEC) + 1;
450 pipe = (pipe_id % CIK_PIPE_PER_MEC);
451
452 lock_srbm(kgd, mec, pipe, 0, 0);
453
454 write_register(kgd, CPC_INT_CNTL,
455 TIME_STAMP_INT_ENABLE | OPCODE_ERROR_INT_ENABLE);
456
457 unlock_srbm(kgd);
458
459 return 0;
460}
461
a84a9903
BG		 462static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
463{
464 uint32_t retval;
465
466 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
467 m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
468
469 pr_debug("kfd: sdma base address: 0x%x\n", retval);
470
471 return retval;
472}
473
e28740ec
OG		 474static inline struct cik_mqd *get_mqd(void *mqd)
475{
476 return (struct cik_mqd *)mqd;
477}
478
a84a9903
BG		 479static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
480{
481 return (struct cik_sdma_rlc_registers *)mqd;
482}
483
e28740ec
OG		 484static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
485 uint32_t queue_id, uint32_t __user *wptr)
486{
487 uint32_t wptr_shadow, is_wptr_shadow_valid;
488 struct cik_mqd *m;
489
490 m = get_mqd(mqd);
491
492 is_wptr_shadow_valid = !get_user(wptr_shadow, wptr);
493
494 acquire_queue(kgd, pipe_id, queue_id);
495 write_register(kgd, CP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo);
496 write_register(kgd, CP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi);
497 write_register(kgd, CP_MQD_CONTROL, m->cp_mqd_control);
498
499 write_register(kgd, CP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo);
500 write_register(kgd, CP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi);
501 write_register(kgd, CP_HQD_PQ_CONTROL, m->cp_hqd_pq_control);
502
503 write_register(kgd, CP_HQD_IB_CONTROL, m->cp_hqd_ib_control);
504 write_register(kgd, CP_HQD_IB_BASE_ADDR, m->cp_hqd_ib_base_addr_lo);
505 write_register(kgd, CP_HQD_IB_BASE_ADDR_HI, m->cp_hqd_ib_base_addr_hi);
506
507 write_register(kgd, CP_HQD_IB_RPTR, m->cp_hqd_ib_rptr);
508
509 write_register(kgd, CP_HQD_PERSISTENT_STATE,
510 m->cp_hqd_persistent_state);
511 write_register(kgd, CP_HQD_SEMA_CMD, m->cp_hqd_sema_cmd);
512 write_register(kgd, CP_HQD_MSG_TYPE, m->cp_hqd_msg_type);
513
514 write_register(kgd, CP_HQD_ATOMIC0_PREOP_LO,
515 m->cp_hqd_atomic0_preop_lo);
516
517 write_register(kgd, CP_HQD_ATOMIC0_PREOP_HI,
518 m->cp_hqd_atomic0_preop_hi);
519
520 write_register(kgd, CP_HQD_ATOMIC1_PREOP_LO,
521 m->cp_hqd_atomic1_preop_lo);
522
523 write_register(kgd, CP_HQD_ATOMIC1_PREOP_HI,
524 m->cp_hqd_atomic1_preop_hi);
525
526 write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR,
527 m->cp_hqd_pq_rptr_report_addr_lo);
528
529 write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR_HI,
530 m->cp_hqd_pq_rptr_report_addr_hi);
531
532 write_register(kgd, CP_HQD_PQ_RPTR, m->cp_hqd_pq_rptr);
533
534 write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR,
535 m->cp_hqd_pq_wptr_poll_addr_lo);
536
537 write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR_HI,
538 m->cp_hqd_pq_wptr_poll_addr_hi);
539
540 write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL,
541 m->cp_hqd_pq_doorbell_control);
542
543 write_register(kgd, CP_HQD_VMID, m->cp_hqd_vmid);
544
545 write_register(kgd, CP_HQD_QUANTUM, m->cp_hqd_quantum);
546
547 write_register(kgd, CP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority);
548 write_register(kgd, CP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority);
549
550 write_register(kgd, CP_HQD_IQ_RPTR, m->cp_hqd_iq_rptr);
551
552 if (is_wptr_shadow_valid)
553 write_register(kgd, CP_HQD_PQ_WPTR, wptr_shadow);
554
555 write_register(kgd, CP_HQD_ACTIVE, m->cp_hqd_active);
556 release_queue(kgd);
557
558 return 0;
559}
560
a84a9903
BG		 561static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
562{
563 struct cik_sdma_rlc_registers *m;
564 uint32_t sdma_base_addr;
565
566 m = get_sdma_mqd(mqd);
567 sdma_base_addr = get_sdma_base_addr(m);
568
569 write_register(kgd,
570 sdma_base_addr + SDMA0_RLC0_VIRTUAL_ADDR,
571 m->sdma_rlc_virtual_addr);
572
573 write_register(kgd,
574 sdma_base_addr + SDMA0_RLC0_RB_BASE,
575 m->sdma_rlc_rb_base);
576
577 write_register(kgd,
578 sdma_base_addr + SDMA0_RLC0_RB_BASE_HI,
579 m->sdma_rlc_rb_base_hi);
580
581 write_register(kgd,
582 sdma_base_addr + SDMA0_RLC0_RB_RPTR_ADDR_LO,
583 m->sdma_rlc_rb_rptr_addr_lo);
584
585 write_register(kgd,
586 sdma_base_addr + SDMA0_RLC0_RB_RPTR_ADDR_HI,
587 m->sdma_rlc_rb_rptr_addr_hi);
588
589 write_register(kgd,
590 sdma_base_addr + SDMA0_RLC0_DOORBELL,
591 m->sdma_rlc_doorbell);
592
593 write_register(kgd,
594 sdma_base_addr + SDMA0_RLC0_RB_CNTL,
595 m->sdma_rlc_rb_cntl);
596
597 return 0;
598}
599
b64b8afc 600static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
e28740ec
OG		 601 uint32_t pipe_id, uint32_t queue_id)
602{
603 uint32_t act;
604 bool retval = false;
605 uint32_t low, high;
606
607 acquire_queue(kgd, pipe_id, queue_id);
608 act = read_register(kgd, CP_HQD_ACTIVE);
609 if (act) {
610 low = lower_32_bits(queue_address >> 8);
611 high = upper_32_bits(queue_address >> 8);
612
613 if (low == read_register(kgd, CP_HQD_PQ_BASE) &&
614 high == read_register(kgd, CP_HQD_PQ_BASE_HI))
615 retval = true;
616 }
617 release_queue(kgd);
618 return retval;
619}
620
a84a9903
BG		 621static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
622{
623 struct cik_sdma_rlc_registers *m;
624 uint32_t sdma_base_addr;
625 uint32_t sdma_rlc_rb_cntl;
626
627 m = get_sdma_mqd(mqd);
628 sdma_base_addr = get_sdma_base_addr(m);
629
630 sdma_rlc_rb_cntl = read_register(kgd,
631 sdma_base_addr + SDMA0_RLC0_RB_CNTL);
632
633 if (sdma_rlc_rb_cntl & SDMA_RB_ENABLE)
634 return true;
635
636 return false;
637}
638
e28740ec
OG		 639static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
640 unsigned int timeout, uint32_t pipe_id,
641 uint32_t queue_id)
642{
643 uint32_t temp;
644
645 acquire_queue(kgd, pipe_id, queue_id);
646 write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL, 0);
647
648 write_register(kgd, CP_HQD_DEQUEUE_REQUEST, reset_type);
649
650 while (true) {
651 temp = read_register(kgd, CP_HQD_ACTIVE);
652 if (temp & 0x1)
653 break;
654 if (timeout == 0) {
655 pr_err("kfd: cp queue preemption time out (%dms)\n",
656 temp);
4c18442e 657 release_queue(kgd);
e28740ec
OG		 658 return -ETIME;
659 }
660 msleep(20);
661 timeout -= 20;
662 }
663
664 release_queue(kgd);
665 return 0;
666}
f7694323 667
a84a9903
BG		 668static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
669 unsigned int timeout)
670{
671 struct cik_sdma_rlc_registers *m;
672 uint32_t sdma_base_addr;
673 uint32_t temp;
674
675 m = get_sdma_mqd(mqd);
676 sdma_base_addr = get_sdma_base_addr(m);
677
678 temp = read_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_CNTL);
679 temp = temp & ~SDMA_RB_ENABLE;
680 write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_CNTL, temp);
681
682 while (true) {
683 temp = read_register(kgd, sdma_base_addr +
684 SDMA0_RLC0_CONTEXT_STATUS);
685 if (temp & SDMA_RLC_IDLE)
686 break;
687 if (timeout == 0)
688 return -ETIME;
689 msleep(20);
690 timeout -= 20;
691 }
692
693 write_register(kgd, sdma_base_addr + SDMA0_RLC0_DOORBELL, 0);
694 write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_RPTR, 0);
695 write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_WPTR, 0);
696 write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_BASE, 0);
697
698 return 0;
699}
700
a6186f4d
YS		 701static int kgd_address_watch_disable(struct kgd_dev *kgd)
702{
703 union TCP_WATCH_CNTL_BITS cntl;
704 unsigned int i;
705
706 cntl.u32All = 0;
707
708 cntl.bitfields.valid = 0;
709 cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
710 cntl.bitfields.atc = 1;
711
712 /* Turning off this address until we set all the registers */
713 for (i = 0; i < MAX_WATCH_ADDRESSES; i++)
714 write_register(kgd,
715 watchRegs[i * ADDRESS_WATCH_REG_MAX +
716 ADDRESS_WATCH_REG_CNTL],
717 cntl.u32All);
718
719 return 0;
720}
721
722static int kgd_address_watch_execute(struct kgd_dev *kgd,
723 unsigned int watch_point_id,
724 uint32_t cntl_val,
725 uint32_t addr_hi,
726 uint32_t addr_lo)
727{
728 union TCP_WATCH_CNTL_BITS cntl;
729
730 cntl.u32All = cntl_val;
731
732 /* Turning off this watch point until we set all the registers */
733 cntl.bitfields.valid = 0;
734 write_register(kgd,
735 watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
736 ADDRESS_WATCH_REG_CNTL],
737 cntl.u32All);
738
739 write_register(kgd,
740 watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
741 ADDRESS_WATCH_REG_ADDR_HI],
742 addr_hi);
743
744 write_register(kgd,
745 watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
746 ADDRESS_WATCH_REG_ADDR_LO],
747 addr_lo);
748
749 /* Enable the watch point */
750 cntl.bitfields.valid = 1;
751
752 write_register(kgd,
753 watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
754 ADDRESS_WATCH_REG_CNTL],
755 cntl.u32All);
756
757 return 0;
758}
759
760static int kgd_wave_control_execute(struct kgd_dev *kgd,
761 uint32_t gfx_index_val,
762 uint32_t sq_cmd)
763{
764 struct radeon_device *rdev = get_radeon_device(kgd);
765 uint32_t data;
766
767 mutex_lock(&rdev->grbm_idx_mutex);
768
769 write_register(kgd, GRBM_GFX_INDEX, gfx_index_val);
770 write_register(kgd, SQ_CMD, sq_cmd);
771
772 /* Restore the GRBM_GFX_INDEX register */
773
774 data = INSTANCE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
775 SE_BROADCAST_WRITES;
776
777 write_register(kgd, GRBM_GFX_INDEX, data);
778
779 mutex_unlock(&rdev->grbm_idx_mutex);
780
781 return 0;
782}
783
784static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
785 unsigned int watch_point_id,
786 unsigned int reg_offset)
787{
788 return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
789}
790
edad4023
AS		 791static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid)
792{
793 uint32_t reg;
794 struct radeon_device *rdev = (struct radeon_device *) kgd;
795
796 reg = RREG32(ATC_VMID0_PASID_MAPPING + vmid*4);
797 return reg & ATC_VMID_PASID_MAPPING_VALID_MASK;
798}
799
800static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
801 uint8_t vmid)
802{
803 uint32_t reg;
804 struct radeon_device *rdev = (struct radeon_device *) kgd;
805
806 reg = RREG32(ATC_VMID0_PASID_MAPPING + vmid*4);
807 return reg & ATC_VMID_PASID_MAPPING_PASID_MASK;
808}
809
810static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid)
811{
812 struct radeon_device *rdev = (struct radeon_device *) kgd;
813
814 return WREG32(VM_INVALIDATE_REQUEST, 1 << vmid);
815}
816
f7694323
OG		 817static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
818{
819 struct radeon_device *rdev = (struct radeon_device *) kgd;
820 const union radeon_firmware_header *hdr;
821
822 BUG_ON(kgd == NULL || rdev->mec_fw == NULL);
823
824 switch (type) {
825 case KGD_ENGINE_PFP:
826 hdr = (const union radeon_firmware_header *) rdev->pfp_fw->data;
827 break;
828
829 case KGD_ENGINE_ME:
830 hdr = (const union radeon_firmware_header *) rdev->me_fw->data;
831 break;
832
833 case KGD_ENGINE_CE:
834 hdr = (const union radeon_firmware_header *) rdev->ce_fw->data;
835 break;
836
837 case KGD_ENGINE_MEC1:
838 hdr = (const union radeon_firmware_header *) rdev->mec_fw->data;
839 break;
840
841 case KGD_ENGINE_MEC2:
842 hdr = (const union radeon_firmware_header *)
843 rdev->mec2_fw->data;
844 break;
845
846 case KGD_ENGINE_RLC:
847 hdr = (const union radeon_firmware_header *) rdev->rlc_fw->data;
848 break;
849
22801f76
OG		 850 case KGD_ENGINE_SDMA1:
851 case KGD_ENGINE_SDMA2:
f7694323
OG		 852 hdr = (const union radeon_firmware_header *)
853 rdev->sdma_fw->data;
854 break;
855
856 default:
857 return 0;
858 }
859
860 if (hdr == NULL)
861 return 0;
862
863 /* Only 12 bit in use*/
864 return hdr->common.ucode_version;
865}
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