]>
Commit | Line | Data |
---|---|---|
771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include "drmP.h" | |
29 | #include "drm_sarea.h" | |
30 | #include "radeon.h" | |
31 | #include "radeon_drm.h" | |
32 | ||
6a9ee8af | 33 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
6a9ee8af | 35 | |
cf0fe456 JG |
36 | int radeon_driver_unload_kms(struct drm_device *dev) |
37 | { | |
38 | struct radeon_device *rdev = dev->dev_private; | |
39 | ||
40 | if (rdev == NULL) | |
41 | return 0; | |
42 | radeon_modeset_fini(rdev); | |
43 | radeon_device_fini(rdev); | |
44 | kfree(rdev); | |
45 | dev->dev_private = NULL; | |
46 | return 0; | |
47 | } | |
771fe6b9 | 48 | |
771fe6b9 JG |
49 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
50 | { | |
51 | struct radeon_device *rdev; | |
52 | int r; | |
53 | ||
54 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); | |
55 | if (rdev == NULL) { | |
56 | return -ENOMEM; | |
57 | } | |
58 | dev->dev_private = (void *)rdev; | |
59 | ||
60 | /* update BUS flag */ | |
61 | if (drm_device_is_agp(dev)) { | |
62 | flags |= RADEON_IS_AGP; | |
63 | } else if (drm_device_is_pcie(dev)) { | |
64 | flags |= RADEON_IS_PCIE; | |
65 | } else { | |
66 | flags |= RADEON_IS_PCI; | |
67 | } | |
68 | ||
6cf8a3f5 JG |
69 | /* radeon_device_init should report only fatal error |
70 | * like memory allocation failure or iomapping failure, | |
71 | * or memory manager initialization failure, it must | |
72 | * properly initialize the GPU MC controller and permit | |
73 | * VRAM allocation | |
74 | */ | |
771fe6b9 JG |
75 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
76 | if (r) { | |
cf0fe456 JG |
77 | dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); |
78 | goto out; | |
6cf8a3f5 JG |
79 | } |
80 | /* Again modeset_init should fail only on fatal error | |
81 | * otherwise it should provide enough functionalities | |
82 | * for shadowfb to run | |
83 | */ | |
84 | r = radeon_modeset_init(rdev); | |
cf0fe456 JG |
85 | if (r) |
86 | dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); | |
87 | out: | |
88 | if (r) | |
89 | radeon_driver_unload_kms(dev); | |
90 | return r; | |
771fe6b9 JG |
91 | } |
92 | ||
93 | ||
94 | /* | |
95 | * Userspace get informations ioctl | |
96 | */ | |
97 | int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |
98 | { | |
99 | struct radeon_device *rdev = dev->dev_private; | |
100 | struct drm_radeon_info *info; | |
bc35afdb | 101 | struct radeon_mode_info *minfo = &rdev->mode_info; |
771fe6b9 JG |
102 | uint32_t *value_ptr; |
103 | uint32_t value; | |
bc35afdb JG |
104 | struct drm_crtc *crtc; |
105 | int i, found; | |
771fe6b9 JG |
106 | |
107 | info = data; | |
108 | value_ptr = (uint32_t *)((unsigned long)info->value); | |
bc35afdb | 109 | value = *value_ptr; |
771fe6b9 JG |
110 | switch (info->request) { |
111 | case RADEON_INFO_DEVICE_ID: | |
112 | value = dev->pci_device; | |
113 | break; | |
114 | case RADEON_INFO_NUM_GB_PIPES: | |
115 | value = rdev->num_gb_pipes; | |
116 | break; | |
f779b3e5 AD |
117 | case RADEON_INFO_NUM_Z_PIPES: |
118 | value = rdev->num_z_pipes; | |
119 | break; | |
733289c2 | 120 | case RADEON_INFO_ACCEL_WORKING: |
148a03bc AD |
121 | /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ |
122 | if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) | |
123 | value = false; | |
124 | else | |
125 | value = rdev->accel_working; | |
733289c2 | 126 | break; |
bc35afdb JG |
127 | case RADEON_INFO_CRTC_FROM_ID: |
128 | for (i = 0, found = 0; i < rdev->num_crtc; i++) { | |
129 | crtc = (struct drm_crtc *)minfo->crtcs[i]; | |
130 | if (crtc && crtc->base.id == value) { | |
131 | value = i; | |
132 | found = 1; | |
133 | break; | |
134 | } | |
135 | } | |
136 | if (!found) { | |
137 | DRM_DEBUG("unknown crtc id %d\n", value); | |
138 | return -EINVAL; | |
139 | } | |
140 | break; | |
148a03bc AD |
141 | case RADEON_INFO_ACCEL_WORKING2: |
142 | value = rdev->accel_working; | |
143 | break; | |
771fe6b9 JG |
144 | default: |
145 | DRM_DEBUG("Invalid request %d\n", info->request); | |
146 | return -EINVAL; | |
147 | } | |
148 | if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) { | |
149 | DRM_ERROR("copy_to_user\n"); | |
150 | return -EFAULT; | |
151 | } | |
152 | return 0; | |
153 | } | |
154 | ||
155 | ||
156 | /* | |
157 | * Outdated mess for old drm with Xorg being in charge (void function now). | |
158 | */ | |
159 | int radeon_driver_firstopen_kms(struct drm_device *dev) | |
160 | { | |
161 | return 0; | |
162 | } | |
163 | ||
164 | ||
165 | void radeon_driver_lastclose_kms(struct drm_device *dev) | |
166 | { | |
6a9ee8af | 167 | vga_switcheroo_process_delayed_switch(); |
771fe6b9 JG |
168 | } |
169 | ||
170 | int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) | |
171 | { | |
172 | return 0; | |
173 | } | |
174 | ||
175 | void radeon_driver_postclose_kms(struct drm_device *dev, | |
176 | struct drm_file *file_priv) | |
177 | { | |
178 | } | |
179 | ||
180 | void radeon_driver_preclose_kms(struct drm_device *dev, | |
181 | struct drm_file *file_priv) | |
182 | { | |
183 | } | |
184 | ||
185 | ||
186 | /* | |
187 | * VBlank related functions. | |
188 | */ | |
189 | u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) | |
190 | { | |
7ed220d7 MD |
191 | struct radeon_device *rdev = dev->dev_private; |
192 | ||
9c950a43 | 193 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
7ed220d7 MD |
194 | DRM_ERROR("Invalid crtc %d\n", crtc); |
195 | return -EINVAL; | |
196 | } | |
197 | ||
198 | return radeon_get_vblank_counter(rdev, crtc); | |
771fe6b9 JG |
199 | } |
200 | ||
201 | int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) | |
202 | { | |
7ed220d7 MD |
203 | struct radeon_device *rdev = dev->dev_private; |
204 | ||
9c950a43 | 205 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
7ed220d7 MD |
206 | DRM_ERROR("Invalid crtc %d\n", crtc); |
207 | return -EINVAL; | |
208 | } | |
209 | ||
210 | rdev->irq.crtc_vblank_int[crtc] = true; | |
211 | ||
212 | return radeon_irq_set(rdev); | |
771fe6b9 JG |
213 | } |
214 | ||
215 | void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) | |
216 | { | |
7ed220d7 MD |
217 | struct radeon_device *rdev = dev->dev_private; |
218 | ||
9c950a43 | 219 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
7ed220d7 MD |
220 | DRM_ERROR("Invalid crtc %d\n", crtc); |
221 | return; | |
222 | } | |
223 | ||
224 | rdev->irq.crtc_vblank_int[crtc] = false; | |
225 | ||
226 | radeon_irq_set(rdev); | |
771fe6b9 JG |
227 | } |
228 | ||
229 | ||
771fe6b9 JG |
230 | /* |
231 | * IOCTL. | |
232 | */ | |
233 | int radeon_dma_ioctl_kms(struct drm_device *dev, void *data, | |
234 | struct drm_file *file_priv) | |
235 | { | |
236 | /* Not valid in KMS. */ | |
237 | return -EINVAL; | |
238 | } | |
239 | ||
240 | #define KMS_INVALID_IOCTL(name) \ | |
241 | int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\ | |
242 | { \ | |
243 | DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ | |
244 | return -EINVAL; \ | |
245 | } | |
246 | ||
247 | /* | |
248 | * All these ioctls are invalid in kms world. | |
249 | */ | |
250 | KMS_INVALID_IOCTL(radeon_cp_init_kms) | |
251 | KMS_INVALID_IOCTL(radeon_cp_start_kms) | |
252 | KMS_INVALID_IOCTL(radeon_cp_stop_kms) | |
253 | KMS_INVALID_IOCTL(radeon_cp_reset_kms) | |
254 | KMS_INVALID_IOCTL(radeon_cp_idle_kms) | |
255 | KMS_INVALID_IOCTL(radeon_cp_resume_kms) | |
256 | KMS_INVALID_IOCTL(radeon_engine_reset_kms) | |
257 | KMS_INVALID_IOCTL(radeon_fullscreen_kms) | |
258 | KMS_INVALID_IOCTL(radeon_cp_swap_kms) | |
259 | KMS_INVALID_IOCTL(radeon_cp_clear_kms) | |
260 | KMS_INVALID_IOCTL(radeon_cp_vertex_kms) | |
261 | KMS_INVALID_IOCTL(radeon_cp_indices_kms) | |
262 | KMS_INVALID_IOCTL(radeon_cp_texture_kms) | |
263 | KMS_INVALID_IOCTL(radeon_cp_stipple_kms) | |
264 | KMS_INVALID_IOCTL(radeon_cp_indirect_kms) | |
265 | KMS_INVALID_IOCTL(radeon_cp_vertex2_kms) | |
266 | KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms) | |
267 | KMS_INVALID_IOCTL(radeon_cp_getparam_kms) | |
268 | KMS_INVALID_IOCTL(radeon_cp_flip_kms) | |
269 | KMS_INVALID_IOCTL(radeon_mem_alloc_kms) | |
270 | KMS_INVALID_IOCTL(radeon_mem_free_kms) | |
271 | KMS_INVALID_IOCTL(radeon_mem_init_heap_kms) | |
272 | KMS_INVALID_IOCTL(radeon_irq_emit_kms) | |
273 | KMS_INVALID_IOCTL(radeon_irq_wait_kms) | |
274 | KMS_INVALID_IOCTL(radeon_cp_setparam_kms) | |
275 | KMS_INVALID_IOCTL(radeon_surface_alloc_kms) | |
276 | KMS_INVALID_IOCTL(radeon_surface_free_kms) | |
277 | ||
278 | ||
279 | struct drm_ioctl_desc radeon_ioctls_kms[] = { | |
280 | DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
281 | DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
282 | DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
283 | DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
284 | DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), | |
285 | DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), | |
286 | DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), | |
287 | DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), | |
288 | DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), | |
289 | DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), | |
290 | DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), | |
291 | DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), | |
292 | DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), | |
293 | DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), | |
294 | DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
295 | DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), | |
296 | DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), | |
297 | DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), | |
298 | DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), | |
299 | DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), | |
300 | DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), | |
301 | DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
302 | DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), | |
303 | DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), | |
304 | DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), | |
305 | DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), | |
306 | DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), | |
307 | /* KMS */ | |
a0c07a69 DA |
308 | DRM_IOCTL_DEF(DRM_RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED), |
309 | DRM_IOCTL_DEF(DRM_RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
310 | DRM_IOCTL_DEF(DRM_RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
311 | DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
312 | DRM_IOCTL_DEF(DRM_RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
313 | DRM_IOCTL_DEF(DRM_RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
314 | DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
315 | DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
316 | DRM_IOCTL_DEF(DRM_RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
317 | DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
318 | DRM_IOCTL_DEF(DRM_RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
319 | DRM_IOCTL_DEF(DRM_RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
771fe6b9 JG |
320 | }; |
321 | int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms); |