[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / radeon / radeon_kms.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include "drmP.h"
#include "drm_sarea.h"
#include "radeon.h"
#include "radeon_drm.h"

#include <linux/vga_switcheroo.h>
#include <linux/slab.h>

int radeon_driver_unload_kms(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;

	if (rdev == NULL)
		return 0;
	radeon_modeset_fini(rdev);
	radeon_device_fini(rdev);
	kfree(rdev);
	dev->dev_private = NULL;
	return 0;
}

int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
{
	struct radeon_device *rdev;
	int r, acpi_status;

	rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
	if (rdev == NULL) {
		return -ENOMEM;
	}
	dev->dev_private = (void *)rdev;

	/* update BUS flag */
	if (drm_pci_device_is_agp(dev)) {
		flags |= RADEON_IS_AGP;
	} else if (drm_pci_device_is_pcie(dev)) {
		flags |= RADEON_IS_PCIE;
	} else {
		flags |= RADEON_IS_PCI;
	}

	/* radeon_device_init should report only fatal error
	 * like memory allocation failure or iomapping failure,
	 * or memory manager initialization failure, it must
	 * properly initialize the GPU MC controller and permit
	 * VRAM allocation
	 */
	r = radeon_device_init(rdev, dev, dev->pdev, flags);
	if (r) {
		dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
		goto out;
	}

	/* Call ACPI methods */
	acpi_status = radeon_acpi_init(rdev);
	if (acpi_status)
		dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");

	/* Again modeset_init should fail only on fatal error
	 * otherwise it should provide enough functionalities
	 * for shadowfb to run
	 */
	r = radeon_modeset_init(rdev);
	if (r)
		dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
out:
	if (r)
		radeon_driver_unload_kms(dev);
	return r;
}

static void radeon_set_filp_rights(struct drm_device *dev,
				   struct drm_file **owner,
				   struct drm_file *applier,
				   uint32_t *value)
{
	mutex_lock(&dev->struct_mutex);
	if (*value == 1) {
		/* wants rights */
		if (!*owner)
			*owner = applier;
	} else if (*value == 0) {
		/* revokes rights */
		if (*owner == applier)
			*owner = NULL;
	}
	*value = *owner == applier ? 1 : 0;
	mutex_unlock(&dev->struct_mutex);
}

/*
 * Userspace get information ioctl
 */
int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
	struct radeon_device *rdev = dev->dev_private;
	struct drm_radeon_info *info;
	struct radeon_mode_info *minfo = &rdev->mode_info;
	uint32_t *value_ptr;
	uint32_t value;
	struct drm_crtc *crtc;
	int i, found;

	info = data;
	value_ptr = (uint32_t *)((unsigned long)info->value);
	if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value)))
		return -EFAULT;

	switch (info->request) {
	case RADEON_INFO_DEVICE_ID:
		value = dev->pci_device;
		break;
	case RADEON_INFO_NUM_GB_PIPES:
		value = rdev->num_gb_pipes;
		break;
	case RADEON_INFO_NUM_Z_PIPES:
		value = rdev->num_z_pipes;
		break;
	case RADEON_INFO_ACCEL_WORKING:
		/* xf86-video-ati 6.13.0 relies on this being false for evergreen */
		if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
			value = false;
		else
			value = rdev->accel_working;
		break;
	case RADEON_INFO_CRTC_FROM_ID:
		for (i = 0, found = 0; i < rdev->num_crtc; i++) {
			crtc = (struct drm_crtc *)minfo->crtcs[i];
			if (crtc && crtc->base.id == value) {
				struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
				value = radeon_crtc->crtc_id;
				found = 1;
				break;
			}
		}
		if (!found) {
			DRM_DEBUG_KMS("unknown crtc id %d\n", value);
			return -EINVAL;
		}
		break;
	case RADEON_INFO_ACCEL_WORKING2:
		value = rdev->accel_working;
		break;
	case RADEON_INFO_TILING_CONFIG:
		if (rdev->family >= CHIP_CAYMAN)
			value = rdev->config.cayman.tile_config;
		else if (rdev->family >= CHIP_CEDAR)
			value = rdev->config.evergreen.tile_config;
		else if (rdev->family >= CHIP_RV770)
			value = rdev->config.rv770.tile_config;
		else if (rdev->family >= CHIP_R600)
			value = rdev->config.r600.tile_config;
		else {
			DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
			return -EINVAL;
		}
		break;
	case RADEON_INFO_WANT_HYPERZ:
		/* The "value" here is both an input and output parameter.
		 * If the input value is 1, filp requests hyper-z access.
		 * If the input value is 0, filp revokes its hyper-z access.
		 *
		 * When returning, the value is 1 if filp owns hyper-z access,
		 * 0 otherwise. */
		if (value >= 2) {
			DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
			return -EINVAL;
		}
		radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value);
		break;
	case RADEON_INFO_WANT_CMASK:
		/* The same logic as Hyper-Z. */
		if (value >= 2) {
			DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value);
			return -EINVAL;
		}
		radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value);
		break;
	case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
		/* return clock value in KHz */
		value = rdev->clock.spll.reference_freq * 10;
		break;
	case RADEON_INFO_NUM_BACKENDS:
		if (rdev->family >= CHIP_CAYMAN)
			value = rdev->config.cayman.max_backends_per_se *
				rdev->config.cayman.max_shader_engines;
		else if (rdev->family >= CHIP_CEDAR)
			value = rdev->config.evergreen.max_backends;
		else if (rdev->family >= CHIP_RV770)
			value = rdev->config.rv770.max_backends;
		else if (rdev->family >= CHIP_R600)
			value = rdev->config.r600.max_backends;
		else {
			return -EINVAL;
		}
		break;
	case RADEON_INFO_NUM_TILE_PIPES:
		if (rdev->family >= CHIP_CAYMAN)
			value = rdev->config.cayman.max_tile_pipes;
		else if (rdev->family >= CHIP_CEDAR)
			value = rdev->config.evergreen.max_tile_pipes;
		else if (rdev->family >= CHIP_RV770)
			value = rdev->config.rv770.max_tile_pipes;
		else if (rdev->family >= CHIP_R600)
			value = rdev->config.r600.max_tile_pipes;
		else {
			return -EINVAL;
		}
		break;
	case RADEON_INFO_FUSION_GART_WORKING:
		value = 1;
		break;
	default:
		DRM_DEBUG_KMS("Invalid request %d\n", info->request);
		return -EINVAL;
	}
	if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
		DRM_ERROR("copy_to_user\n");
		return -EFAULT;
	}
	return 0;
}


/*
 * Outdated mess for old drm with Xorg being in charge (void function now).
 */
int radeon_driver_firstopen_kms(struct drm_device *dev)
{
	return 0;
}


void radeon_driver_lastclose_kms(struct drm_device *dev)
{
	vga_switcheroo_process_delayed_switch();
}

int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
{
	return 0;
}

void radeon_driver_postclose_kms(struct drm_device *dev,
				 struct drm_file *file_priv)
{
}

void radeon_driver_preclose_kms(struct drm_device *dev,
				struct drm_file *file_priv)
{
	struct radeon_device *rdev = dev->dev_private;
	if (rdev->hyperz_filp == file_priv)
		rdev->hyperz_filp = NULL;
	if (rdev->cmask_filp == file_priv)
		rdev->cmask_filp = NULL;
}

/*
 * VBlank related functions.
 */
u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
{
	struct radeon_device *rdev = dev->dev_private;

	if (crtc < 0 || crtc >= rdev->num_crtc) {
		DRM_ERROR("Invalid crtc %d\n", crtc);
		return -EINVAL;
	}

	return radeon_get_vblank_counter(rdev, crtc);
}

int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
{
	struct radeon_device *rdev = dev->dev_private;

	if (crtc < 0 || crtc >= rdev->num_crtc) {
		DRM_ERROR("Invalid crtc %d\n", crtc);
		return -EINVAL;
	}

	rdev->irq.crtc_vblank_int[crtc] = true;

	return radeon_irq_set(rdev);
}

void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
{
	struct radeon_device *rdev = dev->dev_private;

	if (crtc < 0 || crtc >= rdev->num_crtc) {
		DRM_ERROR("Invalid crtc %d\n", crtc);
		return;
	}

	rdev->irq.crtc_vblank_int[crtc] = false;

	radeon_irq_set(rdev);
}

int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
				    int *max_error,
				    struct timeval *vblank_time,
				    unsigned flags)
{
	struct drm_crtc *drmcrtc;
	struct radeon_device *rdev = dev->dev_private;

	if (crtc < 0 || crtc >= dev->num_crtcs) {
		DRM_ERROR("Invalid crtc %d\n", crtc);
		return -EINVAL;
	}

	/* Get associated drm_crtc: */
	drmcrtc = &rdev->mode_info.crtcs[crtc]->base;

	/* Helper routine in DRM core does all the work: */
	return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
						     vblank_time, flags,
						     drmcrtc);
}

/*
 * IOCTL.
 */
int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	/* Not valid in KMS. */
	return -EINVAL;
}

#define KMS_INVALID_IOCTL(name)						\
int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
{									\
	DRM_ERROR("invalid ioctl with kms %s\n", __func__);		\
	return -EINVAL;							\
}

/*
 * All these ioctls are invalid in kms world.
 */
KMS_INVALID_IOCTL(radeon_cp_init_kms)
KMS_INVALID_IOCTL(radeon_cp_start_kms)
KMS_INVALID_IOCTL(radeon_cp_stop_kms)
KMS_INVALID_IOCTL(radeon_cp_reset_kms)
KMS_INVALID_IOCTL(radeon_cp_idle_kms)
KMS_INVALID_IOCTL(radeon_cp_resume_kms)
KMS_INVALID_IOCTL(radeon_engine_reset_kms)
KMS_INVALID_IOCTL(radeon_fullscreen_kms)
KMS_INVALID_IOCTL(radeon_cp_swap_kms)
KMS_INVALID_IOCTL(radeon_cp_clear_kms)
KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
KMS_INVALID_IOCTL(radeon_cp_indices_kms)
KMS_INVALID_IOCTL(radeon_cp_texture_kms)
KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
KMS_INVALID_IOCTL(radeon_cp_flip_kms)
KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
KMS_INVALID_IOCTL(radeon_mem_free_kms)
KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
KMS_INVALID_IOCTL(radeon_irq_emit_kms)
KMS_INVALID_IOCTL(radeon_irq_wait_kms)
KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
KMS_INVALID_IOCTL(radeon_surface_free_kms)


struct drm_ioctl_desc radeon_ioctls_kms[] = {
	DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
	/* KMS */
	DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
};
int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#include "drmP.h"
	29	#include "drm_sarea.h"
	30	#include "radeon.h"
	31	#include "radeon_drm.h"
	32
6a9ee8af	33	#include <linux/vga_switcheroo.h>
5a0e3ad6	34	#include <linux/slab.h>
6a9ee8af	35
cf0fe456 JG	36	int radeon_driver_unload_kms(struct drm_device *dev)
	37	{
	38	struct radeon_device *rdev = dev->dev_private;
	39
	40	if (rdev == NULL)
	41	return 0;
	42	radeon_modeset_fini(rdev);
	43	radeon_device_fini(rdev);
	44	kfree(rdev);
	45	dev->dev_private = NULL;
	46	return 0;
	47	}
771fe6b9	48
771fe6b9 JG	49	int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
	50	{
	51	struct radeon_device *rdev;
d7a2952f	52	int r, acpi_status;
771fe6b9 JG	53
	54	rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
	55	if (rdev == NULL) {
	56	return -ENOMEM;
	57	}
	58	dev->dev_private = (void *)rdev;
	59
	60	/* update BUS flag */
8410ea3b	61	if (drm_pci_device_is_agp(dev)) {
771fe6b9	62	flags \|= RADEON_IS_AGP;
8410ea3b	63	} else if (drm_pci_device_is_pcie(dev)) {
771fe6b9 JG	64	flags \|= RADEON_IS_PCIE;
	65	} else {
	66	flags \|= RADEON_IS_PCI;
	67	}
	68
6cf8a3f5 JG	69	/* radeon_device_init should report only fatal error
	70	* like memory allocation failure or iomapping failure,
	71	* or memory manager initialization failure, it must
	72	* properly initialize the GPU MC controller and permit
	73	* VRAM allocation
	74	*/
771fe6b9 JG	75	r = radeon_device_init(rdev, dev, dev->pdev, flags);
771fe6b9 JG	76	if (r) {
cf0fe456 JG	77	dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
cf0fe456 JG	78	goto out;
6cf8a3f5	79	}
d7a2952f AM	80
	81	/* Call ACPI methods */
	82	acpi_status = radeon_acpi_init(rdev);
	83	if (acpi_status)
dc77de12	84	dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
d7a2952f	85
6cf8a3f5 JG	86	/* Again modeset_init should fail only on fatal error
	87	* otherwise it should provide enough functionalities
	88	* for shadowfb to run
	89	*/
	90	r = radeon_modeset_init(rdev);
cf0fe456 JG	91	if (r)
	92	dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
	93	out:
	94	if (r)
	95	radeon_driver_unload_kms(dev);
	96	return r;
771fe6b9 JG	97	}
771fe6b9 JG	98
9eba4a93 MO	99	static void radeon_set_filp_rights(struct drm_device *dev,
	100	struct drm_file **owner,
	101	struct drm_file *applier,
	102	uint32_t *value)
	103	{
	104	mutex_lock(&dev->struct_mutex);
	105	if (*value == 1) {
	106	/* wants rights */
	107	if (!*owner)
	108	*owner = applier;
	109	} else if (*value == 0) {
	110	/* revokes rights */
	111	if (*owner == applier)
	112	*owner = NULL;
	113	}
	114	value = owner == applier ? 1 : 0;
	115	mutex_unlock(&dev->struct_mutex);
	116	}
771fe6b9 JG	117
771fe6b9 JG	118	/*
9eba4a93	119	* Userspace get information ioctl
771fe6b9 JG	120	*/
	121	int radeon_info_ioctl(struct drm_device dev, void data, struct drm_file *filp)
	122	{
	123	struct radeon_device *rdev = dev->dev_private;
	124	struct drm_radeon_info *info;
bc35afdb	125	struct radeon_mode_info *minfo = &rdev->mode_info;
771fe6b9 JG	126	uint32_t *value_ptr;
771fe6b9 JG	127	uint32_t value;
bc35afdb JG	128	struct drm_crtc *crtc;
bc35afdb JG	129	int i, found;
771fe6b9 JG	130
	131	info = data;
	132	value_ptr = (uint32_t *)((unsigned long)info->value);
d8ab3557 DDAG	133	if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value)))
	134	return -EFAULT;
	135
771fe6b9 JG	136	switch (info->request) {
	137	case RADEON_INFO_DEVICE_ID:
	138	value = dev->pci_device;
	139	break;
	140	case RADEON_INFO_NUM_GB_PIPES:
	141	value = rdev->num_gb_pipes;
	142	break;
f779b3e5 AD	143	case RADEON_INFO_NUM_Z_PIPES:
	144	value = rdev->num_z_pipes;
	145	break;
733289c2	146	case RADEON_INFO_ACCEL_WORKING:
148a03bc AD	147	/* xf86-video-ati 6.13.0 relies on this being false for evergreen */
	148	if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
	149	value = false;
	150	else
	151	value = rdev->accel_working;
733289c2	152	break;
bc35afdb JG	153	case RADEON_INFO_CRTC_FROM_ID:
	154	for (i = 0, found = 0; i < rdev->num_crtc; i++) {
	155	crtc = (struct drm_crtc *)minfo->crtcs[i];
	156	if (crtc && crtc->base.id == value) {
0baf2d8f AD	157	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
0baf2d8f AD	158	value = radeon_crtc->crtc_id;
bc35afdb JG	159	found = 1;
	160	break;
	161	}
	162	}
	163	if (!found) {
d9fdaafb	164	DRM_DEBUG_KMS("unknown crtc id %d\n", value);
bc35afdb JG	165	return -EINVAL;
	166	}
	167	break;
148a03bc AD	168	case RADEON_INFO_ACCEL_WORKING2:
	169	value = rdev->accel_working;
	170	break;
e7aeeba6	171	case RADEON_INFO_TILING_CONFIG:
fecf1d07 AD	172	if (rdev->family >= CHIP_CAYMAN)
	173	value = rdev->config.cayman.tile_config;
	174	else if (rdev->family >= CHIP_CEDAR)
e7aeeba6 AD	175	value = rdev->config.evergreen.tile_config;
	176	else if (rdev->family >= CHIP_RV770)
	177	value = rdev->config.rv770.tile_config;
	178	else if (rdev->family >= CHIP_R600)
	179	value = rdev->config.r600.tile_config;
	180	else {
d9fdaafb	181	DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
e7aeeba6 AD	182	return -EINVAL;
e7aeeba6 AD	183	}
b824b364	184	break;
ab9e1f59	185	case RADEON_INFO_WANT_HYPERZ:
43861f71 MO	186	/* The "value" here is both an input and output parameter.
	187	* If the input value is 1, filp requests hyper-z access.
	188	* If the input value is 0, filp revokes its hyper-z access.
	189	*
	190	* When returning, the value is 1 if filp owns hyper-z access,
	191	* 0 otherwise. */
	192	if (value >= 2) {
	193	DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
	194	return -EINVAL;
	195	}
9eba4a93 MO	196	radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value);
	197	break;
	198	case RADEON_INFO_WANT_CMASK:
	199	/* The same logic as Hyper-Z. */
	200	if (value >= 2) {
	201	DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value);
	202	return -EINVAL;
ab9e1f59	203	}
9eba4a93	204	radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value);
e7aeeba6	205	break;
58bbf018 AD	206	case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
	207	/* return clock value in KHz */
	208	value = rdev->clock.spll.reference_freq * 10;
	209	break;
486af189	210	case RADEON_INFO_NUM_BACKENDS:
fecf1d07 AD	211	if (rdev->family >= CHIP_CAYMAN)
	212	value = rdev->config.cayman.max_backends_per_se *
	213	rdev->config.cayman.max_shader_engines;
	214	else if (rdev->family >= CHIP_CEDAR)
486af189 DA	215	value = rdev->config.evergreen.max_backends;
	216	else if (rdev->family >= CHIP_RV770)
	217	value = rdev->config.rv770.max_backends;
	218	else if (rdev->family >= CHIP_R600)
	219	value = rdev->config.r600.max_backends;
	220	else {
	221	return -EINVAL;
	222	}
	223	break;
6565945b AD	224	case RADEON_INFO_NUM_TILE_PIPES:
	225	if (rdev->family >= CHIP_CAYMAN)
	226	value = rdev->config.cayman.max_tile_pipes;
	227	else if (rdev->family >= CHIP_CEDAR)
	228	value = rdev->config.evergreen.max_tile_pipes;
	229	else if (rdev->family >= CHIP_RV770)
	230	value = rdev->config.rv770.max_tile_pipes;
	231	else if (rdev->family >= CHIP_R600)
	232	value = rdev->config.r600.max_tile_pipes;
	233	else {
	234	return -EINVAL;
	235	}
	236	break;
8aeb96f8 AD	237	case RADEON_INFO_FUSION_GART_WORKING:
	238	value = 1;
	239	break;
771fe6b9	240	default:
d9fdaafb	241	DRM_DEBUG_KMS("Invalid request %d\n", info->request);
771fe6b9 JG	242	return -EINVAL;
	243	}
	244	if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
	245	DRM_ERROR("copy_to_user\n");
	246	return -EFAULT;
	247	}
	248	return 0;
	249	}
	250
	251
	252	/*
	253	* Outdated mess for old drm with Xorg being in charge (void function now).
	254	*/
	255	int radeon_driver_firstopen_kms(struct drm_device *dev)
	256	{
	257	return 0;
	258	}
	259
	260
	261	void radeon_driver_lastclose_kms(struct drm_device *dev)
	262	{
6a9ee8af	263	vga_switcheroo_process_delayed_switch();
771fe6b9 JG	264	}
	265
	266	int radeon_driver_open_kms(struct drm_device dev, struct drm_file file_priv)
	267	{
	268	return 0;
	269	}
	270
	271	void radeon_driver_postclose_kms(struct drm_device *dev,
	272	struct drm_file *file_priv)
	273	{
	274	}
	275
	276	void radeon_driver_preclose_kms(struct drm_device *dev,
	277	struct drm_file *file_priv)
	278	{
ab9e1f59 DA	279	struct radeon_device *rdev = dev->dev_private;
	280	if (rdev->hyperz_filp == file_priv)
	281	rdev->hyperz_filp = NULL;
dca0d612 MO	282	if (rdev->cmask_filp == file_priv)
dca0d612 MO	283	rdev->cmask_filp = NULL;
771fe6b9 JG	284	}
771fe6b9 JG	285
771fe6b9 JG	286	/*
	287	* VBlank related functions.
	288	*/
	289	u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
	290	{
7ed220d7 MD	291	struct radeon_device *rdev = dev->dev_private;
7ed220d7 MD	292
9c950a43	293	if (crtc < 0 \|\| crtc >= rdev->num_crtc) {
7ed220d7 MD	294	DRM_ERROR("Invalid crtc %d\n", crtc);
	295	return -EINVAL;
	296	}
	297
	298	return radeon_get_vblank_counter(rdev, crtc);
771fe6b9 JG	299	}
	300
	301	int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
	302	{
7ed220d7 MD	303	struct radeon_device *rdev = dev->dev_private;
7ed220d7 MD	304
9c950a43	305	if (crtc < 0 \|\| crtc >= rdev->num_crtc) {
7ed220d7 MD	306	DRM_ERROR("Invalid crtc %d\n", crtc);
	307	return -EINVAL;
	308	}
	309
	310	rdev->irq.crtc_vblank_int[crtc] = true;
	311
	312	return radeon_irq_set(rdev);
771fe6b9 JG	313	}
	314
	315	void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
	316	{
7ed220d7 MD	317	struct radeon_device *rdev = dev->dev_private;
7ed220d7 MD	318
9c950a43	319	if (crtc < 0 \|\| crtc >= rdev->num_crtc) {
7ed220d7 MD	320	DRM_ERROR("Invalid crtc %d\n", crtc);
	321	return;
	322	}
	323
	324	rdev->irq.crtc_vblank_int[crtc] = false;
	325
	326	radeon_irq_set(rdev);
771fe6b9 JG	327	}
771fe6b9 JG	328
f5a80209 MK	329	int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
	330	int *max_error,
	331	struct timeval *vblank_time,
	332	unsigned flags)
	333	{
	334	struct drm_crtc *drmcrtc;
	335	struct radeon_device *rdev = dev->dev_private;
	336
	337	if (crtc < 0 \|\| crtc >= dev->num_crtcs) {
	338	DRM_ERROR("Invalid crtc %d\n", crtc);
	339	return -EINVAL;
	340	}
	341
	342	/* Get associated drm_crtc: */
	343	drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
	344
	345	/* Helper routine in DRM core does all the work: */
	346	return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
	347	vblank_time, flags,
	348	drmcrtc);
	349	}
771fe6b9	350
771fe6b9 JG	351	/*
	352	* IOCTL.
	353	*/
	354	int radeon_dma_ioctl_kms(struct drm_device dev, void data,
	355	struct drm_file *file_priv)
	356	{
	357	/* Not valid in KMS. */
	358	return -EINVAL;
	359	}
	360
	361	#define KMS_INVALID_IOCTL(name) \
	362	int name(struct drm_device dev, void data, struct drm_file *file_priv)\
	363	{ \
	364	DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
	365	return -EINVAL; \
	366	}
	367
	368	/*
	369	* All these ioctls are invalid in kms world.
	370	*/
	371	KMS_INVALID_IOCTL(radeon_cp_init_kms)
	372	KMS_INVALID_IOCTL(radeon_cp_start_kms)
	373	KMS_INVALID_IOCTL(radeon_cp_stop_kms)
	374	KMS_INVALID_IOCTL(radeon_cp_reset_kms)
	375	KMS_INVALID_IOCTL(radeon_cp_idle_kms)
	376	KMS_INVALID_IOCTL(radeon_cp_resume_kms)
	377	KMS_INVALID_IOCTL(radeon_engine_reset_kms)
	378	KMS_INVALID_IOCTL(radeon_fullscreen_kms)
	379	KMS_INVALID_IOCTL(radeon_cp_swap_kms)
	380	KMS_INVALID_IOCTL(radeon_cp_clear_kms)
	381	KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
	382	KMS_INVALID_IOCTL(radeon_cp_indices_kms)
	383	KMS_INVALID_IOCTL(radeon_cp_texture_kms)
	384	KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
	385	KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
	386	KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
	387	KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
	388	KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
	389	KMS_INVALID_IOCTL(radeon_cp_flip_kms)
	390	KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
	391	KMS_INVALID_IOCTL(radeon_mem_free_kms)
	392	KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
	393	KMS_INVALID_IOCTL(radeon_irq_emit_kms)
	394	KMS_INVALID_IOCTL(radeon_irq_wait_kms)
	395	KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
	396	KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
	397	KMS_INVALID_IOCTL(radeon_surface_free_kms)
	398
	399
	400	struct drm_ioctl_desc radeon_ioctls_kms[] = {
1b2f1489 DA	401	DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	402	DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	403	DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	404	DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	405	DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
	406	DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
	407	DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
	408	DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
	409	DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
	410	DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
	411	DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
	412	DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
	413	DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
	414	DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
	415	DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	416	DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
	417	DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
	418	DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
	419	DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
	420	DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
	421	DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
	422	DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	423	DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
	424	DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
	425	DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
	426	DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
	427	DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
771fe6b9	428	/* KMS */
1b2f1489 DA	429	DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	430	DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	431	DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	432	DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	433	DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	434	DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	435	DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	436	DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	437	DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	438	DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	439	DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	440	DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH\|DRM_UNLOCKED),
771fe6b9 JG	441	};
771fe6b9 JG	442	int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);