[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / radeon / radeon_kms.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include "drmP.h"
#include "drm_sarea.h"
#include "radeon.h"
#include "radeon_drm.h"

#include <linux/vga_switcheroo.h>
#include <linux/slab.h>

int radeon_driver_unload_kms(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;

	if (rdev == NULL)
		return 0;
	radeon_modeset_fini(rdev);
	radeon_device_fini(rdev);
	kfree(rdev);
	dev->dev_private = NULL;
	return 0;
}

int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
{
	struct radeon_device *rdev;
	int r, acpi_status;

	rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
	if (rdev == NULL) {
		return -ENOMEM;
	}
	dev->dev_private = (void *)rdev;

	pci_set_master(dev->pdev);

	/* update BUS flag */
	if (drm_pci_device_is_agp(dev)) {
		flags |= RADEON_IS_AGP;
	} else if (pci_is_pcie(dev->pdev)) {
		flags |= RADEON_IS_PCIE;
	} else {
		flags |= RADEON_IS_PCI;
	}

	/* radeon_device_init should report only fatal error
	 * like memory allocation failure or iomapping failure,
	 * or memory manager initialization failure, it must
	 * properly initialize the GPU MC controller and permit
	 * VRAM allocation
	 */
	r = radeon_device_init(rdev, dev, dev->pdev, flags);
	if (r) {
		dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
		goto out;
	}

	/* Call ACPI methods */
	acpi_status = radeon_acpi_init(rdev);
	if (acpi_status)
		dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");

	/* Again modeset_init should fail only on fatal error
	 * otherwise it should provide enough functionalities
	 * for shadowfb to run
	 */
	r = radeon_modeset_init(rdev);
	if (r)
		dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
out:
	if (r)
		radeon_driver_unload_kms(dev);
	return r;
}

static void radeon_set_filp_rights(struct drm_device *dev,
				   struct drm_file **owner,
				   struct drm_file *applier,
				   uint32_t *value)
{
	mutex_lock(&dev->struct_mutex);
	if (*value == 1) {
		/* wants rights */
		if (!*owner)
			*owner = applier;
	} else if (*value == 0) {
		/* revokes rights */
		if (*owner == applier)
			*owner = NULL;
	}
	*value = *owner == applier ? 1 : 0;
	mutex_unlock(&dev->struct_mutex);
}

/*
 * Userspace get information ioctl
 */
int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
	struct radeon_device *rdev = dev->dev_private;
	struct drm_radeon_info *info;
	struct radeon_mode_info *minfo = &rdev->mode_info;
	uint32_t *value_ptr;
	uint32_t value;
	struct drm_crtc *crtc;
	int i, found;

	info = data;
	value_ptr = (uint32_t *)((unsigned long)info->value);
	if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value)))
		return -EFAULT;

	switch (info->request) {
	case RADEON_INFO_DEVICE_ID:
		value = dev->pci_device;
		break;
	case RADEON_INFO_NUM_GB_PIPES:
		value = rdev->num_gb_pipes;
		break;
	case RADEON_INFO_NUM_Z_PIPES:
		value = rdev->num_z_pipes;
		break;
	case RADEON_INFO_ACCEL_WORKING:
		/* xf86-video-ati 6.13.0 relies on this being false for evergreen */
		if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
			value = false;
		else
			value = rdev->accel_working;
		break;
	case RADEON_INFO_CRTC_FROM_ID:
		for (i = 0, found = 0; i < rdev->num_crtc; i++) {
			crtc = (struct drm_crtc *)minfo->crtcs[i];
			if (crtc && crtc->base.id == value) {
				struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
				value = radeon_crtc->crtc_id;
				found = 1;
				break;
			}
		}
		if (!found) {
			DRM_DEBUG_KMS("unknown crtc id %d\n", value);
			return -EINVAL;
		}
		break;
	case RADEON_INFO_ACCEL_WORKING2:
		value = rdev->accel_working;
		break;
	case RADEON_INFO_TILING_CONFIG:
		if (rdev->family >= CHIP_CAYMAN)
			value = rdev->config.cayman.tile_config;
		else if (rdev->family >= CHIP_CEDAR)
			value = rdev->config.evergreen.tile_config;
		else if (rdev->family >= CHIP_RV770)
			value = rdev->config.rv770.tile_config;
		else if (rdev->family >= CHIP_R600)
			value = rdev->config.r600.tile_config;
		else {
			DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
			return -EINVAL;
		}
		break;
	case RADEON_INFO_WANT_HYPERZ:
		/* The "value" here is both an input and output parameter.
		 * If the input value is 1, filp requests hyper-z access.
		 * If the input value is 0, filp revokes its hyper-z access.
		 *
		 * When returning, the value is 1 if filp owns hyper-z access,
		 * 0 otherwise. */
		if (value >= 2) {
			DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
			return -EINVAL;
		}
		radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value);
		break;
	case RADEON_INFO_WANT_CMASK:
		/* The same logic as Hyper-Z. */
		if (value >= 2) {
			DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value);
			return -EINVAL;
		}
		radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value);
		break;
	case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
		/* return clock value in KHz */
		value = rdev->clock.spll.reference_freq * 10;
		break;
	case RADEON_INFO_NUM_BACKENDS:
		if (rdev->family >= CHIP_CAYMAN)
			value = rdev->config.cayman.max_backends_per_se *
				rdev->config.cayman.max_shader_engines;
		else if (rdev->family >= CHIP_CEDAR)
			value = rdev->config.evergreen.max_backends;
		else if (rdev->family >= CHIP_RV770)
			value = rdev->config.rv770.max_backends;
		else if (rdev->family >= CHIP_R600)
			value = rdev->config.r600.max_backends;
		else {
			return -EINVAL;
		}
		break;
	case RADEON_INFO_NUM_TILE_PIPES:
		if (rdev->family >= CHIP_CAYMAN)
			value = rdev->config.cayman.max_tile_pipes;
		else if (rdev->family >= CHIP_CEDAR)
			value = rdev->config.evergreen.max_tile_pipes;
		else if (rdev->family >= CHIP_RV770)
			value = rdev->config.rv770.max_tile_pipes;
		else if (rdev->family >= CHIP_R600)
			value = rdev->config.r600.max_tile_pipes;
		else {
			return -EINVAL;
		}
		break;
	case RADEON_INFO_FUSION_GART_WORKING:
		value = 1;
		break;
	case RADEON_INFO_BACKEND_MAP:
		if (rdev->family >= CHIP_CAYMAN)
			value = rdev->config.cayman.backend_map;
		else if (rdev->family >= CHIP_CEDAR)
			value = rdev->config.evergreen.backend_map;
		else if (rdev->family >= CHIP_RV770)
			value = rdev->config.rv770.backend_map;
		else if (rdev->family >= CHIP_R600)
			value = rdev->config.r600.backend_map;
		else {
			return -EINVAL;
		}
		break;
	case RADEON_INFO_VA_START:
		/* this is where we report if vm is supported or not */
		if (rdev->family < CHIP_CAYMAN)
			return -EINVAL;
		value = RADEON_VA_RESERVED_SIZE;
		break;
	case RADEON_INFO_IB_VM_MAX_SIZE:
		/* this is where we report if vm is supported or not */
		if (rdev->family < CHIP_CAYMAN)
			return -EINVAL;
		value = RADEON_IB_VM_MAX_SIZE;
		break;
	default:
		DRM_DEBUG_KMS("Invalid request %d\n", info->request);
		return -EINVAL;
	}
	if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
		DRM_ERROR("copy_to_user\n");
		return -EFAULT;
	}
	return 0;
}


/*
 * Outdated mess for old drm with Xorg being in charge (void function now).
 */
int radeon_driver_firstopen_kms(struct drm_device *dev)
{
	return 0;
}

void radeon_driver_lastclose_kms(struct drm_device *dev)
{
	vga_switcheroo_process_delayed_switch();
}

int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
{
	struct radeon_device *rdev = dev->dev_private;

	file_priv->driver_priv = NULL;

	/* new gpu have virtual address space support */
	if (rdev->family >= CHIP_CAYMAN) {
		struct radeon_fpriv *fpriv;
		int r;

		fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
		if (unlikely(!fpriv)) {
			return -ENOMEM;
		}

		r = radeon_vm_init(rdev, &fpriv->vm);
		if (r) {
			radeon_vm_fini(rdev, &fpriv->vm);
			kfree(fpriv);
			return r;
		}

		file_priv->driver_priv = fpriv;
	}
	return 0;
}

void radeon_driver_postclose_kms(struct drm_device *dev,
				 struct drm_file *file_priv)
{
	struct radeon_device *rdev = dev->dev_private;

	/* new gpu have virtual address space support */
	if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
		struct radeon_fpriv *fpriv = file_priv->driver_priv;

		radeon_vm_fini(rdev, &fpriv->vm);
		kfree(fpriv);
		file_priv->driver_priv = NULL;
	}
}

void radeon_driver_preclose_kms(struct drm_device *dev,
				struct drm_file *file_priv)
{
	struct radeon_device *rdev = dev->dev_private;
	if (rdev->hyperz_filp == file_priv)
		rdev->hyperz_filp = NULL;
	if (rdev->cmask_filp == file_priv)
		rdev->cmask_filp = NULL;
}

/*
 * VBlank related functions.
 */
u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
{
	struct radeon_device *rdev = dev->dev_private;

	if (crtc < 0 || crtc >= rdev->num_crtc) {
		DRM_ERROR("Invalid crtc %d\n", crtc);
		return -EINVAL;
	}

	return radeon_get_vblank_counter(rdev, crtc);
}

int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
{
	struct radeon_device *rdev = dev->dev_private;

	if (crtc < 0 || crtc >= rdev->num_crtc) {
		DRM_ERROR("Invalid crtc %d\n", crtc);
		return -EINVAL;
	}

	rdev->irq.crtc_vblank_int[crtc] = true;

	return radeon_irq_set(rdev);
}

void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
{
	struct radeon_device *rdev = dev->dev_private;

	if (crtc < 0 || crtc >= rdev->num_crtc) {
		DRM_ERROR("Invalid crtc %d\n", crtc);
		return;
	}

	rdev->irq.crtc_vblank_int[crtc] = false;

	radeon_irq_set(rdev);
}

int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
				    int *max_error,
				    struct timeval *vblank_time,
				    unsigned flags)
{
	struct drm_crtc *drmcrtc;
	struct radeon_device *rdev = dev->dev_private;

	if (crtc < 0 || crtc >= dev->num_crtcs) {
		DRM_ERROR("Invalid crtc %d\n", crtc);
		return -EINVAL;
	}

	/* Get associated drm_crtc: */
	drmcrtc = &rdev->mode_info.crtcs[crtc]->base;

	/* Helper routine in DRM core does all the work: */
	return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
						     vblank_time, flags,
						     drmcrtc);
}

/*
 * IOCTL.
 */
int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	/* Not valid in KMS. */
	return -EINVAL;
}

#define KMS_INVALID_IOCTL(name)						\
int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
{									\
	DRM_ERROR("invalid ioctl with kms %s\n", __func__);		\
	return -EINVAL;							\
}

/*
 * All these ioctls are invalid in kms world.
 */
KMS_INVALID_IOCTL(radeon_cp_init_kms)
KMS_INVALID_IOCTL(radeon_cp_start_kms)
KMS_INVALID_IOCTL(radeon_cp_stop_kms)
KMS_INVALID_IOCTL(radeon_cp_reset_kms)
KMS_INVALID_IOCTL(radeon_cp_idle_kms)
KMS_INVALID_IOCTL(radeon_cp_resume_kms)
KMS_INVALID_IOCTL(radeon_engine_reset_kms)
KMS_INVALID_IOCTL(radeon_fullscreen_kms)
KMS_INVALID_IOCTL(radeon_cp_swap_kms)
KMS_INVALID_IOCTL(radeon_cp_clear_kms)
KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
KMS_INVALID_IOCTL(radeon_cp_indices_kms)
KMS_INVALID_IOCTL(radeon_cp_texture_kms)
KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
KMS_INVALID_IOCTL(radeon_cp_flip_kms)
KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
KMS_INVALID_IOCTL(radeon_mem_free_kms)
KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
KMS_INVALID_IOCTL(radeon_irq_emit_kms)
KMS_INVALID_IOCTL(radeon_irq_wait_kms)
KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
KMS_INVALID_IOCTL(radeon_surface_free_kms)


struct drm_ioctl_desc radeon_ioctls_kms[] = {
	DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
	/* KMS */
	DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED),
};
int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#include "drmP.h"
	29	#include "drm_sarea.h"
	30	#include "radeon.h"
	31	#include "radeon_drm.h"
	32
6a9ee8af	33	#include <linux/vga_switcheroo.h>
5a0e3ad6	34	#include <linux/slab.h>
6a9ee8af	35
cf0fe456 JG	36	int radeon_driver_unload_kms(struct drm_device *dev)
	37	{
	38	struct radeon_device *rdev = dev->dev_private;
	39
	40	if (rdev == NULL)
	41	return 0;
	42	radeon_modeset_fini(rdev);
	43	radeon_device_fini(rdev);
	44	kfree(rdev);
	45	dev->dev_private = NULL;
	46	return 0;
	47	}
771fe6b9	48
771fe6b9 JG	49	int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
	50	{
	51	struct radeon_device *rdev;
d7a2952f	52	int r, acpi_status;
771fe6b9 JG	53
	54	rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
	55	if (rdev == NULL) {
	56	return -ENOMEM;
	57	}
	58	dev->dev_private = (void *)rdev;
	59
466e69b8 DA	60	pci_set_master(dev->pdev);
466e69b8 DA	61
771fe6b9	62	/* update BUS flag */
8410ea3b	63	if (drm_pci_device_is_agp(dev)) {
771fe6b9	64	flags \|= RADEON_IS_AGP;
58b6542b	65	} else if (pci_is_pcie(dev->pdev)) {
771fe6b9 JG	66	flags \|= RADEON_IS_PCIE;
	67	} else {
	68	flags \|= RADEON_IS_PCI;
	69	}
	70
6cf8a3f5 JG	71	/* radeon_device_init should report only fatal error
	72	* like memory allocation failure or iomapping failure,
	73	* or memory manager initialization failure, it must
	74	* properly initialize the GPU MC controller and permit
	75	* VRAM allocation
	76	*/
771fe6b9 JG	77	r = radeon_device_init(rdev, dev, dev->pdev, flags);
771fe6b9 JG	78	if (r) {
cf0fe456 JG	79	dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
cf0fe456 JG	80	goto out;
6cf8a3f5	81	}
d7a2952f AM	82
	83	/* Call ACPI methods */
	84	acpi_status = radeon_acpi_init(rdev);
	85	if (acpi_status)
dc77de12	86	dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
d7a2952f	87
6cf8a3f5 JG	88	/* Again modeset_init should fail only on fatal error
	89	* otherwise it should provide enough functionalities
	90	* for shadowfb to run
	91	*/
	92	r = radeon_modeset_init(rdev);
cf0fe456 JG	93	if (r)
	94	dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
	95	out:
	96	if (r)
	97	radeon_driver_unload_kms(dev);
	98	return r;
771fe6b9 JG	99	}
771fe6b9 JG	100
9eba4a93 MO	101	static void radeon_set_filp_rights(struct drm_device *dev,
	102	struct drm_file **owner,
	103	struct drm_file *applier,
	104	uint32_t *value)
	105	{
	106	mutex_lock(&dev->struct_mutex);
	107	if (*value == 1) {
	108	/* wants rights */
	109	if (!*owner)
	110	*owner = applier;
	111	} else if (*value == 0) {
	112	/* revokes rights */
	113	if (*owner == applier)
	114	*owner = NULL;
	115	}
	116	value = owner == applier ? 1 : 0;
	117	mutex_unlock(&dev->struct_mutex);
	118	}
771fe6b9 JG	119
771fe6b9 JG	120	/*
9eba4a93	121	* Userspace get information ioctl
771fe6b9 JG	122	*/
	123	int radeon_info_ioctl(struct drm_device dev, void data, struct drm_file *filp)
	124	{
	125	struct radeon_device *rdev = dev->dev_private;
	126	struct drm_radeon_info *info;
bc35afdb	127	struct radeon_mode_info *minfo = &rdev->mode_info;
771fe6b9 JG	128	uint32_t *value_ptr;
771fe6b9 JG	129	uint32_t value;
bc35afdb JG	130	struct drm_crtc *crtc;
bc35afdb JG	131	int i, found;
771fe6b9 JG	132
	133	info = data;
	134	value_ptr = (uint32_t *)((unsigned long)info->value);
d8ab3557 DDAG	135	if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value)))
	136	return -EFAULT;
	137
771fe6b9 JG	138	switch (info->request) {
	139	case RADEON_INFO_DEVICE_ID:
	140	value = dev->pci_device;
	141	break;
	142	case RADEON_INFO_NUM_GB_PIPES:
	143	value = rdev->num_gb_pipes;
	144	break;
f779b3e5 AD	145	case RADEON_INFO_NUM_Z_PIPES:
	146	value = rdev->num_z_pipes;
	147	break;
733289c2	148	case RADEON_INFO_ACCEL_WORKING:
148a03bc AD	149	/* xf86-video-ati 6.13.0 relies on this being false for evergreen */
	150	if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
	151	value = false;
	152	else
	153	value = rdev->accel_working;
733289c2	154	break;
bc35afdb JG	155	case RADEON_INFO_CRTC_FROM_ID:
	156	for (i = 0, found = 0; i < rdev->num_crtc; i++) {
	157	crtc = (struct drm_crtc *)minfo->crtcs[i];
	158	if (crtc && crtc->base.id == value) {
0baf2d8f AD	159	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
0baf2d8f AD	160	value = radeon_crtc->crtc_id;
bc35afdb JG	161	found = 1;
	162	break;
	163	}
	164	}
	165	if (!found) {
d9fdaafb	166	DRM_DEBUG_KMS("unknown crtc id %d\n", value);
bc35afdb JG	167	return -EINVAL;
	168	}
	169	break;
148a03bc AD	170	case RADEON_INFO_ACCEL_WORKING2:
	171	value = rdev->accel_working;
	172	break;
e7aeeba6	173	case RADEON_INFO_TILING_CONFIG:
fecf1d07 AD	174	if (rdev->family >= CHIP_CAYMAN)
	175	value = rdev->config.cayman.tile_config;
	176	else if (rdev->family >= CHIP_CEDAR)
e7aeeba6 AD	177	value = rdev->config.evergreen.tile_config;
	178	else if (rdev->family >= CHIP_RV770)
	179	value = rdev->config.rv770.tile_config;
	180	else if (rdev->family >= CHIP_R600)
	181	value = rdev->config.r600.tile_config;
	182	else {
d9fdaafb	183	DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
e7aeeba6 AD	184	return -EINVAL;
e7aeeba6 AD	185	}
b824b364	186	break;
ab9e1f59	187	case RADEON_INFO_WANT_HYPERZ:
43861f71 MO	188	/* The "value" here is both an input and output parameter.
	189	* If the input value is 1, filp requests hyper-z access.
	190	* If the input value is 0, filp revokes its hyper-z access.
	191	*
	192	* When returning, the value is 1 if filp owns hyper-z access,
	193	* 0 otherwise. */
	194	if (value >= 2) {
	195	DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
	196	return -EINVAL;
	197	}
9eba4a93 MO	198	radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value);
	199	break;
	200	case RADEON_INFO_WANT_CMASK:
	201	/* The same logic as Hyper-Z. */
	202	if (value >= 2) {
	203	DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value);
	204	return -EINVAL;
ab9e1f59	205	}
9eba4a93	206	radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value);
e7aeeba6	207	break;
58bbf018 AD	208	case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
	209	/* return clock value in KHz */
	210	value = rdev->clock.spll.reference_freq * 10;
	211	break;
486af189	212	case RADEON_INFO_NUM_BACKENDS:
fecf1d07 AD	213	if (rdev->family >= CHIP_CAYMAN)
	214	value = rdev->config.cayman.max_backends_per_se *
	215	rdev->config.cayman.max_shader_engines;
	216	else if (rdev->family >= CHIP_CEDAR)
486af189 DA	217	value = rdev->config.evergreen.max_backends;
	218	else if (rdev->family >= CHIP_RV770)
	219	value = rdev->config.rv770.max_backends;
	220	else if (rdev->family >= CHIP_R600)
	221	value = rdev->config.r600.max_backends;
	222	else {
	223	return -EINVAL;
	224	}
	225	break;
6565945b AD	226	case RADEON_INFO_NUM_TILE_PIPES:
	227	if (rdev->family >= CHIP_CAYMAN)
	228	value = rdev->config.cayman.max_tile_pipes;
	229	else if (rdev->family >= CHIP_CEDAR)
	230	value = rdev->config.evergreen.max_tile_pipes;
	231	else if (rdev->family >= CHIP_RV770)
	232	value = rdev->config.rv770.max_tile_pipes;
	233	else if (rdev->family >= CHIP_R600)
	234	value = rdev->config.r600.max_tile_pipes;
	235	else {
	236	return -EINVAL;
	237	}
	238	break;
8aeb96f8 AD	239	case RADEON_INFO_FUSION_GART_WORKING:
	240	value = 1;
	241	break;
e55b9422 AD	242	case RADEON_INFO_BACKEND_MAP:
	243	if (rdev->family >= CHIP_CAYMAN)
	244	value = rdev->config.cayman.backend_map;
	245	else if (rdev->family >= CHIP_CEDAR)
	246	value = rdev->config.evergreen.backend_map;
	247	else if (rdev->family >= CHIP_RV770)
	248	value = rdev->config.rv770.backend_map;
	249	else if (rdev->family >= CHIP_R600)
	250	value = rdev->config.r600.backend_map;
	251	else {
	252	return -EINVAL;
	253	}
	254	break;
721604a1 JG	255	case RADEON_INFO_VA_START:
	256	/* this is where we report if vm is supported or not */
	257	if (rdev->family < CHIP_CAYMAN)
	258	return -EINVAL;
	259	value = RADEON_VA_RESERVED_SIZE;
	260	break;
	261	case RADEON_INFO_IB_VM_MAX_SIZE:
	262	/* this is where we report if vm is supported or not */
	263	if (rdev->family < CHIP_CAYMAN)
	264	return -EINVAL;
	265	value = RADEON_IB_VM_MAX_SIZE;
	266	break;
771fe6b9	267	default:
d9fdaafb	268	DRM_DEBUG_KMS("Invalid request %d\n", info->request);
771fe6b9 JG	269	return -EINVAL;
	270	}
	271	if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
	272	DRM_ERROR("copy_to_user\n");
	273	return -EFAULT;
	274	}
	275	return 0;
	276	}
	277
	278
	279	/*
	280	* Outdated mess for old drm with Xorg being in charge (void function now).
	281	*/
	282	int radeon_driver_firstopen_kms(struct drm_device *dev)
	283	{
	284	return 0;
	285	}
	286
771fe6b9 JG	287	void radeon_driver_lastclose_kms(struct drm_device *dev)
771fe6b9 JG	288	{
6a9ee8af	289	vga_switcheroo_process_delayed_switch();
771fe6b9 JG	290	}
	291
	292	int radeon_driver_open_kms(struct drm_device dev, struct drm_file file_priv)
	293	{
721604a1 JG	294	struct radeon_device *rdev = dev->dev_private;
	295
	296	file_priv->driver_priv = NULL;
	297
	298	/* new gpu have virtual address space support */
	299	if (rdev->family >= CHIP_CAYMAN) {
	300	struct radeon_fpriv *fpriv;
	301	int r;
	302
	303	fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
	304	if (unlikely(!fpriv)) {
	305	return -ENOMEM;
	306	}
	307
	308	r = radeon_vm_init(rdev, &fpriv->vm);
	309	if (r) {
	310	radeon_vm_fini(rdev, &fpriv->vm);
	311	kfree(fpriv);
	312	return r;
	313	}
	314
	315	file_priv->driver_priv = fpriv;
	316	}
771fe6b9 JG	317	return 0;
	318	}
	319
	320	void radeon_driver_postclose_kms(struct drm_device *dev,
	321	struct drm_file *file_priv)
	322	{
721604a1 JG	323	struct radeon_device *rdev = dev->dev_private;
	324
	325	/* new gpu have virtual address space support */
	326	if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
	327	struct radeon_fpriv *fpriv = file_priv->driver_priv;
	328
	329	radeon_vm_fini(rdev, &fpriv->vm);
	330	kfree(fpriv);
	331	file_priv->driver_priv = NULL;
	332	}
771fe6b9 JG	333	}
	334
	335	void radeon_driver_preclose_kms(struct drm_device *dev,
	336	struct drm_file *file_priv)
	337	{
ab9e1f59 DA	338	struct radeon_device *rdev = dev->dev_private;
	339	if (rdev->hyperz_filp == file_priv)
	340	rdev->hyperz_filp = NULL;
dca0d612 MO	341	if (rdev->cmask_filp == file_priv)
dca0d612 MO	342	rdev->cmask_filp = NULL;
771fe6b9 JG	343	}
771fe6b9 JG	344
771fe6b9 JG	345	/*
	346	* VBlank related functions.
	347	*/
	348	u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
	349	{
7ed220d7 MD	350	struct radeon_device *rdev = dev->dev_private;
7ed220d7 MD	351
9c950a43	352	if (crtc < 0 \|\| crtc >= rdev->num_crtc) {
7ed220d7 MD	353	DRM_ERROR("Invalid crtc %d\n", crtc);
	354	return -EINVAL;
	355	}
	356
	357	return radeon_get_vblank_counter(rdev, crtc);
771fe6b9 JG	358	}
	359
	360	int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
	361	{
7ed220d7 MD	362	struct radeon_device *rdev = dev->dev_private;
7ed220d7 MD	363
9c950a43	364	if (crtc < 0 \|\| crtc >= rdev->num_crtc) {
7ed220d7 MD	365	DRM_ERROR("Invalid crtc %d\n", crtc);
	366	return -EINVAL;
	367	}
	368
	369	rdev->irq.crtc_vblank_int[crtc] = true;
	370
	371	return radeon_irq_set(rdev);
771fe6b9 JG	372	}
	373
	374	void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
	375	{
7ed220d7 MD	376	struct radeon_device *rdev = dev->dev_private;
7ed220d7 MD	377
9c950a43	378	if (crtc < 0 \|\| crtc >= rdev->num_crtc) {
7ed220d7 MD	379	DRM_ERROR("Invalid crtc %d\n", crtc);
	380	return;
	381	}
	382
	383	rdev->irq.crtc_vblank_int[crtc] = false;
	384
	385	radeon_irq_set(rdev);
771fe6b9 JG	386	}
771fe6b9 JG	387
f5a80209 MK	388	int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
	389	int *max_error,
	390	struct timeval *vblank_time,
	391	unsigned flags)
	392	{
	393	struct drm_crtc *drmcrtc;
	394	struct radeon_device *rdev = dev->dev_private;
	395
	396	if (crtc < 0 \|\| crtc >= dev->num_crtcs) {
	397	DRM_ERROR("Invalid crtc %d\n", crtc);
	398	return -EINVAL;
	399	}
	400
	401	/* Get associated drm_crtc: */
	402	drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
	403
	404	/* Helper routine in DRM core does all the work: */
	405	return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
	406	vblank_time, flags,
	407	drmcrtc);
	408	}
771fe6b9	409
771fe6b9 JG	410	/*
	411	* IOCTL.
	412	*/
	413	int radeon_dma_ioctl_kms(struct drm_device dev, void data,
	414	struct drm_file *file_priv)
	415	{
	416	/* Not valid in KMS. */
	417	return -EINVAL;
	418	}
	419
	420	#define KMS_INVALID_IOCTL(name) \
	421	int name(struct drm_device dev, void data, struct drm_file *file_priv)\
	422	{ \
	423	DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
	424	return -EINVAL; \
	425	}
	426
	427	/*
	428	* All these ioctls are invalid in kms world.
	429	*/
	430	KMS_INVALID_IOCTL(radeon_cp_init_kms)
	431	KMS_INVALID_IOCTL(radeon_cp_start_kms)
	432	KMS_INVALID_IOCTL(radeon_cp_stop_kms)
	433	KMS_INVALID_IOCTL(radeon_cp_reset_kms)
	434	KMS_INVALID_IOCTL(radeon_cp_idle_kms)
	435	KMS_INVALID_IOCTL(radeon_cp_resume_kms)
	436	KMS_INVALID_IOCTL(radeon_engine_reset_kms)
	437	KMS_INVALID_IOCTL(radeon_fullscreen_kms)
	438	KMS_INVALID_IOCTL(radeon_cp_swap_kms)
	439	KMS_INVALID_IOCTL(radeon_cp_clear_kms)
	440	KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
	441	KMS_INVALID_IOCTL(radeon_cp_indices_kms)
	442	KMS_INVALID_IOCTL(radeon_cp_texture_kms)
	443	KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
	444	KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
	445	KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
	446	KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
	447	KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
	448	KMS_INVALID_IOCTL(radeon_cp_flip_kms)
	449	KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
	450	KMS_INVALID_IOCTL(radeon_mem_free_kms)
	451	KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
	452	KMS_INVALID_IOCTL(radeon_irq_emit_kms)
	453	KMS_INVALID_IOCTL(radeon_irq_wait_kms)
	454	KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
	455	KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
	456	KMS_INVALID_IOCTL(radeon_surface_free_kms)
	457
	458
	459	struct drm_ioctl_desc radeon_ioctls_kms[] = {
1b2f1489 DA	460	DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	461	DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	462	DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	463	DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	464	DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
	465	DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
	466	DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
	467	DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
	468	DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
	469	DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
	470	DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
	471	DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
	472	DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
	473	DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
	474	DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	475	DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
	476	DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
	477	DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
	478	DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
	479	DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
	480	DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
	481	DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	482	DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
	483	DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
	484	DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
	485	DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
	486	DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
771fe6b9	487	/* KMS */
1b2f1489 DA	488	DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	489	DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	490	DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	491	DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	492	DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	493	DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	494	DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	495	DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	496	DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	497	DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	498	DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	499	DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH\|DRM_UNLOCKED),
721604a1	500	DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH\|DRM_UNLOCKED),
771fe6b9 JG	501	};
771fe6b9 JG	502	int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);