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drm/radeon: update radeon_atom_get_clock_dividers() for SI
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / radeon / radeon_mode.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
760285e7
DH		 33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
35#include <drm/drm_dp_helper.h>
36#include <drm/drm_fixed.h>
37#include <drm/drm_crtc_helper.h>
771fe6b9 38#include <linux/i2c.h>
771fe6b9 39#include <linux/i2c-algo-bit.h>
c93bb85b 40
38651674 41struct radeon_bo;
c93bb85b 42struct radeon_device;
771fe6b9
JG		 43
44#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
45#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
46#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
47#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
48
771fe6b9
JG		 49enum radeon_rmx_type {
50 RMX_OFF,
51 RMX_FULL,
52 RMX_CENTER,
53 RMX_ASPECT
54};
55
56enum radeon_tv_std {
57 TV_STD_NTSC,
58 TV_STD_PAL,
59 TV_STD_PAL_M,
60 TV_STD_PAL_60,
61 TV_STD_NTSC_J,
62 TV_STD_SCART_PAL,
63 TV_STD_SECAM,
64 TV_STD_PAL_CN,
d79766fa 65 TV_STD_PAL_N,
771fe6b9
JG		 66};
67
5b1714d3
AD		 68enum radeon_underscan_type {
69 UNDERSCAN_OFF,
70 UNDERSCAN_ON,
71 UNDERSCAN_AUTO,
72};
73
8e36ed00
AD		 74enum radeon_hpd_id {
75 RADEON_HPD_1 = 0,
76 RADEON_HPD_2,
77 RADEON_HPD_3,
78 RADEON_HPD_4,
79 RADEON_HPD_5,
80 RADEON_HPD_6,
81 RADEON_HPD_NONE = 0xff,
82};
83
f376b94f
AD		 84#define RADEON_MAX_I2C_BUS 16
85
9b9fe724
AD		 86/* radeon gpio-based i2c
87 * 1. "mask" reg and bits
88 * grabs the gpio pins for software use
89 * 0=not held 1=held
90 * 2. "a" reg and bits
91 * output pin value
92 * 0=low 1=high
93 * 3. "en" reg and bits
94 * sets the pin direction
95 * 0=input 1=output
96 * 4. "y" reg and bits
97 * input pin value
98 * 0=low 1=high
99 */
771fe6b9
JG		 100struct radeon_i2c_bus_rec {
101 bool valid;
6a93cb25
AD		 102 /* id used by atom */
103 uint8_t i2c_id;
bcc1c2a1 104 /* id used by atom */
8e36ed00 105 enum radeon_hpd_id hpd;
6a93cb25
AD		 106 /* can be used with hw i2c engine */
107 bool hw_capable;
108 /* uses multi-media i2c engine */
109 bool mm_i2c;
110 /* regs and bits */
771fe6b9
JG		 111 uint32_t mask_clk_reg;
112 uint32_t mask_data_reg;
113 uint32_t a_clk_reg;
114 uint32_t a_data_reg;
9b9fe724
AD		 115 uint32_t en_clk_reg;
116 uint32_t en_data_reg;
117 uint32_t y_clk_reg;
118 uint32_t y_data_reg;
771fe6b9
JG		 119 uint32_t mask_clk_mask;
120 uint32_t mask_data_mask;
771fe6b9
JG		 121 uint32_t a_clk_mask;
122 uint32_t a_data_mask;
9b9fe724
AD		 123 uint32_t en_clk_mask;
124 uint32_t en_data_mask;
125 uint32_t y_clk_mask;
126 uint32_t y_data_mask;
771fe6b9
JG		 127};
128
129struct radeon_tmds_pll {
130 uint32_t freq;
131 uint32_t value;
132};
133
134#define RADEON_MAX_BIOS_CONNECTOR 16
135
7c27f87d 136/* pll flags */
771fe6b9
JG		 137#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
138#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
139#define RADEON_PLL_USE_REF_DIV (1 << 2)
140#define RADEON_PLL_LEGACY (1 << 3)
141#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
142#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
143#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
144#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
145#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
146#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
147#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
d0e275a9 148#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
fc10332b 149#define RADEON_PLL_USE_POST_DIV (1 << 12)
86cb2bbf 150#define RADEON_PLL_IS_LCD (1 << 13)
f523f74e 151#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
771fe6b9
JG		 152
153struct radeon_pll {
fc10332b
AD		 154 /* reference frequency */
155 uint32_t reference_freq;
156
157 /* fixed dividers */
158 uint32_t reference_div;
159 uint32_t post_div;
160
161 /* pll in/out limits */
771fe6b9
JG		 162 uint32_t pll_in_min;
163 uint32_t pll_in_max;
164 uint32_t pll_out_min;
165 uint32_t pll_out_max;
86cb2bbf
AD		 166 uint32_t lcd_pll_out_min;
167 uint32_t lcd_pll_out_max;
fc10332b 168 uint32_t best_vco;
771fe6b9 169
fc10332b 170 /* divider limits */
771fe6b9
JG		 171 uint32_t min_ref_div;
172 uint32_t max_ref_div;
173 uint32_t min_post_div;
174 uint32_t max_post_div;
175 uint32_t min_feedback_div;
176 uint32_t max_feedback_div;
177 uint32_t min_frac_feedback_div;
178 uint32_t max_frac_feedback_div;
fc10332b
AD		 179
180 /* flags for the current clock */
181 uint32_t flags;
182
183 /* pll id */
184 uint32_t id;
771fe6b9
JG		 185};
186
187struct radeon_i2c_chan {
771fe6b9 188 struct i2c_adapter adapter;
746c1aa4
DA		 189 struct drm_device *dev;
190 union {
ac1aade6 191 struct i2c_algo_bit_data bit;
746c1aa4 192 struct i2c_algo_dp_aux_data dp;
746c1aa4 193 } algo;
771fe6b9
JG		 194 struct radeon_i2c_bus_rec rec;
195};
196
197/* mostly for macs, but really any system without connector tables */
198enum radeon_connector_table {
aa74fbb4 199 CT_NONE = 0,
771fe6b9
JG		 200 CT_GENERIC,
201 CT_IBOOK,
202 CT_POWERBOOK_EXTERNAL,
203 CT_POWERBOOK_INTERNAL,
204 CT_POWERBOOK_VGA,
205 CT_MINI_EXTERNAL,
206 CT_MINI_INTERNAL,
207 CT_IMAC_G5_ISIGHT,
208 CT_EMAC,
76a7142a 209 CT_RN50_POWER,
aa74fbb4 210 CT_MAC_X800,
9fad321a 211 CT_MAC_G5_9600,
cafa59b9
AD		 212 CT_SAM440EP,
213 CT_MAC_G4_SILVER
771fe6b9
JG		 214};
215
fcec570b
AD		 216enum radeon_dvo_chip {
217 DVO_SIL164,
218 DVO_SIL1178,
219};
220
8be48d92 221struct radeon_fbdev;
38651674 222
0783986a
AD		 223struct radeon_afmt {
224 bool enabled;
225 int offset;
226 bool last_buffer_filled_status;
227 int id;
228};
229
771fe6b9
JG		 230struct radeon_mode_info {
231 struct atom_context *atom_context;
61c4b24b 232 struct card_info *atom_card_info;
771fe6b9
JG		 233 enum radeon_connector_table connector_table;
234 bool mode_config_initialized;
bcc1c2a1 235 struct radeon_crtc *crtcs[6];
0783986a 236 struct radeon_afmt *afmt[6];
445282db
DA		 237 /* DVI-I properties */
238 struct drm_property *coherent_mode_property;
239 /* DAC enable load detect */
240 struct drm_property *load_detect_property;
5b1714d3 241 /* TV standard */
445282db
DA		 242 struct drm_property *tv_std_property;
243 /* legacy TMDS PLL detect */
244 struct drm_property *tmds_pll_property;
5b1714d3
AD		 245 /* underscan */
246 struct drm_property *underscan_property;
5bccf5e3
MG		 247 struct drm_property *underscan_hborder_property;
248 struct drm_property *underscan_vborder_property;
3c537889
AD		 249 /* hardcoded DFP edid from BIOS */
250 struct edid *bios_hardcoded_edid;
fafcf94e 251 int bios_hardcoded_edid_size;
38651674
DA		 252
253 /* pointer to fbdev info structure */
8be48d92 254 struct radeon_fbdev *rfbdev;
af7912e5
AD		 255 /* firmware flags */
256 u16 firmware_flags;
bced76f2
AD		 257 /* pointer to backlight encoder */
258 struct radeon_encoder *bl_encoder;
c93bb85b
JG		 259};
260
91030880
AD		 261#define RADEON_MAX_BL_LEVEL 0xFF
262
bced76f2
AD		 263#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
264
91030880
AD		 265struct radeon_backlight_privdata {
266 struct radeon_encoder *encoder;
267 uint8_t negative;
268};
269
270#endif
271
4ce001ab
DA		 272#define MAX_H_CODE_TIMING_LEN 32
273#define MAX_V_CODE_TIMING_LEN 32
274
275/* need to store these as reading
276 back code tables is excessive */
277struct radeon_tv_regs {
278 uint32_t tv_uv_adr;
279 uint32_t timing_cntl;
280 uint32_t hrestart;
281 uint32_t vrestart;
282 uint32_t frestart;
283 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
284 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
285};
286
19eca43e
AD		 287struct radeon_atom_ss {
288 uint16_t percentage;
289 uint8_t type;
290 uint16_t step;
291 uint8_t delay;
292 uint8_t range;
293 uint8_t refdiv;
294 /* asic_ss */
295 uint16_t rate;
296 uint16_t amount;
297};
298
771fe6b9
JG		 299struct radeon_crtc {
300 struct drm_crtc base;
301 int crtc_id;
302 u16 lut_r[256], lut_g[256], lut_b[256];
303 bool enabled;
304 bool can_tile;
305 uint32_t crtc_offset;
771fe6b9
JG		 306 struct drm_gem_object *cursor_bo;
307 uint64_t cursor_addr;
308 int cursor_width;
309 int cursor_height;
9e05fa1d
AD		 310 int max_cursor_width;
311 int max_cursor_height;
4162338a 312 uint32_t legacy_display_base_addr;
c836e862 313 uint32_t legacy_cursor_offset;
c93bb85b 314 enum radeon_rmx_type rmx_type;
5b1714d3
AD		 315 u8 h_border;
316 u8 v_border;
c93bb85b
JG		 317 fixed20_12 vsc;
318 fixed20_12 hsc;
de2103e4 319 struct drm_display_mode native_mode;
bcc1c2a1 320 int pll_id;
6f34be50
AD		 321 /* page flipping */
322 struct radeon_unpin_work *unpin_work;
323 int deferred_flip_completion;
19eca43e
AD		 324 /* pll sharing */
325 struct radeon_atom_ss ss;
326 bool ss_enabled;
327 u32 adjusted_clock;
328 int bpc;
329 u32 pll_reference_div;
330 u32 pll_post_div;
331 u32 pll_flags;
5df3196b 332 struct drm_encoder *encoder;
57b35e29 333 struct drm_connector *connector;
771fe6b9
JG		 334};
335
336struct radeon_encoder_primary_dac {
337 /* legacy primary dac */
338 uint32_t ps2_pdac_adj;
339};
340
341struct radeon_encoder_lvds {
342 /* legacy lvds */
343 uint16_t panel_vcc_delay;
344 uint8_t panel_pwr_delay;
345 uint8_t panel_digon_delay;
346 uint8_t panel_blon_delay;
347 uint16_t panel_ref_divider;
348 uint8_t panel_post_divider;
349 uint16_t panel_fb_divider;
350 bool use_bios_dividers;
351 uint32_t lvds_gen_cntl;
352 /* panel mode */
de2103e4 353 struct drm_display_mode native_mode;
63ec0119
MD		 354 struct backlight_device *bl_dev;
355 int dpms_mode;
356 uint8_t backlight_level;
771fe6b9
JG		 357};
358
359struct radeon_encoder_tv_dac {
360 /* legacy tv dac */
361 uint32_t ps2_tvdac_adj;
362 uint32_t ntsc_tvdac_adj;
363 uint32_t pal_tvdac_adj;
364
4ce001ab
DA		 365 int h_pos;
366 int v_pos;
367 int h_size;
368 int supported_tv_stds;
369 bool tv_on;
771fe6b9 370 enum radeon_tv_std tv_std;
4ce001ab 371 struct radeon_tv_regs tv;
771fe6b9
JG		 372};
373
374struct radeon_encoder_int_tmds {
375 /* legacy int tmds */
376 struct radeon_tmds_pll tmds_pll[4];
377};
378
fcec570b
AD		 379struct radeon_encoder_ext_tmds {
380 /* tmds over dvo */
381 struct radeon_i2c_chan *i2c_bus;
382 uint8_t slave_addr;
383 enum radeon_dvo_chip dvo_chip;
384};
385
ebbe1cb9 386/* spread spectrum */
771fe6b9 387struct radeon_encoder_atom_dig {
5137ee94 388 bool linkb;
771fe6b9
JG		 389 /* atom dig */
390 bool coherent_mode;
ba032a58
AD		 391 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
392 /* atom lvds/edp */
393 uint32_t lcd_misc;
771fe6b9 394 uint16_t panel_pwr_delay;
ba032a58 395 uint32_t lcd_ss_id;
771fe6b9 396 /* panel mode */
de2103e4 397 struct drm_display_mode native_mode;
63ec0119
MD		 398 struct backlight_device *bl_dev;
399 int dpms_mode;
400 uint8_t backlight_level;
386d4d75 401 int panel_mode;
0783986a 402 struct radeon_afmt *afmt;
771fe6b9
JG		 403};
404
4ce001ab
DA		 405struct radeon_encoder_atom_dac {
406 enum radeon_tv_std tv_std;
407};
408
771fe6b9
JG		 409struct radeon_encoder {
410 struct drm_encoder base;
5137ee94 411 uint32_t encoder_enum;
771fe6b9
JG		 412 uint32_t encoder_id;
413 uint32_t devices;
4ce001ab 414 uint32_t active_device;
771fe6b9
JG		 415 uint32_t flags;
416 uint32_t pixel_clock;
417 enum radeon_rmx_type rmx_type;
5b1714d3 418 enum radeon_underscan_type underscan_type;
5bccf5e3
MG		 419 uint32_t underscan_hborder;
420 uint32_t underscan_vborder;
de2103e4 421 struct drm_display_mode native_mode;
771fe6b9 422 void *enc_priv;
58bd0863 423 int audio_polling_active;
3e4b9982 424 bool is_ext_encoder;
36868bda 425 u16 caps;
771fe6b9
JG		 426};
427
428struct radeon_connector_atom_dig {
429 uint32_t igp_lane_info;
4143e919 430 /* displayport */
746c1aa4 431 struct radeon_i2c_chan *dp_i2c_bus;
1a644cd4 432 u8 dpcd[DP_RECEIVER_CAP_SIZE];
4143e919 433 u8 dp_sink_type;
5801ead6
AD		 434 int dp_clock;
435 int dp_lane_count;
8b834852 436 bool edp_on;
771fe6b9
JG		 437};
438
eed45b30
AD		 439struct radeon_gpio_rec {
440 bool valid;
441 u8 id;
442 u32 reg;
443 u32 mask;
444};
445
eed45b30
AD		 446struct radeon_hpd {
447 enum radeon_hpd_id hpd;
448 u8 plugged_state;
449 struct radeon_gpio_rec gpio;
450};
451
26b5bc98 452struct radeon_router {
26b5bc98
AD		 453 u32 router_id;
454 struct radeon_i2c_bus_rec i2c_info;
455 u8 i2c_addr;
fb939dfc
AD		 456 /* i2c mux */
457 bool ddc_valid;
458 u8 ddc_mux_type;
459 u8 ddc_mux_control_pin;
460 u8 ddc_mux_state;
461 /* clock/data mux */
462 bool cd_valid;
463 u8 cd_mux_type;
464 u8 cd_mux_control_pin;
465 u8 cd_mux_state;
26b5bc98
AD		 466};
467
771fe6b9
JG		 468struct radeon_connector {
469 struct drm_connector base;
470 uint32_t connector_id;
471 uint32_t devices;
472 struct radeon_i2c_chan *ddc_bus;
5b1714d3 473 /* some systems have an hdmi and vga port with a shared ddc line */
0294cf4f 474 bool shared_ddc;
4ce001ab
DA		 475 bool use_digital;
476 /* we need to mind the EDID between detect
477 and get modes due to analog/digital/tvencoder */
478 struct edid *edid;
771fe6b9 479 void *con_priv;
445282db 480 bool dac_load_detect;
d0d0a225 481 bool detected_by_load; /* if the connection status was determined by load */
b75fad06 482 uint16_t connector_object_id;
eed45b30 483 struct radeon_hpd hpd;
26b5bc98
AD		 484 struct radeon_router router;
485 struct radeon_i2c_chan *router_bus;
771fe6b9
JG		 486};
487
488struct radeon_framebuffer {
489 struct drm_framebuffer base;
490 struct drm_gem_object *obj;
491};
492
996d5c59
AD		 493#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
494 ((em) == ATOM_ENCODER_MODE_DP_MST))
6383cf7d 495
7062ab67
CK		 496struct atom_clock_dividers {
497 u32 post_div;
498 union {
499 struct {
500#ifdef __BIG_ENDIAN
501 u32 reserved : 6;
502 u32 whole_fb_div : 12;
503 u32 frac_fb_div : 14;
504#else
505 u32 frac_fb_div : 14;
506 u32 whole_fb_div : 12;
507 u32 reserved : 6;
508#endif
509 };
510 u32 fb_div;
511 };
512 u32 ref_div;
513 bool enable_post_div;
514 bool enable_dithen;
515 u32 vco_mode;
516 u32 real_clock;
517};
518
d79766fa
AD		 519extern enum radeon_tv_std
520radeon_combios_get_tv_info(struct radeon_device *rdev);
521extern enum radeon_tv_std
522radeon_atombios_get_tv_info(struct radeon_device *rdev);
523
5b1714d3
AD		 524extern struct drm_connector *
525radeon_get_connector_for_encoder(struct drm_encoder *encoder);
9aa59993
AD		 526extern struct drm_connector *
527radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
528extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
529 u32 pixel_clock);
5b1714d3 530
1d33e1fc
AD		 531extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
532extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
d7fa8bb3
AD		 533extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector);
534extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
eccea792 535extern int radeon_get_monitor_bpc(struct drm_connector *connector);
d7fa8bb3 536
d4877cf2 537extern void radeon_connector_hotplug(struct drm_connector *connector);
224d94b1 538extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
5801ead6
AD		 539 struct drm_display_mode *mode);
540extern void radeon_dp_set_link_config(struct drm_connector *connector,
e811f5ae 541 const struct drm_display_mode *mode);
224d94b1
AD		 542extern void radeon_dp_link_train(struct drm_encoder *encoder,
543 struct drm_connector *connector);
d5811e87 544extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
4143e919 545extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
9fa05c98 546extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
386d4d75
AD		 547extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
548 struct drm_connector *connector);
558e27db 549extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
ac89af1e 550extern void radeon_atom_encoder_init(struct radeon_device *rdev);
f3f1f03e 551extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
5801ead6
AD		 552extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
553 int action, uint8_t lane_num,
554 uint8_t lane_set);
591a10e1 555extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
3f03ced8 556extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
746c1aa4 557extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
834b2904 558 u8 write_byte, u8 *read_byte);
746c1aa4 559
f376b94f
AD		 560extern void radeon_i2c_init(struct radeon_device *rdev);
561extern void radeon_i2c_fini(struct radeon_device *rdev);
562extern void radeon_combios_i2c_init(struct radeon_device *rdev);
563extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
564extern void radeon_i2c_add(struct radeon_device *rdev,
565 struct radeon_i2c_bus_rec *rec,
566 const char *name);
567extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
568 struct radeon_i2c_bus_rec *i2c_bus);
746c1aa4 569extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
6a93cb25
AD		 570 struct radeon_i2c_bus_rec *rec,
571 const char *name);
771fe6b9
JG		 572extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
573 struct radeon_i2c_bus_rec *rec,
574 const char *name);
575extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
5a6f98f5
AD		 576extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
577 u8 slave_addr,
578 u8 addr,
579 u8 *val);
580extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
581 u8 slave_addr,
582 u8 addr,
583 u8 val);
fb939dfc
AD		 584extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
585extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
0a9069d3 586extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
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JG		 587extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
588
589extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
590
ba032a58
AD		 591extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
592 struct radeon_atom_ss *ss,
593 int id);
594extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
595 struct radeon_atom_ss *ss,
596 int id, u32 clock);
597
f523f74e
AD		 598extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
599 uint64_t freq,
600 uint32_t *dot_clock_p,
601 uint32_t *fb_div_p,
602 uint32_t *frac_fb_div_p,
603 uint32_t *ref_div_p,
604 uint32_t *post_div_p);
605
606extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
607 u32 freq,
608 u32 *dot_clock_p,
609 u32 *fb_div_p,
610 u32 *frac_fb_div_p,
611 u32 *ref_div_p,
612 u32 *post_div_p);
771fe6b9 613
1f3b6a45
DA		 614extern void radeon_setup_encoder_clones(struct drm_device *dev);
615
771fe6b9
JG		 616struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
617struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
618struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
619struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
620struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
99999aaa 621extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
32f48ffe 622extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
771fe6b9 623extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
2dafb74d 624extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
4ce001ab 625extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
771fe6b9
JG		 626
627extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
628extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
629 struct drm_framebuffer *old_fb);
4dd19b0d
CB		 630extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
631 struct drm_framebuffer *fb,
21c74a8e
JW		 632 int x, int y,
633 enum mode_set_atomic state);
771fe6b9
JG		 634extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
635 struct drm_display_mode *mode,
636 struct drm_display_mode *adjusted_mode,
637 int x, int y,
638 struct drm_framebuffer *old_fb);
639extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
640
641extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
642 struct drm_framebuffer *old_fb);
4dd19b0d
CB		 643extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
644 struct drm_framebuffer *fb,
21c74a8e
JW		 645 int x, int y,
646 enum mode_set_atomic state);
4dd19b0d
CB		 647extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
648 struct drm_framebuffer *fb,
649 int x, int y, int atomic);
771fe6b9
JG		 650extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
651 struct drm_file *file_priv,
652 uint32_t handle,
653 uint32_t width,
654 uint32_t height);
655extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
656 int x, int y);
657
f5a80209
MK		 658extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
659 int *vpos, int *hpos);
6383cf7d 660
3c537889
AD		 661extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
662extern struct edid *
c324acd5 663radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
771fe6b9
JG		 664extern bool radeon_atom_get_clock_info(struct drm_device *dev);
665extern bool radeon_combios_get_clock_info(struct drm_device *dev);
666extern struct radeon_encoder_atom_dig *
667radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
fcec570b
AD		 668extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
669 struct radeon_encoder_int_tmds *tmds);
670extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
671 struct radeon_encoder_int_tmds *tmds);
672extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
673 struct radeon_encoder_int_tmds *tmds);
674extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
675 struct radeon_encoder_ext_tmds *tmds);
676extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
677 struct radeon_encoder_ext_tmds *tmds);
6fe7ac3f
AD		 678extern struct radeon_encoder_primary_dac *
679radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
680extern struct radeon_encoder_tv_dac *
681radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
771fe6b9
JG		 682extern struct radeon_encoder_lvds *
683radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
771fe6b9
JG		 684extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
685extern struct radeon_encoder_tv_dac *
686radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
687extern struct radeon_encoder_primary_dac *
688radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
fcec570b
AD		 689extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
690extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
771fe6b9
JG		 691extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
692extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
693extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
694extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
f657c2a7
YZ		 695extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
696extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
771fe6b9
JG		 697extern void
698radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
699extern void
700radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
701extern void
702radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
703extern void
704radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
705extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
706 u16 blue, int regno);
b8c00ac5
DA		 707extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
708 u16 *blue, int regno);
aaefcd42 709int radeon_framebuffer_init(struct drm_device *dev,
38651674 710 struct radeon_framebuffer *rfb,
308e5bcb 711 struct drm_mode_fb_cmd2 *mode_cmd,
38651674 712 struct drm_gem_object *obj);
771fe6b9
JG		 713
714int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
715bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
716bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
717void radeon_atombios_init_crtc(struct drm_device *dev,
718 struct radeon_crtc *radeon_crtc);
719void radeon_legacy_init_crtc(struct drm_device *dev,
720 struct radeon_crtc *radeon_crtc);
771fe6b9
JG		 721
722void radeon_get_clock_info(struct drm_device *dev);
723
724extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
725extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
726
771fe6b9
JG		 727void radeon_enc_destroy(struct drm_encoder *encoder);
728void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
729void radeon_combios_asic_init(struct drm_device *dev);
c93bb85b 730bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
e811f5ae 731 const struct drm_display_mode *mode,
c93bb85b 732 struct drm_display_mode *adjusted_mode);
3515387b
AD		 733void radeon_panel_mode_fixup(struct drm_encoder *encoder,
734 struct drm_display_mode *adjusted_mode);
4ce001ab
DA		 735void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
736
737/* legacy tv */
738void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
739 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
740 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
741void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
742 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
743 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
744void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
745 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
746 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
747void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
748 struct drm_display_mode *mode,
749 struct drm_display_mode *adjusted_mode);
38651674
DA		 750
751/* fbdev layer */
752int radeon_fbdev_init(struct radeon_device *rdev);
753void radeon_fbdev_fini(struct radeon_device *rdev);
754void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
755int radeon_fbdev_total_size(struct radeon_device *rdev);
756bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
eb1f8e4f
DA		 757
758void radeon_fb_output_poll_changed(struct radeon_device *rdev);
6f34be50
AD		 759
760void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
761
ff72145b 762int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
771fe6b9 763#endif
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