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drm/radeon/kms: move disp eng pll setup to init path
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / radeon / radeon_mode.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm_crtc.h>
34#include <drm_mode.h>
35#include <drm_edid.h>
746c1aa4 36#include <drm_dp_helper.h>
68adac5e 37#include <drm_fixed.h>
21c74a8e 38#include <drm_crtc_helper.h>
771fe6b9 39#include <linux/i2c.h>
771fe6b9 40#include <linux/i2c-algo-bit.h>
c93bb85b 41
38651674 42struct radeon_bo;
c93bb85b 43struct radeon_device;
771fe6b9
JG		 44
45#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
46#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
47#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
48#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
49
771fe6b9
JG		 50enum radeon_rmx_type {
51 RMX_OFF,
52 RMX_FULL,
53 RMX_CENTER,
54 RMX_ASPECT
55};
56
57enum radeon_tv_std {
58 TV_STD_NTSC,
59 TV_STD_PAL,
60 TV_STD_PAL_M,
61 TV_STD_PAL_60,
62 TV_STD_NTSC_J,
63 TV_STD_SCART_PAL,
64 TV_STD_SECAM,
65 TV_STD_PAL_CN,
d79766fa 66 TV_STD_PAL_N,
771fe6b9
JG		 67};
68
5b1714d3
AD		 69enum radeon_underscan_type {
70 UNDERSCAN_OFF,
71 UNDERSCAN_ON,
72 UNDERSCAN_AUTO,
73};
74
8e36ed00
AD		 75enum radeon_hpd_id {
76 RADEON_HPD_1 = 0,
77 RADEON_HPD_2,
78 RADEON_HPD_3,
79 RADEON_HPD_4,
80 RADEON_HPD_5,
81 RADEON_HPD_6,
82 RADEON_HPD_NONE = 0xff,
83};
84
f376b94f
AD		 85#define RADEON_MAX_I2C_BUS 16
86
9b9fe724
AD		 87/* radeon gpio-based i2c
88 * 1. "mask" reg and bits
89 * grabs the gpio pins for software use
90 * 0=not held 1=held
91 * 2. "a" reg and bits
92 * output pin value
93 * 0=low 1=high
94 * 3. "en" reg and bits
95 * sets the pin direction
96 * 0=input 1=output
97 * 4. "y" reg and bits
98 * input pin value
99 * 0=low 1=high
100 */
771fe6b9
JG		 101struct radeon_i2c_bus_rec {
102 bool valid;
6a93cb25
AD		 103 /* id used by atom */
104 uint8_t i2c_id;
bcc1c2a1 105 /* id used by atom */
8e36ed00 106 enum radeon_hpd_id hpd;
6a93cb25
AD		 107 /* can be used with hw i2c engine */
108 bool hw_capable;
109 /* uses multi-media i2c engine */
110 bool mm_i2c;
111 /* regs and bits */
771fe6b9
JG		 112 uint32_t mask_clk_reg;
113 uint32_t mask_data_reg;
114 uint32_t a_clk_reg;
115 uint32_t a_data_reg;
9b9fe724
AD		 116 uint32_t en_clk_reg;
117 uint32_t en_data_reg;
118 uint32_t y_clk_reg;
119 uint32_t y_data_reg;
771fe6b9
JG		 120 uint32_t mask_clk_mask;
121 uint32_t mask_data_mask;
771fe6b9
JG		 122 uint32_t a_clk_mask;
123 uint32_t a_data_mask;
9b9fe724
AD		 124 uint32_t en_clk_mask;
125 uint32_t en_data_mask;
126 uint32_t y_clk_mask;
127 uint32_t y_data_mask;
771fe6b9
JG		 128};
129
130struct radeon_tmds_pll {
131 uint32_t freq;
132 uint32_t value;
133};
134
135#define RADEON_MAX_BIOS_CONNECTOR 16
136
7c27f87d 137/* pll flags */
771fe6b9
JG		 138#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
139#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
140#define RADEON_PLL_USE_REF_DIV (1 << 2)
141#define RADEON_PLL_LEGACY (1 << 3)
142#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
143#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
144#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
145#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
146#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
147#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
148#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
d0e275a9 149#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
fc10332b 150#define RADEON_PLL_USE_POST_DIV (1 << 12)
86cb2bbf 151#define RADEON_PLL_IS_LCD (1 << 13)
f523f74e 152#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
771fe6b9
JG		 153
154struct radeon_pll {
fc10332b
AD		 155 /* reference frequency */
156 uint32_t reference_freq;
157
158 /* fixed dividers */
159 uint32_t reference_div;
160 uint32_t post_div;
161
162 /* pll in/out limits */
771fe6b9
JG		 163 uint32_t pll_in_min;
164 uint32_t pll_in_max;
165 uint32_t pll_out_min;
166 uint32_t pll_out_max;
86cb2bbf
AD		 167 uint32_t lcd_pll_out_min;
168 uint32_t lcd_pll_out_max;
fc10332b 169 uint32_t best_vco;
771fe6b9 170
fc10332b 171 /* divider limits */
771fe6b9
JG		 172 uint32_t min_ref_div;
173 uint32_t max_ref_div;
174 uint32_t min_post_div;
175 uint32_t max_post_div;
176 uint32_t min_feedback_div;
177 uint32_t max_feedback_div;
178 uint32_t min_frac_feedback_div;
179 uint32_t max_frac_feedback_div;
fc10332b
AD		 180
181 /* flags for the current clock */
182 uint32_t flags;
183
184 /* pll id */
185 uint32_t id;
771fe6b9
JG		 186};
187
188struct radeon_i2c_chan {
771fe6b9 189 struct i2c_adapter adapter;
746c1aa4
DA		 190 struct drm_device *dev;
191 union {
ac1aade6 192 struct i2c_algo_bit_data bit;
746c1aa4 193 struct i2c_algo_dp_aux_data dp;
746c1aa4 194 } algo;
771fe6b9
JG		 195 struct radeon_i2c_bus_rec rec;
196};
197
198/* mostly for macs, but really any system without connector tables */
199enum radeon_connector_table {
aa74fbb4 200 CT_NONE = 0,
771fe6b9
JG		 201 CT_GENERIC,
202 CT_IBOOK,
203 CT_POWERBOOK_EXTERNAL,
204 CT_POWERBOOK_INTERNAL,
205 CT_POWERBOOK_VGA,
206 CT_MINI_EXTERNAL,
207 CT_MINI_INTERNAL,
208 CT_IMAC_G5_ISIGHT,
209 CT_EMAC,
76a7142a 210 CT_RN50_POWER,
aa74fbb4 211 CT_MAC_X800,
9fad321a 212 CT_MAC_G5_9600,
771fe6b9
JG		 213};
214
fcec570b
AD		 215enum radeon_dvo_chip {
216 DVO_SIL164,
217 DVO_SIL1178,
218};
219
8be48d92 220struct radeon_fbdev;
38651674 221
771fe6b9
JG		 222struct radeon_mode_info {
223 struct atom_context *atom_context;
61c4b24b 224 struct card_info *atom_card_info;
771fe6b9
JG		 225 enum radeon_connector_table connector_table;
226 bool mode_config_initialized;
bcc1c2a1 227 struct radeon_crtc *crtcs[6];
445282db
DA		 228 /* DVI-I properties */
229 struct drm_property *coherent_mode_property;
230 /* DAC enable load detect */
231 struct drm_property *load_detect_property;
5b1714d3 232 /* TV standard */
445282db
DA		 233 struct drm_property *tv_std_property;
234 /* legacy TMDS PLL detect */
235 struct drm_property *tmds_pll_property;
5b1714d3
AD		 236 /* underscan */
237 struct drm_property *underscan_property;
5bccf5e3
MG		 238 struct drm_property *underscan_hborder_property;
239 struct drm_property *underscan_vborder_property;
3c537889
AD		 240 /* hardcoded DFP edid from BIOS */
241 struct edid *bios_hardcoded_edid;
fafcf94e 242 int bios_hardcoded_edid_size;
38651674
DA		 243
244 /* pointer to fbdev info structure */
8be48d92 245 struct radeon_fbdev *rfbdev;
c93bb85b
JG		 246};
247
4ce001ab
DA		 248#define MAX_H_CODE_TIMING_LEN 32
249#define MAX_V_CODE_TIMING_LEN 32
250
251/* need to store these as reading
252 back code tables is excessive */
253struct radeon_tv_regs {
254 uint32_t tv_uv_adr;
255 uint32_t timing_cntl;
256 uint32_t hrestart;
257 uint32_t vrestart;
258 uint32_t frestart;
259 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
260 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
261};
262
771fe6b9
JG		 263struct radeon_crtc {
264 struct drm_crtc base;
265 int crtc_id;
266 u16 lut_r[256], lut_g[256], lut_b[256];
267 bool enabled;
268 bool can_tile;
269 uint32_t crtc_offset;
771fe6b9
JG		 270 struct drm_gem_object *cursor_bo;
271 uint64_t cursor_addr;
272 int cursor_width;
273 int cursor_height;
4162338a 274 uint32_t legacy_display_base_addr;
c836e862 275 uint32_t legacy_cursor_offset;
c93bb85b 276 enum radeon_rmx_type rmx_type;
5b1714d3
AD		 277 u8 h_border;
278 u8 v_border;
c93bb85b
JG		 279 fixed20_12 vsc;
280 fixed20_12 hsc;
de2103e4 281 struct drm_display_mode native_mode;
bcc1c2a1 282 int pll_id;
6f34be50
AD		 283 /* page flipping */
284 struct radeon_unpin_work *unpin_work;
285 int deferred_flip_completion;
771fe6b9
JG		 286};
287
288struct radeon_encoder_primary_dac {
289 /* legacy primary dac */
290 uint32_t ps2_pdac_adj;
291};
292
293struct radeon_encoder_lvds {
294 /* legacy lvds */
295 uint16_t panel_vcc_delay;
296 uint8_t panel_pwr_delay;
297 uint8_t panel_digon_delay;
298 uint8_t panel_blon_delay;
299 uint16_t panel_ref_divider;
300 uint8_t panel_post_divider;
301 uint16_t panel_fb_divider;
302 bool use_bios_dividers;
303 uint32_t lvds_gen_cntl;
304 /* panel mode */
de2103e4 305 struct drm_display_mode native_mode;
63ec0119
MD		 306 struct backlight_device *bl_dev;
307 int dpms_mode;
308 uint8_t backlight_level;
771fe6b9
JG		 309};
310
311struct radeon_encoder_tv_dac {
312 /* legacy tv dac */
313 uint32_t ps2_tvdac_adj;
314 uint32_t ntsc_tvdac_adj;
315 uint32_t pal_tvdac_adj;
316
4ce001ab
DA		 317 int h_pos;
318 int v_pos;
319 int h_size;
320 int supported_tv_stds;
321 bool tv_on;
771fe6b9 322 enum radeon_tv_std tv_std;
4ce001ab 323 struct radeon_tv_regs tv;
771fe6b9
JG		 324};
325
326struct radeon_encoder_int_tmds {
327 /* legacy int tmds */
328 struct radeon_tmds_pll tmds_pll[4];
329};
330
fcec570b
AD		 331struct radeon_encoder_ext_tmds {
332 /* tmds over dvo */
333 struct radeon_i2c_chan *i2c_bus;
334 uint8_t slave_addr;
335 enum radeon_dvo_chip dvo_chip;
336};
337
ebbe1cb9
AD		 338/* spread spectrum */
339struct radeon_atom_ss {
340 uint16_t percentage;
341 uint8_t type;
ba032a58 342 uint16_t step;
ebbe1cb9
AD		 343 uint8_t delay;
344 uint8_t range;
345 uint8_t refdiv;
ba032a58
AD		 346 /* asic_ss */
347 uint16_t rate;
348 uint16_t amount;
ebbe1cb9
AD		 349};
350
771fe6b9 351struct radeon_encoder_atom_dig {
5137ee94 352 bool linkb;
771fe6b9
JG		 353 /* atom dig */
354 bool coherent_mode;
ba032a58
AD		 355 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
356 /* atom lvds/edp */
357 uint32_t lcd_misc;
771fe6b9 358 uint16_t panel_pwr_delay;
ba032a58 359 uint32_t lcd_ss_id;
771fe6b9 360 /* panel mode */
de2103e4 361 struct drm_display_mode native_mode;
63ec0119
MD		 362 struct backlight_device *bl_dev;
363 int dpms_mode;
364 uint8_t backlight_level;
771fe6b9
JG		 365};
366
4ce001ab
DA		 367struct radeon_encoder_atom_dac {
368 enum radeon_tv_std tv_std;
369};
370
771fe6b9
JG		 371struct radeon_encoder {
372 struct drm_encoder base;
5137ee94 373 uint32_t encoder_enum;
771fe6b9
JG		 374 uint32_t encoder_id;
375 uint32_t devices;
4ce001ab 376 uint32_t active_device;
771fe6b9
JG		 377 uint32_t flags;
378 uint32_t pixel_clock;
379 enum radeon_rmx_type rmx_type;
5b1714d3 380 enum radeon_underscan_type underscan_type;
5bccf5e3
MG		 381 uint32_t underscan_hborder;
382 uint32_t underscan_vborder;
de2103e4 383 struct drm_display_mode native_mode;
771fe6b9 384 void *enc_priv;
58bd0863 385 int audio_polling_active;
dafc3bd5 386 int hdmi_offset;
808032ee 387 int hdmi_config_offset;
dafc3bd5
CK		 388 int hdmi_audio_workaround;
389 int hdmi_buffer_status;
3e4b9982 390 bool is_ext_encoder;
36868bda 391 u16 caps;
771fe6b9
JG		 392};
393
394struct radeon_connector_atom_dig {
395 uint32_t igp_lane_info;
4143e919 396 /* displayport */
746c1aa4 397 struct radeon_i2c_chan *dp_i2c_bus;
1a66c95a 398 u8 dpcd[8];
4143e919 399 u8 dp_sink_type;
5801ead6
AD		 400 int dp_clock;
401 int dp_lane_count;
8b834852 402 bool edp_on;
771fe6b9
JG		 403};
404
eed45b30
AD		 405struct radeon_gpio_rec {
406 bool valid;
407 u8 id;
408 u32 reg;
409 u32 mask;
410};
411
eed45b30
AD		 412struct radeon_hpd {
413 enum radeon_hpd_id hpd;
414 u8 plugged_state;
415 struct radeon_gpio_rec gpio;
416};
417
26b5bc98 418struct radeon_router {
26b5bc98
AD		 419 u32 router_id;
420 struct radeon_i2c_bus_rec i2c_info;
421 u8 i2c_addr;
fb939dfc
AD		 422 /* i2c mux */
423 bool ddc_valid;
424 u8 ddc_mux_type;
425 u8 ddc_mux_control_pin;
426 u8 ddc_mux_state;
427 /* clock/data mux */
428 bool cd_valid;
429 u8 cd_mux_type;
430 u8 cd_mux_control_pin;
431 u8 cd_mux_state;
26b5bc98
AD		 432};
433
771fe6b9
JG		 434struct radeon_connector {
435 struct drm_connector base;
436 uint32_t connector_id;
437 uint32_t devices;
438 struct radeon_i2c_chan *ddc_bus;
5b1714d3 439 /* some systems have an hdmi and vga port with a shared ddc line */
0294cf4f 440 bool shared_ddc;
4ce001ab
DA		 441 bool use_digital;
442 /* we need to mind the EDID between detect
443 and get modes due to analog/digital/tvencoder */
444 struct edid *edid;
771fe6b9 445 void *con_priv;
445282db 446 bool dac_load_detect;
d0d0a225 447 bool detected_by_load; /* if the connection status was determined by load */
b75fad06 448 uint16_t connector_object_id;
eed45b30 449 struct radeon_hpd hpd;
26b5bc98
AD		 450 struct radeon_router router;
451 struct radeon_i2c_chan *router_bus;
771fe6b9
JG		 452};
453
454struct radeon_framebuffer {
455 struct drm_framebuffer base;
456 struct drm_gem_object *obj;
457};
458
996d5c59
AD		 459#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
460 ((em) == ATOM_ENCODER_MODE_DP_MST))
6383cf7d 461
d79766fa
AD		 462extern enum radeon_tv_std
463radeon_combios_get_tv_info(struct radeon_device *rdev);
464extern enum radeon_tv_std
465radeon_atombios_get_tv_info(struct radeon_device *rdev);
466
5b1714d3
AD		 467extern struct drm_connector *
468radeon_get_connector_for_encoder(struct drm_encoder *encoder);
469
1d33e1fc
AD		 470extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
471extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
d7fa8bb3
AD		 472extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector);
473extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
474
d4877cf2 475extern void radeon_connector_hotplug(struct drm_connector *connector);
224d94b1 476extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
5801ead6
AD		 477 struct drm_display_mode *mode);
478extern void radeon_dp_set_link_config(struct drm_connector *connector,
479 struct drm_display_mode *mode);
224d94b1
AD		 480extern void radeon_dp_link_train(struct drm_encoder *encoder,
481 struct drm_connector *connector);
d5811e87 482extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
4143e919 483extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
9fa05c98 484extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
558e27db 485extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
ac89af1e 486extern void radeon_atom_encoder_init(struct radeon_device *rdev);
3fa47d9e 487extern void radeon_atom_dcpll_init(struct radeon_device *rdev);
5801ead6
AD		 488extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
489 int action, uint8_t lane_num,
490 uint8_t lane_set);
591a10e1 491extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
3f03ced8 492extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
746c1aa4 493extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
834b2904 494 u8 write_byte, u8 *read_byte);
746c1aa4 495
f376b94f
AD		 496extern void radeon_i2c_init(struct radeon_device *rdev);
497extern void radeon_i2c_fini(struct radeon_device *rdev);
498extern void radeon_combios_i2c_init(struct radeon_device *rdev);
499extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
500extern void radeon_i2c_add(struct radeon_device *rdev,
501 struct radeon_i2c_bus_rec *rec,
502 const char *name);
503extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
504 struct radeon_i2c_bus_rec *i2c_bus);
746c1aa4 505extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
6a93cb25
AD		 506 struct radeon_i2c_bus_rec *rec,
507 const char *name);
771fe6b9
JG		 508extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
509 struct radeon_i2c_bus_rec *rec,
510 const char *name);
511extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
5a6f98f5
AD		 512extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
513 u8 slave_addr,
514 u8 addr,
515 u8 *val);
516extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
517 u8 slave_addr,
518 u8 addr,
519 u8 val);
fb939dfc
AD		 520extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
521extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
bc1c4dc3 522extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
771fe6b9
JG		 523extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
524
525extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
526
ba032a58
AD		 527extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
528 struct radeon_atom_ss *ss,
529 int id);
530extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
531 struct radeon_atom_ss *ss,
532 int id, u32 clock);
533
f523f74e
AD		 534extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
535 uint64_t freq,
536 uint32_t *dot_clock_p,
537 uint32_t *fb_div_p,
538 uint32_t *frac_fb_div_p,
539 uint32_t *ref_div_p,
540 uint32_t *post_div_p);
541
542extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
543 u32 freq,
544 u32 *dot_clock_p,
545 u32 *fb_div_p,
546 u32 *frac_fb_div_p,
547 u32 *ref_div_p,
548 u32 *post_div_p);
771fe6b9 549
1f3b6a45
DA		 550extern void radeon_setup_encoder_clones(struct drm_device *dev);
551
771fe6b9
JG		 552struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
553struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
554struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
555struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
556struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
99999aaa 557extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
32f48ffe 558extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
771fe6b9 559extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
2dafb74d 560extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
4ce001ab 561extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
771fe6b9
JG		 562
563extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
564extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
565 struct drm_framebuffer *old_fb);
4dd19b0d
CB		 566extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
567 struct drm_framebuffer *fb,
21c74a8e
JW		 568 int x, int y,
569 enum mode_set_atomic state);
771fe6b9
JG		 570extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
571 struct drm_display_mode *mode,
572 struct drm_display_mode *adjusted_mode,
573 int x, int y,
574 struct drm_framebuffer *old_fb);
575extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
576
577extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
578 struct drm_framebuffer *old_fb);
4dd19b0d
CB		 579extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
580 struct drm_framebuffer *fb,
21c74a8e
JW		 581 int x, int y,
582 enum mode_set_atomic state);
4dd19b0d
CB		 583extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
584 struct drm_framebuffer *fb,
585 int x, int y, int atomic);
771fe6b9
JG		 586extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
587 struct drm_file *file_priv,
588 uint32_t handle,
589 uint32_t width,
590 uint32_t height);
591extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
592 int x, int y);
593
f5a80209
MK		 594extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
595 int *vpos, int *hpos);
6383cf7d 596
3c537889
AD		 597extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
598extern struct edid *
c324acd5 599radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
771fe6b9
JG		 600extern bool radeon_atom_get_clock_info(struct drm_device *dev);
601extern bool radeon_combios_get_clock_info(struct drm_device *dev);
602extern struct radeon_encoder_atom_dig *
603radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
fcec570b
AD		 604extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
605 struct radeon_encoder_int_tmds *tmds);
606extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
607 struct radeon_encoder_int_tmds *tmds);
608extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
609 struct radeon_encoder_int_tmds *tmds);
610extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
611 struct radeon_encoder_ext_tmds *tmds);
612extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
613 struct radeon_encoder_ext_tmds *tmds);
6fe7ac3f
AD		 614extern struct radeon_encoder_primary_dac *
615radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
616extern struct radeon_encoder_tv_dac *
617radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
771fe6b9
JG		 618extern struct radeon_encoder_lvds *
619radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
771fe6b9
JG		 620extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
621extern struct radeon_encoder_tv_dac *
622radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
623extern struct radeon_encoder_primary_dac *
624radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
fcec570b
AD		 625extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
626extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
771fe6b9
JG		 627extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
628extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
629extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
630extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
f657c2a7
YZ		 631extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
632extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
771fe6b9
JG		 633extern void
634radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
635extern void
636radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
637extern void
638radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
639extern void
640radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
641extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
642 u16 blue, int regno);
b8c00ac5
DA		 643extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
644 u16 *blue, int regno);
38651674
DA		 645void radeon_framebuffer_init(struct drm_device *dev,
646 struct radeon_framebuffer *rfb,
308e5bcb 647 struct drm_mode_fb_cmd2 *mode_cmd,
38651674 648 struct drm_gem_object *obj);
771fe6b9
JG		 649
650int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
651bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
652bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
653void radeon_atombios_init_crtc(struct drm_device *dev,
654 struct radeon_crtc *radeon_crtc);
655void radeon_legacy_init_crtc(struct drm_device *dev,
656 struct radeon_crtc *radeon_crtc);
771fe6b9
JG		 657
658void radeon_get_clock_info(struct drm_device *dev);
659
660extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
661extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
662
771fe6b9
JG		 663void radeon_enc_destroy(struct drm_encoder *encoder);
664void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
665void radeon_combios_asic_init(struct drm_device *dev);
c93bb85b
JG		 666bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
667 struct drm_display_mode *mode,
668 struct drm_display_mode *adjusted_mode);
3515387b
AD		 669void radeon_panel_mode_fixup(struct drm_encoder *encoder,
670 struct drm_display_mode *adjusted_mode);
4ce001ab
DA		 671void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
672
673/* legacy tv */
674void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
675 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
676 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
677void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
678 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
679 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
680void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
681 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
682 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
683void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
684 struct drm_display_mode *mode,
685 struct drm_display_mode *adjusted_mode);
38651674
DA		 686
687/* fbdev layer */
688int radeon_fbdev_init(struct radeon_device *rdev);
689void radeon_fbdev_fini(struct radeon_device *rdev);
690void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
691int radeon_fbdev_total_size(struct radeon_device *rdev);
692bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
eb1f8e4f
DA		 693
694void radeon_fb_output_poll_changed(struct radeon_device *rdev);
6f34be50
AD		 695
696void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
697
ff72145b 698int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
771fe6b9 699#endif
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