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Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and | |
3 | * VA Linux Systems Inc., Fremont, California. | |
4 | * Copyright 2008 Red Hat Inc. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Original Authors: | |
25 | * Kevin E. Martin, Rickard E. Faith, Alan Hourihane | |
26 | * | |
27 | * Kernel port Author: Dave Airlie | |
28 | */ | |
29 | ||
30 | #ifndef RADEON_MODE_H | |
31 | #define RADEON_MODE_H | |
32 | ||
760285e7 DH |
33 | #include <drm/drm_crtc.h> |
34 | #include <drm/drm_edid.h> | |
35 | #include <drm/drm_dp_helper.h> | |
36 | #include <drm/drm_fixed.h> | |
37 | #include <drm/drm_crtc_helper.h> | |
771fe6b9 | 38 | #include <linux/i2c.h> |
771fe6b9 | 39 | #include <linux/i2c-algo-bit.h> |
c93bb85b | 40 | |
38651674 | 41 | struct radeon_bo; |
c93bb85b | 42 | struct radeon_device; |
771fe6b9 JG |
43 | |
44 | #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) | |
45 | #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) | |
46 | #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) | |
47 | #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) | |
48 | ||
88f39063 SB |
49 | #define RADEON_MAX_HPD_PINS 7 |
50 | #define RADEON_MAX_CRTCS 6 | |
51 | #define RADEON_MAX_AFMT_BLOCKS 7 | |
52 | ||
771fe6b9 JG |
53 | enum radeon_rmx_type { |
54 | RMX_OFF, | |
55 | RMX_FULL, | |
56 | RMX_CENTER, | |
57 | RMX_ASPECT | |
58 | }; | |
59 | ||
60 | enum radeon_tv_std { | |
61 | TV_STD_NTSC, | |
62 | TV_STD_PAL, | |
63 | TV_STD_PAL_M, | |
64 | TV_STD_PAL_60, | |
65 | TV_STD_NTSC_J, | |
66 | TV_STD_SCART_PAL, | |
67 | TV_STD_SECAM, | |
68 | TV_STD_PAL_CN, | |
d79766fa | 69 | TV_STD_PAL_N, |
771fe6b9 JG |
70 | }; |
71 | ||
5b1714d3 AD |
72 | enum radeon_underscan_type { |
73 | UNDERSCAN_OFF, | |
74 | UNDERSCAN_ON, | |
75 | UNDERSCAN_AUTO, | |
76 | }; | |
77 | ||
8e36ed00 AD |
78 | enum radeon_hpd_id { |
79 | RADEON_HPD_1 = 0, | |
80 | RADEON_HPD_2, | |
81 | RADEON_HPD_3, | |
82 | RADEON_HPD_4, | |
83 | RADEON_HPD_5, | |
84 | RADEON_HPD_6, | |
85 | RADEON_HPD_NONE = 0xff, | |
86 | }; | |
87 | ||
f376b94f AD |
88 | #define RADEON_MAX_I2C_BUS 16 |
89 | ||
9b9fe724 AD |
90 | /* radeon gpio-based i2c |
91 | * 1. "mask" reg and bits | |
92 | * grabs the gpio pins for software use | |
93 | * 0=not held 1=held | |
94 | * 2. "a" reg and bits | |
95 | * output pin value | |
96 | * 0=low 1=high | |
97 | * 3. "en" reg and bits | |
98 | * sets the pin direction | |
99 | * 0=input 1=output | |
100 | * 4. "y" reg and bits | |
101 | * input pin value | |
102 | * 0=low 1=high | |
103 | */ | |
771fe6b9 JG |
104 | struct radeon_i2c_bus_rec { |
105 | bool valid; | |
6a93cb25 AD |
106 | /* id used by atom */ |
107 | uint8_t i2c_id; | |
bcc1c2a1 | 108 | /* id used by atom */ |
8e36ed00 | 109 | enum radeon_hpd_id hpd; |
6a93cb25 AD |
110 | /* can be used with hw i2c engine */ |
111 | bool hw_capable; | |
112 | /* uses multi-media i2c engine */ | |
113 | bool mm_i2c; | |
114 | /* regs and bits */ | |
771fe6b9 JG |
115 | uint32_t mask_clk_reg; |
116 | uint32_t mask_data_reg; | |
117 | uint32_t a_clk_reg; | |
118 | uint32_t a_data_reg; | |
9b9fe724 AD |
119 | uint32_t en_clk_reg; |
120 | uint32_t en_data_reg; | |
121 | uint32_t y_clk_reg; | |
122 | uint32_t y_data_reg; | |
771fe6b9 JG |
123 | uint32_t mask_clk_mask; |
124 | uint32_t mask_data_mask; | |
771fe6b9 JG |
125 | uint32_t a_clk_mask; |
126 | uint32_t a_data_mask; | |
9b9fe724 AD |
127 | uint32_t en_clk_mask; |
128 | uint32_t en_data_mask; | |
129 | uint32_t y_clk_mask; | |
130 | uint32_t y_data_mask; | |
771fe6b9 JG |
131 | }; |
132 | ||
133 | struct radeon_tmds_pll { | |
134 | uint32_t freq; | |
135 | uint32_t value; | |
136 | }; | |
137 | ||
138 | #define RADEON_MAX_BIOS_CONNECTOR 16 | |
139 | ||
7c27f87d | 140 | /* pll flags */ |
771fe6b9 JG |
141 | #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) |
142 | #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) | |
143 | #define RADEON_PLL_USE_REF_DIV (1 << 2) | |
144 | #define RADEON_PLL_LEGACY (1 << 3) | |
145 | #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) | |
146 | #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) | |
147 | #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) | |
148 | #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) | |
149 | #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) | |
150 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) | |
151 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) | |
d0e275a9 | 152 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
fc10332b | 153 | #define RADEON_PLL_USE_POST_DIV (1 << 12) |
86cb2bbf | 154 | #define RADEON_PLL_IS_LCD (1 << 13) |
f523f74e | 155 | #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) |
771fe6b9 JG |
156 | |
157 | struct radeon_pll { | |
fc10332b AD |
158 | /* reference frequency */ |
159 | uint32_t reference_freq; | |
160 | ||
161 | /* fixed dividers */ | |
162 | uint32_t reference_div; | |
163 | uint32_t post_div; | |
164 | ||
165 | /* pll in/out limits */ | |
771fe6b9 JG |
166 | uint32_t pll_in_min; |
167 | uint32_t pll_in_max; | |
168 | uint32_t pll_out_min; | |
169 | uint32_t pll_out_max; | |
86cb2bbf AD |
170 | uint32_t lcd_pll_out_min; |
171 | uint32_t lcd_pll_out_max; | |
fc10332b | 172 | uint32_t best_vco; |
771fe6b9 | 173 | |
fc10332b | 174 | /* divider limits */ |
771fe6b9 JG |
175 | uint32_t min_ref_div; |
176 | uint32_t max_ref_div; | |
177 | uint32_t min_post_div; | |
178 | uint32_t max_post_div; | |
179 | uint32_t min_feedback_div; | |
180 | uint32_t max_feedback_div; | |
181 | uint32_t min_frac_feedback_div; | |
182 | uint32_t max_frac_feedback_div; | |
fc10332b AD |
183 | |
184 | /* flags for the current clock */ | |
185 | uint32_t flags; | |
186 | ||
187 | /* pll id */ | |
188 | uint32_t id; | |
771fe6b9 JG |
189 | }; |
190 | ||
191 | struct radeon_i2c_chan { | |
771fe6b9 | 192 | struct i2c_adapter adapter; |
746c1aa4 | 193 | struct drm_device *dev; |
379dfc25 | 194 | struct i2c_algo_bit_data bit; |
771fe6b9 | 195 | struct radeon_i2c_bus_rec rec; |
496263bf | 196 | struct drm_dp_aux aux; |
379dfc25 | 197 | bool has_aux; |
831719d6 | 198 | struct mutex mutex; |
771fe6b9 JG |
199 | }; |
200 | ||
201 | /* mostly for macs, but really any system without connector tables */ | |
202 | enum radeon_connector_table { | |
aa74fbb4 | 203 | CT_NONE = 0, |
771fe6b9 JG |
204 | CT_GENERIC, |
205 | CT_IBOOK, | |
206 | CT_POWERBOOK_EXTERNAL, | |
207 | CT_POWERBOOK_INTERNAL, | |
208 | CT_POWERBOOK_VGA, | |
209 | CT_MINI_EXTERNAL, | |
210 | CT_MINI_INTERNAL, | |
211 | CT_IMAC_G5_ISIGHT, | |
212 | CT_EMAC, | |
76a7142a | 213 | CT_RN50_POWER, |
aa74fbb4 | 214 | CT_MAC_X800, |
9fad321a | 215 | CT_MAC_G5_9600, |
cafa59b9 AD |
216 | CT_SAM440EP, |
217 | CT_MAC_G4_SILVER | |
771fe6b9 JG |
218 | }; |
219 | ||
fcec570b AD |
220 | enum radeon_dvo_chip { |
221 | DVO_SIL164, | |
222 | DVO_SIL1178, | |
223 | }; | |
224 | ||
8be48d92 | 225 | struct radeon_fbdev; |
38651674 | 226 | |
0783986a AD |
227 | struct radeon_afmt { |
228 | bool enabled; | |
229 | int offset; | |
230 | bool last_buffer_filled_status; | |
231 | int id; | |
b530602f | 232 | struct r600_audio_pin *pin; |
0783986a AD |
233 | }; |
234 | ||
771fe6b9 JG |
235 | struct radeon_mode_info { |
236 | struct atom_context *atom_context; | |
61c4b24b | 237 | struct card_info *atom_card_info; |
771fe6b9 JG |
238 | enum radeon_connector_table connector_table; |
239 | bool mode_config_initialized; | |
88f39063 SB |
240 | struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; |
241 | struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS]; | |
445282db DA |
242 | /* DVI-I properties */ |
243 | struct drm_property *coherent_mode_property; | |
244 | /* DAC enable load detect */ | |
245 | struct drm_property *load_detect_property; | |
5b1714d3 | 246 | /* TV standard */ |
445282db DA |
247 | struct drm_property *tv_std_property; |
248 | /* legacy TMDS PLL detect */ | |
249 | struct drm_property *tmds_pll_property; | |
5b1714d3 AD |
250 | /* underscan */ |
251 | struct drm_property *underscan_property; | |
5bccf5e3 MG |
252 | struct drm_property *underscan_hborder_property; |
253 | struct drm_property *underscan_vborder_property; | |
8666c076 AD |
254 | /* audio */ |
255 | struct drm_property *audio_property; | |
6214bb74 AD |
256 | /* FMT dithering */ |
257 | struct drm_property *dither_property; | |
3c537889 AD |
258 | /* hardcoded DFP edid from BIOS */ |
259 | struct edid *bios_hardcoded_edid; | |
fafcf94e | 260 | int bios_hardcoded_edid_size; |
38651674 DA |
261 | |
262 | /* pointer to fbdev info structure */ | |
8be48d92 | 263 | struct radeon_fbdev *rfbdev; |
af7912e5 AD |
264 | /* firmware flags */ |
265 | u16 firmware_flags; | |
bced76f2 AD |
266 | /* pointer to backlight encoder */ |
267 | struct radeon_encoder *bl_encoder; | |
c93bb85b JG |
268 | }; |
269 | ||
91030880 AD |
270 | #define RADEON_MAX_BL_LEVEL 0xFF |
271 | ||
bced76f2 AD |
272 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
273 | ||
91030880 AD |
274 | struct radeon_backlight_privdata { |
275 | struct radeon_encoder *encoder; | |
276 | uint8_t negative; | |
277 | }; | |
278 | ||
279 | #endif | |
280 | ||
4ce001ab DA |
281 | #define MAX_H_CODE_TIMING_LEN 32 |
282 | #define MAX_V_CODE_TIMING_LEN 32 | |
283 | ||
284 | /* need to store these as reading | |
285 | back code tables is excessive */ | |
286 | struct radeon_tv_regs { | |
287 | uint32_t tv_uv_adr; | |
288 | uint32_t timing_cntl; | |
289 | uint32_t hrestart; | |
290 | uint32_t vrestart; | |
291 | uint32_t frestart; | |
292 | uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; | |
293 | uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; | |
294 | }; | |
295 | ||
19eca43e AD |
296 | struct radeon_atom_ss { |
297 | uint16_t percentage; | |
18f8f52b | 298 | uint16_t percentage_divider; |
19eca43e AD |
299 | uint8_t type; |
300 | uint16_t step; | |
301 | uint8_t delay; | |
302 | uint8_t range; | |
303 | uint8_t refdiv; | |
304 | /* asic_ss */ | |
305 | uint16_t rate; | |
306 | uint16_t amount; | |
307 | }; | |
308 | ||
a2b6d3b3 MD |
309 | enum radeon_flip_status { |
310 | RADEON_FLIP_NONE, | |
311 | RADEON_FLIP_PENDING, | |
312 | RADEON_FLIP_SUBMITTED | |
313 | }; | |
314 | ||
771fe6b9 JG |
315 | struct radeon_crtc { |
316 | struct drm_crtc base; | |
317 | int crtc_id; | |
318 | u16 lut_r[256], lut_g[256], lut_b[256]; | |
319 | bool enabled; | |
320 | bool can_tile; | |
321 | uint32_t crtc_offset; | |
771fe6b9 JG |
322 | struct drm_gem_object *cursor_bo; |
323 | uint64_t cursor_addr; | |
78b1a601 MD |
324 | int cursor_x; |
325 | int cursor_y; | |
326 | int cursor_hot_x; | |
327 | int cursor_hot_y; | |
771fe6b9 JG |
328 | int cursor_width; |
329 | int cursor_height; | |
9e05fa1d AD |
330 | int max_cursor_width; |
331 | int max_cursor_height; | |
4162338a | 332 | uint32_t legacy_display_base_addr; |
c836e862 | 333 | uint32_t legacy_cursor_offset; |
c93bb85b | 334 | enum radeon_rmx_type rmx_type; |
5b1714d3 AD |
335 | u8 h_border; |
336 | u8 v_border; | |
c93bb85b JG |
337 | fixed20_12 vsc; |
338 | fixed20_12 hsc; | |
de2103e4 | 339 | struct drm_display_mode native_mode; |
bcc1c2a1 | 340 | int pll_id; |
6f34be50 | 341 | /* page flipping */ |
fa7f517c CK |
342 | struct workqueue_struct *flip_queue; |
343 | struct radeon_flip_work *flip_work; | |
a2b6d3b3 | 344 | enum radeon_flip_status flip_status; |
19eca43e AD |
345 | /* pll sharing */ |
346 | struct radeon_atom_ss ss; | |
347 | bool ss_enabled; | |
348 | u32 adjusted_clock; | |
349 | int bpc; | |
350 | u32 pll_reference_div; | |
351 | u32 pll_post_div; | |
352 | u32 pll_flags; | |
5df3196b | 353 | struct drm_encoder *encoder; |
57b35e29 | 354 | struct drm_connector *connector; |
7178d2a6 AD |
355 | /* for dpm */ |
356 | u32 line_time; | |
357 | u32 wm_low; | |
358 | u32 wm_high; | |
66edc1c9 | 359 | struct drm_display_mode hw_mode; |
771fe6b9 JG |
360 | }; |
361 | ||
362 | struct radeon_encoder_primary_dac { | |
363 | /* legacy primary dac */ | |
364 | uint32_t ps2_pdac_adj; | |
365 | }; | |
366 | ||
367 | struct radeon_encoder_lvds { | |
368 | /* legacy lvds */ | |
369 | uint16_t panel_vcc_delay; | |
370 | uint8_t panel_pwr_delay; | |
371 | uint8_t panel_digon_delay; | |
372 | uint8_t panel_blon_delay; | |
373 | uint16_t panel_ref_divider; | |
374 | uint8_t panel_post_divider; | |
375 | uint16_t panel_fb_divider; | |
376 | bool use_bios_dividers; | |
377 | uint32_t lvds_gen_cntl; | |
378 | /* panel mode */ | |
de2103e4 | 379 | struct drm_display_mode native_mode; |
63ec0119 MD |
380 | struct backlight_device *bl_dev; |
381 | int dpms_mode; | |
382 | uint8_t backlight_level; | |
771fe6b9 JG |
383 | }; |
384 | ||
385 | struct radeon_encoder_tv_dac { | |
386 | /* legacy tv dac */ | |
387 | uint32_t ps2_tvdac_adj; | |
388 | uint32_t ntsc_tvdac_adj; | |
389 | uint32_t pal_tvdac_adj; | |
390 | ||
4ce001ab DA |
391 | int h_pos; |
392 | int v_pos; | |
393 | int h_size; | |
394 | int supported_tv_stds; | |
395 | bool tv_on; | |
771fe6b9 | 396 | enum radeon_tv_std tv_std; |
4ce001ab | 397 | struct radeon_tv_regs tv; |
771fe6b9 JG |
398 | }; |
399 | ||
400 | struct radeon_encoder_int_tmds { | |
401 | /* legacy int tmds */ | |
402 | struct radeon_tmds_pll tmds_pll[4]; | |
403 | }; | |
404 | ||
fcec570b AD |
405 | struct radeon_encoder_ext_tmds { |
406 | /* tmds over dvo */ | |
407 | struct radeon_i2c_chan *i2c_bus; | |
408 | uint8_t slave_addr; | |
409 | enum radeon_dvo_chip dvo_chip; | |
410 | }; | |
411 | ||
ebbe1cb9 | 412 | /* spread spectrum */ |
771fe6b9 | 413 | struct radeon_encoder_atom_dig { |
5137ee94 | 414 | bool linkb; |
771fe6b9 JG |
415 | /* atom dig */ |
416 | bool coherent_mode; | |
ba032a58 AD |
417 | int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ |
418 | /* atom lvds/edp */ | |
419 | uint32_t lcd_misc; | |
771fe6b9 | 420 | uint16_t panel_pwr_delay; |
ba032a58 | 421 | uint32_t lcd_ss_id; |
771fe6b9 | 422 | /* panel mode */ |
de2103e4 | 423 | struct drm_display_mode native_mode; |
63ec0119 MD |
424 | struct backlight_device *bl_dev; |
425 | int dpms_mode; | |
426 | uint8_t backlight_level; | |
386d4d75 | 427 | int panel_mode; |
0783986a | 428 | struct radeon_afmt *afmt; |
771fe6b9 JG |
429 | }; |
430 | ||
4ce001ab DA |
431 | struct radeon_encoder_atom_dac { |
432 | enum radeon_tv_std tv_std; | |
433 | }; | |
434 | ||
771fe6b9 JG |
435 | struct radeon_encoder { |
436 | struct drm_encoder base; | |
5137ee94 | 437 | uint32_t encoder_enum; |
771fe6b9 JG |
438 | uint32_t encoder_id; |
439 | uint32_t devices; | |
4ce001ab | 440 | uint32_t active_device; |
771fe6b9 JG |
441 | uint32_t flags; |
442 | uint32_t pixel_clock; | |
443 | enum radeon_rmx_type rmx_type; | |
5b1714d3 | 444 | enum radeon_underscan_type underscan_type; |
5bccf5e3 MG |
445 | uint32_t underscan_hborder; |
446 | uint32_t underscan_vborder; | |
de2103e4 | 447 | struct drm_display_mode native_mode; |
771fe6b9 | 448 | void *enc_priv; |
58bd0863 | 449 | int audio_polling_active; |
3e4b9982 | 450 | bool is_ext_encoder; |
36868bda | 451 | u16 caps; |
1a626b68 | 452 | struct radeon_audio_funcs *audio; |
771fe6b9 JG |
453 | }; |
454 | ||
455 | struct radeon_connector_atom_dig { | |
456 | uint32_t igp_lane_info; | |
4143e919 | 457 | /* displayport */ |
1a644cd4 | 458 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
4143e919 | 459 | u8 dp_sink_type; |
5801ead6 AD |
460 | int dp_clock; |
461 | int dp_lane_count; | |
8b834852 | 462 | bool edp_on; |
771fe6b9 JG |
463 | }; |
464 | ||
eed45b30 AD |
465 | struct radeon_gpio_rec { |
466 | bool valid; | |
467 | u8 id; | |
468 | u32 reg; | |
469 | u32 mask; | |
727b3d25 | 470 | u32 shift; |
eed45b30 AD |
471 | }; |
472 | ||
eed45b30 AD |
473 | struct radeon_hpd { |
474 | enum radeon_hpd_id hpd; | |
475 | u8 plugged_state; | |
476 | struct radeon_gpio_rec gpio; | |
477 | }; | |
478 | ||
26b5bc98 | 479 | struct radeon_router { |
26b5bc98 AD |
480 | u32 router_id; |
481 | struct radeon_i2c_bus_rec i2c_info; | |
482 | u8 i2c_addr; | |
fb939dfc AD |
483 | /* i2c mux */ |
484 | bool ddc_valid; | |
485 | u8 ddc_mux_type; | |
486 | u8 ddc_mux_control_pin; | |
487 | u8 ddc_mux_state; | |
488 | /* clock/data mux */ | |
489 | bool cd_valid; | |
490 | u8 cd_mux_type; | |
491 | u8 cd_mux_control_pin; | |
492 | u8 cd_mux_state; | |
26b5bc98 AD |
493 | }; |
494 | ||
8666c076 AD |
495 | enum radeon_connector_audio { |
496 | RADEON_AUDIO_DISABLE = 0, | |
497 | RADEON_AUDIO_ENABLE = 1, | |
498 | RADEON_AUDIO_AUTO = 2 | |
499 | }; | |
500 | ||
6214bb74 AD |
501 | enum radeon_connector_dither { |
502 | RADEON_FMT_DITHER_DISABLE = 0, | |
503 | RADEON_FMT_DITHER_ENABLE = 1, | |
504 | }; | |
505 | ||
771fe6b9 JG |
506 | struct radeon_connector { |
507 | struct drm_connector base; | |
508 | uint32_t connector_id; | |
509 | uint32_t devices; | |
510 | struct radeon_i2c_chan *ddc_bus; | |
5b1714d3 | 511 | /* some systems have an hdmi and vga port with a shared ddc line */ |
0294cf4f | 512 | bool shared_ddc; |
4ce001ab DA |
513 | bool use_digital; |
514 | /* we need to mind the EDID between detect | |
515 | and get modes due to analog/digital/tvencoder */ | |
516 | struct edid *edid; | |
771fe6b9 | 517 | void *con_priv; |
445282db | 518 | bool dac_load_detect; |
d0d0a225 | 519 | bool detected_by_load; /* if the connection status was determined by load */ |
b75fad06 | 520 | uint16_t connector_object_id; |
eed45b30 | 521 | struct radeon_hpd hpd; |
26b5bc98 AD |
522 | struct radeon_router router; |
523 | struct radeon_i2c_chan *router_bus; | |
8666c076 | 524 | enum radeon_connector_audio audio; |
6214bb74 | 525 | enum radeon_connector_dither dither; |
ea292861 | 526 | int pixelclock_for_modeset; |
771fe6b9 JG |
527 | }; |
528 | ||
529 | struct radeon_framebuffer { | |
530 | struct drm_framebuffer base; | |
531 | struct drm_gem_object *obj; | |
532 | }; | |
533 | ||
996d5c59 AD |
534 | #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ |
535 | ((em) == ATOM_ENCODER_MODE_DP_MST)) | |
6383cf7d | 536 | |
7062ab67 CK |
537 | struct atom_clock_dividers { |
538 | u32 post_div; | |
539 | union { | |
540 | struct { | |
541 | #ifdef __BIG_ENDIAN | |
542 | u32 reserved : 6; | |
543 | u32 whole_fb_div : 12; | |
544 | u32 frac_fb_div : 14; | |
545 | #else | |
546 | u32 frac_fb_div : 14; | |
547 | u32 whole_fb_div : 12; | |
548 | u32 reserved : 6; | |
549 | #endif | |
550 | }; | |
551 | u32 fb_div; | |
552 | }; | |
553 | u32 ref_div; | |
554 | bool enable_post_div; | |
555 | bool enable_dithen; | |
556 | u32 vco_mode; | |
557 | u32 real_clock; | |
9219ed65 AD |
558 | /* added for CI */ |
559 | u32 post_divider; | |
560 | u32 flags; | |
7062ab67 CK |
561 | }; |
562 | ||
eaa778af AD |
563 | struct atom_mpll_param { |
564 | union { | |
565 | struct { | |
566 | #ifdef __BIG_ENDIAN | |
567 | u32 reserved : 8; | |
568 | u32 clkfrac : 12; | |
569 | u32 clkf : 12; | |
570 | #else | |
571 | u32 clkf : 12; | |
572 | u32 clkfrac : 12; | |
573 | u32 reserved : 8; | |
574 | #endif | |
575 | }; | |
576 | u32 fb_div; | |
577 | }; | |
578 | u32 post_div; | |
579 | u32 bwcntl; | |
580 | u32 dll_speed; | |
581 | u32 vco_mode; | |
582 | u32 yclk_sel; | |
583 | u32 qdr; | |
584 | u32 half_rate; | |
585 | }; | |
586 | ||
ae5b0abb AD |
587 | #define MEM_TYPE_GDDR5 0x50 |
588 | #define MEM_TYPE_GDDR4 0x40 | |
589 | #define MEM_TYPE_GDDR3 0x30 | |
590 | #define MEM_TYPE_DDR2 0x20 | |
591 | #define MEM_TYPE_GDDR1 0x10 | |
592 | #define MEM_TYPE_DDR3 0xb0 | |
593 | #define MEM_TYPE_MASK 0xf0 | |
594 | ||
595 | struct atom_memory_info { | |
596 | u8 mem_vendor; | |
597 | u8 mem_type; | |
598 | }; | |
599 | ||
600 | #define MAX_AC_TIMING_ENTRIES 16 | |
601 | ||
602 | struct atom_memory_clock_range_table | |
603 | { | |
604 | u8 num_entries; | |
605 | u8 rsv[3]; | |
606 | u32 mclk[MAX_AC_TIMING_ENTRIES]; | |
607 | }; | |
608 | ||
609 | #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 | |
610 | #define VBIOS_MAX_AC_TIMING_ENTRIES 20 | |
611 | ||
612 | struct atom_mc_reg_entry { | |
613 | u32 mclk_max; | |
614 | u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; | |
615 | }; | |
616 | ||
617 | struct atom_mc_register_address { | |
618 | u16 s1; | |
619 | u8 pre_reg_data; | |
620 | }; | |
621 | ||
622 | struct atom_mc_reg_table { | |
623 | u8 last; | |
624 | u8 num_entries; | |
625 | struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; | |
626 | struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; | |
627 | }; | |
628 | ||
629 | #define MAX_VOLTAGE_ENTRIES 32 | |
630 | ||
631 | struct atom_voltage_table_entry | |
632 | { | |
633 | u16 value; | |
634 | u32 smio_low; | |
635 | }; | |
636 | ||
637 | struct atom_voltage_table | |
638 | { | |
639 | u32 count; | |
640 | u32 mask_low; | |
65171944 | 641 | u32 phase_delay; |
ae5b0abb AD |
642 | struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; |
643 | }; | |
644 | ||
a38eab52 RK |
645 | |
646 | extern void | |
647 | radeon_add_atom_connector(struct drm_device *dev, | |
648 | uint32_t connector_id, | |
649 | uint32_t supported_device, | |
650 | int connector_type, | |
651 | struct radeon_i2c_bus_rec *i2c_bus, | |
652 | uint32_t igp_lane_info, | |
653 | uint16_t connector_object_id, | |
654 | struct radeon_hpd *hpd, | |
655 | struct radeon_router *router); | |
656 | extern void | |
657 | radeon_add_legacy_connector(struct drm_device *dev, | |
658 | uint32_t connector_id, | |
659 | uint32_t supported_device, | |
660 | int connector_type, | |
661 | struct radeon_i2c_bus_rec *i2c_bus, | |
662 | uint16_t connector_object_id, | |
663 | struct radeon_hpd *hpd); | |
0091fc13 RK |
664 | extern uint32_t |
665 | radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, | |
666 | uint8_t dac); | |
667 | extern void radeon_link_encoder_connector(struct drm_device *dev); | |
a38eab52 | 668 | |
d79766fa AD |
669 | extern enum radeon_tv_std |
670 | radeon_combios_get_tv_info(struct radeon_device *rdev); | |
671 | extern enum radeon_tv_std | |
672 | radeon_atombios_get_tv_info(struct radeon_device *rdev); | |
4a6369e9 | 673 | extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, |
2abba66e | 674 | u16 *vddc, u16 *vddci, u16 *mvdd); |
d79766fa | 675 | |
84ac68e0 AD |
676 | extern void |
677 | radeon_combios_connected_scratch_regs(struct drm_connector *connector, | |
678 | struct drm_encoder *encoder, | |
679 | bool connected); | |
680 | extern void | |
681 | radeon_atombios_connected_scratch_regs(struct drm_connector *connector, | |
682 | struct drm_encoder *encoder, | |
683 | bool connected); | |
684 | ||
5b1714d3 AD |
685 | extern struct drm_connector * |
686 | radeon_get_connector_for_encoder(struct drm_encoder *encoder); | |
9aa59993 AD |
687 | extern struct drm_connector * |
688 | radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); | |
689 | extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, | |
690 | u32 pixel_clock); | |
5b1714d3 | 691 | |
1d33e1fc AD |
692 | extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); |
693 | extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); | |
d7fa8bb3 | 694 | extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); |
eccea792 | 695 | extern int radeon_get_monitor_bpc(struct drm_connector *connector); |
d7fa8bb3 | 696 | |
377bd8a9 AD |
697 | extern struct edid *radeon_connector_edid(struct drm_connector *connector); |
698 | ||
d4877cf2 | 699 | extern void radeon_connector_hotplug(struct drm_connector *connector); |
224d94b1 | 700 | extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
5801ead6 AD |
701 | struct drm_display_mode *mode); |
702 | extern void radeon_dp_set_link_config(struct drm_connector *connector, | |
e811f5ae | 703 | const struct drm_display_mode *mode); |
224d94b1 AD |
704 | extern void radeon_dp_link_train(struct drm_encoder *encoder, |
705 | struct drm_connector *connector); | |
d5811e87 | 706 | extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); |
4143e919 | 707 | extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); |
9fa05c98 | 708 | extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); |
386d4d75 AD |
709 | extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
710 | struct drm_connector *connector); | |
2953da15 AD |
711 | extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, |
712 | u8 power_state); | |
496263bf | 713 | extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); |
558e27db | 714 | extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); |
ac89af1e | 715 | extern void radeon_atom_encoder_init(struct radeon_device *rdev); |
f3f1f03e | 716 | extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); |
5801ead6 AD |
717 | extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, |
718 | int action, uint8_t lane_num, | |
719 | uint8_t lane_set); | |
591a10e1 | 720 | extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); |
3f03ced8 | 721 | extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); |
4cf3b494 | 722 | void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); |
746c1aa4 | 723 | |
f376b94f AD |
724 | extern void radeon_i2c_init(struct radeon_device *rdev); |
725 | extern void radeon_i2c_fini(struct radeon_device *rdev); | |
726 | extern void radeon_combios_i2c_init(struct radeon_device *rdev); | |
727 | extern void radeon_atombios_i2c_init(struct radeon_device *rdev); | |
728 | extern void radeon_i2c_add(struct radeon_device *rdev, | |
729 | struct radeon_i2c_bus_rec *rec, | |
730 | const char *name); | |
731 | extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, | |
732 | struct radeon_i2c_bus_rec *i2c_bus); | |
771fe6b9 JG |
733 | extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
734 | struct radeon_i2c_bus_rec *rec, | |
735 | const char *name); | |
736 | extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); | |
5a6f98f5 AD |
737 | extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, |
738 | u8 slave_addr, | |
739 | u8 addr, | |
740 | u8 *val); | |
741 | extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, | |
742 | u8 slave_addr, | |
743 | u8 addr, | |
744 | u8 val); | |
fb939dfc AD |
745 | extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); |
746 | extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); | |
0a9069d3 | 747 | extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); |
771fe6b9 | 748 | |
ba032a58 AD |
749 | extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, |
750 | struct radeon_atom_ss *ss, | |
751 | int id); | |
752 | extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, | |
753 | struct radeon_atom_ss *ss, | |
754 | int id, u32 clock); | |
09e619c0 AD |
755 | extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, |
756 | u8 id); | |
ba032a58 | 757 | |
f523f74e AD |
758 | extern void radeon_compute_pll_legacy(struct radeon_pll *pll, |
759 | uint64_t freq, | |
760 | uint32_t *dot_clock_p, | |
761 | uint32_t *fb_div_p, | |
762 | uint32_t *frac_fb_div_p, | |
763 | uint32_t *ref_div_p, | |
764 | uint32_t *post_div_p); | |
765 | ||
766 | extern void radeon_compute_pll_avivo(struct radeon_pll *pll, | |
767 | u32 freq, | |
768 | u32 *dot_clock_p, | |
769 | u32 *fb_div_p, | |
770 | u32 *frac_fb_div_p, | |
771 | u32 *ref_div_p, | |
772 | u32 *post_div_p); | |
771fe6b9 | 773 | |
1f3b6a45 DA |
774 | extern void radeon_setup_encoder_clones(struct drm_device *dev); |
775 | ||
771fe6b9 JG |
776 | struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); |
777 | struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); | |
778 | struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); | |
779 | struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); | |
780 | struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); | |
99999aaa | 781 | extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); |
32f48ffe | 782 | extern void atombios_digital_setup(struct drm_encoder *encoder, int action); |
771fe6b9 | 783 | extern int atombios_get_encoder_mode(struct drm_encoder *encoder); |
2dafb74d | 784 | extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); |
4ce001ab | 785 | extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); |
d740a933 | 786 | extern bool radeon_encoder_is_digital(struct drm_encoder *encoder); |
771fe6b9 JG |
787 | |
788 | extern void radeon_crtc_load_lut(struct drm_crtc *crtc); | |
789 | extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |
790 | struct drm_framebuffer *old_fb); | |
4dd19b0d CB |
791 | extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, |
792 | struct drm_framebuffer *fb, | |
21c74a8e JW |
793 | int x, int y, |
794 | enum mode_set_atomic state); | |
771fe6b9 JG |
795 | extern int atombios_crtc_mode_set(struct drm_crtc *crtc, |
796 | struct drm_display_mode *mode, | |
797 | struct drm_display_mode *adjusted_mode, | |
798 | int x, int y, | |
799 | struct drm_framebuffer *old_fb); | |
800 | extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); | |
801 | ||
802 | extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |
803 | struct drm_framebuffer *old_fb); | |
4dd19b0d CB |
804 | extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, |
805 | struct drm_framebuffer *fb, | |
21c74a8e JW |
806 | int x, int y, |
807 | enum mode_set_atomic state); | |
4dd19b0d CB |
808 | extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, |
809 | struct drm_framebuffer *fb, | |
810 | int x, int y, int atomic); | |
78b1a601 MD |
811 | extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc, |
812 | struct drm_file *file_priv, | |
813 | uint32_t handle, | |
814 | uint32_t width, | |
815 | uint32_t height, | |
816 | int32_t hot_x, | |
817 | int32_t hot_y); | |
771fe6b9 JG |
818 | extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, |
819 | int x, int y); | |
6d3759fa | 820 | extern void radeon_cursor_reset(struct drm_crtc *crtc); |
771fe6b9 | 821 | |
f5a80209 | 822 | extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, |
abca9e45 | 823 | unsigned int flags, |
d47abc58 MK |
824 | int *vpos, int *hpos, ktime_t *stime, |
825 | ktime_t *etime); | |
6383cf7d | 826 | |
3c537889 AD |
827 | extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); |
828 | extern struct edid * | |
c324acd5 | 829 | radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); |
771fe6b9 JG |
830 | extern bool radeon_atom_get_clock_info(struct drm_device *dev); |
831 | extern bool radeon_combios_get_clock_info(struct drm_device *dev); | |
832 | extern struct radeon_encoder_atom_dig * | |
833 | radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); | |
fcec570b AD |
834 | extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
835 | struct radeon_encoder_int_tmds *tmds); | |
836 | extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, | |
837 | struct radeon_encoder_int_tmds *tmds); | |
838 | extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, | |
839 | struct radeon_encoder_int_tmds *tmds); | |
840 | extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, | |
841 | struct radeon_encoder_ext_tmds *tmds); | |
842 | extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, | |
843 | struct radeon_encoder_ext_tmds *tmds); | |
6fe7ac3f AD |
844 | extern struct radeon_encoder_primary_dac * |
845 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); | |
846 | extern struct radeon_encoder_tv_dac * | |
847 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); | |
771fe6b9 JG |
848 | extern struct radeon_encoder_lvds * |
849 | radeon_combios_get_lvds_info(struct radeon_encoder *encoder); | |
771fe6b9 JG |
850 | extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); |
851 | extern struct radeon_encoder_tv_dac * | |
852 | radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); | |
853 | extern struct radeon_encoder_primary_dac * | |
854 | radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); | |
fcec570b AD |
855 | extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); |
856 | extern void radeon_external_tmds_setup(struct drm_encoder *encoder); | |
771fe6b9 JG |
857 | extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); |
858 | extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); | |
859 | extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); | |
860 | extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); | |
f657c2a7 YZ |
861 | extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); |
862 | extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); | |
771fe6b9 JG |
863 | extern void |
864 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); | |
865 | extern void | |
866 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); | |
867 | extern void | |
868 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); | |
869 | extern void | |
870 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); | |
871 | extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
872 | u16 blue, int regno); | |
b8c00ac5 DA |
873 | extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
874 | u16 *blue, int regno); | |
aaefcd42 | 875 | int radeon_framebuffer_init(struct drm_device *dev, |
38651674 | 876 | struct radeon_framebuffer *rfb, |
308e5bcb | 877 | struct drm_mode_fb_cmd2 *mode_cmd, |
38651674 | 878 | struct drm_gem_object *obj); |
771fe6b9 JG |
879 | |
880 | int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); | |
881 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); | |
882 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); | |
883 | void radeon_atombios_init_crtc(struct drm_device *dev, | |
884 | struct radeon_crtc *radeon_crtc); | |
885 | void radeon_legacy_init_crtc(struct drm_device *dev, | |
886 | struct radeon_crtc *radeon_crtc); | |
771fe6b9 JG |
887 | |
888 | void radeon_get_clock_info(struct drm_device *dev); | |
889 | ||
890 | extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); | |
891 | extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); | |
892 | ||
771fe6b9 JG |
893 | void radeon_enc_destroy(struct drm_encoder *encoder); |
894 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); | |
895 | void radeon_combios_asic_init(struct drm_device *dev); | |
c93bb85b | 896 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
e811f5ae | 897 | const struct drm_display_mode *mode, |
c93bb85b | 898 | struct drm_display_mode *adjusted_mode); |
3515387b AD |
899 | void radeon_panel_mode_fixup(struct drm_encoder *encoder, |
900 | struct drm_display_mode *adjusted_mode); | |
4ce001ab DA |
901 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); |
902 | ||
903 | /* legacy tv */ | |
904 | void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, | |
905 | uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, | |
906 | uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); | |
907 | void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, | |
908 | uint32_t *htotal_cntl, uint32_t *ppll_ref_div, | |
909 | uint32_t *ppll_div_3, uint32_t *pixclks_cntl); | |
910 | void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, | |
911 | uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, | |
912 | uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); | |
913 | void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, | |
914 | struct drm_display_mode *mode, | |
915 | struct drm_display_mode *adjusted_mode); | |
38651674 | 916 | |
134b480f AD |
917 | /* fmt blocks */ |
918 | void avivo_program_fmt(struct drm_encoder *encoder); | |
919 | void dce3_program_fmt(struct drm_encoder *encoder); | |
920 | void dce4_program_fmt(struct drm_encoder *encoder); | |
921 | void dce8_program_fmt(struct drm_encoder *encoder); | |
922 | ||
38651674 DA |
923 | /* fbdev layer */ |
924 | int radeon_fbdev_init(struct radeon_device *rdev); | |
925 | void radeon_fbdev_fini(struct radeon_device *rdev); | |
926 | void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); | |
38651674 | 927 | bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); |
eb1f8e4f DA |
928 | |
929 | void radeon_fb_output_poll_changed(struct radeon_device *rdev); | |
6f34be50 | 930 | |
1a0e7918 | 931 | void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); |
6f34be50 AD |
932 | void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); |
933 | ||
ff72145b | 934 | int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); |
771fe6b9 | 935 | #endif |