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Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and | |
3 | * VA Linux Systems Inc., Fremont, California. | |
4 | * Copyright 2008 Red Hat Inc. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Original Authors: | |
25 | * Kevin E. Martin, Rickard E. Faith, Alan Hourihane | |
26 | * | |
27 | * Kernel port Author: Dave Airlie | |
28 | */ | |
29 | ||
30 | #ifndef RADEON_MODE_H | |
31 | #define RADEON_MODE_H | |
32 | ||
760285e7 DH |
33 | #include <drm/drm_crtc.h> |
34 | #include <drm/drm_edid.h> | |
35 | #include <drm/drm_dp_helper.h> | |
36 | #include <drm/drm_fixed.h> | |
37 | #include <drm/drm_crtc_helper.h> | |
771fe6b9 | 38 | #include <linux/i2c.h> |
771fe6b9 | 39 | #include <linux/i2c-algo-bit.h> |
c93bb85b | 40 | |
38651674 | 41 | struct radeon_bo; |
c93bb85b | 42 | struct radeon_device; |
771fe6b9 JG |
43 | |
44 | #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) | |
45 | #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) | |
46 | #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) | |
47 | #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) | |
48 | ||
771fe6b9 JG |
49 | enum radeon_rmx_type { |
50 | RMX_OFF, | |
51 | RMX_FULL, | |
52 | RMX_CENTER, | |
53 | RMX_ASPECT | |
54 | }; | |
55 | ||
56 | enum radeon_tv_std { | |
57 | TV_STD_NTSC, | |
58 | TV_STD_PAL, | |
59 | TV_STD_PAL_M, | |
60 | TV_STD_PAL_60, | |
61 | TV_STD_NTSC_J, | |
62 | TV_STD_SCART_PAL, | |
63 | TV_STD_SECAM, | |
64 | TV_STD_PAL_CN, | |
d79766fa | 65 | TV_STD_PAL_N, |
771fe6b9 JG |
66 | }; |
67 | ||
5b1714d3 AD |
68 | enum radeon_underscan_type { |
69 | UNDERSCAN_OFF, | |
70 | UNDERSCAN_ON, | |
71 | UNDERSCAN_AUTO, | |
72 | }; | |
73 | ||
8e36ed00 AD |
74 | enum radeon_hpd_id { |
75 | RADEON_HPD_1 = 0, | |
76 | RADEON_HPD_2, | |
77 | RADEON_HPD_3, | |
78 | RADEON_HPD_4, | |
79 | RADEON_HPD_5, | |
80 | RADEON_HPD_6, | |
81 | RADEON_HPD_NONE = 0xff, | |
82 | }; | |
83 | ||
f376b94f AD |
84 | #define RADEON_MAX_I2C_BUS 16 |
85 | ||
9b9fe724 AD |
86 | /* radeon gpio-based i2c |
87 | * 1. "mask" reg and bits | |
88 | * grabs the gpio pins for software use | |
89 | * 0=not held 1=held | |
90 | * 2. "a" reg and bits | |
91 | * output pin value | |
92 | * 0=low 1=high | |
93 | * 3. "en" reg and bits | |
94 | * sets the pin direction | |
95 | * 0=input 1=output | |
96 | * 4. "y" reg and bits | |
97 | * input pin value | |
98 | * 0=low 1=high | |
99 | */ | |
771fe6b9 JG |
100 | struct radeon_i2c_bus_rec { |
101 | bool valid; | |
6a93cb25 AD |
102 | /* id used by atom */ |
103 | uint8_t i2c_id; | |
bcc1c2a1 | 104 | /* id used by atom */ |
8e36ed00 | 105 | enum radeon_hpd_id hpd; |
6a93cb25 AD |
106 | /* can be used with hw i2c engine */ |
107 | bool hw_capable; | |
108 | /* uses multi-media i2c engine */ | |
109 | bool mm_i2c; | |
110 | /* regs and bits */ | |
771fe6b9 JG |
111 | uint32_t mask_clk_reg; |
112 | uint32_t mask_data_reg; | |
113 | uint32_t a_clk_reg; | |
114 | uint32_t a_data_reg; | |
9b9fe724 AD |
115 | uint32_t en_clk_reg; |
116 | uint32_t en_data_reg; | |
117 | uint32_t y_clk_reg; | |
118 | uint32_t y_data_reg; | |
771fe6b9 JG |
119 | uint32_t mask_clk_mask; |
120 | uint32_t mask_data_mask; | |
771fe6b9 JG |
121 | uint32_t a_clk_mask; |
122 | uint32_t a_data_mask; | |
9b9fe724 AD |
123 | uint32_t en_clk_mask; |
124 | uint32_t en_data_mask; | |
125 | uint32_t y_clk_mask; | |
126 | uint32_t y_data_mask; | |
771fe6b9 JG |
127 | }; |
128 | ||
129 | struct radeon_tmds_pll { | |
130 | uint32_t freq; | |
131 | uint32_t value; | |
132 | }; | |
133 | ||
134 | #define RADEON_MAX_BIOS_CONNECTOR 16 | |
135 | ||
7c27f87d | 136 | /* pll flags */ |
771fe6b9 JG |
137 | #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) |
138 | #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) | |
139 | #define RADEON_PLL_USE_REF_DIV (1 << 2) | |
140 | #define RADEON_PLL_LEGACY (1 << 3) | |
141 | #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) | |
142 | #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) | |
143 | #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) | |
144 | #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) | |
145 | #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) | |
146 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) | |
147 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) | |
d0e275a9 | 148 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
fc10332b | 149 | #define RADEON_PLL_USE_POST_DIV (1 << 12) |
86cb2bbf | 150 | #define RADEON_PLL_IS_LCD (1 << 13) |
f523f74e | 151 | #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) |
771fe6b9 JG |
152 | |
153 | struct radeon_pll { | |
fc10332b AD |
154 | /* reference frequency */ |
155 | uint32_t reference_freq; | |
156 | ||
157 | /* fixed dividers */ | |
158 | uint32_t reference_div; | |
159 | uint32_t post_div; | |
160 | ||
161 | /* pll in/out limits */ | |
771fe6b9 JG |
162 | uint32_t pll_in_min; |
163 | uint32_t pll_in_max; | |
164 | uint32_t pll_out_min; | |
165 | uint32_t pll_out_max; | |
86cb2bbf AD |
166 | uint32_t lcd_pll_out_min; |
167 | uint32_t lcd_pll_out_max; | |
fc10332b | 168 | uint32_t best_vco; |
771fe6b9 | 169 | |
fc10332b | 170 | /* divider limits */ |
771fe6b9 JG |
171 | uint32_t min_ref_div; |
172 | uint32_t max_ref_div; | |
173 | uint32_t min_post_div; | |
174 | uint32_t max_post_div; | |
175 | uint32_t min_feedback_div; | |
176 | uint32_t max_feedback_div; | |
177 | uint32_t min_frac_feedback_div; | |
178 | uint32_t max_frac_feedback_div; | |
fc10332b AD |
179 | |
180 | /* flags for the current clock */ | |
181 | uint32_t flags; | |
182 | ||
183 | /* pll id */ | |
184 | uint32_t id; | |
771fe6b9 JG |
185 | }; |
186 | ||
187 | struct radeon_i2c_chan { | |
771fe6b9 | 188 | struct i2c_adapter adapter; |
746c1aa4 DA |
189 | struct drm_device *dev; |
190 | union { | |
ac1aade6 | 191 | struct i2c_algo_bit_data bit; |
746c1aa4 | 192 | struct i2c_algo_dp_aux_data dp; |
746c1aa4 | 193 | } algo; |
771fe6b9 JG |
194 | struct radeon_i2c_bus_rec rec; |
195 | }; | |
196 | ||
197 | /* mostly for macs, but really any system without connector tables */ | |
198 | enum radeon_connector_table { | |
aa74fbb4 | 199 | CT_NONE = 0, |
771fe6b9 JG |
200 | CT_GENERIC, |
201 | CT_IBOOK, | |
202 | CT_POWERBOOK_EXTERNAL, | |
203 | CT_POWERBOOK_INTERNAL, | |
204 | CT_POWERBOOK_VGA, | |
205 | CT_MINI_EXTERNAL, | |
206 | CT_MINI_INTERNAL, | |
207 | CT_IMAC_G5_ISIGHT, | |
208 | CT_EMAC, | |
76a7142a | 209 | CT_RN50_POWER, |
aa74fbb4 | 210 | CT_MAC_X800, |
9fad321a | 211 | CT_MAC_G5_9600, |
cafa59b9 AD |
212 | CT_SAM440EP, |
213 | CT_MAC_G4_SILVER | |
771fe6b9 JG |
214 | }; |
215 | ||
fcec570b AD |
216 | enum radeon_dvo_chip { |
217 | DVO_SIL164, | |
218 | DVO_SIL1178, | |
219 | }; | |
220 | ||
8be48d92 | 221 | struct radeon_fbdev; |
38651674 | 222 | |
0783986a AD |
223 | struct radeon_afmt { |
224 | bool enabled; | |
225 | int offset; | |
226 | bool last_buffer_filled_status; | |
227 | int id; | |
b530602f | 228 | struct r600_audio_pin *pin; |
0783986a AD |
229 | }; |
230 | ||
771fe6b9 JG |
231 | struct radeon_mode_info { |
232 | struct atom_context *atom_context; | |
61c4b24b | 233 | struct card_info *atom_card_info; |
771fe6b9 JG |
234 | enum radeon_connector_table connector_table; |
235 | bool mode_config_initialized; | |
bcc1c2a1 | 236 | struct radeon_crtc *crtcs[6]; |
b530602f | 237 | struct radeon_afmt *afmt[7]; |
445282db DA |
238 | /* DVI-I properties */ |
239 | struct drm_property *coherent_mode_property; | |
240 | /* DAC enable load detect */ | |
241 | struct drm_property *load_detect_property; | |
5b1714d3 | 242 | /* TV standard */ |
445282db DA |
243 | struct drm_property *tv_std_property; |
244 | /* legacy TMDS PLL detect */ | |
245 | struct drm_property *tmds_pll_property; | |
5b1714d3 AD |
246 | /* underscan */ |
247 | struct drm_property *underscan_property; | |
5bccf5e3 MG |
248 | struct drm_property *underscan_hborder_property; |
249 | struct drm_property *underscan_vborder_property; | |
8666c076 AD |
250 | /* audio */ |
251 | struct drm_property *audio_property; | |
6214bb74 AD |
252 | /* FMT dithering */ |
253 | struct drm_property *dither_property; | |
3c537889 AD |
254 | /* hardcoded DFP edid from BIOS */ |
255 | struct edid *bios_hardcoded_edid; | |
fafcf94e | 256 | int bios_hardcoded_edid_size; |
38651674 DA |
257 | |
258 | /* pointer to fbdev info structure */ | |
8be48d92 | 259 | struct radeon_fbdev *rfbdev; |
af7912e5 AD |
260 | /* firmware flags */ |
261 | u16 firmware_flags; | |
bced76f2 AD |
262 | /* pointer to backlight encoder */ |
263 | struct radeon_encoder *bl_encoder; | |
c93bb85b JG |
264 | }; |
265 | ||
91030880 AD |
266 | #define RADEON_MAX_BL_LEVEL 0xFF |
267 | ||
bced76f2 AD |
268 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
269 | ||
91030880 AD |
270 | struct radeon_backlight_privdata { |
271 | struct radeon_encoder *encoder; | |
272 | uint8_t negative; | |
273 | }; | |
274 | ||
275 | #endif | |
276 | ||
4ce001ab DA |
277 | #define MAX_H_CODE_TIMING_LEN 32 |
278 | #define MAX_V_CODE_TIMING_LEN 32 | |
279 | ||
280 | /* need to store these as reading | |
281 | back code tables is excessive */ | |
282 | struct radeon_tv_regs { | |
283 | uint32_t tv_uv_adr; | |
284 | uint32_t timing_cntl; | |
285 | uint32_t hrestart; | |
286 | uint32_t vrestart; | |
287 | uint32_t frestart; | |
288 | uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; | |
289 | uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; | |
290 | }; | |
291 | ||
19eca43e AD |
292 | struct radeon_atom_ss { |
293 | uint16_t percentage; | |
294 | uint8_t type; | |
295 | uint16_t step; | |
296 | uint8_t delay; | |
297 | uint8_t range; | |
298 | uint8_t refdiv; | |
299 | /* asic_ss */ | |
300 | uint16_t rate; | |
301 | uint16_t amount; | |
302 | }; | |
303 | ||
771fe6b9 JG |
304 | struct radeon_crtc { |
305 | struct drm_crtc base; | |
306 | int crtc_id; | |
307 | u16 lut_r[256], lut_g[256], lut_b[256]; | |
308 | bool enabled; | |
309 | bool can_tile; | |
310 | uint32_t crtc_offset; | |
771fe6b9 JG |
311 | struct drm_gem_object *cursor_bo; |
312 | uint64_t cursor_addr; | |
313 | int cursor_width; | |
314 | int cursor_height; | |
9e05fa1d AD |
315 | int max_cursor_width; |
316 | int max_cursor_height; | |
4162338a | 317 | uint32_t legacy_display_base_addr; |
c836e862 | 318 | uint32_t legacy_cursor_offset; |
c93bb85b | 319 | enum radeon_rmx_type rmx_type; |
5b1714d3 AD |
320 | u8 h_border; |
321 | u8 v_border; | |
c93bb85b JG |
322 | fixed20_12 vsc; |
323 | fixed20_12 hsc; | |
de2103e4 | 324 | struct drm_display_mode native_mode; |
bcc1c2a1 | 325 | int pll_id; |
6f34be50 AD |
326 | /* page flipping */ |
327 | struct radeon_unpin_work *unpin_work; | |
328 | int deferred_flip_completion; | |
19eca43e AD |
329 | /* pll sharing */ |
330 | struct radeon_atom_ss ss; | |
331 | bool ss_enabled; | |
332 | u32 adjusted_clock; | |
333 | int bpc; | |
334 | u32 pll_reference_div; | |
335 | u32 pll_post_div; | |
336 | u32 pll_flags; | |
5df3196b | 337 | struct drm_encoder *encoder; |
57b35e29 | 338 | struct drm_connector *connector; |
7178d2a6 AD |
339 | /* for dpm */ |
340 | u32 line_time; | |
341 | u32 wm_low; | |
342 | u32 wm_high; | |
66edc1c9 | 343 | struct drm_display_mode hw_mode; |
771fe6b9 JG |
344 | }; |
345 | ||
346 | struct radeon_encoder_primary_dac { | |
347 | /* legacy primary dac */ | |
348 | uint32_t ps2_pdac_adj; | |
349 | }; | |
350 | ||
351 | struct radeon_encoder_lvds { | |
352 | /* legacy lvds */ | |
353 | uint16_t panel_vcc_delay; | |
354 | uint8_t panel_pwr_delay; | |
355 | uint8_t panel_digon_delay; | |
356 | uint8_t panel_blon_delay; | |
357 | uint16_t panel_ref_divider; | |
358 | uint8_t panel_post_divider; | |
359 | uint16_t panel_fb_divider; | |
360 | bool use_bios_dividers; | |
361 | uint32_t lvds_gen_cntl; | |
362 | /* panel mode */ | |
de2103e4 | 363 | struct drm_display_mode native_mode; |
63ec0119 MD |
364 | struct backlight_device *bl_dev; |
365 | int dpms_mode; | |
366 | uint8_t backlight_level; | |
771fe6b9 JG |
367 | }; |
368 | ||
369 | struct radeon_encoder_tv_dac { | |
370 | /* legacy tv dac */ | |
371 | uint32_t ps2_tvdac_adj; | |
372 | uint32_t ntsc_tvdac_adj; | |
373 | uint32_t pal_tvdac_adj; | |
374 | ||
4ce001ab DA |
375 | int h_pos; |
376 | int v_pos; | |
377 | int h_size; | |
378 | int supported_tv_stds; | |
379 | bool tv_on; | |
771fe6b9 | 380 | enum radeon_tv_std tv_std; |
4ce001ab | 381 | struct radeon_tv_regs tv; |
771fe6b9 JG |
382 | }; |
383 | ||
384 | struct radeon_encoder_int_tmds { | |
385 | /* legacy int tmds */ | |
386 | struct radeon_tmds_pll tmds_pll[4]; | |
387 | }; | |
388 | ||
fcec570b AD |
389 | struct radeon_encoder_ext_tmds { |
390 | /* tmds over dvo */ | |
391 | struct radeon_i2c_chan *i2c_bus; | |
392 | uint8_t slave_addr; | |
393 | enum radeon_dvo_chip dvo_chip; | |
394 | }; | |
395 | ||
ebbe1cb9 | 396 | /* spread spectrum */ |
771fe6b9 | 397 | struct radeon_encoder_atom_dig { |
5137ee94 | 398 | bool linkb; |
771fe6b9 JG |
399 | /* atom dig */ |
400 | bool coherent_mode; | |
ba032a58 AD |
401 | int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ |
402 | /* atom lvds/edp */ | |
403 | uint32_t lcd_misc; | |
771fe6b9 | 404 | uint16_t panel_pwr_delay; |
ba032a58 | 405 | uint32_t lcd_ss_id; |
771fe6b9 | 406 | /* panel mode */ |
de2103e4 | 407 | struct drm_display_mode native_mode; |
63ec0119 MD |
408 | struct backlight_device *bl_dev; |
409 | int dpms_mode; | |
410 | uint8_t backlight_level; | |
386d4d75 | 411 | int panel_mode; |
0783986a | 412 | struct radeon_afmt *afmt; |
771fe6b9 JG |
413 | }; |
414 | ||
4ce001ab DA |
415 | struct radeon_encoder_atom_dac { |
416 | enum radeon_tv_std tv_std; | |
417 | }; | |
418 | ||
771fe6b9 JG |
419 | struct radeon_encoder { |
420 | struct drm_encoder base; | |
5137ee94 | 421 | uint32_t encoder_enum; |
771fe6b9 JG |
422 | uint32_t encoder_id; |
423 | uint32_t devices; | |
4ce001ab | 424 | uint32_t active_device; |
771fe6b9 JG |
425 | uint32_t flags; |
426 | uint32_t pixel_clock; | |
427 | enum radeon_rmx_type rmx_type; | |
5b1714d3 | 428 | enum radeon_underscan_type underscan_type; |
5bccf5e3 MG |
429 | uint32_t underscan_hborder; |
430 | uint32_t underscan_vborder; | |
de2103e4 | 431 | struct drm_display_mode native_mode; |
771fe6b9 | 432 | void *enc_priv; |
58bd0863 | 433 | int audio_polling_active; |
3e4b9982 | 434 | bool is_ext_encoder; |
36868bda | 435 | u16 caps; |
771fe6b9 JG |
436 | }; |
437 | ||
438 | struct radeon_connector_atom_dig { | |
439 | uint32_t igp_lane_info; | |
4143e919 | 440 | /* displayport */ |
746c1aa4 | 441 | struct radeon_i2c_chan *dp_i2c_bus; |
1a644cd4 | 442 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
4143e919 | 443 | u8 dp_sink_type; |
5801ead6 AD |
444 | int dp_clock; |
445 | int dp_lane_count; | |
8b834852 | 446 | bool edp_on; |
771fe6b9 JG |
447 | }; |
448 | ||
eed45b30 AD |
449 | struct radeon_gpio_rec { |
450 | bool valid; | |
451 | u8 id; | |
452 | u32 reg; | |
453 | u32 mask; | |
454 | }; | |
455 | ||
eed45b30 AD |
456 | struct radeon_hpd { |
457 | enum radeon_hpd_id hpd; | |
458 | u8 plugged_state; | |
459 | struct radeon_gpio_rec gpio; | |
460 | }; | |
461 | ||
26b5bc98 | 462 | struct radeon_router { |
26b5bc98 AD |
463 | u32 router_id; |
464 | struct radeon_i2c_bus_rec i2c_info; | |
465 | u8 i2c_addr; | |
fb939dfc AD |
466 | /* i2c mux */ |
467 | bool ddc_valid; | |
468 | u8 ddc_mux_type; | |
469 | u8 ddc_mux_control_pin; | |
470 | u8 ddc_mux_state; | |
471 | /* clock/data mux */ | |
472 | bool cd_valid; | |
473 | u8 cd_mux_type; | |
474 | u8 cd_mux_control_pin; | |
475 | u8 cd_mux_state; | |
26b5bc98 AD |
476 | }; |
477 | ||
8666c076 AD |
478 | enum radeon_connector_audio { |
479 | RADEON_AUDIO_DISABLE = 0, | |
480 | RADEON_AUDIO_ENABLE = 1, | |
481 | RADEON_AUDIO_AUTO = 2 | |
482 | }; | |
483 | ||
6214bb74 AD |
484 | enum radeon_connector_dither { |
485 | RADEON_FMT_DITHER_DISABLE = 0, | |
486 | RADEON_FMT_DITHER_ENABLE = 1, | |
487 | }; | |
488 | ||
771fe6b9 JG |
489 | struct radeon_connector { |
490 | struct drm_connector base; | |
491 | uint32_t connector_id; | |
492 | uint32_t devices; | |
493 | struct radeon_i2c_chan *ddc_bus; | |
5b1714d3 | 494 | /* some systems have an hdmi and vga port with a shared ddc line */ |
0294cf4f | 495 | bool shared_ddc; |
4ce001ab DA |
496 | bool use_digital; |
497 | /* we need to mind the EDID between detect | |
498 | and get modes due to analog/digital/tvencoder */ | |
499 | struct edid *edid; | |
771fe6b9 | 500 | void *con_priv; |
445282db | 501 | bool dac_load_detect; |
d0d0a225 | 502 | bool detected_by_load; /* if the connection status was determined by load */ |
b75fad06 | 503 | uint16_t connector_object_id; |
eed45b30 | 504 | struct radeon_hpd hpd; |
26b5bc98 AD |
505 | struct radeon_router router; |
506 | struct radeon_i2c_chan *router_bus; | |
8666c076 | 507 | enum radeon_connector_audio audio; |
6214bb74 | 508 | enum radeon_connector_dither dither; |
771fe6b9 JG |
509 | }; |
510 | ||
511 | struct radeon_framebuffer { | |
512 | struct drm_framebuffer base; | |
513 | struct drm_gem_object *obj; | |
514 | }; | |
515 | ||
996d5c59 AD |
516 | #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ |
517 | ((em) == ATOM_ENCODER_MODE_DP_MST)) | |
6383cf7d | 518 | |
7062ab67 CK |
519 | struct atom_clock_dividers { |
520 | u32 post_div; | |
521 | union { | |
522 | struct { | |
523 | #ifdef __BIG_ENDIAN | |
524 | u32 reserved : 6; | |
525 | u32 whole_fb_div : 12; | |
526 | u32 frac_fb_div : 14; | |
527 | #else | |
528 | u32 frac_fb_div : 14; | |
529 | u32 whole_fb_div : 12; | |
530 | u32 reserved : 6; | |
531 | #endif | |
532 | }; | |
533 | u32 fb_div; | |
534 | }; | |
535 | u32 ref_div; | |
536 | bool enable_post_div; | |
537 | bool enable_dithen; | |
538 | u32 vco_mode; | |
539 | u32 real_clock; | |
9219ed65 AD |
540 | /* added for CI */ |
541 | u32 post_divider; | |
542 | u32 flags; | |
7062ab67 CK |
543 | }; |
544 | ||
eaa778af AD |
545 | struct atom_mpll_param { |
546 | union { | |
547 | struct { | |
548 | #ifdef __BIG_ENDIAN | |
549 | u32 reserved : 8; | |
550 | u32 clkfrac : 12; | |
551 | u32 clkf : 12; | |
552 | #else | |
553 | u32 clkf : 12; | |
554 | u32 clkfrac : 12; | |
555 | u32 reserved : 8; | |
556 | #endif | |
557 | }; | |
558 | u32 fb_div; | |
559 | }; | |
560 | u32 post_div; | |
561 | u32 bwcntl; | |
562 | u32 dll_speed; | |
563 | u32 vco_mode; | |
564 | u32 yclk_sel; | |
565 | u32 qdr; | |
566 | u32 half_rate; | |
567 | }; | |
568 | ||
ae5b0abb AD |
569 | #define MEM_TYPE_GDDR5 0x50 |
570 | #define MEM_TYPE_GDDR4 0x40 | |
571 | #define MEM_TYPE_GDDR3 0x30 | |
572 | #define MEM_TYPE_DDR2 0x20 | |
573 | #define MEM_TYPE_GDDR1 0x10 | |
574 | #define MEM_TYPE_DDR3 0xb0 | |
575 | #define MEM_TYPE_MASK 0xf0 | |
576 | ||
577 | struct atom_memory_info { | |
578 | u8 mem_vendor; | |
579 | u8 mem_type; | |
580 | }; | |
581 | ||
582 | #define MAX_AC_TIMING_ENTRIES 16 | |
583 | ||
584 | struct atom_memory_clock_range_table | |
585 | { | |
586 | u8 num_entries; | |
587 | u8 rsv[3]; | |
588 | u32 mclk[MAX_AC_TIMING_ENTRIES]; | |
589 | }; | |
590 | ||
591 | #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 | |
592 | #define VBIOS_MAX_AC_TIMING_ENTRIES 20 | |
593 | ||
594 | struct atom_mc_reg_entry { | |
595 | u32 mclk_max; | |
596 | u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; | |
597 | }; | |
598 | ||
599 | struct atom_mc_register_address { | |
600 | u16 s1; | |
601 | u8 pre_reg_data; | |
602 | }; | |
603 | ||
604 | struct atom_mc_reg_table { | |
605 | u8 last; | |
606 | u8 num_entries; | |
607 | struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; | |
608 | struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; | |
609 | }; | |
610 | ||
611 | #define MAX_VOLTAGE_ENTRIES 32 | |
612 | ||
613 | struct atom_voltage_table_entry | |
614 | { | |
615 | u16 value; | |
616 | u32 smio_low; | |
617 | }; | |
618 | ||
619 | struct atom_voltage_table | |
620 | { | |
621 | u32 count; | |
622 | u32 mask_low; | |
65171944 | 623 | u32 phase_delay; |
ae5b0abb AD |
624 | struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; |
625 | }; | |
626 | ||
d79766fa AD |
627 | extern enum radeon_tv_std |
628 | radeon_combios_get_tv_info(struct radeon_device *rdev); | |
629 | extern enum radeon_tv_std | |
630 | radeon_atombios_get_tv_info(struct radeon_device *rdev); | |
4a6369e9 | 631 | extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, |
2abba66e | 632 | u16 *vddc, u16 *vddci, u16 *mvdd); |
d79766fa | 633 | |
5b1714d3 AD |
634 | extern struct drm_connector * |
635 | radeon_get_connector_for_encoder(struct drm_encoder *encoder); | |
9aa59993 AD |
636 | extern struct drm_connector * |
637 | radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); | |
638 | extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, | |
639 | u32 pixel_clock); | |
5b1714d3 | 640 | |
1d33e1fc AD |
641 | extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); |
642 | extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); | |
d7fa8bb3 AD |
643 | extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector); |
644 | extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); | |
eccea792 | 645 | extern int radeon_get_monitor_bpc(struct drm_connector *connector); |
d7fa8bb3 | 646 | |
d4877cf2 | 647 | extern void radeon_connector_hotplug(struct drm_connector *connector); |
224d94b1 | 648 | extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
5801ead6 AD |
649 | struct drm_display_mode *mode); |
650 | extern void radeon_dp_set_link_config(struct drm_connector *connector, | |
e811f5ae | 651 | const struct drm_display_mode *mode); |
224d94b1 AD |
652 | extern void radeon_dp_link_train(struct drm_encoder *encoder, |
653 | struct drm_connector *connector); | |
d5811e87 | 654 | extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); |
4143e919 | 655 | extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); |
9fa05c98 | 656 | extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); |
386d4d75 AD |
657 | extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
658 | struct drm_connector *connector); | |
558e27db | 659 | extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); |
ac89af1e | 660 | extern void radeon_atom_encoder_init(struct radeon_device *rdev); |
f3f1f03e | 661 | extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); |
5801ead6 AD |
662 | extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, |
663 | int action, uint8_t lane_num, | |
664 | uint8_t lane_set); | |
591a10e1 | 665 | extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); |
3f03ced8 | 666 | extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); |
746c1aa4 | 667 | extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
834b2904 | 668 | u8 write_byte, u8 *read_byte); |
746c1aa4 | 669 | |
f376b94f AD |
670 | extern void radeon_i2c_init(struct radeon_device *rdev); |
671 | extern void radeon_i2c_fini(struct radeon_device *rdev); | |
672 | extern void radeon_combios_i2c_init(struct radeon_device *rdev); | |
673 | extern void radeon_atombios_i2c_init(struct radeon_device *rdev); | |
674 | extern void radeon_i2c_add(struct radeon_device *rdev, | |
675 | struct radeon_i2c_bus_rec *rec, | |
676 | const char *name); | |
677 | extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, | |
678 | struct radeon_i2c_bus_rec *i2c_bus); | |
746c1aa4 | 679 | extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, |
6a93cb25 AD |
680 | struct radeon_i2c_bus_rec *rec, |
681 | const char *name); | |
771fe6b9 JG |
682 | extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
683 | struct radeon_i2c_bus_rec *rec, | |
684 | const char *name); | |
685 | extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); | |
5a6f98f5 AD |
686 | extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, |
687 | u8 slave_addr, | |
688 | u8 addr, | |
689 | u8 *val); | |
690 | extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, | |
691 | u8 slave_addr, | |
692 | u8 addr, | |
693 | u8 val); | |
fb939dfc AD |
694 | extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); |
695 | extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); | |
0a9069d3 | 696 | extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); |
771fe6b9 JG |
697 | extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); |
698 | ||
699 | extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); | |
700 | ||
ba032a58 AD |
701 | extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, |
702 | struct radeon_atom_ss *ss, | |
703 | int id); | |
704 | extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, | |
705 | struct radeon_atom_ss *ss, | |
706 | int id, u32 clock); | |
707 | ||
f523f74e AD |
708 | extern void radeon_compute_pll_legacy(struct radeon_pll *pll, |
709 | uint64_t freq, | |
710 | uint32_t *dot_clock_p, | |
711 | uint32_t *fb_div_p, | |
712 | uint32_t *frac_fb_div_p, | |
713 | uint32_t *ref_div_p, | |
714 | uint32_t *post_div_p); | |
715 | ||
716 | extern void radeon_compute_pll_avivo(struct radeon_pll *pll, | |
717 | u32 freq, | |
718 | u32 *dot_clock_p, | |
719 | u32 *fb_div_p, | |
720 | u32 *frac_fb_div_p, | |
721 | u32 *ref_div_p, | |
722 | u32 *post_div_p); | |
771fe6b9 | 723 | |
1f3b6a45 DA |
724 | extern void radeon_setup_encoder_clones(struct drm_device *dev); |
725 | ||
771fe6b9 JG |
726 | struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); |
727 | struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); | |
728 | struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); | |
729 | struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); | |
730 | struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); | |
99999aaa | 731 | extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); |
32f48ffe | 732 | extern void atombios_digital_setup(struct drm_encoder *encoder, int action); |
771fe6b9 | 733 | extern int atombios_get_encoder_mode(struct drm_encoder *encoder); |
2dafb74d | 734 | extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); |
4ce001ab | 735 | extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); |
771fe6b9 JG |
736 | |
737 | extern void radeon_crtc_load_lut(struct drm_crtc *crtc); | |
738 | extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |
739 | struct drm_framebuffer *old_fb); | |
4dd19b0d CB |
740 | extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, |
741 | struct drm_framebuffer *fb, | |
21c74a8e JW |
742 | int x, int y, |
743 | enum mode_set_atomic state); | |
771fe6b9 JG |
744 | extern int atombios_crtc_mode_set(struct drm_crtc *crtc, |
745 | struct drm_display_mode *mode, | |
746 | struct drm_display_mode *adjusted_mode, | |
747 | int x, int y, | |
748 | struct drm_framebuffer *old_fb); | |
749 | extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); | |
750 | ||
751 | extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |
752 | struct drm_framebuffer *old_fb); | |
4dd19b0d CB |
753 | extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, |
754 | struct drm_framebuffer *fb, | |
21c74a8e JW |
755 | int x, int y, |
756 | enum mode_set_atomic state); | |
4dd19b0d CB |
757 | extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, |
758 | struct drm_framebuffer *fb, | |
759 | int x, int y, int atomic); | |
771fe6b9 JG |
760 | extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, |
761 | struct drm_file *file_priv, | |
762 | uint32_t handle, | |
763 | uint32_t width, | |
764 | uint32_t height); | |
765 | extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, | |
766 | int x, int y); | |
767 | ||
f5a80209 | 768 | extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, |
d47abc58 MK |
769 | int *vpos, int *hpos, ktime_t *stime, |
770 | ktime_t *etime); | |
6383cf7d | 771 | |
3c537889 AD |
772 | extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); |
773 | extern struct edid * | |
c324acd5 | 774 | radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); |
771fe6b9 JG |
775 | extern bool radeon_atom_get_clock_info(struct drm_device *dev); |
776 | extern bool radeon_combios_get_clock_info(struct drm_device *dev); | |
777 | extern struct radeon_encoder_atom_dig * | |
778 | radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); | |
fcec570b AD |
779 | extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
780 | struct radeon_encoder_int_tmds *tmds); | |
781 | extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, | |
782 | struct radeon_encoder_int_tmds *tmds); | |
783 | extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, | |
784 | struct radeon_encoder_int_tmds *tmds); | |
785 | extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, | |
786 | struct radeon_encoder_ext_tmds *tmds); | |
787 | extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, | |
788 | struct radeon_encoder_ext_tmds *tmds); | |
6fe7ac3f AD |
789 | extern struct radeon_encoder_primary_dac * |
790 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); | |
791 | extern struct radeon_encoder_tv_dac * | |
792 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); | |
771fe6b9 JG |
793 | extern struct radeon_encoder_lvds * |
794 | radeon_combios_get_lvds_info(struct radeon_encoder *encoder); | |
771fe6b9 JG |
795 | extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); |
796 | extern struct radeon_encoder_tv_dac * | |
797 | radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); | |
798 | extern struct radeon_encoder_primary_dac * | |
799 | radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); | |
fcec570b AD |
800 | extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); |
801 | extern void radeon_external_tmds_setup(struct drm_encoder *encoder); | |
771fe6b9 JG |
802 | extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); |
803 | extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); | |
804 | extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); | |
805 | extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); | |
f657c2a7 YZ |
806 | extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); |
807 | extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); | |
771fe6b9 JG |
808 | extern void |
809 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); | |
810 | extern void | |
811 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); | |
812 | extern void | |
813 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); | |
814 | extern void | |
815 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); | |
816 | extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
817 | u16 blue, int regno); | |
b8c00ac5 DA |
818 | extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
819 | u16 *blue, int regno); | |
aaefcd42 | 820 | int radeon_framebuffer_init(struct drm_device *dev, |
38651674 | 821 | struct radeon_framebuffer *rfb, |
308e5bcb | 822 | struct drm_mode_fb_cmd2 *mode_cmd, |
38651674 | 823 | struct drm_gem_object *obj); |
771fe6b9 JG |
824 | |
825 | int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); | |
826 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); | |
827 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); | |
828 | void radeon_atombios_init_crtc(struct drm_device *dev, | |
829 | struct radeon_crtc *radeon_crtc); | |
830 | void radeon_legacy_init_crtc(struct drm_device *dev, | |
831 | struct radeon_crtc *radeon_crtc); | |
771fe6b9 JG |
832 | |
833 | void radeon_get_clock_info(struct drm_device *dev); | |
834 | ||
835 | extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); | |
836 | extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); | |
837 | ||
771fe6b9 JG |
838 | void radeon_enc_destroy(struct drm_encoder *encoder); |
839 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); | |
840 | void radeon_combios_asic_init(struct drm_device *dev); | |
c93bb85b | 841 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
e811f5ae | 842 | const struct drm_display_mode *mode, |
c93bb85b | 843 | struct drm_display_mode *adjusted_mode); |
3515387b AD |
844 | void radeon_panel_mode_fixup(struct drm_encoder *encoder, |
845 | struct drm_display_mode *adjusted_mode); | |
4ce001ab DA |
846 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); |
847 | ||
848 | /* legacy tv */ | |
849 | void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, | |
850 | uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, | |
851 | uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); | |
852 | void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, | |
853 | uint32_t *htotal_cntl, uint32_t *ppll_ref_div, | |
854 | uint32_t *ppll_div_3, uint32_t *pixclks_cntl); | |
855 | void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, | |
856 | uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, | |
857 | uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); | |
858 | void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, | |
859 | struct drm_display_mode *mode, | |
860 | struct drm_display_mode *adjusted_mode); | |
38651674 | 861 | |
134b480f AD |
862 | /* fmt blocks */ |
863 | void avivo_program_fmt(struct drm_encoder *encoder); | |
864 | void dce3_program_fmt(struct drm_encoder *encoder); | |
865 | void dce4_program_fmt(struct drm_encoder *encoder); | |
866 | void dce8_program_fmt(struct drm_encoder *encoder); | |
867 | ||
38651674 DA |
868 | /* fbdev layer */ |
869 | int radeon_fbdev_init(struct radeon_device *rdev); | |
870 | void radeon_fbdev_fini(struct radeon_device *rdev); | |
871 | void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); | |
872 | int radeon_fbdev_total_size(struct radeon_device *rdev); | |
873 | bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); | |
eb1f8e4f DA |
874 | |
875 | void radeon_fb_output_poll_changed(struct radeon_device *rdev); | |
6f34be50 AD |
876 | |
877 | void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); | |
878 | ||
ff72145b | 879 | int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); |
771fe6b9 | 880 | #endif |