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UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / radeon / radeon_mode.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
760285e7
DH		 33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
35#include <drm/drm_dp_helper.h>
36#include <drm/drm_fixed.h>
37#include <drm/drm_crtc_helper.h>
771fe6b9 38#include <linux/i2c.h>
771fe6b9 39#include <linux/i2c-algo-bit.h>
c93bb85b 40
38651674 41struct radeon_bo;
c93bb85b 42struct radeon_device;
771fe6b9
JG		 43
44#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
45#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
46#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
47#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
48
771fe6b9
JG		 49enum radeon_rmx_type {
50 RMX_OFF,
51 RMX_FULL,
52 RMX_CENTER,
53 RMX_ASPECT
54};
55
56enum radeon_tv_std {
57 TV_STD_NTSC,
58 TV_STD_PAL,
59 TV_STD_PAL_M,
60 TV_STD_PAL_60,
61 TV_STD_NTSC_J,
62 TV_STD_SCART_PAL,
63 TV_STD_SECAM,
64 TV_STD_PAL_CN,
d79766fa 65 TV_STD_PAL_N,
771fe6b9
JG		 66};
67
5b1714d3
AD		 68enum radeon_underscan_type {
69 UNDERSCAN_OFF,
70 UNDERSCAN_ON,
71 UNDERSCAN_AUTO,
72};
73
8e36ed00
AD		 74enum radeon_hpd_id {
75 RADEON_HPD_1 = 0,
76 RADEON_HPD_2,
77 RADEON_HPD_3,
78 RADEON_HPD_4,
79 RADEON_HPD_5,
80 RADEON_HPD_6,
81 RADEON_HPD_NONE = 0xff,
82};
83
f376b94f
AD		 84#define RADEON_MAX_I2C_BUS 16
85
9b9fe724
AD		 86/* radeon gpio-based i2c
87 * 1. "mask" reg and bits
88 * grabs the gpio pins for software use
89 * 0=not held 1=held
90 * 2. "a" reg and bits
91 * output pin value
92 * 0=low 1=high
93 * 3. "en" reg and bits
94 * sets the pin direction
95 * 0=input 1=output
96 * 4. "y" reg and bits
97 * input pin value
98 * 0=low 1=high
99 */
771fe6b9
JG		 100struct radeon_i2c_bus_rec {
101 bool valid;
6a93cb25
AD		 102 /* id used by atom */
103 uint8_t i2c_id;
bcc1c2a1 104 /* id used by atom */
8e36ed00 105 enum radeon_hpd_id hpd;
6a93cb25
AD		 106 /* can be used with hw i2c engine */
107 bool hw_capable;
108 /* uses multi-media i2c engine */
109 bool mm_i2c;
110 /* regs and bits */
771fe6b9
JG		 111 uint32_t mask_clk_reg;
112 uint32_t mask_data_reg;
113 uint32_t a_clk_reg;
114 uint32_t a_data_reg;
9b9fe724
AD		 115 uint32_t en_clk_reg;
116 uint32_t en_data_reg;
117 uint32_t y_clk_reg;
118 uint32_t y_data_reg;
771fe6b9
JG		 119 uint32_t mask_clk_mask;
120 uint32_t mask_data_mask;
771fe6b9
JG		 121 uint32_t a_clk_mask;
122 uint32_t a_data_mask;
9b9fe724
AD		 123 uint32_t en_clk_mask;
124 uint32_t en_data_mask;
125 uint32_t y_clk_mask;
126 uint32_t y_data_mask;
771fe6b9
JG		 127};
128
129struct radeon_tmds_pll {
130 uint32_t freq;
131 uint32_t value;
132};
133
134#define RADEON_MAX_BIOS_CONNECTOR 16
135
7c27f87d 136/* pll flags */
771fe6b9
JG		 137#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
138#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
139#define RADEON_PLL_USE_REF_DIV (1 << 2)
140#define RADEON_PLL_LEGACY (1 << 3)
141#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
142#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
143#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
144#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
145#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
146#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
147#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
d0e275a9 148#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
fc10332b 149#define RADEON_PLL_USE_POST_DIV (1 << 12)
86cb2bbf 150#define RADEON_PLL_IS_LCD (1 << 13)
f523f74e 151#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
771fe6b9
JG		 152
153struct radeon_pll {
fc10332b
AD		 154 /* reference frequency */
155 uint32_t reference_freq;
156
157 /* fixed dividers */
158 uint32_t reference_div;
159 uint32_t post_div;
160
161 /* pll in/out limits */
771fe6b9
JG		 162 uint32_t pll_in_min;
163 uint32_t pll_in_max;
164 uint32_t pll_out_min;
165 uint32_t pll_out_max;
86cb2bbf
AD		 166 uint32_t lcd_pll_out_min;
167 uint32_t lcd_pll_out_max;
fc10332b 168 uint32_t best_vco;
771fe6b9 169
fc10332b 170 /* divider limits */
771fe6b9
JG		 171 uint32_t min_ref_div;
172 uint32_t max_ref_div;
173 uint32_t min_post_div;
174 uint32_t max_post_div;
175 uint32_t min_feedback_div;
176 uint32_t max_feedback_div;
177 uint32_t min_frac_feedback_div;
178 uint32_t max_frac_feedback_div;
fc10332b
AD		 179
180 /* flags for the current clock */
181 uint32_t flags;
182
183 /* pll id */
184 uint32_t id;
771fe6b9
JG		 185};
186
187struct radeon_i2c_chan {
771fe6b9 188 struct i2c_adapter adapter;
746c1aa4
DA		 189 struct drm_device *dev;
190 union {
ac1aade6 191 struct i2c_algo_bit_data bit;
746c1aa4 192 struct i2c_algo_dp_aux_data dp;
746c1aa4 193 } algo;
771fe6b9
JG		 194 struct radeon_i2c_bus_rec rec;
195};
196
197/* mostly for macs, but really any system without connector tables */
198enum radeon_connector_table {
aa74fbb4 199 CT_NONE = 0,
771fe6b9
JG		 200 CT_GENERIC,
201 CT_IBOOK,
202 CT_POWERBOOK_EXTERNAL,
203 CT_POWERBOOK_INTERNAL,
204 CT_POWERBOOK_VGA,
205 CT_MINI_EXTERNAL,
206 CT_MINI_INTERNAL,
207 CT_IMAC_G5_ISIGHT,
208 CT_EMAC,
76a7142a 209 CT_RN50_POWER,
aa74fbb4 210 CT_MAC_X800,
9fad321a 211 CT_MAC_G5_9600,
6a556039 212 CT_SAM440EP
771fe6b9
JG		 213};
214
fcec570b
AD		 215enum radeon_dvo_chip {
216 DVO_SIL164,
217 DVO_SIL1178,
218};
219
8be48d92 220struct radeon_fbdev;
38651674 221
0783986a
AD		 222struct radeon_afmt {
223 bool enabled;
224 int offset;
225 bool last_buffer_filled_status;
226 int id;
227};
228
771fe6b9
JG		 229struct radeon_mode_info {
230 struct atom_context *atom_context;
61c4b24b 231 struct card_info *atom_card_info;
771fe6b9
JG		 232 enum radeon_connector_table connector_table;
233 bool mode_config_initialized;
bcc1c2a1 234 struct radeon_crtc *crtcs[6];
0783986a 235 struct radeon_afmt *afmt[6];
445282db
DA		 236 /* DVI-I properties */
237 struct drm_property *coherent_mode_property;
238 /* DAC enable load detect */
239 struct drm_property *load_detect_property;
5b1714d3 240 /* TV standard */
445282db
DA		 241 struct drm_property *tv_std_property;
242 /* legacy TMDS PLL detect */
243 struct drm_property *tmds_pll_property;
5b1714d3
AD		 244 /* underscan */
245 struct drm_property *underscan_property;
5bccf5e3
MG		 246 struct drm_property *underscan_hborder_property;
247 struct drm_property *underscan_vborder_property;
3c537889
AD		 248 /* hardcoded DFP edid from BIOS */
249 struct edid *bios_hardcoded_edid;
fafcf94e 250 int bios_hardcoded_edid_size;
38651674
DA		 251
252 /* pointer to fbdev info structure */
8be48d92 253 struct radeon_fbdev *rfbdev;
c93bb85b
JG		 254};
255
4ce001ab
DA		 256#define MAX_H_CODE_TIMING_LEN 32
257#define MAX_V_CODE_TIMING_LEN 32
258
259/* need to store these as reading
260 back code tables is excessive */
261struct radeon_tv_regs {
262 uint32_t tv_uv_adr;
263 uint32_t timing_cntl;
264 uint32_t hrestart;
265 uint32_t vrestart;
266 uint32_t frestart;
267 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
268 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
269};
270
771fe6b9
JG		 271struct radeon_crtc {
272 struct drm_crtc base;
273 int crtc_id;
274 u16 lut_r[256], lut_g[256], lut_b[256];
275 bool enabled;
276 bool can_tile;
6c0ae2ab 277 bool in_mode_set;
771fe6b9 278 uint32_t crtc_offset;
771fe6b9
JG		 279 struct drm_gem_object *cursor_bo;
280 uint64_t cursor_addr;
281 int cursor_width;
282 int cursor_height;
4162338a 283 uint32_t legacy_display_base_addr;
c836e862 284 uint32_t legacy_cursor_offset;
c93bb85b 285 enum radeon_rmx_type rmx_type;
5b1714d3
AD		 286 u8 h_border;
287 u8 v_border;
c93bb85b
JG		 288 fixed20_12 vsc;
289 fixed20_12 hsc;
de2103e4 290 struct drm_display_mode native_mode;
bcc1c2a1 291 int pll_id;
6f34be50
AD		 292 /* page flipping */
293 struct radeon_unpin_work *unpin_work;
294 int deferred_flip_completion;
771fe6b9
JG		 295};
296
297struct radeon_encoder_primary_dac {
298 /* legacy primary dac */
299 uint32_t ps2_pdac_adj;
300};
301
302struct radeon_encoder_lvds {
303 /* legacy lvds */
304 uint16_t panel_vcc_delay;
305 uint8_t panel_pwr_delay;
306 uint8_t panel_digon_delay;
307 uint8_t panel_blon_delay;
308 uint16_t panel_ref_divider;
309 uint8_t panel_post_divider;
310 uint16_t panel_fb_divider;
311 bool use_bios_dividers;
312 uint32_t lvds_gen_cntl;
313 /* panel mode */
de2103e4 314 struct drm_display_mode native_mode;
63ec0119
MD		 315 struct backlight_device *bl_dev;
316 int dpms_mode;
317 uint8_t backlight_level;
771fe6b9
JG		 318};
319
320struct radeon_encoder_tv_dac {
321 /* legacy tv dac */
322 uint32_t ps2_tvdac_adj;
323 uint32_t ntsc_tvdac_adj;
324 uint32_t pal_tvdac_adj;
325
4ce001ab
DA		 326 int h_pos;
327 int v_pos;
328 int h_size;
329 int supported_tv_stds;
330 bool tv_on;
771fe6b9 331 enum radeon_tv_std tv_std;
4ce001ab 332 struct radeon_tv_regs tv;
771fe6b9
JG		 333};
334
335struct radeon_encoder_int_tmds {
336 /* legacy int tmds */
337 struct radeon_tmds_pll tmds_pll[4];
338};
339
fcec570b
AD		 340struct radeon_encoder_ext_tmds {
341 /* tmds over dvo */
342 struct radeon_i2c_chan *i2c_bus;
343 uint8_t slave_addr;
344 enum radeon_dvo_chip dvo_chip;
345};
346
ebbe1cb9
AD		 347/* spread spectrum */
348struct radeon_atom_ss {
349 uint16_t percentage;
350 uint8_t type;
ba032a58 351 uint16_t step;
ebbe1cb9
AD		 352 uint8_t delay;
353 uint8_t range;
354 uint8_t refdiv;
ba032a58
AD		 355 /* asic_ss */
356 uint16_t rate;
357 uint16_t amount;
ebbe1cb9
AD		 358};
359
771fe6b9 360struct radeon_encoder_atom_dig {
5137ee94 361 bool linkb;
771fe6b9
JG		 362 /* atom dig */
363 bool coherent_mode;
ba032a58
AD		 364 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
365 /* atom lvds/edp */
366 uint32_t lcd_misc;
771fe6b9 367 uint16_t panel_pwr_delay;
ba032a58 368 uint32_t lcd_ss_id;
771fe6b9 369 /* panel mode */
de2103e4 370 struct drm_display_mode native_mode;
63ec0119
MD		 371 struct backlight_device *bl_dev;
372 int dpms_mode;
373 uint8_t backlight_level;
386d4d75 374 int panel_mode;
0783986a 375 struct radeon_afmt *afmt;
771fe6b9
JG		 376};
377
4ce001ab
DA		 378struct radeon_encoder_atom_dac {
379 enum radeon_tv_std tv_std;
380};
381
771fe6b9
JG		 382struct radeon_encoder {
383 struct drm_encoder base;
5137ee94 384 uint32_t encoder_enum;
771fe6b9
JG		 385 uint32_t encoder_id;
386 uint32_t devices;
4ce001ab 387 uint32_t active_device;
771fe6b9
JG		 388 uint32_t flags;
389 uint32_t pixel_clock;
390 enum radeon_rmx_type rmx_type;
5b1714d3 391 enum radeon_underscan_type underscan_type;
5bccf5e3
MG		 392 uint32_t underscan_hborder;
393 uint32_t underscan_vborder;
de2103e4 394 struct drm_display_mode native_mode;
771fe6b9 395 void *enc_priv;
58bd0863 396 int audio_polling_active;
3e4b9982 397 bool is_ext_encoder;
36868bda 398 u16 caps;
771fe6b9
JG		 399};
400
401struct radeon_connector_atom_dig {
402 uint32_t igp_lane_info;
4143e919 403 /* displayport */
746c1aa4 404 struct radeon_i2c_chan *dp_i2c_bus;
1a66c95a 405 u8 dpcd[8];
4143e919 406 u8 dp_sink_type;
5801ead6
AD		 407 int dp_clock;
408 int dp_lane_count;
8b834852 409 bool edp_on;
771fe6b9
JG		 410};
411
eed45b30
AD		 412struct radeon_gpio_rec {
413 bool valid;
414 u8 id;
415 u32 reg;
416 u32 mask;
417};
418
eed45b30
AD		 419struct radeon_hpd {
420 enum radeon_hpd_id hpd;
421 u8 plugged_state;
422 struct radeon_gpio_rec gpio;
423};
424
26b5bc98 425struct radeon_router {
26b5bc98
AD		 426 u32 router_id;
427 struct radeon_i2c_bus_rec i2c_info;
428 u8 i2c_addr;
fb939dfc
AD		 429 /* i2c mux */
430 bool ddc_valid;
431 u8 ddc_mux_type;
432 u8 ddc_mux_control_pin;
433 u8 ddc_mux_state;
434 /* clock/data mux */
435 bool cd_valid;
436 u8 cd_mux_type;
437 u8 cd_mux_control_pin;
438 u8 cd_mux_state;
26b5bc98
AD		 439};
440
771fe6b9
JG		 441struct radeon_connector {
442 struct drm_connector base;
443 uint32_t connector_id;
444 uint32_t devices;
445 struct radeon_i2c_chan *ddc_bus;
5b1714d3 446 /* some systems have an hdmi and vga port with a shared ddc line */
0294cf4f 447 bool shared_ddc;
4ce001ab
DA		 448 bool use_digital;
449 /* we need to mind the EDID between detect
450 and get modes due to analog/digital/tvencoder */
451 struct edid *edid;
771fe6b9 452 void *con_priv;
445282db 453 bool dac_load_detect;
d0d0a225 454 bool detected_by_load; /* if the connection status was determined by load */
b75fad06 455 uint16_t connector_object_id;
eed45b30 456 struct radeon_hpd hpd;
26b5bc98
AD		 457 struct radeon_router router;
458 struct radeon_i2c_chan *router_bus;
771fe6b9
JG		 459};
460
461struct radeon_framebuffer {
462 struct drm_framebuffer base;
463 struct drm_gem_object *obj;
464};
465
996d5c59
AD		 466#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
467 ((em) == ATOM_ENCODER_MODE_DP_MST))
6383cf7d 468
d79766fa
AD		 469extern enum radeon_tv_std
470radeon_combios_get_tv_info(struct radeon_device *rdev);
471extern enum radeon_tv_std
472radeon_atombios_get_tv_info(struct radeon_device *rdev);
473
5b1714d3
AD		 474extern struct drm_connector *
475radeon_get_connector_for_encoder(struct drm_encoder *encoder);
9aa59993
AD		 476extern struct drm_connector *
477radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
478extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
479 u32 pixel_clock);
5b1714d3 480
1d33e1fc
AD		 481extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
482extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
d7fa8bb3
AD		 483extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector);
484extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
eccea792 485extern int radeon_get_monitor_bpc(struct drm_connector *connector);
d7fa8bb3 486
d4877cf2 487extern void radeon_connector_hotplug(struct drm_connector *connector);
224d94b1 488extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
5801ead6
AD		 489 struct drm_display_mode *mode);
490extern void radeon_dp_set_link_config(struct drm_connector *connector,
e811f5ae 491 const struct drm_display_mode *mode);
224d94b1
AD		 492extern void radeon_dp_link_train(struct drm_encoder *encoder,
493 struct drm_connector *connector);
d5811e87 494extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
4143e919 495extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
9fa05c98 496extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
386d4d75
AD		 497extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
498 struct drm_connector *connector);
558e27db 499extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
ac89af1e 500extern void radeon_atom_encoder_init(struct radeon_device *rdev);
f3f1f03e 501extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
5801ead6
AD		 502extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
503 int action, uint8_t lane_num,
504 uint8_t lane_set);
591a10e1 505extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
3f03ced8 506extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
746c1aa4 507extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
834b2904 508 u8 write_byte, u8 *read_byte);
746c1aa4 509
f376b94f
AD		 510extern void radeon_i2c_init(struct radeon_device *rdev);
511extern void radeon_i2c_fini(struct radeon_device *rdev);
512extern void radeon_combios_i2c_init(struct radeon_device *rdev);
513extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
514extern void radeon_i2c_add(struct radeon_device *rdev,
515 struct radeon_i2c_bus_rec *rec,
516 const char *name);
517extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
518 struct radeon_i2c_bus_rec *i2c_bus);
746c1aa4 519extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
6a93cb25
AD		 520 struct radeon_i2c_bus_rec *rec,
521 const char *name);
771fe6b9
JG		 522extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
523 struct radeon_i2c_bus_rec *rec,
524 const char *name);
525extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
5a6f98f5
AD		 526extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
527 u8 slave_addr,
528 u8 addr,
529 u8 *val);
530extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
531 u8 slave_addr,
532 u8 addr,
533 u8 val);
fb939dfc
AD		 534extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
535extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
bc1c4dc3 536extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
771fe6b9
JG		 537extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
538
539extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
540
ba032a58
AD		 541extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
542 struct radeon_atom_ss *ss,
543 int id);
544extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
545 struct radeon_atom_ss *ss,
546 int id, u32 clock);
547
f523f74e
AD		 548extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
549 uint64_t freq,
550 uint32_t *dot_clock_p,
551 uint32_t *fb_div_p,
552 uint32_t *frac_fb_div_p,
553 uint32_t *ref_div_p,
554 uint32_t *post_div_p);
555
556extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
557 u32 freq,
558 u32 *dot_clock_p,
559 u32 *fb_div_p,
560 u32 *frac_fb_div_p,
561 u32 *ref_div_p,
562 u32 *post_div_p);
771fe6b9 563
1f3b6a45
DA		 564extern void radeon_setup_encoder_clones(struct drm_device *dev);
565
771fe6b9
JG		 566struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
567struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
568struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
569struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
570struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
99999aaa 571extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
32f48ffe 572extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
771fe6b9 573extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
2dafb74d 574extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
4ce001ab 575extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
771fe6b9
JG		 576
577extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
578extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
579 struct drm_framebuffer *old_fb);
4dd19b0d
CB		 580extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
581 struct drm_framebuffer *fb,
21c74a8e
JW		 582 int x, int y,
583 enum mode_set_atomic state);
771fe6b9
JG		 584extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
585 struct drm_display_mode *mode,
586 struct drm_display_mode *adjusted_mode,
587 int x, int y,
588 struct drm_framebuffer *old_fb);
589extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
590
591extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
592 struct drm_framebuffer *old_fb);
4dd19b0d
CB		 593extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
594 struct drm_framebuffer *fb,
21c74a8e
JW		 595 int x, int y,
596 enum mode_set_atomic state);
4dd19b0d
CB		 597extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
598 struct drm_framebuffer *fb,
599 int x, int y, int atomic);
771fe6b9
JG		 600extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
601 struct drm_file *file_priv,
602 uint32_t handle,
603 uint32_t width,
604 uint32_t height);
605extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
606 int x, int y);
607
f5a80209
MK		 608extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
609 int *vpos, int *hpos);
6383cf7d 610
3c537889
AD		 611extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
612extern struct edid *
c324acd5 613radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
771fe6b9
JG		 614extern bool radeon_atom_get_clock_info(struct drm_device *dev);
615extern bool radeon_combios_get_clock_info(struct drm_device *dev);
616extern struct radeon_encoder_atom_dig *
617radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
fcec570b
AD		 618extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
619 struct radeon_encoder_int_tmds *tmds);
620extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
621 struct radeon_encoder_int_tmds *tmds);
622extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
623 struct radeon_encoder_int_tmds *tmds);
624extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
625 struct radeon_encoder_ext_tmds *tmds);
626extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
627 struct radeon_encoder_ext_tmds *tmds);
6fe7ac3f
AD		 628extern struct radeon_encoder_primary_dac *
629radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
630extern struct radeon_encoder_tv_dac *
631radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
771fe6b9
JG		 632extern struct radeon_encoder_lvds *
633radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
771fe6b9
JG		 634extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
635extern struct radeon_encoder_tv_dac *
636radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
637extern struct radeon_encoder_primary_dac *
638radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
fcec570b
AD		 639extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
640extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
771fe6b9
JG		 641extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
642extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
643extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
644extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
f657c2a7
YZ		 645extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
646extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
771fe6b9
JG		 647extern void
648radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
649extern void
650radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
651extern void
652radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
653extern void
654radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
655extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
656 u16 blue, int regno);
b8c00ac5
DA		 657extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
658 u16 *blue, int regno);
aaefcd42 659int radeon_framebuffer_init(struct drm_device *dev,
38651674 660 struct radeon_framebuffer *rfb,
308e5bcb 661 struct drm_mode_fb_cmd2 *mode_cmd,
38651674 662 struct drm_gem_object *obj);
771fe6b9
JG		 663
664int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
665bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
666bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
667void radeon_atombios_init_crtc(struct drm_device *dev,
668 struct radeon_crtc *radeon_crtc);
669void radeon_legacy_init_crtc(struct drm_device *dev,
670 struct radeon_crtc *radeon_crtc);
771fe6b9
JG		 671
672void radeon_get_clock_info(struct drm_device *dev);
673
674extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
675extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
676
771fe6b9
JG		 677void radeon_enc_destroy(struct drm_encoder *encoder);
678void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
679void radeon_combios_asic_init(struct drm_device *dev);
c93bb85b 680bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
e811f5ae 681 const struct drm_display_mode *mode,
c93bb85b 682 struct drm_display_mode *adjusted_mode);
3515387b
AD		 683void radeon_panel_mode_fixup(struct drm_encoder *encoder,
684 struct drm_display_mode *adjusted_mode);
4ce001ab
DA		 685void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
686
687/* legacy tv */
688void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
689 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
690 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
691void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
692 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
693 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
694void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
695 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
696 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
697void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
698 struct drm_display_mode *mode,
699 struct drm_display_mode *adjusted_mode);
38651674
DA		 700
701/* fbdev layer */
702int radeon_fbdev_init(struct radeon_device *rdev);
703void radeon_fbdev_fini(struct radeon_device *rdev);
704void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
705int radeon_fbdev_total_size(struct radeon_device *rdev);
706bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
eb1f8e4f
DA		 707
708void radeon_fb_output_poll_changed(struct radeon_device *rdev);
6f34be50
AD		 709
710void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
711
ff72145b 712int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
771fe6b9 713#endif
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