[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / radeon / radeon_mode.h

/*
 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
 *                VA Linux Systems Inc., Fremont, California.
 * Copyright 2008 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Original Authors:
 *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
 *
 * Kernel port Author: Dave Airlie
 */

#ifndef RADEON_MODE_H
#define RADEON_MODE_H

#include <drm_crtc.h>
#include <drm_mode.h>
#include <drm_edid.h>
#include <drm_dp_helper.h>
#include <linux/i2c.h>
#include <linux/i2c-id.h>
#include <linux/i2c-algo-bit.h>
#include "radeon_fixed.h"

struct radeon_device;

#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)

enum radeon_rmx_type {
	RMX_OFF,
	RMX_FULL,
	RMX_CENTER,
	RMX_ASPECT
};

enum radeon_tv_std {
	TV_STD_NTSC,
	TV_STD_PAL,
	TV_STD_PAL_M,
	TV_STD_PAL_60,
	TV_STD_NTSC_J,
	TV_STD_SCART_PAL,
	TV_STD_SECAM,
	TV_STD_PAL_CN,
	TV_STD_PAL_N,
};

/* radeon gpio-based i2c
 * 1. "mask" reg and bits
 *    grabs the gpio pins for software use
 *    0=not held  1=held
 * 2. "a" reg and bits
 *    output pin value
 *    0=low 1=high
 * 3. "en" reg and bits
 *    sets the pin direction
 *    0=input 1=output
 * 4. "y" reg and bits
 *    input pin value
 *    0=low 1=high
 */
struct radeon_i2c_bus_rec {
	bool valid;
	/* id used by atom */
	uint8_t i2c_id;
	/* can be used with hw i2c engine */
	bool hw_capable;
	/* uses multi-media i2c engine */
	bool mm_i2c;
	/* regs and bits */
	uint32_t mask_clk_reg;
	uint32_t mask_data_reg;
	uint32_t a_clk_reg;
	uint32_t a_data_reg;
	uint32_t en_clk_reg;
	uint32_t en_data_reg;
	uint32_t y_clk_reg;
	uint32_t y_data_reg;
	uint32_t mask_clk_mask;
	uint32_t mask_data_mask;
	uint32_t a_clk_mask;
	uint32_t a_data_mask;
	uint32_t en_clk_mask;
	uint32_t en_data_mask;
	uint32_t y_clk_mask;
	uint32_t y_data_mask;
};

struct radeon_tmds_pll {
    uint32_t freq;
    uint32_t value;
};

#define RADEON_MAX_BIOS_CONNECTOR 16

#define RADEON_PLL_USE_BIOS_DIVS        (1 << 0)
#define RADEON_PLL_NO_ODD_POST_DIV      (1 << 1)
#define RADEON_PLL_USE_REF_DIV          (1 << 2)
#define RADEON_PLL_LEGACY               (1 << 3)
#define RADEON_PLL_PREFER_LOW_REF_DIV   (1 << 4)
#define RADEON_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
#define RADEON_PLL_PREFER_LOW_FB_DIV    (1 << 6)
#define RADEON_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
#define RADEON_PLL_PREFER_LOW_POST_DIV  (1 << 8)
#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
#define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 10)
#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)

struct radeon_pll {
	uint16_t reference_freq;
	uint16_t reference_div;
	uint32_t pll_in_min;
	uint32_t pll_in_max;
	uint32_t pll_out_min;
	uint32_t pll_out_max;
	uint16_t xclk;

	uint32_t min_ref_div;
	uint32_t max_ref_div;
	uint32_t min_post_div;
	uint32_t max_post_div;
	uint32_t min_feedback_div;
	uint32_t max_feedback_div;
	uint32_t min_frac_feedback_div;
	uint32_t max_frac_feedback_div;
	uint32_t best_vco;
};

struct radeon_i2c_chan {
	struct i2c_adapter adapter;
	struct drm_device *dev;
	union {
		struct i2c_algo_dp_aux_data dp;
		struct i2c_algo_bit_data bit;
	} algo;
	struct radeon_i2c_bus_rec rec;
};

/* mostly for macs, but really any system without connector tables */
enum radeon_connector_table {
	CT_NONE,
	CT_GENERIC,
	CT_IBOOK,
	CT_POWERBOOK_EXTERNAL,
	CT_POWERBOOK_INTERNAL,
	CT_POWERBOOK_VGA,
	CT_MINI_EXTERNAL,
	CT_MINI_INTERNAL,
	CT_IMAC_G5_ISIGHT,
	CT_EMAC,
};

enum radeon_dvo_chip {
	DVO_SIL164,
	DVO_SIL1178,
};

struct radeon_mode_info {
	struct atom_context *atom_context;
	struct card_info *atom_card_info;
	enum radeon_connector_table connector_table;
	bool mode_config_initialized;
	struct radeon_crtc *crtcs[2];
	/* DVI-I properties */
	struct drm_property *coherent_mode_property;
	/* DAC enable load detect */
	struct drm_property *load_detect_property;
	/* TV standard load detect */
	struct drm_property *tv_std_property;
	/* legacy TMDS PLL detect */
	struct drm_property *tmds_pll_property;

};

#define MAX_H_CODE_TIMING_LEN 32
#define MAX_V_CODE_TIMING_LEN 32

/* need to store these as reading
   back code tables is excessive */
struct radeon_tv_regs {
	uint32_t tv_uv_adr;
	uint32_t timing_cntl;
	uint32_t hrestart;
	uint32_t vrestart;
	uint32_t frestart;
	uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
	uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
};

struct radeon_crtc {
	struct drm_crtc base;
	int crtc_id;
	u16 lut_r[256], lut_g[256], lut_b[256];
	bool enabled;
	bool can_tile;
	uint32_t crtc_offset;
	struct drm_gem_object *cursor_bo;
	uint64_t cursor_addr;
	int cursor_width;
	int cursor_height;
	uint32_t legacy_display_base_addr;
	uint32_t legacy_cursor_offset;
	enum radeon_rmx_type rmx_type;
	fixed20_12 vsc;
	fixed20_12 hsc;
	struct drm_display_mode native_mode;
};

struct radeon_encoder_primary_dac {
	/* legacy primary dac */
	uint32_t ps2_pdac_adj;
};

struct radeon_encoder_lvds {
	/* legacy lvds */
	uint16_t panel_vcc_delay;
	uint8_t  panel_pwr_delay;
	uint8_t  panel_digon_delay;
	uint8_t  panel_blon_delay;
	uint16_t panel_ref_divider;
	uint8_t  panel_post_divider;
	uint16_t panel_fb_divider;
	bool     use_bios_dividers;
	uint32_t lvds_gen_cntl;
	/* panel mode */
	struct drm_display_mode native_mode;
};

struct radeon_encoder_tv_dac {
	/* legacy tv dac */
	uint32_t ps2_tvdac_adj;
	uint32_t ntsc_tvdac_adj;
	uint32_t pal_tvdac_adj;

	int               h_pos;
	int               v_pos;
	int               h_size;
	int               supported_tv_stds;
	bool              tv_on;
	enum radeon_tv_std tv_std;
	struct radeon_tv_regs tv;
};

struct radeon_encoder_int_tmds {
	/* legacy int tmds */
	struct radeon_tmds_pll tmds_pll[4];
};

struct radeon_encoder_ext_tmds {
	/* tmds over dvo */
	struct radeon_i2c_chan *i2c_bus;
	uint8_t slave_addr;
	enum radeon_dvo_chip dvo_chip;
};

/* spread spectrum */
struct radeon_atom_ss {
	uint16_t percentage;
	uint8_t type;
	uint8_t step;
	uint8_t delay;
	uint8_t range;
	uint8_t refdiv;
};

struct radeon_encoder_atom_dig {
	/* atom dig */
	bool coherent_mode;
	int dig_block;
	/* atom lvds */
	uint32_t lvds_misc;
	uint16_t panel_pwr_delay;
	struct radeon_atom_ss *ss;
	/* panel mode */
	struct drm_display_mode native_mode;
};

struct radeon_encoder_atom_dac {
	enum radeon_tv_std tv_std;
};

struct radeon_encoder {
	struct drm_encoder base;
	uint32_t encoder_id;
	uint32_t devices;
	uint32_t active_device;
	uint32_t flags;
	uint32_t pixel_clock;
	enum radeon_rmx_type rmx_type;
	struct drm_display_mode native_mode;
	void *enc_priv;
	int hdmi_offset;
	int hdmi_audio_workaround;
	int hdmi_buffer_status;
};

struct radeon_connector_atom_dig {
	uint32_t igp_lane_info;
	bool linkb;
	/* displayport */
	struct radeon_i2c_chan *dp_i2c_bus;
	u8 dpcd[8];
	u8 dp_sink_type;
	int dp_clock;
	int dp_lane_count;
};

struct radeon_gpio_rec {
	bool valid;
	u8 id;
	u32 reg;
	u32 mask;
};

enum radeon_hpd_id {
	RADEON_HPD_NONE = 0,
	RADEON_HPD_1,
	RADEON_HPD_2,
	RADEON_HPD_3,
	RADEON_HPD_4,
	RADEON_HPD_5,
	RADEON_HPD_6,
};

struct radeon_hpd {
	enum radeon_hpd_id hpd;
	u8 plugged_state;
	struct radeon_gpio_rec gpio;
};

struct radeon_connector {
	struct drm_connector base;
	uint32_t connector_id;
	uint32_t devices;
	struct radeon_i2c_chan *ddc_bus;
	/* some systems have a an hdmi and vga port with a shared ddc line */
	bool shared_ddc;
	bool use_digital;
	/* we need to mind the EDID between detect
	   and get modes due to analog/digital/tvencoder */
	struct edid *edid;
	void *con_priv;
	bool dac_load_detect;
	uint16_t connector_object_id;
	struct radeon_hpd hpd;
};

struct radeon_framebuffer {
	struct drm_framebuffer base;
	struct drm_gem_object *obj;
};

extern enum radeon_tv_std
radeon_combios_get_tv_info(struct radeon_device *rdev);
extern enum radeon_tv_std
radeon_atombios_get_tv_info(struct radeon_device *rdev);

extern void radeon_connector_hotplug(struct drm_connector *connector);
extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
				       struct drm_display_mode *mode);
extern void radeon_dp_set_link_config(struct drm_connector *connector,
				      struct drm_display_mode *mode);
extern void dp_link_train(struct drm_encoder *encoder,
			  struct drm_connector *connector);
extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
					   int action, uint8_t lane_num,
					   uint8_t lane_set);
extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
				uint8_t write_byte, uint8_t *read_byte);

extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
						    struct radeon_i2c_bus_rec *rec,
						    const char *name);
extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
						 struct radeon_i2c_bus_rec *rec,
						 const char *name);
extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
extern void radeon_i2c_sw_get_byte(struct radeon_i2c_chan *i2c_bus,
				   u8 slave_addr,
				   u8 addr,
				   u8 *val);
extern void radeon_i2c_sw_put_byte(struct radeon_i2c_chan *i2c,
				   u8 slave_addr,
				   u8 addr,
				   u8 val);
extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);

extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);

extern void radeon_compute_pll(struct radeon_pll *pll,
			       uint64_t freq,
			       uint32_t *dot_clock_p,
			       uint32_t *fb_div_p,
			       uint32_t *frac_fb_div_p,
			       uint32_t *ref_div_p,
			       uint32_t *post_div_p,
			       int flags);

extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
				     uint64_t freq,
				     uint32_t *dot_clock_p,
				     uint32_t *fb_div_p,
				     uint32_t *frac_fb_div_p,
				     uint32_t *ref_div_p,
				     uint32_t *post_div_p,
				     int flags);

extern void radeon_setup_encoder_clones(struct drm_device *dev);

struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);

extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
				   struct drm_framebuffer *old_fb);
extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
				   struct drm_display_mode *mode,
				   struct drm_display_mode *adjusted_mode,
				   int x, int y,
				   struct drm_framebuffer *old_fb);
extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);

extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
				 struct drm_framebuffer *old_fb);

extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
				  struct drm_file *file_priv,
				  uint32_t handle,
				  uint32_t width,
				  uint32_t height);
extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
				   int x, int y);

extern bool radeon_atom_get_clock_info(struct drm_device *dev);
extern bool radeon_combios_get_clock_info(struct drm_device *dev);
extern struct radeon_encoder_atom_dig *
radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
					  struct radeon_encoder_int_tmds *tmds);
extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
						     struct radeon_encoder_int_tmds *tmds);
extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
						   struct radeon_encoder_int_tmds *tmds);
extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
							 struct radeon_encoder_ext_tmds *tmds);
extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
						       struct radeon_encoder_ext_tmds *tmds);
extern struct radeon_encoder_primary_dac *
radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
extern struct radeon_encoder_tv_dac *
radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
extern struct radeon_encoder_lvds *
radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
extern struct radeon_encoder_tv_dac *
radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
extern struct radeon_encoder_primary_dac *
radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
extern void
radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
extern void
radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
extern void
radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
extern void
radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
				     u16 blue, int regno);
extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
				     u16 *blue, int regno);
struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev,
						  struct drm_mode_fb_cmd *mode_cmd,
						  struct drm_gem_object *obj);

int radeonfb_probe(struct drm_device *dev);

int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
void radeon_atombios_init_crtc(struct drm_device *dev,
			       struct radeon_crtc *radeon_crtc);
void radeon_legacy_init_crtc(struct drm_device *dev,
			     struct radeon_crtc *radeon_crtc);
extern void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state);

void radeon_get_clock_info(struct drm_device *dev);

extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);

void radeon_enc_destroy(struct drm_encoder *encoder);
void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
void radeon_combios_asic_init(struct drm_device *dev);
extern int radeon_static_clocks_init(struct drm_device *dev);
bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
					struct drm_display_mode *mode,
					struct drm_display_mode *adjusted_mode);
void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);

/* legacy tv */
void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
				      uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
				      uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
				  uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
				  uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
				  uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
				  uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
			       struct drm_display_mode *mode,
			       struct drm_display_mode *adjusted_mode);
#endif
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
	3	* VA Linux Systems Inc., Fremont, California.
	4	* Copyright 2008 Red Hat Inc.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Original Authors:
	25	* Kevin E. Martin, Rickard E. Faith, Alan Hourihane
	26	*
	27	* Kernel port Author: Dave Airlie
	28	*/
	29
	30	#ifndef RADEON_MODE_H
	31	#define RADEON_MODE_H
	32
	33	#include <drm_crtc.h>
	34	#include <drm_mode.h>
	35	#include <drm_edid.h>
746c1aa4	36	#include <drm_dp_helper.h>
771fe6b9 JG	37	#include <linux/i2c.h>
	38	#include <linux/i2c-id.h>
	39	#include <linux/i2c-algo-bit.h>
c93bb85b JG	40	#include "radeon_fixed.h"
	41
	42	struct radeon_device;
771fe6b9 JG	43
	44	#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
	45	#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
	46	#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
	47	#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
	48
771fe6b9 JG	49	enum radeon_rmx_type {
	50	RMX_OFF,
	51	RMX_FULL,
	52	RMX_CENTER,
	53	RMX_ASPECT
	54	};
	55
	56	enum radeon_tv_std {
	57	TV_STD_NTSC,
	58	TV_STD_PAL,
	59	TV_STD_PAL_M,
	60	TV_STD_PAL_60,
	61	TV_STD_NTSC_J,
	62	TV_STD_SCART_PAL,
	63	TV_STD_SECAM,
	64	TV_STD_PAL_CN,
d79766fa	65	TV_STD_PAL_N,
771fe6b9 JG	66	};
771fe6b9 JG	67
9b9fe724 AD	68	/* radeon gpio-based i2c
	69	* 1. "mask" reg and bits
	70	* grabs the gpio pins for software use
	71	* 0=not held 1=held
	72	* 2. "a" reg and bits
	73	* output pin value
	74	* 0=low 1=high
	75	* 3. "en" reg and bits
	76	* sets the pin direction
	77	* 0=input 1=output
	78	* 4. "y" reg and bits
	79	* input pin value
	80	* 0=low 1=high
	81	*/
771fe6b9 JG	82	struct radeon_i2c_bus_rec {
771fe6b9 JG	83	bool valid;
6a93cb25 AD	84	/* id used by atom */
	85	uint8_t i2c_id;
	86	/* can be used with hw i2c engine */
	87	bool hw_capable;
	88	/* uses multi-media i2c engine */
	89	bool mm_i2c;
	90	/* regs and bits */
771fe6b9 JG	91	uint32_t mask_clk_reg;
	92	uint32_t mask_data_reg;
	93	uint32_t a_clk_reg;
	94	uint32_t a_data_reg;
9b9fe724 AD	95	uint32_t en_clk_reg;
	96	uint32_t en_data_reg;
	97	uint32_t y_clk_reg;
	98	uint32_t y_data_reg;
771fe6b9 JG	99	uint32_t mask_clk_mask;
771fe6b9 JG	100	uint32_t mask_data_mask;
771fe6b9 JG	101	uint32_t a_clk_mask;
771fe6b9 JG	102	uint32_t a_data_mask;
9b9fe724 AD	103	uint32_t en_clk_mask;
	104	uint32_t en_data_mask;
	105	uint32_t y_clk_mask;
	106	uint32_t y_data_mask;
771fe6b9 JG	107	};
	108
	109	struct radeon_tmds_pll {
	110	uint32_t freq;
	111	uint32_t value;
	112	};
	113
	114	#define RADEON_MAX_BIOS_CONNECTOR 16
	115
	116	#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
	117	#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
	118	#define RADEON_PLL_USE_REF_DIV (1 << 2)
	119	#define RADEON_PLL_LEGACY (1 << 3)
	120	#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
	121	#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
	122	#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
	123	#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
	124	#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
	125	#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
	126	#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
d0e275a9	127	#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
771fe6b9 JG	128
	129	struct radeon_pll {
	130	uint16_t reference_freq;
	131	uint16_t reference_div;
	132	uint32_t pll_in_min;
	133	uint32_t pll_in_max;
	134	uint32_t pll_out_min;
	135	uint32_t pll_out_max;
	136	uint16_t xclk;
	137
	138	uint32_t min_ref_div;
	139	uint32_t max_ref_div;
	140	uint32_t min_post_div;
	141	uint32_t max_post_div;
	142	uint32_t min_feedback_div;
	143	uint32_t max_feedback_div;
	144	uint32_t min_frac_feedback_div;
	145	uint32_t max_frac_feedback_div;
	146	uint32_t best_vco;
	147	};
	148
	149	struct radeon_i2c_chan {
771fe6b9	150	struct i2c_adapter adapter;
746c1aa4 DA	151	struct drm_device *dev;
	152	union {
	153	struct i2c_algo_dp_aux_data dp;
	154	struct i2c_algo_bit_data bit;
	155	} algo;
771fe6b9 JG	156	struct radeon_i2c_bus_rec rec;
	157	};
	158
	159	/* mostly for macs, but really any system without connector tables */
	160	enum radeon_connector_table {
	161	CT_NONE,
	162	CT_GENERIC,
	163	CT_IBOOK,
	164	CT_POWERBOOK_EXTERNAL,
	165	CT_POWERBOOK_INTERNAL,
	166	CT_POWERBOOK_VGA,
	167	CT_MINI_EXTERNAL,
	168	CT_MINI_INTERNAL,
	169	CT_IMAC_G5_ISIGHT,
	170	CT_EMAC,
	171	};
	172
fcec570b AD	173	enum radeon_dvo_chip {
	174	DVO_SIL164,
	175	DVO_SIL1178,
	176	};
	177
771fe6b9 JG	178	struct radeon_mode_info {
771fe6b9 JG	179	struct atom_context *atom_context;
61c4b24b	180	struct card_info *atom_card_info;
771fe6b9 JG	181	enum radeon_connector_table connector_table;
771fe6b9 JG	182	bool mode_config_initialized;
c93bb85b	183	struct radeon_crtc *crtcs[2];
445282db DA	184	/* DVI-I properties */
	185	struct drm_property *coherent_mode_property;
	186	/* DAC enable load detect */
	187	struct drm_property *load_detect_property;
	188	/* TV standard load detect */
	189	struct drm_property *tv_std_property;
	190	/* legacy TMDS PLL detect */
	191	struct drm_property *tmds_pll_property;
	192
c93bb85b JG	193	};
c93bb85b JG	194
4ce001ab DA	195	#define MAX_H_CODE_TIMING_LEN 32
	196	#define MAX_V_CODE_TIMING_LEN 32
	197
	198	/* need to store these as reading
	199	back code tables is excessive */
	200	struct radeon_tv_regs {
	201	uint32_t tv_uv_adr;
	202	uint32_t timing_cntl;
	203	uint32_t hrestart;
	204	uint32_t vrestart;
	205	uint32_t frestart;
	206	uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
	207	uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
	208	};
	209
771fe6b9 JG	210	struct radeon_crtc {
	211	struct drm_crtc base;
	212	int crtc_id;
	213	u16 lut_r[256], lut_g[256], lut_b[256];
	214	bool enabled;
	215	bool can_tile;
	216	uint32_t crtc_offset;
771fe6b9 JG	217	struct drm_gem_object *cursor_bo;
	218	uint64_t cursor_addr;
	219	int cursor_width;
	220	int cursor_height;
4162338a	221	uint32_t legacy_display_base_addr;
c836e862	222	uint32_t legacy_cursor_offset;
c93bb85b	223	enum radeon_rmx_type rmx_type;
c93bb85b JG	224	fixed20_12 vsc;
c93bb85b JG	225	fixed20_12 hsc;
de2103e4	226	struct drm_display_mode native_mode;
771fe6b9 JG	227	};
	228
	229	struct radeon_encoder_primary_dac {
	230	/* legacy primary dac */
	231	uint32_t ps2_pdac_adj;
	232	};
	233
	234	struct radeon_encoder_lvds {
	235	/* legacy lvds */
	236	uint16_t panel_vcc_delay;
	237	uint8_t panel_pwr_delay;
	238	uint8_t panel_digon_delay;
	239	uint8_t panel_blon_delay;
	240	uint16_t panel_ref_divider;
	241	uint8_t panel_post_divider;
	242	uint16_t panel_fb_divider;
	243	bool use_bios_dividers;
	244	uint32_t lvds_gen_cntl;
	245	/* panel mode */
de2103e4	246	struct drm_display_mode native_mode;
771fe6b9 JG	247	};
	248
	249	struct radeon_encoder_tv_dac {
	250	/* legacy tv dac */
	251	uint32_t ps2_tvdac_adj;
	252	uint32_t ntsc_tvdac_adj;
	253	uint32_t pal_tvdac_adj;
	254
4ce001ab DA	255	int h_pos;
	256	int v_pos;
	257	int h_size;
	258	int supported_tv_stds;
	259	bool tv_on;
771fe6b9	260	enum radeon_tv_std tv_std;
4ce001ab	261	struct radeon_tv_regs tv;
771fe6b9 JG	262	};
	263
	264	struct radeon_encoder_int_tmds {
	265	/* legacy int tmds */
	266	struct radeon_tmds_pll tmds_pll[4];
	267	};
	268
fcec570b AD	269	struct radeon_encoder_ext_tmds {
	270	/* tmds over dvo */
	271	struct radeon_i2c_chan *i2c_bus;
	272	uint8_t slave_addr;
	273	enum radeon_dvo_chip dvo_chip;
	274	};
	275
ebbe1cb9 AD	276	/* spread spectrum */
	277	struct radeon_atom_ss {
	278	uint16_t percentage;
	279	uint8_t type;
	280	uint8_t step;
	281	uint8_t delay;
	282	uint8_t range;
	283	uint8_t refdiv;
	284	};
	285
771fe6b9 JG	286	struct radeon_encoder_atom_dig {
	287	/* atom dig */
	288	bool coherent_mode;
	289	int dig_block;
	290	/* atom lvds */
	291	uint32_t lvds_misc;
	292	uint16_t panel_pwr_delay;
ebbe1cb9	293	struct radeon_atom_ss *ss;
771fe6b9	294	/* panel mode */
de2103e4	295	struct drm_display_mode native_mode;
771fe6b9 JG	296	};
771fe6b9 JG	297
4ce001ab DA	298	struct radeon_encoder_atom_dac {
	299	enum radeon_tv_std tv_std;
	300	};
	301
771fe6b9 JG	302	struct radeon_encoder {
	303	struct drm_encoder base;
	304	uint32_t encoder_id;
	305	uint32_t devices;
4ce001ab	306	uint32_t active_device;
771fe6b9 JG	307	uint32_t flags;
	308	uint32_t pixel_clock;
	309	enum radeon_rmx_type rmx_type;
de2103e4	310	struct drm_display_mode native_mode;
771fe6b9	311	void *enc_priv;
dafc3bd5 CK	312	int hdmi_offset;
	313	int hdmi_audio_workaround;
	314	int hdmi_buffer_status;
771fe6b9 JG	315	};
	316
	317	struct radeon_connector_atom_dig {
	318	uint32_t igp_lane_info;
	319	bool linkb;
4143e919	320	/* displayport */
746c1aa4	321	struct radeon_i2c_chan *dp_i2c_bus;
1a66c95a	322	u8 dpcd[8];
4143e919	323	u8 dp_sink_type;
5801ead6 AD	324	int dp_clock;
5801ead6 AD	325	int dp_lane_count;
771fe6b9 JG	326	};
771fe6b9 JG	327
eed45b30 AD	328	struct radeon_gpio_rec {
	329	bool valid;
	330	u8 id;
	331	u32 reg;
	332	u32 mask;
	333	};
	334
	335	enum radeon_hpd_id {
	336	RADEON_HPD_NONE = 0,
	337	RADEON_HPD_1,
	338	RADEON_HPD_2,
	339	RADEON_HPD_3,
	340	RADEON_HPD_4,
	341	RADEON_HPD_5,
	342	RADEON_HPD_6,
	343	};
	344
	345	struct radeon_hpd {
	346	enum radeon_hpd_id hpd;
	347	u8 plugged_state;
	348	struct radeon_gpio_rec gpio;
	349	};
	350
771fe6b9 JG	351	struct radeon_connector {
	352	struct drm_connector base;
	353	uint32_t connector_id;
	354	uint32_t devices;
	355	struct radeon_i2c_chan *ddc_bus;
0294cf4f AD	356	/* some systems have a an hdmi and vga port with a shared ddc line */
0294cf4f AD	357	bool shared_ddc;
4ce001ab DA	358	bool use_digital;
	359	/* we need to mind the EDID between detect
	360	and get modes due to analog/digital/tvencoder */
	361	struct edid *edid;
771fe6b9	362	void *con_priv;
445282db	363	bool dac_load_detect;
b75fad06	364	uint16_t connector_object_id;
eed45b30	365	struct radeon_hpd hpd;
771fe6b9 JG	366	};
	367
	368	struct radeon_framebuffer {
	369	struct drm_framebuffer base;
	370	struct drm_gem_object *obj;
	371	};
	372
d79766fa AD	373	extern enum radeon_tv_std
	374	radeon_combios_get_tv_info(struct radeon_device *rdev);
	375	extern enum radeon_tv_std
	376	radeon_atombios_get_tv_info(struct radeon_device *rdev);
	377
d4877cf2 AD	378	extern void radeon_connector_hotplug(struct drm_connector *connector);
d4877cf2 AD	379	extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
5801ead6 AD	380	extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
	381	struct drm_display_mode *mode);
	382	extern void radeon_dp_set_link_config(struct drm_connector *connector,
	383	struct drm_display_mode *mode);
	384	extern void dp_link_train(struct drm_encoder *encoder,
	385	struct drm_connector *connector);
4143e919	386	extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
9fa05c98	387	extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
5801ead6 AD	388	extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
	389	int action, uint8_t lane_num,
	390	uint8_t lane_set);
746c1aa4 DA	391	extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
	392	uint8_t write_byte, uint8_t *read_byte);
	393
	394	extern struct radeon_i2c_chan radeon_i2c_create_dp(struct drm_device dev,
6a93cb25 AD	395	struct radeon_i2c_bus_rec *rec,
6a93cb25 AD	396	const char *name);
771fe6b9 JG	397	extern struct radeon_i2c_chan radeon_i2c_create(struct drm_device dev,
	398	struct radeon_i2c_bus_rec *rec,
	399	const char *name);
	400	extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
fcec570b AD	401	extern void radeon_i2c_sw_get_byte(struct radeon_i2c_chan *i2c_bus,
	402	u8 slave_addr,
	403	u8 addr,
	404	u8 *val);
	405	extern void radeon_i2c_sw_put_byte(struct radeon_i2c_chan *i2c,
	406	u8 slave_addr,
	407	u8 addr,
	408	u8 val);
771fe6b9 JG	409	extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
	410	extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
	411
	412	extern struct drm_encoder radeon_best_encoder(struct drm_connector connector);
	413
	414	extern void radeon_compute_pll(struct radeon_pll *pll,
	415	uint64_t freq,
	416	uint32_t *dot_clock_p,
	417	uint32_t *fb_div_p,
	418	uint32_t *frac_fb_div_p,
	419	uint32_t *ref_div_p,
	420	uint32_t *post_div_p,
	421	int flags);
	422
b27b6375 AD	423	extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
	424	uint64_t freq,
	425	uint32_t *dot_clock_p,
	426	uint32_t *fb_div_p,
	427	uint32_t *frac_fb_div_p,
	428	uint32_t *ref_div_p,
	429	uint32_t *post_div_p,
	430	int flags);
	431
1f3b6a45 DA	432	extern void radeon_setup_encoder_clones(struct drm_device *dev);
1f3b6a45 DA	433
771fe6b9 JG	434	struct drm_encoder radeon_encoder_legacy_lvds_add(struct drm_device dev, int bios_index);
	435	struct drm_encoder radeon_encoder_legacy_primary_dac_add(struct drm_device dev, int bios_index, int with_tv);
	436	struct drm_encoder radeon_encoder_legacy_tv_dac_add(struct drm_device dev, int bios_index, int with_tv);
	437	struct drm_encoder radeon_encoder_legacy_tmds_int_add(struct drm_device dev, int bios_index);
	438	struct drm_encoder radeon_encoder_legacy_tmds_ext_add(struct drm_device dev, int bios_index);
	439	extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
32f48ffe	440	extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
771fe6b9	441	extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
4ce001ab	442	extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
771fe6b9 JG	443
	444	extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
	445	extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
	446	struct drm_framebuffer *old_fb);
	447	extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
	448	struct drm_display_mode *mode,
	449	struct drm_display_mode *adjusted_mode,
	450	int x, int y,
	451	struct drm_framebuffer *old_fb);
	452	extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
	453
	454	extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
	455	struct drm_framebuffer *old_fb);
771fe6b9 JG	456
	457	extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
	458	struct drm_file *file_priv,
	459	uint32_t handle,
	460	uint32_t width,
	461	uint32_t height);
	462	extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
	463	int x, int y);
	464
	465	extern bool radeon_atom_get_clock_info(struct drm_device *dev);
	466	extern bool radeon_combios_get_clock_info(struct drm_device *dev);
	467	extern struct radeon_encoder_atom_dig *
	468	radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
fcec570b AD	469	extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
	470	struct radeon_encoder_int_tmds *tmds);
	471	extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
	472	struct radeon_encoder_int_tmds *tmds);
	473	extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
	474	struct radeon_encoder_int_tmds *tmds);
	475	extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
	476	struct radeon_encoder_ext_tmds *tmds);
	477	extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
	478	struct radeon_encoder_ext_tmds *tmds);
6fe7ac3f AD	479	extern struct radeon_encoder_primary_dac *
	480	radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
	481	extern struct radeon_encoder_tv_dac *
	482	radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
771fe6b9 JG	483	extern struct radeon_encoder_lvds *
771fe6b9 JG	484	radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
771fe6b9 JG	485	extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
	486	extern struct radeon_encoder_tv_dac *
	487	radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
	488	extern struct radeon_encoder_primary_dac *
	489	radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
fcec570b AD	490	extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
fcec570b AD	491	extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
771fe6b9 JG	492	extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
	493	extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
	494	extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
	495	extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
f657c2a7 YZ	496	extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
f657c2a7 YZ	497	extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
771fe6b9 JG	498	extern void
	499	radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
	500	extern void
	501	radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
	502	extern void
	503	radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
	504	extern void
	505	radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
	506	extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
	507	u16 blue, int regno);
b8c00ac5 DA	508	extern void radeon_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
b8c00ac5 DA	509	u16 *blue, int regno);
771fe6b9 JG	510	struct drm_framebuffer radeon_framebuffer_create(struct drm_device dev,
	511	struct drm_mode_fb_cmd *mode_cmd,
	512	struct drm_gem_object *obj);
	513
	514	int radeonfb_probe(struct drm_device *dev);
	515
	516	int radeonfb_remove(struct drm_device dev, struct drm_framebuffer fb);
	517	bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
	518	bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
	519	void radeon_atombios_init_crtc(struct drm_device *dev,
	520	struct radeon_crtc *radeon_crtc);
	521	void radeon_legacy_init_crtc(struct drm_device *dev,
	522	struct radeon_crtc *radeon_crtc);
ab1e9ea0	523	extern void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state);
771fe6b9 JG	524
	525	void radeon_get_clock_info(struct drm_device *dev);
	526
	527	extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
	528	extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
	529
771fe6b9 JG	530	void radeon_enc_destroy(struct drm_encoder *encoder);
	531	void radeon_copy_fb(struct drm_device dev, struct drm_gem_object dst_obj);
	532	void radeon_combios_asic_init(struct drm_device *dev);
	533	extern int radeon_static_clocks_init(struct drm_device *dev);
c93bb85b JG	534	bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
	535	struct drm_display_mode *mode,
	536	struct drm_display_mode *adjusted_mode);
4ce001ab DA	537	void atom_rv515_force_tv_scaler(struct radeon_device rdev, struct radeon_crtc radeon_crtc);
	538
	539	/* legacy tv */
	540	void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
	541	uint32_t h_total_disp, uint32_t h_sync_strt_wid,
	542	uint32_t v_total_disp, uint32_t v_sync_strt_wid);
	543	void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
	544	uint32_t htotal_cntl, uint32_t ppll_ref_div,
	545	uint32_t ppll_div_3, uint32_t pixclks_cntl);
	546	void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
	547	uint32_t htotal2_cntl, uint32_t p2pll_ref_div,
	548	uint32_t p2pll_div_0, uint32_t pixclks_cntl);
	549	void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
	550	struct drm_display_mode *mode,
	551	struct drm_display_mode *adjusted_mode);
771fe6b9	552	#endif